CN1831791B - Method for quickly changing address by software - Google Patents
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- CN1831791B CN1831791B CN200610011644A CN200610011644A CN1831791B CN 1831791 B CN1831791 B CN 1831791B CN 200610011644 A CN200610011644 A CN 200610011644A CN 200610011644 A CN200610011644 A CN 200610011644A CN 1831791 B CN1831791 B CN 1831791B
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- 238000013507 mapping Methods 0.000 claims description 8
- 238000004364 calculation method Methods 0.000 claims description 2
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Abstract
A method of utilizing fast changing address by software includes initializing parameter used in method, initializing data of buffer region, selecting mode of data address conversion, carrying out data operation, inputting new data, judging and ending process.
Description
Technical field
The present invention relates to the computer addressing technology, relate in particular to a kind of method of utilizing software to realize quickly changing address.
Background technology
Computer technology has been applied to every field, owing to different application process and various restrictions, the computer addressing technology is had different requirements in each different field.For example, in digital signal processing, digital signal is carried out filtering, convolution, Fourier transform or the like operation.Carry out these action needs historical data is preserved, being used for follow-up computing, and data are gone up if having time the requirement of alignment.
Especially digital filtering is a rudimentary algorithm during voice and Flame Image Process, pattern-recognition, analysis of spectrum etc. are used.
With a convolution algorithm is example.
For must preserving former N data, computing y (n) carries out computing.In order to make data carry out computing on computers, need constantly make amendment to the data address of being preserved.Fig. 1 will be when n=i and n=i+1, and h (k) and x (n) corresponding relation show.
In order to achieve the above object, the most direct amending method is exactly directly overall data to be carried out moving corresponding to the address of a chronomere.This method relatively adapts to the relatively shorter situation of data length; If will expensive extra expense under the long situation of data length.
Above-mentioned convolution algorithm is an example, as shown in Figure 1.After the n=i computing finishes, when need carry out n=i+1, whole data carry out the address move be exactly with figure in express the same, during with n=i, the locational data of N of corresponding h (k) row abandon, successively each data are moved to the right, soared for 0 position of corresponding h (k) row, then new data sample i+1 is placed on 0 position of corresponding h (k) row.Computing finishes and all will carry out the computing that move the lot of data address like this, at every turn.
In order to reduce calculated amount, a kind of thought of cyclic addressing is extensively used.Requirement is opened up a buffer zone as sliding window in storer, participate in computing in order to preserve a up-to-date batch data.If there are new data to arrive, it will cover data the earliest.It is annular in logic that specific implementation is regarded the storage space of one section physically continuous linearity as.When the end address of amount of physical memory is arrived in data addressing, return the start address of pointing to amount of physical memory automatically like this, form the storage space of annular in logic.
Among Fig. 2, Fig. 2-when (a) being depicted as n=i, the corresponding relation between h (k) and the x (n).Be without loss of generality, the start position of x (i) is not in the starting position in physical buffer district.Fig. 2-when (b) being depicted as n=i+1, the corresponding relation between h (k) and the x (n).Can see that data x this moment (i-N) have not needed, so according to the thinking of cyclic addressing is exactly that the sample data of input newly is put into the residing and h (2) of the unwanted historical data x of current time (i-N) on the deserved position, the buffer circle on so just can analog logic.
Some specialized apparatus and device provide the cyclic addressing function of low expense by hardware now.But a lot of general processors do not provide this function, need realize by software engineering.
Above-mentioned first method, under the relatively short situation of historical data length, the calculated amount of directly carrying out data-moving is little, if but under the long situation of historical data, the data-moving that need carry out will very big calculated amount.
Above-mentioned second method because new data is stored in the storage unit of the historical data that does not re-use, makes that each reference position of participating in a series of historical datas of computing all is different, when carries out map addresses so can't predict.Whether the address that at first will judge these data before calculating is the end address of buffer zone, if buffer zone moral end address, next address will use mapping mode.Each participates in the address of computing will judge that all expense is very big.
Now, the computer technology develop rapidly, powerful electronic product enters among people's the life, such as mobile phone, Digital Video or the like.These products are provided amenities for the people, because these products all are to use powered battery, this just has higher requirement to the energy consumption of processor simultaneously.In above-mentioned two methods loaded down with trivial details calculating is arranged all, this just makes the product working time shorten, and uses inconvenient.
Summary of the invention
In view of this, in order to reduce the expense of processor, carry out address mapping fast, the present invention proposes a kind of method of utilizing software to realize quickly changing address.
A kind of method of utilizing software to realize quickly changing address is characterized in that: comprise step:
Parameter in the A initial method;
The initialization of B buffer data;
C data address mapping mode is selected, data operation;
The input of D new data;
E judges and end process.
Further, need initialized parameter to comprise among the described method step A: buffer length, buffer zone start element, buffer zone ending unit.
Further, among the described method step B, the data that needs are handled deposit in the buffer zone successively.When data are filled with whole buffer zone successively or the data that require calculation carry out data operation when all having stored.
Further, data operation among the described method step C when required historical data length is long, according to the position of current pointer, is divided into the data in the whole buffer zone part of two linearities.Two parts are carried out computing respectively and then gather obtaining final result.After data operation finished, whether the judgement of the address of need circulating had arrived the ending of buffer zone with the decision pointer.If pointer has arrived the ending of buffer zone, pointer is mapped to the starting position of buffer zone.When circulating map addresses, when pointer arrives the buffer zone ending, under some situation, can use mapping method fast, promptly directly pointer is mapped to the starting position of buffer zone.
Further, data operation among the described method step C, when required historical data length more in short-term, directly carry out data-moving.
Further, among the described method step D, the data sample of new input, the data operation situation according to having finished leaves on the position of the historical data that does not re-use.
Further, the storage space of described buffer zone adopts physically continuous address location, also can be continuous in logic address location; Described processed data can be a storage unit, also the data block that can combine for several storage unit.
By the present invention, significantly reduced the address in the calculating process and relatively adjudicated calculating, reduced the computing cost of processor, can save the processing time, reduced the processor energy consumption, strong backing the working long hours of electronic product of present use battery.
Description of drawings
Fig. 1 is h (k) and x (n) corresponding relation synoptic diagram when n=i and n=i+1;
Fig. 2 cyclic addressing mode is h (k) and x (n) corresponding relation synoptic diagram when n=i and n=i+1;
The discontinuous buffer zone synoptic diagram of Fig. 3 physics;
The physics consecutive data block synoptic diagram that the several storage unit of Fig. 4 combine;
The physics discrete date piece synoptic diagram that the several storage unit of Fig. 5 combine.
Embodiment
With a convolution algorithm is example.
At first initialization length register (BK), effective base address (EFB), tail address (EOB).Then, according to the order of presentation of buffer zone data are filled successively.
According to the size of length register (BK), decide and adopt data-moving to carry out addressing, the cyclic addressing of still adopting the present invention to mention.If employing data-moving, as shown in Figure 1, after the n=i computing finishes, will carry out the calculating of n=i+1, because and the corresponding data of h (N) become otiose historical data, will and the corresponding data-moving of h (N-1) to and the storage unit of h (N) correspondence.So successively after the moving data, will and the corresponding storage unit of h (0) free out, new sample data i+1 just can be deposited in this storage unit.And then carry out computing, finish up to computing.
If the cyclic addressing of adopting the present invention to mention as shown in Figure 2, is without loss of generality, the starting point of x (n) is not at the start address in physical buffer district, in the corresponding storage unit of h (3).Like this according to decomposition thought of the present invention.Whole serial data is divided into two parts, and h (0)~h (3) and h (4)~h (N) is not interrupted owing to the centre in these two parts, so need not carry out the judgement of address in computation process, directly computing.
After this computing finishes, IP address moves after needing, at this moment just carry out primary address and relatively decide IP address whether to arrive the border of buffer zone (mode shown in Figure 2 is the beginning border of buffer zone), according to shown in Fig. 2-(a), next IP address is h (a 2) corresponding address.If this computing is the border of buffer zone,, just use the circulation map addresses that the computing IP address is mapped to h (N) such as h (0) corresponding address.
So constantly carry out computing, finish up to whole data computation.
In the foregoing description, when circulating map addresses, if the length of buffer zone is 2 integral number power, 4 powers such as 2, buffer length is 16, and promptly N=15 can adopt the fast address mapping, directly the address is added 1, get back four that the address adds after 1 and just got back to the another one border of buffer zone.Distribute to and h (0), h (1) ..., the binary form of h (15) corresponding buffer region address is shown 1111,1110 ..., 0000.When the start address of this computing was 1111, next IP address should be 0000 just.Adding 1 to 1111 becomes 10000, and getting back four has been exactly 0000, need not carry out other calculating just directly fast mapping to correct address.
The foregoing description is that buffer zone is a physically continuous storage unit.It also can be physically discontinuous storage unit.As shown in Figure 3, in this case, address increment is not simply to add 1 operation, but address pointer is to next address.All the other calculate a same specific embodiment.
The foregoing description is that data to be processed are single storage unit. the data block that deal with data also can combine for several storage unit, as shown in Figure 4, data block can be a continuous memory cell physically, A among the figure, B, C represent the data of forming data block respectively, the A that comprises that only represents data block herein, B, three identical data divisions of structure of C are not represented identical concrete data; As shown in Figure 5, data block also can be physically discontinuous storage unit. under first kind of situation, address increment neither add 1, but adds a fixing constant; Under second kind of situation, be that address pointer points to next address. processing procedure is with above-mentioned embodiment.
The above, only for the preferable embodiment of the present invention, but protection scope of the present invention is not limited thereto, so protection domain of the present invention is as the criterion with the protection domain of claims.
Claims (9)
1. one kind is applied in the computer addressing, utilizes software to realize the method for quickly changing address, it is characterized in that: may further comprise the steps:
Parameter in the A initial method;
The initialization of B buffer data;
C data address mapping mode is selected, data operation is when required historical data length is long, according to the position of current pointer, data in the whole buffer zone are divided into the part of two linearities, two parts are carried out computing respectively and then gather obtaining final result;
The input of D new data;
E judges and end process.
2. according to the described method of claim 1, it is characterized in that: need initialized parameter to comprise among the described method step A: buffer length, buffer zone start element, buffer zone ending unit.
3. according to the described method of claim 1, it is characterized in that: among the described method step B, the data that needs are handled deposit in the buffer zone successively, when data are filled with whole buffer zone successively or the data that require calculation carry out data operation when all having stored.
4. according to the described method of claim 1, it is characterized in that: after data operation finishes among the described method step C, the judgement of address need circulate, whether arrived the ending of buffer zone with the decision pointer, if pointer has arrived the ending of buffer zone, pointer is mapped to the starting position of buffer zone.
5. according to the described method of claim 4, it is characterized in that: among the described method step C, when pointer arrives the buffer zone ending, use mapping method fast, promptly directly pointer is mapped to the starting position of buffer zone.
6. according to the described method of claim 1, it is characterized in that: data operation among the described method step C, when required historical data length more in short-term, directly carry out data-moving.
7. according to the described method of claim 1, it is characterized in that: among the described method step D, the data sample of new input, the data operation situation according to having finished leaves on the position of the historical data that does not re-use.
8. according to the described method of claim 1, it is characterized in that: the storage space of described buffer zone adopts physically continuous address location or continuous in logic address location.
9. according to the described method of claim 1, it is characterized in that: described processed data are the data block that a storage unit or several storage unit combine.
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Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6122703A (en) * | 1997-08-15 | 2000-09-19 | Amati Communications Corporation | Generalized fourier transform processing system |
US20030200414A1 (en) * | 2002-03-15 | 2003-10-23 | Thomas Harley | Address generators for mapping arrays in bit reversed order |
CN1201251C (en) * | 1997-01-15 | 2005-05-11 | 艾利森电话股份有限公司 | Method and apparatus for FFT computation |
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Publication number | Priority date | Publication date | Assignee | Title |
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CN1201251C (en) * | 1997-01-15 | 2005-05-11 | 艾利森电话股份有限公司 | Method and apparatus for FFT computation |
US6122703A (en) * | 1997-08-15 | 2000-09-19 | Amati Communications Corporation | Generalized fourier transform processing system |
US20030200414A1 (en) * | 2002-03-15 | 2003-10-23 | Thomas Harley | Address generators for mapping arrays in bit reversed order |
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