Description of drawings
Figure 1A-1G is the manufacturing process sectional view that illustrates according to LCD manufacture method one preferred embodiment of the present invention; And
Fig. 2 A-2G is the manufacturing process sectional view that illustrates according to another preferred embodiment of LCD manufacture method of the present invention.
Description of reference numerals:
110: transparency carrier 112: black matrix"
114: black matrix" 116: chromatic filter layer
118: 120: the first conductor layers of flatness layer
122: doping semiconductor layer 130: thin film transistor (TFT)
132: source/drain electrode 134: source/drain electrode
136: capacitor 137: bottom electrode
138: portion of terminal 139: lower wire
140: semiconductor layer 142: dielectric layer
Conductor layer 150 in 144: the second: source/drain junction
151: source/drain junction 152: channel region
153: gate dielectric layer 154: grid
155: capacitor bonding land 156: the capacitor semiconductor layer
157: capacitor dielectric 158: top electrode
159: portion of terminal bonding land 160: the portion of terminal semiconductor layer
161: portion of terminal dielectric layer 162: upper conductor
170: pixel electrode 172: transparent lead
180: protective seam pattern 210: transparency carrier
212: black matrix" 214: black matrix"
216: chromatic filter layer 218: flatness layer
Conductor layer 222 in 220: the first: doping semiconductor layer
230: thin film transistor (TFT) 232: source/drain electrode
234: source/drain electrode 236: capacitor
237: bottom electrode 238: portion of terminal
239: lower wire 240: semiconductor layer
242: 244: the second conductor layers of dielectric layer
251: source/drain junction 252: source/drain junction
253: channel region 254: gate dielectric layer
255: grid 256: the capacitor bonding land
257: capacitor semiconductor layer 258: capacitor dielectric
259: top electrode 260: the portion of terminal bonding land
261: portion of terminal semiconductor layer 262: the portion of terminal dielectric layer
263: upper conductor 264: sweep trace
265: scanning linear semiconductor layer 266: the sweep trace dielectric layer
267: lead 270: pixel electrode
272: transparent lead 280: protective seam pattern
Embodiment
Below will and describe in detail and clearly demonstrate spirit of the present invention with diagram, as the person skilled in the art after understanding preferred embodiment of the present invention, when can be by the technology of teachings of the present invention, change and modification, it does not break away from spirit of the present invention and scope.
Embodiment one
With reference to Figure 1A-1G, it illustrates the preferred embodiment manufacturing process sectional view according to LCD manufacture method of the present invention.
In Figure 1A, at first, on transparency carrier 110, form black matrix" 112/114, chromatic filter layer 116 and flatness layer 118 in regular turn, to form colored optical filtering substrates.It is red, blue or green that the color of above-mentioned chromatic filter layer 116 can be.Flatness layer 118 can be transparent organic material, for example photoresist.
Then in Figure 1B, form first conductor layer 120 and doping semiconductor layer 122 that is covered on the flatness layer 118 continuously.Wherein, first conductor layer, 120 employed materials can be molybdenum, chromium, iridium, aluminium, titanium, above-mentioned composition or alloy, and its formation method can be physical vaporous deposition, as sputtering method.And doping semiconductor layer 122 employed materials can be N type doped amorphous silicon.
Then in Fig. 1 C, the patterning doping semiconductor layer and first conductor layer are to form source/drain electrode 132/134, the bottom electrode 137 of capacitor 136 and the lower wire 139 of portion of terminal 138 of thin film transistor (TFT) 130 on flatness layer 118.As shown in the figure, the source of thin film transistor (TFT) 130/drain electrode 132/134 is to be formed at the black matrix" of colored optical filtering substrates 112 tops, and the bottom electrode 137 of capacitor 136 then is formed at another black matrix" 114 tops of colored optical filtering substrates.Wherein, the method for the patterning doping semiconductor layer and first conductor layer can be photoetching and etching method.
In Fig. 1 D, on source/drain electrode 132/134, bottom electrode 137 and lower wire 139, form semiconductor layer 140, dielectric layer 142 and second conductor layer 144 continuously.Wherein, semiconductor layer 140 employed materials can be amorphous silicon.Dielectric layer 142 employed materials can be monox, silicon nitride or its composition, and its formation method can for example be a chemical vapour deposition technique.Second conductor layer, 144 employed materials can be molybdenum, chromium, iridium, aluminium, titanium, above-mentioned composition or alloy, and its formation method can be physical vaporous deposition, as sputtering method.
Then in Fig. 1 E, patterning second conductor layer, dielectric layer, semiconductor layer and doping semiconductor layer, with formation source/drain junction 150/151 in source/drain electrode 132/134, and between the source/drain electrode 132/134 of thin film transistor (TFT) 130, form channel region 152, on source/drain junction 150/151 and channel region 152, form the grid 154 of gate dielectric layer 153 and thin film transistor (TFT) 130; In addition, the multiple top electrode 158 that forms capacitor bonding land 155, capacitor semiconductor layer 156, capacitor dielectric 157 and capacitor 136 in bottom electrode 137 tops of capacitor 136; Then form the upper conductor 162 of portion of terminal bonding land 159, portion of terminal semiconductor layer 160, portion of terminal dielectric layer 161 and portion of terminal 138 in lower wire 139 tops of portion of terminal 138.Though not shown, also form sweep trace this moment simultaneously with the grid 154 of electric connection thin film transistor (TFT) 130 and the top electrode 158 of capacitor 136.Wherein, the method for patterning second conductor layer, dielectric layer, semiconductor layer and doping semiconductor layer can be photoetching and etching method.Particularly, this source/drain junction 150/151, capacitor bonding land 155 are ohmic contact regions with portion of terminal bonding land 159, reduce the resistance of conductor and promote the electrical of conductor.
Then in Fig. 1 F, first deposit transparent conductive layer above flatness layer 118, patterned transparent conductive layer again forming pixel electrode 170 in chromatic filter layer 116 tops, and forms the transparent lead 172 of portion of terminal 138 simultaneously in portion of terminal 138 tops.Wherein, pixel electrode 170 is to electrically connect the drain electrode 134 of thin film transistor (TFT) 130 and the bottom electrode 137 of capacitor 136, and the transparent lead 172 of portion of terminal 138 is upper conductor 162 and the lower wires 139 that electrically connect terminal portion 138, holds sluggish (RC-delay) problem of resistance to reduce.The material of above-mentioned transparency conducting layer can for example be tin indium oxide (Indium Tin Oxide; ITO).The method of patterned transparent conductive layer can be photoetching and etching method.
In Fig. 1 G, above flatness layer 118, deposit protective seam earlier at last, define the protective seam pattern 180 on the source of being covered in/drain electrode 132/134, grid 154, top electrode 158, bottom electrode 137 and the transparent lead 172 again.Definition protective seam pattern 180 methods can for example be photoetching and etching method.The thought person of should be specified, the present invention does not need to use any light shield in the processing procedure that forms protective seam pattern 180, only use the mode of exposure behind to carry out lithographic process, can reach the effect of patterning.That is, allow the below of light source self-induced transparency substrate 110 expose to protective seam, to carry out the step of exposure in the lithographic process.Because the black matrix" 112,114 of colored optical filtering substrates and the lower wire 139 of portion of terminal have the shield lights function; and the transparency carrier 110 of colored optical filtering substrates, chromatic filter layer 116 and flatness layer 118 can allow light penetration; so with colored optical filtering substrates and be positioned at structure on the colored optical filtering substrates, can accurately form the protective seam pattern 180 on the source of being covered in/drain electrode 132/134, grid 154, top electrode 158, bottom electrode 137 and the transparent lead 172 as light shield.
Finished colored optical filtering substrates processing procedure after, form parallel in colored optical filtering substrates top and have the substrate of common electrode with this colored optical filtering substrates.Afterwards, between this substrate and colored optical filtering substrates, inject liquid crystal.Certainly, the present invention also can adopt the liquid crystal drip-injection method (One Drop Fill ODF), carries out fixing between substrate and colored optical filtering substrates behind the liquid crystal again in perfusion.
Embodiment two
With reference to Fig. 2 A-2G, it illustrates the manufacturing process sectional view according to another preferred embodiment of LCD manufacture method of the present invention.
In Fig. 2 A, at first, on transparency carrier 210, form black matrix" 212/214, chromatic filter layer 216 and flatness layer 218 in regular turn, to form colored optical filtering substrates.It is red, blue or green that the color of above-mentioned chromatic filter layer 216 can be.
Then in Fig. 2 B, form first conductor layer 220 and doping semiconductor layer 222 that is covered on the flatness layer 218 continuously.Wherein, first conductor layer, 220 employed materials can be molybdenum, chromium, iridium, aluminium, titanium, above-mentioned composition or alloy, and its formation method can be physical vaporous deposition, as sputtering method.And doping semiconductor layer 222 employed materials can be N type doped amorphous silicon.
Then in Fig. 2 C, the patterning doping semiconductor layer and first conductor layer are to form source/drain electrode 232/234, the bottom electrode 237 of capacitor 236 and the lower wire 239 of portion of terminal 238 of thin film transistor (TFT) 230 on flatness layer 218.As shown in the figure, the source of thin film transistor (TFT) 230/drain electrode 232/234 is to be formed at the black matrix" of colored optical filtering substrates 212 tops, and the bottom electrode 237 of capacitor 236 then is formed at chromatic filter layer 216 tops.Wherein, the method for the patterning doping semiconductor layer and first conductor layer can be photoetching and etching method.
In Fig. 2 D, on source/drain electrode 232/234, bottom electrode 237 and lower wire 239, form semiconductor layer 240, dielectric layer 242 and second conductor layer 244 continuously.Wherein, semiconductor layer 240 employed materials can be amorphous silicon.Dielectric layer 242 employed materials can be monox, silicon nitride or its composition, and its formation method can for example be a chemical vapour deposition technique.Second conductor layer, 244 employed materials can be molybdenum, chromium, iridium, aluminium, titanium, above-mentioned composition or alloy, and its formation method can be physical vaporous deposition, as sputtering method.
Then in Fig. 2 E, patterning second conductor layer, dielectric layer, semiconductor layer and doping semiconductor layer, with formation source/drain junction 251/252 in source/drain electrode 232/234, and between the source/drain electrode 232/234 of thin film transistor (TFT) 230, form channel region 253, on source/drain junction 251/252 and channel region 253, form the grid 255 of gate dielectric layer 254 and thin film transistor (TFT) 230.In addition, form capacitor bonding land 256, capacitor semiconductor layer 257, capacitor dielectric 258 and the top electrode 259 of capacitor 236 in bottom electrode 237 tops of capacitor 236, moreover, form the upper conductor 263 of portion of terminal bonding land 260, portion of terminal semiconductor layer 261, portion of terminal dielectric layer 262 and portion of terminal 238 in lower wire 239 tops of portion of terminal 238, then form the lead 267 of scanning linear semiconductor layer 265, sweep trace dielectric layer 266 and the sweep trace 264 of sweep trace 264 in another black matrix" 214 tops of colored optical filtering substrates.Wherein, the method for patterning second conductor layer, dielectric layer, semiconductor layer and doping semiconductor layer can be photoetching and etching method.Particularly, this source/drain junction 251/252, capacitor bonding land 256 are ohmic contact regions with portion of terminal bonding land 260, reduce the resistance of conductor and promote the electrical of conductor.
Then in Fig. 2 F, first deposit transparent conductive layer above flatness layer 218, patterned transparent conductive layer again forming pixel electrode 270 in chromatic filter layer 216 tops, and forms the transparent lead 272 of portion of terminal 238 simultaneously in portion of terminal 238 tops.Pixel electrode 270 is to electrically connect the drain electrode 234 of thin film transistor (TFT) 230 and the bottom electrode 237 of capacitor 236, and the transparent lead 272 of portion of terminal 238 is upper conductor 263 and the lower wires 239 that electrically connect terminal portion 238, holds sluggish (RC-delay) problem of resistance to reduce.The material of transparency conducting layer can for example be tin indium oxide (Indium Tin Oxide; ITO).The method of patterned transparent conductive layer can be photoetching and etching method.
In Fig. 2 G, above flatness layer 218, deposit protective seam earlier at last, form the protective seam pattern 280 on the source of being covered in/drain electrode 232/234, grid 255, top electrode 259, bottom electrode 237 and the transparent lead 272 again.Form protective seam pattern 280 methods and can for example be photoetching and etching method.Only the person of should be specified is not need to use any light shield in the processing procedure that forms protective seam pattern 280, only uses the mode of exposure behind to carry out lithographic process, can reach the effect of patterning.That is, allow the below of light source self-induced transparency substrate 210 expose to protective seam, to carry out the step of exposure in the lithographic process.Because black matrix" 212,214, the bottom electrode 237 of capacitor 236 and the lower wire 239 of portion of terminal 238 of colored optical filtering substrates have the shield lights function; and the transparency carrier 210 of colored optical filtering substrates, chromatic filter layer 216 and flatness layer 218 can allow light penetration; so with colored optical filtering substrates and be positioned at structure on the colored optical filtering substrates, can accurately form the protective seam pattern 280 on the source of being covered in/drain electrode 232/234, grid 255, top electrode 259, bottom electrode 237 and the transparent lead 272 as light shield.
After having finished the processing procedure of colored optical filtering substrates, form parallel again in colored optical filtering substrates top and have the substrate of common electrode with this colored optical filtering substrates.Afterwards, between this colored optical filtering substrates and substrate, inject liquid crystal again.Certainly, the present invention also can adopt the liquid crystal drip-injection method (One Drop Fill ODF), carries out fixing between substrate and colored optical filtering substrates behind the liquid crystal again in perfusion.
By the invention described above preferred embodiment as can be known, use the present invention and have following advantage.
(1),, and there is not the assembling alignment problem so the pixel electrode of array has been aimed at the chromatic filter layer of colored optical filtering substrates when assembling because of the present invention is formed at the thin film transistor (TFT) array of LCD on the colored optical filtering substrates.
(2) because the present invention utilizes the mode of exposure behind to form the protective seam pattern, once make the required light shield processing procedure of transistor base so can be reduced by at least.
(3) the present invention has also avoided the use of half gray-level mask when reducing the light shield processing procedure, so can reduce the processing procedure cost and make risk.
Though the present invention discloses as above with preferred embodiment; right its is not in order to limiting the present invention, anyly has the knack of this skill person, without departing from the spirit and scope of the present invention; when can being used for a variety of modifications and variations, so protection scope of the present invention is as the criterion when looking claims person of defining.