CN1828482A - Control output signal switchinging time to save electric power consumption - Google Patents
Control output signal switchinging time to save electric power consumption Download PDFInfo
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- CN1828482A CN1828482A CN 200610073504 CN200610073504A CN1828482A CN 1828482 A CN1828482 A CN 1828482A CN 200610073504 CN200610073504 CN 200610073504 CN 200610073504 A CN200610073504 A CN 200610073504A CN 1828482 A CN1828482 A CN 1828482A
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Abstract
The invention relates to a method and device for reducing power consumption by reducing the switching times of output signal of processor. The switching simplified unit is installed in output circuit of one processor. The initial output signal of processor containing address, data and controlling signal, and energy generation signal generated by decoding unit of processor are the input signal of said switching simplified unit. The switching simplified unit comprises at least one logical circuit unit used to reduce switching times when said energy generation signal is closed.
Description
Technical field
The present invention relates to a kind of processor, the switching that especially sees through the control output signal is to reduce power consumption.
Background technology
In these electronic epoch, the cheap electronic installation that the multi-functional height of miniaturization is integrated has the great market demand.For catering to this trend, in electronic installation, reduce the subject under discussion of power consumption and just get over fractal key.Owing in counter or be referred to as the electric power of the suitable vast scale of a processor consumption of central processing unit (CPU), had several different methods to be used to reduce the electric power that processor consumes.
Traditional processor design can activate a plurality of outputs that surpass actual needs simultaneously simultaneously, and tolerable is closed the output of not using in many cases.Wherein a kind of situation is to betide the processor situation narrow than the width of bus to the write activity of a storer or any external peripheral device.Eight that for example only write in 32 mean that promptly it is not to be used that 24 positions are arranged.If this circuit of 24 is closed, then must not consume any electric power.When second kind of situation betides the transfer address to storer or any external peripheral device.In case after above-mentioned storer or external peripheral device were learnt the address, neither palpus changed address value before an inferior address occurs.Even some peripheral unit can increase progressively the address automatically when access not.In above-mentioned all as in the situation, switching above-mentioned unnecessary output will waste electric power, so can close above-mentioned output to save electric power.
Summary of the invention
In above-mentioned background of invention, in order to meet the demand of saving electric power on the industry, the invention provides a kind of processor can be in order to solve the target that above-mentioned traditional processor fails to reach.
One embodiment of the invention provide a kind of processor system, it is characterized in that, comprise:
One processor core is present in processor inside to execute instruction and to produce original output signal; And
At least one switching simplified unit is to connect at least one original output signal of this processor, each this switching simplified unit receives an activation signal and this original output signal, each this switching simplified unit comprise at least one logic circuit unit with when this enable signal for close season this original output signal be a default value or be left a preceding value and when this enable signal serve as to open season this original output signal to pass through this switching simplified unit, produce a final output signal in view of the above with this original output signal of replacement.
Wherein above-mentioned switching simplified unit is to be used for each byte output signal channel and this enable signal is to be used to control each other byte output signal channel independently, to work as this enable signal is that each byte output signal of closing seasonal this original output signal is a default value or is left a preceding value, and works as this enable signal and pass through this switching simplified unit for each byte output signal of opening seasonal this original output signal.
Each wherein above-mentioned switching simplified unit is to comprise following may the variation:
Control each;
Control each byte; And
Control is a position arbitrarily.
Wherein above-mentioned enable signal is to be divided into a plurality of signals to control each byte signaling channel independently.
Wherein above-mentioned original output signal is to comprise following may the variation:
One address;
One data; And
One control signal.
Wherein above-mentioned enable signal is to comprise following may the variation:
One address enable signal;
One data enable signal; And
The enable signal of one control signal.
Wherein above-mentioned switching simplified unit still comprises following may the variation:
One with door with when this enable signal for close season this original output signal be a default value and when this enable signal serve as to open seasonal this original output signal to pass through this switching simplified unit;
One or door with when this enable signal for close season this original output signal be a default value and when this enable signal serve as to open seasonal this original output signal to pass through this switching simplified unit;
One multiplexer with when this enable signal for close season this original output signal be a default value and when this enable signal serve as to open seasonal this original output signal to pass through this switching simplified unit; And
One door bolt with when this enable signal for close season this original output signal be a default value and when this enable signal serve as to open seasonal this original output signal to pass through this switching simplified unit.
Wherein above-mentioned switching simplified unit comprises:
One flip-flop; And
One multiplexer, this multiplexer comprise one first input signal from the output of this multiplexer and via this flip-flop receive a feedback signal, one second input signal selects signal to receive this enable signal to receive this original output signal and, be left a preceding value and pass through this switching simplified unit for seasonal this original output signal of unlatching when this enable signal for closing season this original output signal when this enable signal in view of the above.
Wherein above-mentioned switching simplified unit can be positioned at the inside or the outside of this processor.
Another embodiment of the present invention provides a processor system, it is characterized in that, comprises:
One processor core is present in processor inside to execute instruction and to produce original output signal, and this processor core also comprises a decoding unit to produce an activation signal; And
At least one switching simplified unit is to connect at least one original output signal of this processor, each this switching simplified unit receives an activation signal and this original output signal, each this switching simplified unit comprise at least one logic circuit unit with when this enable signal for close season this original output signal be a default value or be left a preceding value and when this enable signal serve as to open season this original output signal to pass through this switching simplified unit, produce a final output signal in view of the above with this original output signal of replacement.
Wherein above-mentioned decoding unit is decoded to produce this enable signal and decoding instruction to receiving instruction.
Wherein above-mentioned this enable signal that decoding unit produced is to be used for judging whether this original output signal needs to upgrade.
Each wherein above-mentioned switching simplified unit comprises control the following of one bus and may change:
Control each;
Control each byte; And
Control is a position arbitrarily.
Wherein above-mentioned enable signal is to be divided into a plurality of signals to control each byte signaling channel independently.
Wherein above-mentioned switching simplified unit still comprises following may the variation:
One with door with when this enable signal for close season this original output signal be a default value and when this enable signal serve as to open seasonal this original output signal to pass through this switching simplified unit;
One or door with when this enable signal for close season this original output signal be a default value and when this enable signal serve as to open seasonal this original output signal to pass through this switching simplified unit;
One multiplexer with when this enable signal for close season this original output signal be a default value and when this enable signal serve as to open seasonal this original output signal to pass through this switching simplified unit; And
One door bolt with when this enable signal for close season this original output signal be a default value and when this enable signal serve as to open seasonal this original output signal to pass through this switching simplified unit.
Wherein above-mentioned switching simplified unit comprises:
One flip-flop; And
One multiplexer, this multiplexer comprise one first input signal from the output of this multiplexer and via this flip-flop receive a feedback signal, one second input signal selects signal to receive this enable signal to receive this original output signal and, be left a preceding value and pass through this switching simplified unit for seasonal this original output signal of unlatching when this enable signal for closing season this original output signal when this enable signal in view of the above.
Another embodiment of the present invention provides a kind of method of saving power consumption of treater, it is characterized in that, comprises:
Receive an original output signal and an activation signal;
Judge whether this enable signal is opened;
When this enable signal when opening, make that this original output signal is a final output signal; And
When this enable signal when closing, to make this original output signal be default value or be left a preceding value.
Wherein above-mentioned original output signal is to comprise following may the variation:
With one is unit;
With a byte is unit; And
With any position is unit.
Wherein also comprise:
Cutting apart this enable signal is that a plurality of signals are to control each byte signaling channel independently.
Description of drawings
For further specifying concrete technology contents of the present invention, below in conjunction with embodiment and accompanying drawing describes in detail as after, wherein:
Figure 1A is the block schematic diagram for a simplification computer system;
Figure 1B is the block schematic diagram for signal transmission in the core of a processor in the known technology;
Fig. 1 C is the block schematic diagram for a decoding unit in the known technology;
Fig. 2 A is the block schematic diagram according to a decoding unit of the present invention;
Fig. 2 B is for having the block schematic diagram of a plurality of switching simplified unit with the processor that connects an OPADD bus, an output data bus and a control signal bus;
Fig. 3 be in the microprocessor about a block schematic diagram of a plurality of switching simplified unit of an output data bus;
Fig. 4 be in the microprocessor about a block schematic diagram of a plurality of switching simplified unit of an output data bus;
Fig. 5 is for having a plurality of switching simplified unit to connect a block schematic diagram of an OPADD bus, an output data bus and a control signal bus in processor outside;
Fig. 6 is the block schematic diagram for the switching simplified unit of one first embodiment according to the present invention;
Fig. 7 is the block schematic diagram for the switching simplified unit of one second embodiment according to the present invention;
Fig. 8 is the block schematic diagram for the switching simplified unit of one the 3rd embodiment according to the present invention;
Fig. 9 is the block schematic diagram for the switching simplified unit of one the 4th embodiment according to the present invention;
Figure 10 is the block schematic diagram for the switching simplified unit of one the 5th embodiment according to the present invention;
Figure 11 is a synoptic diagram of exporting switching times for the first method that makes output valve be made as a default value that first to fourth embodiment according to the present invention is disclosed with minimizing;
Figure 12 is for being the synoptic diagram of the second method of a preceding value with minimizing output switching times according to the reservation output valve that fifth embodiment of the invention disclosed;
Figure 13 is for utilizing an activation signal to economize a synoptic diagram of output switching times with letter in a bus of nybble width;
Figure 14 is for utilizing four enable signals to economize a synoptic diagram of output switching times with letter in a bus of nybble width; And
Figure 15 is the flow process synoptic diagram for the switching simplified unit function mode.
Embodiment
The present invention is a kind of processor in this direction of inquiring into.In order to understand the present invention up hill and dale, detailed step and composition thereof will be proposed in following description.Apparently, execution of the present invention is not defined in the specific details that the operator had the knack of of processor.On the other hand, well-known composition or step are not described in the details, with the restriction of avoiding causing the present invention unnecessary.Preferred embodiment meeting of the present invention is described in detail as follows, yet except these were described in detail, the present invention can also implement in other embodiments widely, and scope of the present invention do not limited, its with after claim be as the criterion.
Shown in Figure 1A, it is the block schematic diagram for a simplification computer system.One computer system can be simplified and only comprise at least three primary clusterings: at least one processor 110, at least one memory cell 120 are gone into subsystem 130 with at least one output.Above-mentioned processor 110 also is called as central processing unit usually.Memory cell 120 is to be used for stored program instructions and data.Output is gone into subsystem 130 and then is situated between with different I/O device 140 and connects, and these I/O devices 140 of computer system connection also are called as peripheral device therewith, and it mainly has two kinds of purposes: link up with the external world and store data.I/O device 140 such as keyboard, display screen, printer and modulator-demodular unit is to be used to provide user's interface; 140 of I/O devices as disk and so on are the secondary data storage devices.
Figure 1A also illustrates a connection network that is called as system bus, and it is the line of communication that is used to provide between above-mentioned three kinds of assemblies.This system bus comprises three primary clusterings: an address bus 150, a data bus 160 and a control bus 170.The width of address bus 150 determines the size of these processor 110 addressable physical storages.The width of data bus 160 determines this processor 110 and memory cell 120 or output to go into the size of swap date between the subsystem 130.170 of control buss comprise one group of control signal.The typical control signal comprises that memory read is got, storer writes, export into read, export into write, interrupt, interrupt cognitive (acknowledge), bus request is assented control signals such as (grant) with bus.Above-mentioned control signal is to be used to indicate the action kind of being carried out on this system bus.
Please refer to shown in Figure 1B, it is the block schematic diagram for signal transmission in the processor core 181 of a processor 180 in the known technology.This processor 180 has three kinds of output signals usually: address, data and control signal.One processor core 181 is to be used to execute instruction and its result to be sent to other assembly of a computer system.In the conventional processors design, above-mentioned three kinds of output signals will be shown in Figure 1B, and processor core 181 directly is sent to output bus thus.In known technology, decoding unit 182 there is no and produces any control signal so that the switching of control output, that is even when some be output as invalid maybe can close the time, also must all output of unlatching.
Please refer to shown in Fig. 1 C, it is the block schematic diagram for a decoding unit 190 in the known technology.One decoding unit 190 receives the data and instruction from the instruction fetch unit of a pipeline architecture processor, so that the instruction that instruction fetch unit transmitted of this pipeline previous stage is decoded.This decoding unit 190 is to be used to produce enough control signals to supply with this pipeline performance element in a time stage, carries out the execution operation of decoding instruction for performance element.Instruct the decoding function square 192 in this decoding unit 190 to decode.Decoded instruction and data decoding unit 190 since then transmit the performance element in time stage of pipeline so far and carry out the execution operation of decoding instruction for it.
Please refer to shown in Fig. 2 A, it is to be the block schematic diagram according to a decoding unit 250 of the present invention.The present invention discloses an extra activation (enable) control signal 257 can provide control when the data of current ordcurrent order need be upgraded.When must data for updating, this activation control signal 257 will be activated; When being in the situation that those must data for updating, 257 of this activation control signals can be closed.Always have the enable signal of three kinds of kenels: address enable signal, data enable signal and control enable signal are with difference control address bus, data bus and control signal bus.One receiving function square 251 of one decoding unit 250 is instruction and the data that are used to receive from the instruction fetch unit of pipeline architecture previous stage.The instruction that is received will be decoded in decoding function square 252.Then, the data that transmitting function square 253 is produced this decoding unit 250 are sent to the pipeline architecture group of execution units for execution in a time stage with decoding instruction, and above-mentioned activation control signal 257 will directly be sent to the output circuit of processor.
Please refer to shown in Fig. 2 B, it is for having the block schematic diagram of a plurality of switching simplified (switching reduction) unit with the processor that connects an OPADD bus, an output data bus and a control signal bus.Shown in Figure 1A, a processor has three kinds of output buss: an address bus 150, a data bus 160 and a control signal bus 170.The present invention respectively adds a switching simplified unit to reduce the switch change action of output circuit on each of above-mentioned each bus.An OPADD ADDR who is produced from a processor core 220 will be by a plurality of switching simplified unit 210-1s to 210-N of feed-in with respect to the OPADD highway width, and thus the address enable signal ADDR_EN that produced of the decoding unit 230 of processor also by the above-mentioned a plurality of switching simplified unit 210-1 to 210-N of feed-in.This decoding unit 230 becomes the operation of reading or writing with an instruction transformation, and it must control address, data and control signal.The quantity of required switching simplified unit is to decide on the width of OPADD bus, and for example one 32 OPADD bus should have 32 switching simplified unit 210-1 to 210-N (N=32).Then, in each switching simplified unit 210-1 to 210-N, carry out letter and economize the function that switch switches, and the result of all switching simplified unit 210-1 to 210-N will be combined into a final output QUIET_ADDR, and according to the destination of above-mentioned OPADD ADD R this final output will be sent to memory cell 120 or export subsystem unit 130.
In an identical manner, letter economizes action that output data DATA switch switches and also can send through a plurality of switching simplified unit 211-1 to 211-N that correspond to data-bus width and reach by export data DATA.Data actuating signal DATA_EN will control the output data DATA that sees through a plurality of switching simplified unit 211 each whether need to make amendment and economize the purpose that switch switches to reach letter.The final output data QUIET_DATA that collects from all switching simplified unit 211 will be sent to the shown memory cell 120 of Figure 1A or export subsystem unit 130.
Some control signal CONT_ROL also can utilize constructed to reduce the switch change action of final control output QUEIT_CONTROL signal.The control enable signal CONTROL_EN of from processor decoding unit 230 and a plurality of switching simplified unit 212-1 to 212-N are used for the switch change action that letter economizes control signal.Also the width of control signal bus is relevant therewith to correspond to the required switching simplified unit number N of control signal bus.
When eight of needs primary access (byte), the number of the switching simplified unit of required construction also can change thereupon.For each byte, can make single switching simplified unit in fact to open and close this eight positions simultaneously.Bus with one 32 bit width is an example, should make four switching simplified unit that allow eight of keyings in fact with independent each byte of control.In view of the above, on a bus the number of the real switching simplified unit of doing also correspond to the width of this bus, the byte number of this bus, also or any required figure place at random.
Please refer to shown in Figure 3, its be in the microprocessor about a block schematic diagram of a plurality of switching simplified unit of an output data bus.Data output bus DATA with one 32 is an example, should make 32 switching simplified unit 311 to 31M in fact shown in Fig. 2 B.Yet above-mentioned 32 switching simplified unit 311 to 31M can be divided into four groups, first group 311 be correspond to first byte everybody, second group 312 be correspond to second byte everybody, the 3rd group 313 be to correspond to everybody of the 3rd byte, and the 4th group of 31M (314) corresponds to everybody of nybble.Also can be the single signal that Fig. 2 B marks by coding unit 330 generations with the data actuating signal DATA_EN that controls above-mentioned 32 switching simplified unit 311 to 31M, maybe can be divided into signal four times, BYTE_1_EN, BYTE_2_EN, BYTE_3_EN and BYTE_M_EN (BYTE_4_EN) are to control four bytes of output data DATA respectively.Single data enable signal DATA_EN is divided into M byte data control signal BYTE_M_EN to have and only need open the byte of necessary change and make the impregnable advantage of other byte.Only suppose must access one bus first byte, each switching simplified unit that only needs activation BYTE_1_EN signal to be correlated with, and can close BYTE_2_EN, BYTE_3_EN and BYTE_4_EN relevant each switching simplified unit.In in the case, single data enable signal DATA_EN is cut into a plurality of signals can saves some electric power with the keying of control individual byte.For data bus with other width, the quantity M of byte data control signal can according to and adjust, be used to control a byte to make a byte data control signal BYTE_M_EN.In view of the above, each byte can be opened and closed independently to minimize exports the switch switching times, and then uses small electric power in a computer system.Though what mark in Fig. 3 is a data output bus, also can in an address out bus and a control signal bus, use constructedly separating enable signal, and then open those bytes that must change and make all the other positions remain unchanged.
Please refer to shown in Figure 4, its be in the microprocessor about a block schematic diagram of a plurality of switching simplified unit of an output data bus.In this figure, each switching simplified unit 411 to 41M is corresponding each byte of data bus DATA so far.Obviously, digital M is the whole byte quantity that are equal to this data bus.Enable signal from decoding unit 430 also is divided into M time signal according to the byte quantity of data bus, that is BYTE_1_EN to BYTE_M_EN.In the enforcement example of this one 32 bit data bus, have 411,412,413 and 414 and four activation data of four switching simplified unit time signal BYTE_1_EN, BYTE_2_EN, BYTE_3_EN and BYTE_4_EN.The data bus that has illustrated through Fig. 4 is an example, and same notion is applicable to address bus ADDR and control signal bus CONTROL.Fig. 4 is that than the superior part of Fig. 3 Fig. 4 only must the eighth switching simplified unit of Fig. 3, and it can reduce many logical circuits significantly.
In another embodiment shown in Figure 5, switching simplified unit 510 to 512 can be positioned at outside the processor 530.The output of this processor 530 comprises an OPADD ADDR, an output data DATA and an output control signal CONTROL usually.Each of above-mentioned address/data/control signal all can be sent to the switching simplified unit 511 to 512 that is positioned at these processor 530 outsides is economized output circuit with letter switching.The decoding circuit unit 540 of this processor 530 also provides enable signal.Also can be applicable to the situation that Fig. 2, Fig. 3 and that class of Fig. 4 place switching simplified unit processor inside in outside these notions that add switching simplified unit 510 to 512 of processor 530.
Five embodiment of switching simplified unit structure will be respectively at disclosing among Fig. 6, Fig. 7, Fig. 8, Fig. 9 and Figure 10.Disclosed preceding four embodiment of Fig. 6 to Fig. 9 have disclosed and have set the first method that invalid output valve is a default value, and embodiment shown in Figure 10 then discloses the second method that invalid output valve is left preceding value.Please refer to shown in Figure 6ly, it is the block schematic diagram for the switching simplified unit 600 of one first embodiment according to the present invention.This switching simplified unit 600 comprises single and door 610.When an original output signal OUTPUT of a processor and an activation signal ENABLE import this simultaneously with door 610, how the enable signal ENABLE of from processor decoding unit will change the above-mentioned original output signal OUTPUT of may command into a final output signal QUIET_OUTPUT.When enable signal ENABLE when opening, this will make above-mentioned original output signal OUTPUT at all unchangeably by this and door 610 with door 610.Otherwise, when enable signal ENABLE when closing, above-mentioned original output signal OUTPUT will be set to a default value 0 to reduce the number of times that output is switched.It should be noted that above-mentioned original output signal OUTPUT can be an address, a data, or a control signal; Similarly, above-mentioned final output signal QUIET_OUTPUT also can be respectively a final address, a final data, or a final control signal.
The operation situation shown in Fig. 6 calcspar that please notes is only for meeting one of numerous embodiment of the scope of the invention and spirit.Utilize one with door 610 only for reducing a kind of mode of may doing in fact of output switching times, the combination that also can use other kind logical block or logical block is to reach same function and purpose.For instance, can utilize a series of and door to replace single and door.When enable signal when closing, a series ofly output valve is set at a default value with Men Yineng.Another practice is two outputs of a rejection gate (NOR) of reversing simultaneously, its function also be equivalent to one with door.Be familiar with this operator can derive easily other kind logic circuit unit with reach above-mentioned when enable signal be to close the identical function that seasonal output valve is a default value.Reduce the output switching times and can reduce the total consumed power of a processor, and prolong the battery service time of an electronic installation.
Fig. 7 mark one or the door 710 also can be used for reaching when enable signal be to close the function that seasonal output valve is a default value.When an activation signal ENABLE was unlatching, an original output signal OUTPUT can become a final output signal QUIET_OUTPUT by this and door 610.One truth table can show easily when this activation signal ENABLE when closing, this final output signal QUIET_OUTPUT can be set to a default value 1, but not uses a default value 0 during with door.Because when this activation signal ENABLE is that final output signal QUIET_OUTPUT when closing can be left in the basket and disregards, so it is set at 0 or 1 is inessential.
The multiplexer 810 that Fig. 8 marks also can be used as another embodiment of the present invention.One first input of this multiplexer 810 is to be used to receive an original output signal OUTPUT, and one second input is to be connected to a stationary value, as 0 or 1.One selection signal ENABLE is the switching that is used to control output.When this selected signal ENABLE for unlatching, above-mentioned original output signal OUTPUT will and become a final output signal QUIET_OUTPUT by this multiplexer 810.Otherwise a selection signal ENABLE who closes will stop above-mentioned original output signal OUTPUT by this multiplexer 810, and makes above-mentioned second input value become final output signal QUIET_OUTPUT.
Please refer to shown in Figure 9ly, it is to be a synoptic diagram of switching simplified unit according to another embodiment of the present invention.When one selected signal ENABLE for unlatching, a transparent door bolt (latch) 910 can allow an original output signal OUTPUT by becoming a final output signal QUIET_OUTPUT.Otherwise a selection signal ENABLE who closes will stop above-mentioned original output signal OUTPUT to pass through, so final output signal QUIET_OUTPUT will be set as a default value.
Figure 10 marks the 5th embodiment of switching simplified unit structure.This switching simplified unit 100 comprises a multiplexer 102, and it has one first input value to receive the feedback signal that produced from the output of above-mentioned multiplexer 102 and by a flip-flop 101 and one second input value to receive an original output signal OUTPUT.Similarly, above-mentioned original output signal OUTPUT can be an address, a data, or a control signal.One of from processor decoding unit selects this multiplexer 102 of signal ENABLE feed-in to switch with control output.The final output valve of this switching simplified unit 100 is called as a final output signal QUIET_OUTPUT, and it can represent a final address, a final data, or a final control signal.Select signal ENABLE when closing when this, this switching simplified unit 100 is carried out the action of these original output signal OUTPUT of reservation.Yet when this selected signal ENABLE for unlatching, original output signal OUTPUT will be by switching simplified unit 100 to form above-mentioned final output signal QUIET_OUTPUT.Utilizing the combination of other logic circuit unit or logical block to replace above-mentioned flip-flop 101 and multiplexer 102 is the function that keeps this original output signal OUTPUT when closing to reach when selecting signal ENABLE, is that scope according to the invention is with spiritual.
Please refer to shown in Figure 11ly, it is to be the synoptic diagram of making of being disclosed of first to fourth embodiment according to the present invention first method that output valve is made as a default value with the output switching times that reduces by a continuous output tape sorting A1-A7.But each output valve A1-A7 representative graph 2B, Fig. 3 and a position shown in Figure 4, a byte or other any figure place.One activation signal (ENABLE) and an original output signal (OUTPUT) marked by feed-in Fig. 6 with door 610 in.When this activation signal when opening, with door 610 allow above-mentioned original output signal by and become final output signal QUIET_OUTPUT.Can be such as signals such as A1, A2, A4 and A5 unchangeably by becoming final output signal.In on the other hand, when this activation signal when closing, as A3, A6 and A7 signal, final output signal promptly is set as default value 0.The default value of output can be set at 0 or 1 in advance.When original output signal A1-A7, in a continuous output tape sorting, can produce six switchings.The advantage that the present invention produced can be to see the continuous output when closing from having two enable signals at least.For example because the enable signal when A6 and A7 signal is all closes, so the time final output signal be all 0 and save the change action of script between A6 and A7 signal.The switching simplified unit that first to fourth embodiment according to the present invention is disclosed, total switching times becomes five times from six times.If each position of original output signal representative shown in Figure 11 because A6 and A7 signal can be made as 0, is then made Fig. 6 in fact and will be had the advantage that reduces by a switching to switching simplified unit shown in Figure 9.Yet if byte of each original output signal representative, the switching between letter province A6 and A7 signal can be saved the switching of a byte effectively.Apparently, the time that enable signal is closed is of a specified duration more, then can letter economize more repeatedly switching and save more electric power according to this.
Please refer to shown in Figure 12ly, it is for being that the second method of a preceding value is to reduce a synoptic diagram of output switching times according to the invalid output valve of reservation that fifth embodiment of the invention disclosed.The letter province switching times that the second method of utilizing first method that identical A1-A7 that Figure 11 marks and enable signal disclose with first to fourth embodiment relatively and the 5th embodiment to disclose is reached.Please refer to the 5th embodiment shown in Figure 10, original output signal (OUTPUT) and enable signal (ENABLE) are the input values of switching simplified unit 100 for this reason, and the function of switching simplified thus the flip-flop 101 of switching simplified unit 100 inside carry out with multiplexer 102.Moreover the final output valve of this switching simplified unit 100 is called as a final output signal QUIET_OUTPUT.For the original output signal that those enable signals are opening, signals such as the A1 that goes out as shown in figure 12, A2, A4 and A5, it can be unchangeably by this switching simplified unit 100 as preceding four embodiment.When enable signal is closed condition, the preceding value that flip-flop 101 in this switching simplified unit 100 and multiplexer 102 will keep input.Lifting the A3 signal is example, and A3 will keep its preceding value, that is the A2 value in the present embodiment.Apparently, but keep preceding value with the switching between cancellation A2 and A3 signal.The A3 signal of Figure 11 and Figure 12 relatively, the first kind of mode that output is made as default value that Figure 11 adopts switch output valve from-effective value to lock control value (A 2 values transfer 0 to), switch to a time effective value (that is transfer A4 value by 0) again; Yet the second method of the reservation preceding value that Figure 12 adopts only begins to switch (directly transferring the A4 value to by the A2 value) when a new effective value occurs.Similarly, A6 will keep the preceding value of A5, and A7 also together.If the final output signal the during A5 to A7 of comparison Figure 11 and Figure 12 has a change action (A5 to A6) among Figure 11, Figure 12 is then without any change action.And the second method that Figure 12 marks has successfully been eliminated the change action between A5 to A6, and then more saves the power consumption of processor.The final output signal of Figure 11 and Figure 12 relatively, Figure 11 has change action altogether five times, and Figure 12 only must three times.When the yardstick of considering output bus or the loading level of bus, it is appreciable can understanding the electric power of being saved.Though real the 5th embodiment of work needs two logic circuit units, that is a flip-flop 101 and a multiplexer 102, yet its quantity of reduce switching obviously than first embodiment with door 610 or second and third, four embodiment's or door 710, multiplexer 810 and door bolt 910 many.
The advantage that increase enable signal quantity is obtained can be learnt in the comparison of Figure 13 and Figure 14 easily.Please refer to shown in Figure 13ly, it is for utilizing an activation signal to economize a synoptic diagram of output switching times with letter in a bus of nybble degree.Please look back Fig. 2, each bus has an activation signal, and the quantity of its switching simplified unit is to correspond to the byte number of highway width to reduce the number of times that output is switched.For making things convenient for the event of icon, what Figure 13 considered is a bus with nybble width.The original output signal of this nybble width bus is that unit represents with eight, and as AnBnCnDn, n can be arbitrary integer.Single enable signal controlled the output of these four bytes with the pattern of completely open and close.For example when this activation signal was unlatching, all four byte A1B1C1D1 will be output as A1B1C1D1.Otherwise when this activation signal is when closing and adopts the method that keeps preceding value, during as A4B4C4D4, then previous A3B3C3D3 value will be left final output valve.
Please refer to shown in Figure 14ly, it is for utilizing four enable signals to economize a synoptic diagram of output switching times with letter in a bus of nybble width.The processor structure of supporting wave mode shown in Figure 14 is to be processor shown in Figure 4.The quantity of switching simplified unit and enable signal all corresponds to the byte number of highway width to reduce the number of times that output is switched.Bus with four byte wides will have independently enable signal of four switching simplified unit and four, and each all controls the output signal of eight positions.Because most bus access action is for 8,16 and 32, so above-mentioned enable signal can be opened 1,2 or 4 positions respectively.When opening four enable signals, A1B1C1D1 for example, then four bytes all will be exported unchangeably.When A2B2C2D2 only opened single enable signal 0001, then three bytes promptly were left preceding value and last byte will be changed into new value, and its final output signal is with A1B1C1D2.When the situation that changes two bytes can be observed A3B3C3D3 and A5B5C5D5.See through the enable signal of disassembling control bus and further reduce the number of times that output is switched with finer and smoother ground.Compare the switching times of this two figure, the Figure 13 with single enable signal has intactly switched three times; Figure 14 with multiple enable signal then partly switches (switched 1/4th during A2B2C2D2, respectively switched half when A3B3C3D3 and A5B5C5D5) three times.Reduced to promptly 40 of (0.25+0.5+0.5) * 32 so the switching times of saving is 96 from 3 * 32, simple province ratio reaches 58.5%.
Please refer to shown in Figure 15ly, it is the flow process synoptic diagram for the switching simplified unit function mode.Carry out step 151 after flow process begins, an output signal of a processor and an activation signal are received by each switching simplified unit.In an inferior step 152, whether judgement is unlatching corresponding to the enable signal of the carry-out bit/byte signal of the address/data/control of exporting at present.If this activation signal really for opening, then carries out step 153 and makes above-mentioned output signal become final output signal by switching simplified unit unchangeably.Otherwise if this activation signal is a closed condition, then flow process is carried out step 154 to carry out two kinds of methods that letter provided by the present invention economizes the output switching times.First method is to be made as a default value as Fig. 6 enable signal of working as extremely shown in Figure 9 for closing seasonal output valve.Second method be as shown in figure 10 be preceding value when enable signal keeps output valve when closing.Above-mentioned two kinds of methods all can reduce the number of times that output is switched effectively.Then in an inferior step 155, judge whether the carry-out bit/byte signal of present address/data/control is the ending of OPADD/data/control signal.If not so, then each carry-out bit/byte signal of remaining address/data/control all will experience the flow process of step 152 to 155, till OPADD/data end.Moreover, if arrived the ending of OPADD/data/control signal, then will be shown in step 156, switching simplified unit will continue to wait for the arrival of next OPADD/data/control signal.When inferior one OPADD/data/control signal arrives, whole circulation will return step 151.Equally again, each carry-out bit/byte signal of a full address/data/control signal all will experience the flow process of step 151 to 155 again, economize the output switching times and and then will reduce power consumption and improve system consumption with letter.
Aforesaid embodiment be see through one with door/or door/multiplexer/door bolt to make output valve be made as a default value or see through a flip-flop and a multiplexer be that the mode of a preceding value is exported switching times with letter province with the reservation output valve to reach.Please note the atypical circuit that also can make other scope according to the invention and spirit in fact.For example wait the combination of other logic circuit unit or logic circuit unit also can make output valve be made as a default value with door with a series of.Similarly, above-mentioned flip-flop and multiplexer also can be replaced by the combination of other equivalent logic circuit unit or logic circuit unit.In the present invention, the content in Fig. 6 to embodiment shown in Figure 10 and this instructions is only as the demonstration of certain benefits, and it can be by being used for reaching for making of switching simplified unit in the various embodiments of the present invention.
Apparently, according to the description among the top embodiment, the present invention has many corrections and difference.Therefore need be understood in the scope of its additional claim item, except above-mentioned detailed description, the present invention can also implement widely in other embodiments.Above-mentioned is preferred embodiment of the present invention only, is not in order to limit claim of the present invention; All other do not break away from the equivalence of being finished under the disclosed spirit and changes or modification, all should be included in the following claim.
Claims (19)
1. a processor system is characterized in that, comprises:
One processor core is present in processor inside to execute instruction and to produce original output signal; And
At least one switching simplified unit is to connect at least one original output signal of this processor, each this switching simplified unit receives an activation signal and this original output signal, each this switching simplified unit comprise at least one logic circuit unit with when this enable signal for close season this original output signal be a default value or be left a preceding value and when this enable signal serve as to open season this original output signal to pass through this switching simplified unit, produce a final output signal in view of the above with this original output signal of replacement.
2. according to the processor system of claim 1, it is characterized in that, wherein above-mentioned switching simplified unit is to be used for each byte output signal channel and this enable signal is to be used to control each other byte output signal channel independently, to work as this enable signal is that each byte output signal of closing seasonal this original output signal is a default value or is left a preceding value, and works as this enable signal and pass through this switching simplified unit for each byte output signal of opening seasonal this original output signal.
3. according to the processor system of claim 1, it is characterized in that each wherein above-mentioned switching simplified unit is to comprise following may the variation:
Control each;
Control each byte; And
Control is a position arbitrarily.
4. according to the processor system of claim 2, it is characterized in that wherein above-mentioned enable signal is to be divided into a plurality of signals to control each byte signaling channel independently.
5. according to the processor system of claim 1, it is characterized in that wherein above-mentioned original output signal is to comprise following may the variation:
One address;
One data; And
One control signal.
6. according to the processor system of claim 1, it is characterized in that wherein above-mentioned enable signal is to comprise following may the variation:
One address enable signal;
One data enable signal; And
The enable signal of one control signal.
7. according to the processor system of claim 1, it is characterized in that wherein above-mentioned switching simplified unit still comprises following may the variation:
One with door with when this enable signal for close season this original output signal be a default value and when this enable signal serve as to open seasonal this original output signal to pass through this switching simplified unit;
One or door with when this enable signal for close season this original output signal be a default value and when this enable signal serve as to open seasonal this original output signal to pass through this switching simplified unit;
One multiplexer with when this enable signal for close season this original output signal be a default value and when this enable signal serve as to open seasonal this original output signal to pass through this switching simplified unit; And
One door bolt with when this enable signal for close season this original output signal be a default value and when this enable signal serve as to open seasonal this original output signal to pass through this switching simplified unit.
8. according to the processor system of claim 1, it is characterized in that wherein above-mentioned switching simplified unit comprises:
One flip-flop; And
One multiplexer, this multiplexer comprise one first input signal from the output of this multiplexer and via this flip-flop receive a feedback signal, one second input signal selects signal to receive this enable signal to receive this original output signal and, be left a preceding value and pass through this switching simplified unit for seasonal this original output signal of unlatching when this enable signal for closing season this original output signal when this enable signal in view of the above.
9. according to the processor system of claim 1, it is characterized in that wherein above-mentioned switching simplified unit can be positioned at the inside or the outside of this processor.
10. a processor system is characterized in that, comprises:
One processor core is present in processor inside to execute instruction and to produce original output signal, and this processor core also comprises a decoding unit to produce an activation signal; And
At least one switching simplified unit is to connect at least one original output signal of this processor, each this switching simplified unit receives an activation signal and this original output signal, each this switching simplified unit comprise at least one logic circuit unit with when this enable signal for close season this original output signal be a default value or be left a preceding value and when this enable signal serve as to open season this original output signal to pass through this switching simplified unit, produce a final output signal in view of the above with this original output signal of replacement.
11. the processor system according to claim 10 is characterized in that, wherein above-mentioned decoding unit is decoded to produce this enable signal and decoding instruction to receiving instruction.
12. the processor system according to claim 10 is characterized in that, wherein above-mentioned this enable signal that decoding unit produced is to be used for judging whether this original output signal needs renewal.
13. the processor system according to claim 10 is characterized in that, each wherein above-mentioned switching simplified unit comprises control the following of one bus and may change:
Control each;
Control each byte; And
Control is a position arbitrarily.
14. the processor system according to claim 10 is characterized in that wherein above-mentioned enable signal is to be divided into a plurality of signals to control each byte signaling channel independently.
15. the processor system according to claim 10 is characterized in that wherein above-mentioned switching simplified unit still comprises following may the variation:
One with door with when this enable signal for close season this original output signal be a default value and when this enable signal serve as to open seasonal this original output signal to pass through this switching simplified unit;
One or door with when this enable signal for close season this original output signal be a default value and when this enable signal serve as to open seasonal this original output signal to pass through this switching simplified unit;
One multiplexer with when this enable signal for close season this original output signal be a default value and when this enable signal serve as to open seasonal this original output signal to pass through this switching simplified unit; And
One door bolt with when this enable signal for close season this original output signal be a default value and when this enable signal serve as to open seasonal this original output signal to pass through this switching simplified unit.
16. the processor system according to claim 10 is characterized in that wherein above-mentioned switching simplified unit comprises:
One flip-flop; And
One multiplexer, this multiplexer comprise one first input signal from the output of this multiplexer and via this flip-flop receive a feedback signal, one second input signal selects signal to receive this enable signal to receive this original output signal and, be left a preceding value and pass through this switching simplified unit for seasonal this original output signal of unlatching when this enable signal for closing season this original output signal when this enable signal in view of the above.
17. a method of saving power consumption of treater is characterized in that, comprises:
Receive an original output signal and an activation signal;
Judge whether this enable signal is opened;
When this enable signal when opening, make that this original output signal is a final output signal; And
When this enable signal when closing, to make this original output signal be default value or be left a preceding value.
18. the method according to the saving power consumption of treater of claim 17 is characterized in that wherein above-mentioned original output signal is to comprise following may the variation:
With one is unit;
With a byte is unit; And
With any position is unit.
19. the method according to the saving power consumption of treater of claim 17 is characterized in that, wherein also comprises:
Cutting apart this enable signal is that a plurality of signals are to control each byte signaling channel independently.
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| US67068105P | 2005-04-13 | 2005-04-13 | |
| US60/670,681 | 2005-04-13 |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2016000174A1 (en) * | 2014-06-30 | 2016-01-07 | 华为技术有限公司 | Power consumption management method, power consumption management device, and processor |
| CN107093459A (en) * | 2010-11-15 | 2017-08-25 | 三星电子株式会社 | Non-volatile memory devices and its read method and accumulator system |
-
2006
- 2006-04-12 TW TW95112948A patent/TWI324299B/en active
- 2006-04-12 CN CNB2006100735041A patent/CN100527048C/en active Active
Cited By (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107093459A (en) * | 2010-11-15 | 2017-08-25 | 三星电子株式会社 | Non-volatile memory devices and its read method and accumulator system |
| USRE48013E1 (en) | 2010-11-15 | 2020-05-26 | Samsung Electronics Co., Ltd. | Nonvolatile memory device, read method for nonvolatile memory device, and memory system incorporating nonvolatile memory device |
| USRE48431E1 (en) | 2010-11-15 | 2021-02-09 | Samsung Electronics Co., Ltd. | Nonvolatile memory device, read method for nonvolatile memory device, and memory system incorporating nonvolatile memory device |
| CN107093459B (en) * | 2010-11-15 | 2021-07-30 | 三星电子株式会社 | Nonvolatile memory device, reading method thereof, and memory system |
| USRE49145E1 (en) | 2010-11-15 | 2022-07-19 | Samsung Electronics Co., Ltd. | Nonvolatile memory device, read method for nonvolatile memory device, and memory system incorporating nonvolatile memory device |
| WO2016000174A1 (en) * | 2014-06-30 | 2016-01-07 | 华为技术有限公司 | Power consumption management method, power consumption management device, and processor |
| CN105393188A (en) * | 2014-06-30 | 2016-03-09 | 华为技术有限公司 | Power consumption management method, power consumption management device, and processor |
| CN105393188B (en) * | 2014-06-30 | 2019-01-18 | 华为技术有限公司 | A kind of power consumption management method, power consumption managing device and processor |
Also Published As
| Publication number | Publication date |
|---|---|
| TWI324299B (en) | 2010-05-01 |
| CN100527048C (en) | 2009-08-12 |
| TW200636440A (en) | 2006-10-16 |
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