CN1822327A - Method of processing and cleaning substrate, and method of and program for manufacturing electronic device - Google Patents

Method of processing and cleaning substrate, and method of and program for manufacturing electronic device Download PDF

Info

Publication number
CN1822327A
CN1822327A CN 200610007478 CN200610007478A CN1822327A CN 1822327 A CN1822327 A CN 1822327A CN 200610007478 CN200610007478 CN 200610007478 CN 200610007478 A CN200610007478 A CN 200610007478A CN 1822327 A CN1822327 A CN 1822327A
Authority
CN
China
Prior art keywords
insulating film
forming
exposed
mixed gas
chemical mechanical
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
CN 200610007478
Other languages
Chinese (zh)
Other versions
CN100449709C (en
Inventor
西村荣一
岩﨑贤也
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Tokyo Electron Ltd
Original Assignee
Tokyo Electron Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Tokyo Electron Ltd filed Critical Tokyo Electron Ltd
Publication of CN1822327A publication Critical patent/CN1822327A/en
Application granted granted Critical
Publication of CN100449709C publication Critical patent/CN100449709C/en
Expired - Fee Related legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Landscapes

  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Cleaning Or Drying Semiconductors (AREA)

Abstract

A method of processing a substrate which enables a surface damaged layer and polishing remnants on the surface of an insulating film to be removed, and enable the amount removed of the surface damaged layer and polishing remnants to be controlled easily. An insulating film on a substrate, which has been revealed by chemical mechanical polishing, is exposed to an atmosphere of a mixed gas containing ammonia and hydrogen fluoride under a predetermined pressure. The insulating film which has been exposed to the atmosphere of the mixed gas is heated to a predetermined temperature.

Description

Substrate processing method, cleaning method, method for manufacturing electronic device, and program
Technical Field
The present invention relates to a substrate processing method, a cleaning method after chemical mechanical polishing, a manufacturing method of an electronic device, and a program; in particular, the present invention relates to a method for manufacturing an electronic device, in which a conductive film formed on a surface is polished by chemical mechanical polishing and then plasma-free etching (plasma-free etching) is performed to improve surface flatness.
Background
In a method for manufacturing an electronic device composed of a silicon wafer (hereinafter simply referred to as "wafer"), a photolithography step of forming a photoresist layer of a desired pattern on an insulating film formed on a surface of the wafer is sequentially repeated; an etching step of forming a conductive film on the gate electrode or forming a wiring groove or a contact hole on the insulating film by using the photoresist layer as a mask; a film formation step such as PVD (Physical Vapor Deposition) for forming a conductive film on the surface of the insulating film on which the wiring groove or the contact hole is formed; and a planarization step (etching step) of removing the formed conductive film to expose the insulating film and planarizing the exposed surface of the insulating film.
In recent years, in the planarization step, a surface Polishing method of a wafer called CMP (chemical mechanical Polishing) is used instead of the dry etching or thermal reflow used in the past. In the CMP, as shown in fig. 11, a wafer is pressed against a turntable 201 to which a polishing cloth 200 made of polyurethane or the like is attached by a head (wafer holding part) 202, the surface of the wafer is brought into close contact with the polishing cloth 200, and silicon dioxide (SiO) is supplied from a slurry supply nozzle 203 to the polishing cloth 2002) A method of polishing the surface of the wafer by rotating the turntable 201 and the head 202 independently of each other while supplying the cleaning liquid with a polishing agent (slurry) as a main component. It is considered that SiO in the polishing slurry is utilized in CMP2Physical contact of particles with a conductive film or insulating film on the surface of a wafer, and SiO2Polishing is promoted by a synergistic effect of a chemical reaction between the particles and the conductive film or the insulating film (see, for example, patent document 1).
In recent years, in order to prevent a decrease in signal transmission speed due to a high dielectric constant of an interlayer insulating film exposed by miniaturization of wiring rules (required dimensions) of electronic devices, a material having a Low relative dielectric constant (Low- κ) has been used as an interlayer insulating film material (see table 1). In particular, recently, since copper is often used as a wiring material, an SiOC-based low dielectric constant material doped with carbon is used as a low dielectric constant interlayer insulating film material. In addition, there is a study on using a porous material having a lower dielectric constant. Here, a relative dielectric constant of 3.0 or less is referred to as a low dielectric constant.
TABLE 1
However, on the surface of the insulating film exposed by CMP, there are generated SiO and SiO residues (shavings) of the insulating film, which are generated by corrosion (erosion due to polishing) of the insulating film on the wiring due to the difference in polishing characteristics of the insulating film with respect to the density of the wiring pattern under the insulating film2Reaction products of the particles and the constituent material of the insulating film.
Further, the interlayer insulating film made of a porous material layer has a low mechanical strength due to a plurality of holes in the film, and the conductive film has a low adhesiveness, and peeling of the interlayer insulating film from the conductive film or disintegration of the interlayer insulating film occurs when the wafer is pressed by the head 202 with a normal pressure in CMP. In contrast, when a porous material is used as an interlayer insulating film material, it is necessary to press the wafer at a low pressure, for example, a pressure of about 1.0KPa or less, but since the interlayer insulating film cannot be sufficiently polished by low-pressure CMP, a cutting residue is generated on the surface of the interlayer insulating film polished by CMP.
The residue, reaction product and cutting residue (hereinafter, simply referred to as "cutting residue and the like") on the surface of the insulating film are factors causing abnormality in wiring resistance of an electronic device manufactured from a wafer or interlayer capacitance of a capacitor of the electronic device, and therefore must be removed.
Further, when a conductive film formed on an insulating film having a low dielectric constant is polished by CMP, the low dielectric interlayer insulating film is chemically damaged by moisture absorption of the low dielectric interlayer insulating film due to contact between the exposed surface of the low dielectric interlayer insulating film and a slurry or a cleaning liquid used in CMP, and thus a surface damaged layer (damaged layer) having a reduced carbon concentration is formed on the surface of the low dielectric interlayer insulating film.
Since the surface damage layer has the same structure as SiO2Since the similar characteristics of the natural Oxide (Native Oxide) are a factor of causing volume shrinkage and generating voids (void) in the insulating film in the heat treatment step performed as the subsequent step, it is necessary to remove the surface damaged layer in advance before performing the subsequent step.
As a step of removing a surface damaged layer, a cutting residue, and the like on the surface of the insulating film, a cleaning step of cleaning the surface of the insulating film with a Post-CMP (Post-CMP) cleaning liquid made of quaternary ammonium hydroxide, polar organic amine, or the like is known.
However, the cleaning step corresponds to a wet etching step using a chemical solution, and the cleaning solution is likely to dissolve the surface damaged layer, the cutting residue, and the like in the cleaning step, and thus there is a problem that it is difficult to control the amount of removal of the surface damaged layer, the cutting residue, and the like. When the cleaning solution excessively dissolves the surface damaged layer, the cutting residue, or the like, the Cu wiring disposed under the insulating film is exposed, and the cleaning solution corrodes (corroded) the Cu wiring.
[ patent document 1 ] Japanese patent application laid-open No. 9-251969
Disclosure of Invention
The invention provides a substrate processing method, a cleaning method after chemical mechanical polishing, a method for manufacturing an electronic device, and a program, which can remove a surface damage layer, a cutting residue, and the like on the surface of an insulating film and can easily control the removal amount of the surface damage layer, the cutting residue, and the like.
In order to achieve the above object, a substrate processing method according to a first aspect of the present invention is a substrate processing method for processing a substrate having an insulating film exposed by chemical mechanical polishing, the substrate processing method including:
an insulating film exposing step of exposing the exposed insulating film to an atmosphere of a mixed gas containing ammonia and hydrogen fluoride under a predetermined pressure; and
and an insulating film heating step of heating the insulating film exposed to the mixed gas atmosphere to a predetermined temperature.
A substrate processing method according to a second aspect of the present invention is the substrate processing method according to the first aspect of the present invention, wherein the exposed insulating film is a low dielectric constant insulating film.
A substrate processing method according to a third aspect of the present invention is the substrate processing method according to the first or second aspect of the present invention, wherein the plasma-free etching treatment is performed on the substrate in the insulating film exposing step.
A substrate processing method according to a fourth aspect of the present invention is the substrate processing method according to the first or second aspect, wherein in the insulating film exposing step, a dry cleaning process is performed on the substrate.
A fifth aspect of the present invention is the substrate processing method according to any one of the first to fourth aspects of the present invention, wherein a volume flow rate ratio of the hydrogen fluoride to the ammonia in the mixed gas is 1to 1/2, and the predetermined pressure is 6.7 × 10-2～4.0Pa。
A substrate processing method according to a sixth aspect of the present invention is the substrate processing method according to any one of the first to fifth aspects, wherein the predetermined temperature is 80 to 200 ℃.
A substrate processing method according to a seventh aspect of the present invention is the substrate processing method according to any one of the first to sixth aspects, further comprising a product formation condition determining step of measuring a shape of the exposed insulating film and determining at least one of a volume flow rate ratio of the hydrogen fluoride to the ammonia in the mixed gas and the predetermined pressure based on the measured shape.
A processing method according to an eighth aspect of the present invention is the substrate processing method according to any one of the first to seventh aspects, wherein the exposed insulating film has a cutting residue caused by the chemical mechanical polishing.
A substrate processing method according to a ninth aspect of the present invention is the substrate processing method according to any one of the first to seventh aspects, wherein the exposed insulating film has a reaction product caused by a polishing agent used for the chemical mechanical polishing.
A substrate processing method according to a tenth aspect of the present invention is the substrate processing method according to any one of the first to seventh aspects, characterized in that: the insulating film has a surface damage layer with a reduced carbon concentration.
In order to achieve the above object, according to an eleventh aspect of the present invention, there is provided a method for cleaning a substrate after chemical mechanical polishing, the method comprising the steps of polishing a conductive film formed on an insulating film formed on a surface of the substrate by chemical mechanical polishing, and then applying the conductive film to the substrate, the method comprising:
an insulating film exposing step of exposing the insulating film exposed by the chemical mechanical polishing to an atmosphere of a mixed gas containing ammonia and hydrogen fluoride under a predetermined pressure; and
and an insulating film heating step of heating the insulating film exposed to the mixed gas atmosphere to a predetermined temperature.
A method for cleaning after chemical mechanical polishing according to a twelfth aspect of the present invention is the method for cleaning after chemical mechanical polishing according to the eleventh aspect, further comprising an insulating film drying step of drying a surface of the exposed insulating film before exposing the exposed insulating film to the mixed gas atmosphere.
In order to achieve the above object, a method for manufacturing an electronic device according to a thirteenth aspect of the present invention includes:
a wiring forming step of forming a wiring made of a first conductive material on a first insulating film formed on a surface of a semiconductor substrate;
a second insulating film forming step of forming a second insulating film on the first insulating film so as to cover the wiring;
a photoresist layer forming step of forming a photoresist layer of a predetermined pattern on the formed second insulating film;
a plasma processing step of processing a connection hole reaching the wiring on the second insulating film by plasma processing using the formed photoresist layer;
an ashing step of removing the photoresist layer;
a connection hole filling step of forming a conductive film made of a second conductive material on the second insulating film and filling the second conductive material in the connection hole;
a conductive film polishing step of polishing the formed conductive film by chemical mechanical polishing;
a second insulating film exposing step of exposing the second insulating film exposed by the chemical mechanical polishing to a mixed gas atmosphere containing ammonia and hydrogen fluoride under a predetermined pressure; and
a second insulating film heating step of heating the second insulating film exposed to the mixed gas atmosphere to a predetermined temperature.
A method for manufacturing an electronic device according to a fourteenth aspect of the present invention is the method for manufacturing an electronic device according to the thirteenth aspect, wherein:
a connecting hole surface exposure step of exposing the surface of the processing-formed connecting hole to a mixed gas atmosphere containing ammonia and hydrogen fluoride under a predetermined pressure; and
and a connecting hole surface heating step of heating the surface of the connecting hole exposed to the mixed gas atmosphere to a predetermined temperature.
A method for manufacturing an electronic device according to a fifteenth aspect of the present invention is the method for manufacturing an electronic device according to the fourteenth aspect, further comprising a connection hole covering step of covering a surface of the connection hole heated to the predetermined temperature with a conductive barrier.
In order to achieve the above object, a sixteenth aspect of the present invention provides a method of manufacturing an electronic device, comprising:
a wiring forming step of forming a wiring made of a first conductive material on a first insulating film formed on a surface of a semiconductor substrate;
a second insulating film forming step of forming a second insulating film on the first insulating film so as to cover the wiring;
a photoresist layer forming step of forming a photoresist layer of a predetermined pattern on the formed second insulating film;
a plasma processing step of processing a connection hole reaching the wiring on the second insulating film by plasma processing using the formed photoresist layer;
a connection hole filling step of forming a conductive film made of a second conductive material on the second insulating film and filling the second conductive material in the connection hole;
a conductive film polishing step of polishing the photoresist layer and the formed conductive film by chemical mechanical polishing;
a second insulating film exposing step of exposing the second insulating film exposed by the chemical mechanical polishing to a mixed gas atmosphere containing ammonia and hydrogen fluoride under a predetermined pressure; and
a second insulating film heating step of heating the second insulating film exposed to the mixed gas atmosphere to a predetermined temperature.
In order to achieve the above object, a seventeenth aspect of the present invention is a program for running a method of processing a substrate having an insulating film exposed by chemical mechanical polishing in a computer, the program comprising:
an insulating film exposing module for exposing the exposed insulating film to a mixed gas atmosphere containing ammonia and hydrogen fluoride under a predetermined pressure; and
and an insulating film heating module for heating the insulating film exposed to the mixed gas atmosphere to a predetermined temperature.
In order to achieve the above object, an eighteenth aspect of the present invention provides a program for causing a computer to execute a method of cleaning a substrate after chemical mechanical polishing after polishing a conductive film formed on an insulating film formed on a surface of the substrate by chemical mechanical polishing, the method comprising:
an insulating film exposing module for exposing the insulating film exposed by the chemical mechanical polishing to an atmosphere of a mixed gas containing ammonia and hydrogen fluoride under a predetermined pressure; and
and an insulating film heating module for heating the insulating film exposed to the mixed gas atmosphere to a predetermined temperature.
In order to achieve the above object, a program according to a nineteenth aspect of the present invention is a program for causing a computer to execute a method for manufacturing an electronic device, the method including:
a wiring forming module for forming a wiring made of a first conductive material on a first insulating film formed on a surface of a semiconductor substrate;
a second insulating film forming module for forming a second insulating film on the first insulating film to cover the wiring;
a photoresist layer forming module for forming a photoresist layer of a predetermined pattern on the formed second insulating film;
a plasma processing and forming module for processing and forming a connection hole reaching the wiring on the second insulating film by plasma processing using the formed photoresist layer;
an ashing module for removing the photoresist layer;
a connection hole filling module for forming a conductive film made of a second conductive material on the second insulating film and filling the connection hole with the second conductive material;
a conductive film polishing module for polishing the formed conductive film by chemical mechanical polishing;
a second insulating film exposure module for exposing the second insulating film exposed by the chemical mechanical polishing to a mixed gas atmosphere containing ammonia and hydrogen fluoride under a predetermined pressure; and
and a second insulating film heating module for heating the second insulating film exposed to the mixed gas atmosphere to a predetermined temperature.
In order to achieve the above object, a program according to a twentieth aspect of the present invention is a program for executing a method of manufacturing an electronic device in a computer, the program including:
a wiring forming module for forming a wiring made of a first conductive material on a first insulating film formed on a surface of a semiconductor substrate;
a second insulating film forming module for forming a second insulating film on the first insulating film to cover the wiring;
a photoresist layer forming module for forming a photoresist layer of a predetermined pattern on the formed second insulating film;
a plasma processing module for processing and forming a connection hole reaching the wiring on the second insulating film by plasma processing using the formed photoresist layer;
a connection hole filling module for forming a conductive film made of a second conductive material on the second insulating film and filling the second conductive material into the connection hole;
a conductive film polishing module for polishing the photoresist layer and the formed conductive film by chemical mechanical polishing;
a second insulating film exposure module for exposing the second insulating film exposed by the chemical mechanical polishing to a mixed gas atmosphere containing ammonia and hydrogen fluoride under a predetermined pressure; and
and a second insulating film heating module for heating the second insulating film exposed to the mixed gas atmosphere to a predetermined temperature.
According to the method for processing a substrate of the first aspect and the program of the seventeenth aspect of the present invention, the exposed insulating film is exposed to an atmosphere of a mixed gas containing ammonia and hydrogen fluoride under a predetermined pressure, and the insulating film exposed to the atmosphere of the mixed gas is heated to a predetermined temperature. A product based on the exposed insulating film and a mixed gas is generated when the exposed insulating film is exposed to a mixed gas atmosphere containing ammonia and hydrogen fluoride under a predetermined pressure, and the generated product is heated and vaporized when the insulating film exposed to the mixed gas atmosphere is heated to a predetermined temperature. By vaporizing the product, a surface damage layer, a cutting residue, and the like on the surface of the insulating film by chemical mechanical polishing can be removed. In this case, the amount of the product to be produced can be controlled by the parameters of the mixed gas. Therefore, the amount of removal of the surface damaged layer, the cutting residue, and the like on the surface of the insulating film can be easily controlled.
According to the substrate processing method of the third aspect of the present invention, since no charge is accumulated on the gate electrode in the electronic device manufactured from the substrate by performing the plasma-free etching process on the substrate, the gate oxide film can be prevented from being deteriorated or broken. At the same time, no energetic particles are irradiated on the electronic device (element), so that the semiconductor can be prevented from generating driving damage (crystal defect). In addition, an unintended chemical reaction due to plasma is not caused, and thus generation of impurities can be prevented, whereby the process chamber can be prevented from being contaminated when a process is performed on the substrate.
According to the substrate processing method of the fourth aspect of the present invention, since the substrate is subjected to the drying and cleaning process, not only the occurrence of surface roughness (roughness) can be prevented, but also the change in the physical properties of the substrate surface can be suppressed, and the deterioration in the wiring reliability can be reliably prevented.
According to the substrate processing method of the fifth aspect of the present invention, the volume flow ratio of hydrogen fluoride to ammonia in the mixed gas is 1to 1/2, and the predetermined pressure is 6.7 × 10-2Since the pressure is about 4.0Pa, the generation of the product is promoted, and the surface damage layer, the cutting residue, and the like on the surface of the insulating film can be reliably removed.
According to the method of processing a substrate of the sixth aspect of the present invention, since the predetermined temperature is 80 to 200 ℃, vaporization of the product can be promoted, and the surface damage layer and the cutting residue on the surface of the insulating film can be reliably removed.
According to the method for treating a surface of a substrate of the seventh aspect of the present invention, since the shape of the exposed insulating film is measured and at least one of the volume flow rate ratio of hydrogen fluoride to ammonia in the mixed gas and the predetermined pressure is determined based on the measured shape, the amount of removal of the surface damaged layer, the cutting residue, and the like on the surface of the insulating film can be accurately controlled, and the efficiency of the surface treatment of the substrate can be improved. Further, when the local etching by the chemical mechanical polishing is eliminated by removing the insulating film, the amount of removal of the insulating film can be accurately controlled, and re-planarization can be accurately performed.
According to the post-chemical mechanical polishing cleaning method according to the eleventh aspect of the present invention and the program according to the eighteenth aspect of the present invention, the insulating film exposed by the chemical mechanical polishing can be exposed to a mixed gas atmosphere containing ammonia and hydrogen fluoride under a predetermined pressure, and the insulating film exposed to the mixed gas atmosphere can be heated to a predetermined temperature. The method includes the steps of generating a product based on the exposed insulating film and a mixed gas when the exposed insulating film is exposed to the mixed gas atmosphere containing ammonia and hydrogen fluoride under a predetermined pressure, and heating and gasifying the generated product when the insulating film exposed to the mixed gas atmosphere is heated to a predetermined temperature. By vaporizing the product, a surface damage layer, a cutting residue, and the like on the surface of the insulating film by chemical mechanical polishing can be removed. In this case, the amount of the product to be produced can be controlled by the parameters of the mixed gas. Therefore, the amount of removal of the surface damaged layer, the cutting residue, and the like on the surface of the insulating film can be easily controlled.
According to the post-chemical mechanical polishing cleaning method of the twelfth aspect of the present invention, the exposed surface of the insulating film is dried before the exposed surface of the insulating film is exposed to the mixed gas. The production of the above product can be promoted in a dry environment. Therefore, removal of the surface damage layer, the cutting residue, and the like on the surface of the insulating film can be promoted.
According to the method for manufacturing an electronic device of the thirteenth aspect of the present invention and the program of the nineteenth aspect of the present invention, the second insulating film exposed by the chemical mechanical polishing is exposed to a mixed gas atmosphere containing ammonia and hydrogen fluoride under a predetermined pressure, and the second insulating film exposed to the mixed gas atmosphere is heated to a predetermined temperature. When the exposed second insulating film is exposed to a mixed gas atmosphere containing ammonia and hydrogen fluoride under a predetermined pressure, a product based on the exposed second insulating film and the mixed gas is generated, and when the second insulating film exposed to the mixed gas atmosphere is heated to a predetermined temperature, the generated product is heated and vaporized. By vaporizing the product, a surface damage layer, a cutting residue, and the like on the surface of the second insulating film by chemical mechanical polishing can be removed. In this case, the amount of the product to be produced can be controlled by the parameters of the mixed gas. Therefore, the amount of removal of the surface damaged layer, the cutting residue, and the like on the surface of the second insulating film can be easily controlled.
According to the method for manufacturing an electronic device of the fourteenth aspect of the present invention, the surface of the connection hole formed in the second insulating film by processing is exposed to the atmosphere of the mixed gas containing ammonia and hydrogen fluoride under a predetermined pressure, and the surface damage layer of the connection hole generated by the plasma treatment can be removed by the generation of the product on the surface of the connection hole and the vaporization by the heating of the product, and the occurrence of the wiring delay due to the surface damage layer can be prevented.
According to the method of manufacturing an electronic device described in the fifteenth aspect of the present invention, the surface of the connection hole heated to the prescribed temperature is covered with the conductive barrier, and therefore, the surface of the connection hole from which the surface damage layer has been removed and the second conductive material filling the connection hole can be prevented from coming into contact, and thus, the second conductive material can be prevented from diffusing into the second insulating film.
According to the method for manufacturing an electronic device according to the sixteenth aspect of the present invention and the program according to the twentieth aspect of the present invention, the exposed second insulating film is chemically mechanically polished under a predetermined pressure, exposed to a mixed gas atmosphere containing ammonia and hydrogen fluoride, and the second insulating film exposed to the mixed gas atmosphere is heated to a predetermined temperature. When the exposed second insulating film is exposed to a mixed gas atmosphere containing ammonia and hydrogen fluoride under a predetermined pressure, a product based on the exposed second insulating film and the mixed gas is generated, and when the second insulating film exposed to the mixed gas atmosphere is heated to a predetermined temperature, the generated product is heated and vaporized. By vaporizing the product, a surface damage layer, a cutting residue, and the like on the surface of the second insulating film by chemical mechanical polishing can be removed. In this case, the amount of the product to be produced can be controlled by the parameters of the mixed gas. Therefore, the amount of removal of the surface damage layer, the cutting residue, and the like on the surface of the second insulating film can be easily controlled. In addition, since the conductive film and the photoresist layer are polished by chemical mechanical polishing at the same time, the yield can be improved.
Drawings
Fig. 1 is a schematic plan view showing a substrate processing apparatus to which the substrate processing method according to the embodiment of the present invention is applied.
Fig. 2 is a sectional view of the second process unit of fig. 1, fig. 2(a) is a sectional view taken along line II-II of fig. 1, and fig. 2(B) is an enlarged view of a portion a of fig. 2 (a).
Fig. 3 is a perspective view showing a schematic structure of the second processing chamber of fig. 1.
Fig. 4 is a schematic configuration diagram illustrating a unit driving dry air supply system of the second load lock unit of fig. 3.
Fig. 5 is a diagram showing a schematic configuration of a system controller of the substrate processing apparatus of fig. 1.
Fig. 6 is a process diagram showing a substrate processing method according to the present embodiment.
Fig. 7 is a process diagram showing a cleaning method after chemical mechanical polishing according to an embodiment of the present invention.
Fig. 8 is a process diagram illustrating a method of manufacturing an electronic device according to an embodiment of the present invention.
Fig. 9 is a plan view schematically showing a configuration of a first modification of a substrate processing apparatus to which the substrate processing method according to the present embodiment is applied.
Fig. 10 is a plan view schematically showing a configuration of a second modification of a substrate processing apparatus using the substrate processing method according to the present embodiment.
FIG. 11 is a schematic diagram showing a polishing apparatus for performing CMP on a wafer.
Description of the symbols
A W wafer; 10, 137, 160 substrate processingA device; 11 a first processing compartment; 12 a second treatment cabin; 13 a loading unit; 17 a first IMS; 18 a second IMS; 25 a first processing unit; 34 a second processing unit; 36 a third processing unit; 37 a second transfer arm; 38, 50, 70 cavitiesA chamber; 39 ESC; 40 spray headers; 41 TMP; 42, 69APC valves; 45 a first buffer chamber; 46 a second buffer chamber; 47, 48 gas vents; 49 a second load lock chamber; 51 a mounting table heater; 57 an ammonia gas supply pipe; 58 a hydrogen fluoride gas supply pipe; 59, 66, 72 pressure gauges; 61 an exhaust system of the second treatment unit; 65, 71 nitrogen gas supply pipes; 67 the exhaust system of the third treatment unit; 73 an exhaust system of a second load lock unit; 74 atmospheric communicating tube; 89 EC; 90, 91, 92 MC; 93 a switching hub; a 95GHOST network; 97, 98, 99I/O modules; 100I/O unit; 101, 110, 116 cutting residues; 102, 111, 117 reaction products; 103, 124 of SiO 22A layer; 104, 104a, 106, 113 insulating films; 105, 112, 123 generating a layer; 107 wiring grooves; 108 a conductive film; 109, 114 wiring; 115 an interlayer insulating film with a low dielectric constant; 118 through-holes; 119 damage the layer; 120 a conductive shielding film; 121 a conductive film; 122 a via filler; 138, 163 transfer unit; 139, 140, 141, 142, 161, 162 processing units; 170 LAN; 171PC
Detailed Description
Embodiments of the present invention are described below with reference to the drawings.
First, a method of processing a substrate according to an embodiment of the present invention will be described.
Fig. 1 is a plan view schematically showing a configuration of a substrate processing apparatus to which the substrate processing method according to the present embodiment is applied.
In fig. 1, a substrate processing apparatus 10 has a first processing chamber 11 for performing reactive ion etching (hereinafter, referred to as "RIE") processing on a wafer (hereinafter, referred to as "wafer") W for electronic equipment; a second processing chamber 12 arranged in parallel with the first processing chamber 11 and configured to perform COR (Chemical Oxide Removal) processing and PHT (Post Heat Treatment) processing, which will be described later, on the wafer W; and a common rectangular transfer chamber loading unit 13 connected to the first processing chamber 11 and the second processing chamber 12, respectively.
Three Pod stages 15, each of which is a Pod (front opening Unified Pod)14 that is a container for placing and storing 25 wafers W, are connected to the loading unit 13 in addition to the first processing Pod 11 and the second processing Pod 12; an orienter 16 for adjusting the position of the wafer W carried out of the pod 14 in advance, and first and second IMS (Integrated Metrology system thermal-Wave, Inc.)17, 18 for measuring the surface condition of the wafer W.
The first processing chamber 11 and the second processing chamber 12 are connected to the longitudinal side walls of the loading unit 13, and are disposed so as to face the three foup stages 15 while sandwiching the loading unit 13, the aligner 16 is disposed at one longitudinal end of the loading unit 13, and the first IMS17 is disposed at the other longitudinal end of the loading unit 13; the second IMS18 is arranged in parallel with the three pod stages 15.
The loading unit 13 includes a SCARA type double-arm transfer arm mechanism 19 disposed inside and configured to transfer the wafer W, and three load ports 20 serving as wafer W inlet ports disposed on the side wall so as to correspond to the wafer pod stages 15. The transfer arm mechanism 19 takes out the wafer W from the pod 14 placed on the pod stage 15 through the load port 20, and carries the taken-out wafer W into and out of the first processing chamber 11, the second processing chamber 12, the aligner 16, the first IMS17, or the second IMS 18.
The first IMS17 is a monitor of an optical system, which has a mounting table 21 on which a loaded wafer W is mounted, and an optical sensor 22 pointed to the wafer W mounted on the mounting table 21, and can measure the surface shape (for example, the film thickness of the surface layer) of the wafer W and the CD (Critical Dimension) value of a wiring groove, a gate electrode, or the like. The second IMS18 is also a monitor of an optical system, and has the stage 23 and the optical sensor 24, and measures the number of particles on the surface of the wafer W, as in the first IMS 17.
The first process compartment 11 has a first process unit 25 as a first vacuum process chamber for performing RIE processing on the wafer W; and a first load lock unit 27 having a first transfer arm 26 of a link type single picker type mounted therein to transfer the wafer W in the first process unit 25.
The first processing unit 25 has a cylindrical processing chamber container (chamber), and an upper electrode and a lower electrode disposed in the chamber. The distance between the upper electrode and the lower electrode is set to an appropriate interval for RIE processing on the wafer W. Further, the ESC28 for clamping the wafer W by coulomb force or the like is provided on the top of the lower electrode.
In the first processing unit 25, a processing gas is introduced into the chamber, an electric field is generated between the upper electrode and the lower electrode, the introduced processing gas is converted into plasma, ions and radicals are generated, and RIE processing is performed on the wafer W using the ions and radicals.
In the first process compartment 0 11, the internal pressure of the loading unit 13 is maintained at atmospheric pressure, and on the other hand, the internal pressure of the first process unit 25 is maintained at vacuum. Thus, the first load lock unit 27 can be configured as a vacuum pre-conveyance chamber whose internal pressure is adjusted by providing the vacuum gate valve 29 at the connection portion with the first processing unit 25 and the atmosphere gate valve 30 at the connection portion with the loading unit 13.
A first transfer arm 26 is provided at a substantially central portion inside the first load lock unit 27, a first buffer 31 is provided on the first processing unit 25 side with respect to the first transfer arm 26, and a second buffer 32 is provided on the loading unit 13 side with respect to the first transfer arm 26. The first buffer 31 and the second buffer 32 are disposed on a moving track of a support part (pickup) 33 that supports the wafer W disposed at the tip of the first transfer arm 26, and the wafer W subjected to the RIE process is temporarily avoided above the track of the support part 33, whereby the wafer W not subjected to the RIE process and the wafer W subjected to the RIE process can be smoothly exchanged with each other in the first processing unit 25.
The second processing chamber 12 has a second processing unit 34 as a second vacuum processing chamber for performing COR processing on the wafer W; a third processing unit 36 serving as a third vacuum processing chamber connected to the second processing unit 34 through a vacuum gate valve 35 and performing PHT processing on the wafer W; and a second load lock unit 49 internally provided with a link-type single picker-type second transfer arm 37 that transfers the wafer W in the second and third process units 34 and 36.
Fig. 2 is a sectional view of the second process unit of fig. 1. Fig. 2(a) is a sectional view taken along line II-II of fig. 1, and fig. 2(B) is an enlarged view of a portion a in fig. 2 (a).
In fig. 2(a), the second processing unit 34 has: a cylindrical processing chamber container (chamber) 38; a stage ESC39 for placing the wafer W in the chamber 38; a showerhead 40 disposed above the chamber 38; a TMP (turbo molecular pump)41 which discharges the gas and the like in the chamber 38; and a variable butterfly valve APC (Automatic Pressure control) valve 42 disposed between the chamber 38 and the TMP41 that controls the Pressure within the chamber 38.
The ESC39 has an electrode plate (not shown) to which a dc voltage is applied, and holds the adsorbed wafer W by coulomb force or Johnsen-Rahbek force generated by the dc voltage. The ESC39 also has a coolant chamber (not shown) as a temperature adjustment mechanism. A coolant, such as cooling water or Galden fluid, at a prescribed temperature is circulated into the coolant chamber and the temperature of the coolant is used to control the process temperature of the wafer W chucking on the upper surface of the ESC 39. In addition, the ESC39 has a heat transfer gas supply system (not shown) that uniformly supplies a heat transfer gas (helium) between the upper surface of the ESC39 and the backside of the wafer W. When the COR process is performed, the heat transfer gas performs heat exchange between the ESC39 and the wafer W, which are maintained at a desired designated temperature by the cryogen, and the wafer W can be efficiently and uniformly cooled.
In addition, the ESC39 has a plurality of push rod pins 56 that are lift pins that protrude freely from its upper face. These push rod pins 56 are housed in the ESC39 when the wafer W is sorptively held within the ESC39, and protrude from the upper surface of the ESC39 when the wafer W having undergone COR processing is carried out of the chamber 38, transferring the wafer W to above.
The shower head 40 has a two-layer structure, and has a first buffer chamber 45 and a second buffer chamber 46 in a lower layer portion 43 and an upper layer portion 44, respectively. The first buffer chamber 45 and the second buffer chamber 46 communicate with the inside of the chamber 38 through gas communication holes 47, 48, respectively. That is, the shower head 40 has an internal passage leading into the chamber 38 for supplying gas to the first buffer chamber 45 and the second buffer chamber 46, respectively, and is composed of two plate-like bodies (the lower portion 43 and the upper portion 44) laminated in layers.
When COR processing is performed on the wafer W, NH is supplied from an ammonia gas supply pipe 57 described later3The first buffer chamber 45 is supplied with (ammonia) gas, and the supplied ammonia gas is supplied into the chamber 38 through the gas vent hole 47, while the second buffer chamber 46 is supplied with HF (hydrogen fluoride) gas from a hydrogen fluoride gas supply pipe 58 described later. The supplied hydrogen fluoride gas is supplied into the chamber 38 through the gas vent 48.
Further, the shower head 40 is internally provided with a heater (not shown), such as a heating element. Preferably, the heating element is disposed on the upper portion 44 to control the temperature of the hydrogen fluoride gas in the second buffer chamber 46.
As shown in fig. 2(B), the openings of the gas communication holes 47 and 48 to the chamber 38 are flared. This allows the ammonia gas or the hydrogen fluoride gas to be efficiently diffused into the chamber 38. Further, since the cross sections of the gas communication holes 47 and 48 are narrowed, the deposits generated in the chamber 38 can be prevented from flowing back to the gas communication holes 47 and 48, and further to the first buffer chamber 45 and the second buffer chamber 46. The gas vent holes 47 and 48 may be spiral vent holes.
The second processing unit 34 performs COR processing on the wafer W by adjusting the pressure in the chamber 38 and the volume flow ratio of the ammonia gas and the hydrogen fluoride gas. In addition, since the second processing unit 34 is designed to mix the ammonia gas and the hydrogen fluoride gas in the chamber 38 first (post-mixing design), the hydrogen fluoride gas and the ammonia gas are prevented from reacting before being introduced into the chamber 38 by preventing the two gases from being mixed before being introduced into the chamber 38.
In addition, in the second processing unit 34, a heater (not shown), for example, a heating element, is installed in a sidewall of the chamber 38 to prevent a temperature of an atmosphere in the chamber 38 from being lowered, thereby improving reproducibility of the COR process. In addition, by controlling the temperature of the sidewall with a heating element within the sidewall, byproducts generated within the chamber 38 may be prevented from adhering to the inside of the sidewall.
Returning to fig. 1, it can be seen that the third processing unit 36 has: a frame-shaped processing chamber container (chamber) 50; a stage heater 51 as a stage for the wafer W disposed in the chamber 50; a buffer arm 52 disposed around the stage heater 51 and configured to move the wafer W placed on the stage heater 51 upward; and a PHT chamber cover (not shown) that closes the chamber from the outside atmosphere.
The stage heater 51 is made of aluminum having an oxide film formed on the surface thereof, and heats the wafer W placed thereon to a predetermined temperature by an electric heating wire or the like installed therein. Specifically, the stage heater 51 directly heats the wafer W to 100 to 200 ℃, preferably about 135 ℃ for at least 1 minute.
A sheet heater made of silicone rubber is provided on the PHT chamber cover. A cartridge heater (not shown) is also installed inside the side wall of the chamber 50. The cartridge heater controls the wall surface temperature of the side wall of the chamber 50 to 25 to 80 ℃. Thus, the byproducts are prevented from being attached to the sidewalls of the chamber 50, particles generated due to the attached byproducts are prevented, and a cleaning cycle of the chamber 50 is extended. Wherein the outer periphery of the chamber 50 is covered with a heat shield.
As a heater for heating the wafer W from above, an ultraviolet radiation (irradiation) heater may be disposed instead of the above-described plate heater. The ultraviolet radiation heater includes an ultraviolet lamp for radiating ultraviolet rays having a wavelength of 190 to 400 mm.
The wafer W subjected to the COR process is temporarily avoided by the buffer arm 52 above the track of the support portion 53 of the second transfer arm 37, and thus the wafer W can be smoothly exchanged between the second processing unit 34 and the third processing unit 36.
The third processing unit 36 adjusts the temperature of the wafer W to perform PHT processing on the wafer W.
The second load lock unit 49 has a frame-shaped transfer chamber (chamber) 70 in which the second transfer arm 37 is mounted. Further, the internal pressure of the loading unit 13 is maintained at atmospheric pressure, and on the other hand, the internal pressures of the second and third processing units 34 and 36 are maintained at vacuum. Thus, the second load-lock unit 49 can be configured as a preliminary vacuum transfer chamber whose internal pressure can be adjusted by providing the vacuum gate valve 54 at the connection portion with the third processing unit 36 and the atmospheric valve 55 at the connection portion with the loading unit 13.
Fig. 3 is a perspective view showing a schematic structure of the second processing chamber shown in fig. 1.
In fig. 3, the second processing unit 34 has an ammonia gas supply pipe 57 that supplies ammonia gas to the first buffer chamber 45; a hydrogen fluoride gas supply pipe 58 for supplying hydrogen fluoride gas to the second buffer chamber 46; a pressure gauge 59 for measuring the pressure in the chamber 38; and a cooling unit 60 that supplies coolant to a cooling system disposed within the ESC 39.
An MFC (Mass flow controller) (not shown) is provided in the ammonia gas supply pipe 57. The MFC adjusts the flow rate of the ammonia gas supplied to the first buffer chamber 45. Meanwhile, the hydrogen fluoride gas supply pipe 58 is also provided with an MFC (not shown) that adjusts the flow rate of the hydrogen fluoride gas supplied to the second buffer chamber 46. The MFC in the ammonia gas supply line 57 and the MFC in the hydrogen fluoride gas supply line 58 cooperate to adjust the volume flow rate ratio of the ammonia gas and the hydrogen fluoride gas to be supplied to the chamber 38.
Further, an exhaust system 61 of the second process unit connected to a DP (dry pump) (not shown) is disposed below the second process unit 34. The exhaust system 61 of the second treatment unit has: an exhaust pipe 63 communicating with an exhaust conduit 62 disposed between the chamber 38 and the APC valve 42; and an exhaust pipe 64 connected to a lower side (exhaust side) of the TMP41, for exhausting gas and the like in the chamber 38. Wherein, before DP, the exhaust pipe 64 is connected to the exhaust pipe 63.
The third processing unit 36 has: nitrogen (N)2) A nitrogen gas supply pipe 65 for supplying the chamber 50; a pressure gauge 66 for measuring the pressure in the chamber 50; and an exhaust system 67 for exhausting the nitrogen gas and the like in the chamber 50.
The nitrogen gas supply pipe 65 is provided with an MFC (not shown) that adjusts the flow rate of nitrogen gas supplied to the chamber 50. The exhaust system 67 of the third treatment unit has: a main exhaust pipe 68 connected to the DP while communicating with the chamber 50; an APC valve 69 disposed in the middle of the main exhaust pipe 68; and a sub-exhaust pipe 68a branched from the main exhaust pipe 68, bypassing the APC valve 69, and connected to the main exhaust pipe 68 before DP. The APC valve 69 controls the pressure within the chamber 50.
The second load lock unit 49 has: a nitrogen gas supply pipe 71 for supplying nitrogen gas to the chamber 70; a pressure gauge 72 that measures the pressure within the chamber 70; an exhaust system 73 of the second load lock unit that exhausts nitrogen gas and the like in the chamber 70; and an atmosphere communication pipe 74 for opening the inside of the chamber 70 to the atmosphere.
An MFC (not shown) is provided in the nitrogen gas supply pipe 71, and adjusts the flow rate of nitrogen gas supplied to the chamber 70. The exhaust system 73 of the second load-lock unit is constituted by one exhaust pipe which communicates with the chamber 70 and which is connected to the main exhaust pipe 68 of the exhaust system 67 of the third process unit before DP. Further, the exhaust system 73 and the atmosphere connection pipe 74 of the second load lock unit have an exhaust valve 75 and a relief valve 76, respectively, which are freely openable and closable. The exhaust valve 75 and the relief valve 76 work in concert to regulate the pressure within the chamber 70 to any value from atmospheric pressure to a desired vacuum level.
Fig. 4 is a schematic configuration diagram illustrating a unit driving dry air supply system of the second load lock unit of fig. 3.
In fig. 4, the dry air of the dry air supply system 77 for unit driving of the second load lock unit 49 is supplied to the gate cylinder for sliding door driving provided in the atmospheric valve 55, the MFC provided in the nitrogen gas supply pipe 71 for nitrogen gas purge unit, the relief valve 76 provided in the atmospheric communication pipe 74 for atmospheric opening relief unit, the exhaust valve 75 provided in the exhaust system 73 for second load lock unit as vacuum evacuation unit, and the gate cylinder for sliding door driving provided in the vacuum gate valve 54.
The unit dry air supply system 77 includes: a secondary dry air supply duct 79 branched from the primary dry air supply chamber 78 provided in the second processing compartment 12; and a first solenoid valve 80 and a second solenoid valve 81 connected to the sub dry air supply pipe 79.
The first solenoid valve 80 is connected to the gate cylinder, the MFC, the relief valve 76, and the gate cylinder through dry air supply pipes 82, 83, 84, and 85, respectively, and controls the operation of each part by controlling the supply amount of dry air to these parts. The second solenoid valve 81 is connected to the exhaust valve 75 through a dry air supply pipe 86, and controls the operation of the exhaust valve 75 by controlling the supply amount of dry air to the exhaust valve 75.
The MFC of the nitrogen gas supply pipe 71 is connected to the nitrogen gas supply system 87.
The second processing unit 34 and the third processing unit 36 also have a unit driving dry air supply system having the same configuration as the unit driving dry air supply system 77 of the second load lock unit 49.
Referring back to fig. 1, the substrate processing apparatus 10 has a system controller that controls the operations of the first process chamber 11, the second process chamber 12, and the loading unit 13; and an operation controller 88 disposed at one end in the longitudinal direction of the loading unit 13.
The operation controller 88 has a display unit formed of, for example, an LCD (Liquid crystal display), and the display unit displays the operating state of each component of the substrate processing apparatus 10.
Further, as shown in fig. 5, the system controller has an EC (equipment controller) 89; three MC (Module Controller)90, 91, 92; and a switching hub (switching hub)93 connecting EC89 with each MC. The System controller is connected from the EC89 to a PC171 of an MES (Manufacturing Execution System) that manages Manufacturing processes in the entire plant in which the substrate processing apparatus 10 is installed, through a LAN (Local Area Network) 170. The MES is connected to a system controller, and feeds back real-time data on the work site process to a basic service system (not shown), and judges the process in consideration of the load of the whole work site.
The EC89 is a master controller (master controller) that integrates the respective MCs and controls the overall operation of the substrate processing apparatus 10. The EC89 has a CPU, a RAM, an HDD, and the like, and the CPU transmits control signals to the respective MCs in accordance with a program corresponding to a recipe, which is a processing method of the wafer W designated by a user instruction in the operation controller 88, thereby controlling the operations of the first processing pod 11, the second processing pod 12, and the loading unit 13.
The switching hub 93 switches the MC as the destination of the EC89 connection in accordance with the control signal issued from the EC 89.
The MC90, 91, and 92 are sub-control units (slave control units) that control the operations of the first processing compartment 11, the second processing compartment 12, and the loading unit 13, respectively. Each MC is connected to each I/O (input/output) module 97, 98, 99 via a dist (distribution) switch 96 via a GHOST network 95. The GHOST network 95 is realized by an LSI (General High-speed optimal Scalable transmitter) mounted on an MC switch included in the MC, and 31 maximum I/O modules are connectable to the GHOST network 95, and in the GHOST network 95, the MC is a master and the I/O modules are slaves.
The I/O module 98 is composed of a plurality of I/O sections 100 connected to respective constituent elements (hereinafter referred to as "terminal devices") of the second processing compartment 12, and performs transmission of control signals to and signals from the respective terminal devices. The terminal devices connected to the I/O unit 100 in the I/O module 98 are, for example: the MFC of the ammonia gas supply pipe 57, the MFC of the hydrogen fluoride gas supply pipe 58, the pressure gauge 59, and the APC valve 42 in the second process unit 34, the MFC of the nitrogen gas supply pipe 65, the pressure gauge 66, the APC valve 69, the buffer arm 52, and the mounting table heater 51 in the third process unit 36, the MFC of the nitrogen gas supply pipe 71, the pressure gauge 72, and the second transfer arm 37 in the second load lock unit 49, and the first solenoid valve 80 and the second solenoid valve 81 of the unit-driving dry air supply system 77, and the like.
The I/O modules 97 and 99 have the same configuration as the I/O module 98, and the connection relationship between the MC90 and the I/O module 97 corresponding to the first process compartment 11 and the connection relationship between the MC92 and the I/O module 99 corresponding to the load cell 13 have the same configuration as the connection relationship between the MC91 and the I/O module 98, and therefore, the description thereof will be omitted.
Further, an I/O switch (not shown) that controls input and output of digital signals, analog signals, and serial signals in the I/O unit 100 is connected to each of the GHOST networks 95.
In the substrate processing apparatus 10, when COR processing is performed on the wafer W, the CPU of the EC89 transmits a control signal to a desired terminal apparatus via the switching hub 93, the MC91, the GHOST network 95, and the I/O unit 100 of the I/O module 98 in accordance with a program corresponding to the recipe of COR processing, and thereby COR processing is performed in the second processing unit 34.
Specifically, the CPU adjusts the volume flow ratio of the ammonia gas and the hydrogen fluoride gas in the chamber 38 to a desired value by sending control signals to the MFC in the ammonia gas supply pipe 57 and the MFC in the hydrogen fluoride gas supply pipe 58; by sending control signals to the TMP41 and the APC valve 42, the pressure within the chamber 38 is adjusted to a desired value. At this time, the pressure gauge 59 sends the pressure value in the chamber 38 as an output signal to the CPU of the EC89, and the CPU determines the control parameters of the MFC in the ammonia gas supply line 57, the MFC in the hydrogen fluoride gas supply line 58, the APC valve 42, and the TMP41, based on the output pressure value in the chamber 38.
When the PHT process is performed on the wafer W, the CPU of the EC89 also transmits a control signal to a desired terminal device in accordance with a program corresponding to the recipe of the PHT process, thereby performing the PHT process in the third processing unit 36.
Specifically, the CPU adjusts the pressure within the chamber 50 to a desired value by delivering control signals to the MFC and APC valves 69 of the nitrogen gas supply pipe 65; the temperature of the wafer W is adjusted to a desired value by transmitting a control signal to the stage heater 51. At this time, the pressure gauge 66 also sends the pressure value in the chamber 50 as an output signal to the CPU of the EC89, and the CPU determines the control parameters of the APC valve 69 and the MFC of the nitrogen gas supply pipe 65 based on the pressure value in the chamber 50 that is sent.
In the system controller of fig. 5, since the plurality of terminal devices are not directly connected to the EC89, the I/O units 100 connected to the plurality of terminal devices are modularized to form I/O modules, and the I/O modules are connected to the EC89 through the MC and the switching hub 93, the communication system can be simplified.
Further, since the control signal output from the CPU of the EC89 includes the address of the I/O unit 100 connected to the desired terminal device and the address of the I/O module including the I/O unit 100, the switching hub 93 refers to the address of the I/O module in the control signal, the ghast of the MC refers to the address of the I/O unit 100 in the control signal, and the switching hub 93 or MC does not need to inquire of the destination to which the control signal is sent in the CPU, thereby achieving smooth transfer of the control signal.
As described above, since the CMP residue or the like is generated on the exposed surface of the insulating film, particularly, when a low dielectric constant interlayer insulating film containing carbon is used as the insulating film, SiO is formed on the surface of the low dielectric constant interlayer insulating film2Surface damage layer having similar characteristics (hereinafter referred to as "pseudo SiO2Layer "). In order to prevent the interlayer insulating film having a low dielectric constant from being crushed by CMP, the film must have a predetermined mechanical strength, specifically, young's modulus (young's modulus) of 4GPa or more. Due to suspected SiO on the surface of these insulating films2Layers, cutting residues, and the like are the main causes of various problems in electronic devices manufactured from wafers W and therefore must be removed, and the pseudo SiO2The layer is also referred to as a "modified layer" or a "sacrificial layer".
The substrate processing method of the present embodiment corresponds to the method for forming a pseudo SiO layer or the like on a substrate having a surface having a cutting residue or the like caused by CMP2The COR process and the PHT process are performed on the wafer W of the insulating film of the layer.
The COR process is a process of chemically reacting an oxide film of an object to be processed with gas molecules to produce a product, and the PHT process is a process of heating an object to be processed that has been subjected to the COR process to gasify and thermally oxidize (thermal oxidation) the product produced on the object by the chemical reaction of the COR process, and removing the product from the object. As described above, the COR process and the PHT process, particularly the COR process, do not use plasma and do not use water to remove an oxide film on a target object, and therefore, are equivalent to the plasma-free etching process and the dry cleaning process.
In the method of treating a substrate of the present embodiment, ammonia is usedGas and hydrogen fluoride gas are used as gases. Here, the hydrogen fluoride gas promotes SiO2Layer or suspected SiO2The etching of the layer, ammonia gas, if necessary, limits the reaction between the oxide film and the hydrogen fluoride gas, and synthesizes a By-product (By-product) which stops the reaction at the end. Specifically, in the COR treatment and the PHT treatment, SiO is removed by utilizing the following chemical reaction2An upper layer of the insulating film, removing the cutting residue on the surface of the insulating film or removing the pseudo SiO formed on the surface of the low dielectric constant interlayer insulating film2And (3) a layer.
(COR treatment)
(PHT treatment)
The present inventors confirmed that the COR treatment and the PHT treatment utilizing the above-mentioned chemical reaction hadHas the following characteristics. In addition, several N's are generated in the PHT process2And H2。
1) The selectivity (removal rate) of the thermal oxide film is high.
Specifically, the thermal oxide films of the COR process and the PHT process have a high selectivity, and on the other hand, the silicon selectivity is low. Therefore, SiO as a thermal oxide film can be removed with high efficiency2Upper layer of insulating film made of film or pseudo SiO having the same characteristics2And (3) a layer.
2) Removing the upper layer or suspected SiO2The growth rate of a natural oxide film on the surface of the insulating film of the layer is slow.
Specifically, the growth time of the natural oxide film having a thickness of 3 Å was 10 minutes by removing the surface of the upper insulating film by wet etching, and the growth time of the natural oxide film having a thickness of 3 Å was 2 hours or more by removing the surface of the upper insulating film by COR processing and PHT processing.
3) The reaction was carried out in a dry environment.
Specifically, in the COR treatment, water is not used in the reaction, and further, since water generated in the COR treatment is also vaporized by the PHT treatment, OH groups are not present on the surface of the insulating film on which the upper layer is removed. Therefore, since the surface of the insulating film does not become hydrophilic and the surface does not absorb moisture, it is possible to prevent a decrease in wiring reliability of the electronic device.
4) After a predetermined time, the amount of the product produced is saturated.
Specifically, when a predetermined time has elapsed, the amount of product generated does not increase even if the insulating layer is subsequently exposed to the mixed gas of ammonia gas and hydrogen fluoride gas. The amount of the product to be produced is determined by parameters of the mixed gas such as the pressure and the volume flow ratio of the mixed gas. Therefore, the amount of the insulating film removed can be easily controlled.
5) The generation of particles is very small.
Specifically, in the second processing unit 34 and the third processing unit 36, even if the removal of the upper layer of the insulating film of 2000 wafers W is performed, the adhesion of particles to the chamber 38 or the inner wall of the chamber 50 or the like is hardly observed. Therefore, in the electronic device, the reliability of the electronic device can be improved without causing a short circuit of the wiring due to particles.
Fig. 6 is a process diagram showing a substrate processing method according to the present embodiment.
In fig. 6, first, a wafer W having a cutting residue 101 (fig. 6 a) caused by CMP on the surface, a reaction product 102 (fig. 6B), a residue (not shown), or SiO is accommodated in the chamber 38 of the second processing unit 342Formed insulating film104; or a pseudo SiO is formed on the surface2The layer 103 and the insulating film 104a made of SiOCH (fig. 6C) are formed by adjusting the pressure in the chamber 38 to a predetermined pressure, introducing ammonia gas, hydrogen fluoride gas and argon (Ar) gas as a diluent gas into the chamber 38 to form a mixed gas atmosphere made of these gases in the chamber 38, and exposing the insulating films 104 and 104a to the mixed gas at a predetermined pressureIn the atmosphere (insulating film exposing step) (fig. 6(a), (B), (C)). Thus, SiO of the insulating film 1042Or suspected SiO2The layer 103, ammonia gas and hydrogen fluoride gas form a product having a complex structure, and the product is formed on the upper layer of the insulating film 104 or the pseudo SiO2The layer 103 is modified to a product layer 105 composed of a product.
Next, the wafer W on which the product layer 105 is formed is placed on the stage heater 51 in the chamber 50 of the third processing unit 36, the pressure in the chamber 50 is adjusted to a predetermined pressure, nitrogen gas is introduced into the chamber 50 to generate a viscous flow, and the wafer W is heated to a predetermined temperature by the stage heater 51 (insulating film heating step). At this time, the complex structure of the product layer 105 is thermally decomposed, and the product 105 is separated and gasified into silicon tetrafluoride (SiF)4) Ammonia, nitrogen, hydrogen fluoride. The vaporized molecules are entrained in the viscous flow and exhausted from the chamber 50 by the exhaust system 67 of the third processing unit. Thereby, the upper layer of the insulating film 104 can be removed, the cutting residue 101, the reaction product 102 and the residue on the surface of the insulating film 104 can be removed, or pseudo SiO can be removed2Layer 103 (fig. 6 (D)).
In the second processing unit 34, since the hydrogen fluoride gas easily reacts with moisture, it is preferable to set the volume of the ammonia gas in the chamber 38 to be larger than the volume of the hydrogen fluoride gas, and to remove water molecules in the chamber 38 as much as possible. Specifically, the volume flow ratio (SCCM) of hydrogen fluoride gas to ammonia gas in the mixed gas in the chamber 38 is preferably 1to 1/2, and the predetermined pressure in the chamber 38 is preferably 6.7X 10-24.0Pa (0.5 to 30 mTorr). This stabilizes the flow rate ratio of the mixed gas in the chamber 38, and promotes the production of the product.
In addition, when the specified pressure in the chamber 38 is 6.7X 10-2When the pressure is 4.0Pa (0.5 to 30mTorr), the amount of the product to be produced can be saturated reliably after a predetermined time has elapsed, and thus the etching depth can be controlled reliably (self-limiting). For example, when the predetermined pressure in the chamber 38 is 1.3Pa (10mTorr), the etching process is stopped after about 3 minutes has elapsed from the start of the COR process. At this time, the etching depth was about 15 nm. The predetermined pressure in the chamber 38 was 2.7Pa (20 mTo)rr), the etching process is stopped after about 3 minutes from the start of the COR process. At this time, the etching depth was about 24 nm.
Since the reaction of the reactants is promoted at around room temperature, the temperature of the ESC39 on which the wafer W is placed is preferably set to 25 ℃. Since the generated by-products are less likely to adhere to the inside of the chamber 38 at higher temperatures, it is preferable to set the temperature of the inner wall of the chamber 38 at 50 ℃ by a heater (not shown) embedded in the side wall.
In the third processing unit 36, the reactant is a complex (Complexcompound) including a coordinate bond. Since the binding force of the complex is weak and thermal decomposition is promoted even at a relatively low temperature, the predetermined temperature of the wafer W is preferably 80 to 200 ℃. The time for performing the PHT treatment on the wafer W is preferably 60 to 180 seconds. Further, since a viscous flow is generated in the chamber 50, it is not preferable to increase the degree of vacuum in the chamber 50, and a gas flow of a certain flow rate is also necessary. Therefore, the predetermined pressure of the chamber 50 is preferably 6.7 × 10 to 1.3 × 102Pa (500 mTorr-1 Torr), and the flow rate of nitrogen gas is preferably 500-3000 SCCM. This makes it possible to reliably generate a viscous flow in the chamber 50 and to reliably remove gas molecules generated by thermal decomposition of the product.
Before the COR process is performed on the wafer W, the surface shape of the insulating films 104 and 104a, for example, the film thickness, or the CD value of the shape of the wiring trench, the gate electrode, or the like, is preferably measured. The CPU of EC89 corresponds to the measured surface shape, based on the surface shape of the insulating film and the amount of removal of the upper layer with the insulating film or pseudo SiO2The value of the process condition parameter in the COR process or the PHT process is determined based on the predetermined relationship between the process condition parameters relating to the removal amount of the layer (product formation condition determining step). Thus, the amount of removal of the upper layer of the insulating film 104, and further, the amount of removal of the cutting residue 101, the reaction product 102 and the residue on the surface of the insulating film 104 or the pseudo SiO can be controlled accurately2The amount of layer 103 removed also increases the efficiency of the surface treatment of the substrate. Furthermore, by removing the insulating film 104, local extinction by CMP can be eliminatedIn etching the insulating film 104, the amount of the insulating film 104 to be removed can be accurately controlled, and re-planarization of the insulating film 104 can be accurately performed.
In the initial stage of processing a batch of a plurality of wafers W, the predetermined relationship may be based on the difference in surface shape of the insulating films 104 and 104a before and after the COR process and the PHT process measured by the first IMS17, that is, the amount of removal of the upper layer of the insulating film 104 formed by the COR process and the PHT process, or the pseudo SiO deposition2The processing condition parameters of the COR processing and the PHT processing in this case include the removal amount of the layer 103, the volume flow ratio of the hydrogen fluoride gas to the ammonia gas, the predetermined pressure in the chamber 38, and the heating temperature of the wafer W placed on the stage heater 51. The predetermined relationship thus set being stored in EC89In the HDD and the like, reference can be made as described above in the processing of the wafers W at the initial stage and the subsequent stage of the lot.
Further, whether or not to perform the COR process and the PHT process again on the wafer W is determined based on the difference in the surface shape of the insulating films 104 and 104a before and after the COR process and the PHT process are performed on the wafer W. When the COR process and the PHT process are performed again, the CPU of the EC89 determines the condition parameters of the COR process and the PHT process based on the predetermined relationship in accordance with the surface shapes of the insulating films 104 and 104a after the COR process and the PHT process are performed on the wafer W. Thus, the amount of removal of the insulating films 104 and 104a can be accurately controlled, and re-planarization of the insulating films 104 and 104a can be accurately performed.
According to the substrate processing method of the present embodiment, the insulating film 104 having the cutting residue 101, the reaction product 102 and the residue on the surface or the pseudo SiO is formed on the surface is formed under a predetermined pressure2The wafer W of the insulating film 104a of the layer 103 is exposed to a mixed gas atmosphere composed of ammonia gas, hydrogen fluoride gas, and argon gas, and the wafer W exposed to the mixed gas atmosphere is heated to a predetermined temperature. Thus, the insulating film 104 is formed of SiO2Or suspected SiO2The layer 103, ammonia gas and hydrogen fluoride gas generate a product having a complex structure, the complex structure of the generated product is thermally decomposed, and the product is separated and gasified to silicon tetrafluorideAmmonia, hydrogen fluoride. By vaporizing the product, the upper layer of the insulating film 104 can be removed, and the cutting residue 101, the reaction product 102 and the residue on the surface of the insulating film 104 can be removed or pseudo SiO can be removed2 Layer 103. In this case, the amount of product produced is saturated when the predetermined time has elapsed, and the amount of product produced can be controlled by using the parameters of the mixed gas. Therefore, it is easy to control the removal amount of the cutting residue 101, the reaction product 102 and the residue on the surface of the insulating film 104, or to control the removal amount of the pseudo SiO2Control of the amount of layer 103 removed.
In addition, according to the substrate processing method of the present embodiment, since the non-plasma etching process is performed on the wafer W, the cutting residue 101, the reaction product 102, the residue, and the pseudo SiO are removed2A layer 103; in an electronic device manufactured from a wafer W, charges are not accumulated in a gate electrode, and deterioration and destruction of a gate oxide film can be prevented; because the energy particles are not irradiated on the electronic equipment, the crystal defects in the semiconductor can be prevented; further, since an unintended chemical reaction due to plasma is not generated, generation of impurities can be prevented, and thus, contamination in the chamber 38 or the chamber 50 can be prevented.
Further, according to the substrate processing method of the present embodiment, the wafer W may be subjected to a dry cleaning process to remove the cutting residue 101, the reaction product 102, the residue, and the pseudo SiO2The layer 103 can prevent the wafer W from surface roughening and inhibit the surface material of the wafer WThe change in the properties can also reliably prevent the deterioration of the wiring reliability of the electronic device manufactured from the wafer W.
Next, the cleaning method after the chemical mechanical polishing according to the present embodiment will be described.
In the post-chemical mechanical polishing cleaning method according to the present embodiment, the pseudo SiO on the surface of the insulating film is removed by the COR treatment and the PHT treatment described above2Layers and cutting residues, etc. Further, the COR process and the PHT process are performed in the second process chamber 12 of the substrate processing apparatus 10.
Fig. 7 is a process diagram showing the post-chemical mechanical polishing cleaning method according to the present embodiment.
In FIG. 7, first, SiO deposited by thermal oxidation is deposited on the surface of the wafer W2 A wiring groove 107 is formed on the insulating film 106 formed in the above-described manner by RIE treatment or the like, and polysilicon as a conductive material is deposited on the insulating film 106 by PVD (physical Vapor Deposition) or CVD (Chemical Vapor Deposition) to form a conductive film 108 (fig. 7 a).
Next, the conductive film 108 is polished by CMP to expose the insulating film 106, thereby forming the wiring 109. At this time, a cutting residue 110, a reaction product 111, and a residue (not shown) by CMP are formed on the surface of the exposed insulator 106 (fig. 7B).
Next, the wafer W provided with the insulating film 106 having the cutting residue 110, the reaction product 111, and the residue on the surface thereof is carried into a drying furnace (not shown), the surface of the insulating film 106 is dried, the wafer W provided with the insulating film 106 having the dried surface is accommodated in the chamber 38 of the second processing unit 34, the pressure in the chamber 38 is adjusted to a predetermined pressure, ammonia gas, hydrogen fluoride gas, and argon gas are introduced into the chamber 38, a mixed gas atmosphere composed of these gases is formed in the chamber 38, and the insulating film 106 is exposed to the mixed gas atmosphere at the predetermined pressure (insulating film exposing step). Thereby, the insulating film 106 is formed of SiO2The ammonia gas and the hydrogen fluoride gas generate a product having a complex structure, and the upper layer of the insulating film 106 is modified to a product layer 112 made of the product (fig. 7C).
Next, the wafer W on which the product layer 112 is formed is placed on the stage heater 51 in the chamber 50 of the third processing unit 36, the pressure in the chamber 50 is adjusted to a predetermined pressure, nitrogen gas is introduced into the chamber 50 to generate a viscous flow, and the wafer W is heated to a predetermined temperature by the stage heater 51 (insulating film heating step). At this time, the complex structure of the product layer 112 is thermally decomposed, and the product is separated and gasified into silicon tetrafluoride (SiF)4) Ammonia, nitrogen and hydrogen fluoride (fig. 7 (D)). The vaporized molecules are entrained in the viscous flow and exhausted from the chamber 50 by the exhaust system 67 of the third processing unit. Thereby, the upper layer of the insulating film 106 is removed, and the upper layer of the insulating film 106 is removed simultaneously with the upper layer of the insulating cavity 106Cutting residue 110, andthe product 111 and the residue (FIG. 7 (E)).
According to the post-chemical mechanical polishing cleaning method of the present embodiment, the wafer W provided with the insulating film 106 having the cutting residue 110, the reaction product 111, and the residue generated by CMP on the surface thereof is exposed to a mixed gas atmosphere composed of ammonia gas, hydrogen fluoride gas, and argon gas under a predetermined pressure, and the wafer W exposed to the mixed gas atmosphere is heated to a predetermined temperature. Thereby, the insulating film 106 is formed of SiO2And the ammonia gas and the hydrogen fluoride gas generate a product with a complex structure, the complex structure of the generated product is subjected to thermal decomposition, and the product is separated and gasified into silicon tetrafluoride, ammonia and hydrogen fluoride. By vaporizing the product, the upper layer of the insulating film 106 can be removed, and the cutting residue 110, the reaction product 111, and the residue on the surface of the insulating film 106 can be removed. In this case, the amount of the product to be produced can be controlled by the parameters of the mixed gas. Therefore, the removal amounts of the cutting residue 110, the reaction product 111, and the residue on the surface of the insulating film 106 can be easily controlled.
In addition, according to the post-chemical mechanical polishing cleaning method of the present embodiment, the surface of the insulating film 106 is dried before the exposed insulating film 106 is exposed to the atmosphere of the mixed gas. Since the production of the above-mentioned product is promoted in a dry environment, the removal of the cutting residue 110, the reaction product 111, and the residue can be promoted.
In the cleaning method after chemical mechanical polishing according to the above-described embodiment, the cut residue and the like on the surface of the insulating film can be removed, and when a low dielectric constant interlayer insulating film made of SiOCH is used as the insulating film, pseudo SiO is formed on the surface of the low dielectric constant interlayer insulating film by CMP2And (3) a layer. Subjecting the suspected SiO2The layer may be modified to a product layer by exposing the layer to the mixed gas atmosphere, and the product layer may be vaporized by heat or removed.
Next, a method for manufacturing an electronic device according to an embodiment of the present invention will be described.
In the method of manufacturing an electronic device according to the present embodiment, the low dielectric constant is removed by the COR process and the PHT processPseudo SiO on surface of electric constant interlayer insulating film2Layers and cutting residues, etc. Further, the COR process and the PHT process are performed in the second process chamber 12 of the substrate processing apparatus 10.
Fig. 8 is a process diagram showing a method of manufacturing an electronic device according to an embodiment of the present invention.
In FIG. 8, first, SiO deposited by thermal oxidation is deposited on the surface of a wafer W2A wiring groove is formed by RIE or the like on the insulating film 113 (first insulating film) formed, and a conductive film (not shown) made of aluminum (Al) or an aluminum alloy (first conductive material) is formed on the insulating film 113. Furthermore, a conductive film formed by a planarization process such as an etch back (etchback) process is polished,the insulating film 113 is exposed, and thereby, the wiring 114 is formed on the insulating film 113 (wiring forming step) (fig. 8 a).
Next, a low-dielectric-constant interlayer insulating film 115 (second insulating film) made of SiOCH is formed on the insulating film 113 by CVD so as to cover the wiring 114 (second insulating film forming step), and a photoresist layer 125 having a pattern that exposes an opening 124 corresponding to a part of the low-dielectric-constant interlayer insulating film 115 directly above the wiring 114 is formed by photolithography (photoresist layer forming step) (fig. 8B).
Next, using the formed photoresist layer 125 as a mask, the low dielectric constant interlayer insulating film 115 is etched by RIE processing, and a through hole (connection hole) 118 reaching the wiring 114 is formed on the low dielectric constant interlayer insulating film 115 (plasma processing forming step) (fig. 8 (C)). At this time, the surface of the via hole 118 is covered with a damaged layer 119 (surface damaged layer) whose carbon concentration is reduced by the RIE process.
Thereafter, once the wafer W is accommodated in the chamber 38 of the second processing unit 34, the surface of the through hole 109 is exposed to a mixed gas atmosphere composed of ammonia gas, hydrogen fluoride gas, and argon gas under a predetermined pressure (connection hole surface exposure step), and the wafer W exposed to the mixed gas atmosphere is placed on the stage heater 51 in the chamber 50 of the third processing unit 36, and the surface of the through hole 109 is heated to a predetermined temperature (connection hole surface heating step). This modifies the damaged layer 119 into a product layer, and the product layer is thermally vaporized to remove the damaged layer 119 covering the surface of the through hole 109. The wafer W is then taken out of the third processing unit 36, and the photoresist layer 125 is removed by ashing or the like (ashing step) (fig. 8D).
Next, the surface of low-dielectric-constant interlayer insulating film 115 including the surface of via hole 118 from which damaged layer 119 was removed is covered with conductive shielding film 120 made of silicon nitride (SiN) or silicon carbide (SiC) (a connection hole covering step) (fig. 8(E)), and copper (Cu) (a second conductive material) is deposited on low-dielectric-constant interlayer insulating film 115 covered with conductive shielding film 120 by a CVD method or a PVD method to form conductive film 121 made of copper, and at the same time, copper is filled in via hole 118 (a connection hole filling step) (fig. 8 (F)).
Next, the conductive film 121 and the conductive shielding film 120 are polished by CMP to expose the low dielectric constant interlayer insulating film 115 (conductive film polishing step), thereby forming a via filling body 122. At this time, pseudo SiO generated by CMP is formed on the surface of the exposed low dielectric interlayer insulating film 1152Layer 124. In the suspected SiO2The cutting residue 116, reaction product 117, and residue (not shown) due to CMP are formed on the layer 124. (FIG. 8 (G)).
Next, the wafer having the cutting residue 116, the reaction product 117, the residue and the pseudo SiO on the surface2The wafer W of the low dielectric constant interlayer insulating film 115 of the layer 124 is accommodated in the chamber 38 of the second processing unit 34, the pressure in the chamber 38 is adjusted to a predetermined pressure, ammonia gas, hydrogen fluoride gas, and argon gas are introduced into the chamber 38, a mixed gas atmosphere composed of these gases is formed in the chamber 38, and the low dielectric constant interlayer insulating film 115 is exposed to the mixed gas atmosphere at the predetermined pressure (second insulating film exposing step). Thereby, the pseudo SiO2Generating a product with a complex structure from the layer, ammonia gas and hydrogen fluoride gas, and subjecting the suspected SiO2The layer 124 is modified to a product layer 123 composed of a product (fig. 8H).
Next, the wafer W on which the product layer 123 is formed is placed on the stage heater 51 in the chamber 50 of the third processing unit 36Then, the pressure in the chamber 50 is adjusted to a predetermined pressure, nitrogen gas is introduced into the chamber 50 to generate a viscous flow, and the wafer W is heated to a predetermined temperature by the stage heater 51 (insulating film heating step). At this time, the complex structure of the product layer 123 is thermally decomposed, and the product is separated and gasified into silicon tetrafluoride, ammonia, and hydrogen fluoride (fig. 8 (I)). The vaporized molecules are entrained in the viscous flow and exhausted from the chamber 50 by the exhaust system 67 of the third processing unit. Thereby, the pseudo SiO can be removed2Layer 124, suspected SiO may also be removed2The cutting residue 116, the reaction product 117, and the residue on the layer 124 (fig. 8J).
According to the method of manufacturing an electronic device of the present embodiment, the cutting residue 116, the reaction product 117, the residue, and the pseudo SiO generated by CMP on the surface are formed under a predetermined pressure2The wafer W of the low dielectric interlayer insulating film 115 of the layer 124 is exposed to a mixed gas atmosphere composed of ammonia gas, hydrogen fluoride gas, and argon gas, and the wafer W exposed to the mixed gas atmosphere is heated to a predetermined temperature. Thereby, the pseudo SiO2The layer, ammonia gas and hydrogen fluoride gas generate a product having a complex structure, the complex structure of the generated product is decomposed by heat, and the product is separated and gasified into silicon tetrafluoride, ammonia and hydrogen fluoride. By vaporizing the product, pseudo SiO is removed2Layer 124, suspected SiO may also be removed2Cutting residue 116, reaction products 117, and residues on layer 124. In this case, the amount of the product to be produced can be controlled by using the parameter of the mixed gas. Therefore, pseudo SiO is easily carried out2Control of the amount of layer 124 removed and suspected SiO2The removal amount of the cutting residue 116, the reaction product 117, and the residue on the layer 124 is controlled.
Further, according to the method of manufacturing an electronic device of the present embodiment, since the surface of the through hole 118 formed on the low dielectric constant interlayer insulating film 115 is exposed to the atmosphere of the mixed gas containing ammonia and hydrogen fluoride under a predetermined pressure, the generation of the product on the surface of the through hole 118 and the heating of the product cause vaporization, and the damaged layer 119 of the through hole 118 caused by the RIE treatment is removed, thereby preventing the occurrence of wiring delay due to the damaged layer 119.
According to the method of manufacturing an electronic device of the present embodiment, the surface of the through hole 118, from which the damaged layer 119 has been removed by heating to a predetermined temperature, is covered with the conductive shielding film 120, and contact between the surface of the through hole 118 and copper filled in the through hole 118 can be prevented, whereby diffusion of copper into the low-dielectric-constant interlayer insulating film 115 can be prevented.
In the method of manufacturing the electronic device in fig. 8, the photoresist layer 125 may be removed before filling copper into the through hole 118, or the photoresist layer 125 may be removed after filling copper into the through hole 118, and for example, when the conductive film 121 and the conductive shielding film 120 are polished by CMP, the CMP may be used simultaneously. Thereby improving the yield.
In the chemical mechanical polishing post-cleaning method or the method for manufacturing an electronic device according to the above-described embodiment, it is preferable that the upper layer of the insulating film or the pseudo SiO is removed2Before the layer formation, the wafer W is carried into the first IMS17, the surface shape of the insulating film is measured, and the CPU of EC89 determines the surface shape of the insulating film, the amount of removal of the upper layer with the insulating film, or pseudo SiO based on the measured surface shape2The predetermined relationship of the process condition parameters relating to the amount of layer removed determines target values such as the volume flow ratio of the hydrogen fluoride gas to the ammonia gas, the predetermined pressure in the chamber 38, and the heating temperature of the wafer W placed on the stage heater 51. Thus, the amount of removal of the upper layer of the insulating film can be accurately controlled, and further, the amount of removal of the cutting residue or the like on the surface of the insulating film or the pseudo SiO can be accurately controlled2The control of the amount of layer removal can also improve the manufacturing efficiency of the electronic device. Further, by removing the insulating film, it is possible to accurately control the amount of removal of the insulating film and accurately perform re-planarization when local etching of the insulating film by CMP is eliminated.
Further, whether or not to remove the upper layer of the insulating film again can be determined based on the difference in the surface shape of the insulating film before and after the removal of the upper layer of the insulating film or the like, and when the upper layer of the insulating film or the like is removed again, the CPU of EC89 can determine the volume flow ratio of the hydrogen fluoride gas to the ammonia gas or determine to polish again by CMP based on the above-described predetermined relationship, based on the surface shape of the insulating film after the removal of the upper layer of the insulating film or the like. This makes it possible to accurately control the amount of removal of the upper insulating film layer and the like again, and to accurately re-planarize the upper insulating film layer and the like.
The substrate processing apparatus to which the substrate processing method according to the present embodiment is applied is not limited to the parallel substrate processing apparatus in which two processing chambers are arranged in parallel to each other as shown in fig. 1, and may be a substrate processing apparatus in which a plurality of processing units as vacuum processing chambers for performing predetermined processing on the wafer W are arranged in a radial manner as shown in fig. 9 or 10.
Fig. 9 is a perspective view showing a schematic configuration of a first modification of a substrate processing apparatus applied to the substrate processing method according to the present embodiment. In fig. 9, the same components as those of the substrate processing apparatus 10 in fig. 1 are denoted by the same reference numerals, and the description thereof is omitted.
In fig. 9, the substrate processing apparatus 137 includes: a transfer unit 138 having a hexagonal shape in plan view; 4 processing units 139 to 142 radially disposed around the transfer unit 138; a loading unit 13; two load lock units 143, 144 disposed between the transfer unit 138 and the loading unit 13 and connecting the transfer unit 138 and the loading unit 13.
The internal pressure of the transfer unit 138 and each of the processing units 139 to 142 is maintained at vacuum, and the transfer unit 138 and each of the processing units 139 to 142 are connected by vacuum gate valves 145 to 148.
In the substrate processing apparatus 137, the internal pressure of the loading unit 13 is maintained at atmospheric pressure, while the internal pressure of the transfer unit 138 is maintained at vacuum. Therefore, the load lock units 143 and 144 each have a vacuum gate valve 149 and 150 at a connection portion with the transfer unit 138, and a large gate valve 151 and 152 at a connection portion with the loading unit 13, respectively, thereby constituting a vacuum preliminary transfer chamber whose internal pressure can be adjusted. The load lock units 143 and 144 each include wafer tables 153 and 154 on which the transferred wafer W is temporarily placed between the loading unit 13 and the transfer unit 138.
The transfer unit 138 has a structure disposed therein that allows the wafers W to be freely flexed and rotated or transferred between the respective load lock units 143, 144.
Each of the processing units 139 to 142 has a mounting table 156 to 159 for mounting a processed wafer W. Here, the processing unit 140 has the same configuration as the first processing unit 25 of the substrate processing apparatus 10, the processing unit 141 has the same configuration as the second processing unit 34, and the processing unit 142 has the same configuration as the third processing unit 36. Therefore, the RIE process may be performed on the wafer W in the processing unit 140, the COR process may be performed on the wafer W in the processing unit 141, and the PHT process may be performed on the wafer W in the processing unit 142.
In the substrate processing apparatus 137, the surface of the substrate is made to have a residual cut or pseudo SiO2The substrate processing method according to the present embodiment can be performed by loading the wafer W having the insulating film layer into the processing unit 141, performing the COR process, and then loading the wafer W into the processing unit 142, and performing the PHT process.
In the substrate processing apparatus 137, the processing unit 139 may be a film forming apparatus (CVD apparatus) for forming an insulating film or the like on the surface of the wafer W; and the processing unit 140 is a polishing apparatus that performs a CMP process on the wafer W. In this case, the transfer arm 155 can transfer the wafer W in the order of the processing units 139 to 142, and can continuously perform the film formation process, the CMP process, the COR process, and the PHT process on the wafer W. Thereby, the yield can be improved. Further, in the continuous process, since the wafer W is not carried out of the loading unit 13 and does not come into contact with the atmosphere, the generation of an oxide film on the insulating film can be prevented, and the adhesion of particles to the surface of the wafer W can be prevented, whereby the reliability of wiring of an electronic device manufactured from the wafer W can be improved.
The operations of the respective constituent elements of the substrate processing apparatus 137 are controlled by a system controller having the same configuration as that of the system controller of the substrate processing apparatus 10.
Fig. 10 is a plan view schematically showing a configuration of a second modification of the substrate processing apparatus to which the substrate processing method according to the present embodiment is applied. In fig. 10, the same components as those of the substrate processing apparatus 10 of fig. 1 and the substrate processing apparatus 137 of fig. 9 are denoted by the same reference numerals, and the description thereof will be omitted.
In fig. 10, a substrate processing apparatus 160 includes two processing units 161 and 162 added to the substrate processing apparatus 137 of fig. 9. Accordingly, the shape of the transfer unit 163 is different from the shape of the transfer unit 138 of the substrate processing apparatus 137. The additional two processing units 161 and 162 are connected to the transfer unit 163 via vacuum gate valves 164 and 165, respectively, and have stages 166 and 167 for placing the wafer W thereon.
Further, the transfer unit 163 has a transfer arm unit 168 constituted by two transfer arms of SCARA type. The transfer arm unit 168 moves along a guide rail 169 disposed in the transfer unit 163, and transfers the wafer W between the process units 139 to 142, 161, and 162 or the load lock units 143 and 144.
In the substrate processing apparatus 160, similarly to the substrate processing apparatus 137, the surface of the substrate is provided with a residual cut or pseudo SiO2The wafer W having the insulating film layer is carried into the processing unit 141 and subjected to COR processing, and is further carried into the processing unit 142 and subjected to PHT processing, whereby the substrate processing method according to the present embodiment can be performed.
In the substrate processing apparatus 160, similarly to the substrate processing apparatus 137, the processing unit 139 (or the processing unit 161) may be a film forming apparatus (CVD apparatus) for forming an insulating film or the like on the surface of the wafer W, and the processing unit 140 (or the processing unit 139) may be a polishing apparatus for performing a CMP process on the wafer W. In this case, the throughput can be improved, and the wiring reliability of the electronic device manufactured from the wafer W can be improved.
The operations of the respective constituent elements in the substrate processing apparatus 160 are controlled by a system controller having the same configuration as that of the system controller of the substrate processing apparatus 10.
The electronic devices include, in addition to so-called semiconductor devices, nonvolatile or large-capacity memory elements having thin films made of insulating metal oxides such as ferroelectric substances and high dielectric materials, particularly materials having perovskite-type crystal structures. Examples of the substance having a perovskite crystal structure include lead zirconate titanate (PZT), barium strontium titanate (PST), and strontium bismuth niobium tantalate (SBT).
The object of the present invention is achieved by supplying a storage medium, in which program codes of software for realizing the functions of the present embodiment are recorded, to EC89, and reading and operating the program codes stored in the storage medium by a computer (or CPU, MPU, or the like) of EC 89.
In this case, the program code itself read out from the storage medium realizes the functions of the above-described embodiment, and the program code and the storage medium storing the program code constitute the present invention.
Examples of the storage medium for supplying the program code include an optical disk such as a floppy (registered trademark) disk, a hard disk, a magneto-optical disk, a CD-ROM, a CD-R, CD-RW, a DVD-ROM, a DVD-RAM, a DVD-RW, and a DVD + RW, a magnetic tape, a nonvolatile memory card, and a ROM. Further, the program code may be downloaded via a network.
Further, the functions of the present embodiment may be realized not only by running the read program codes on a computer but also by performing part or all of actual processing by an OS (operating system) or the like running on the computer in accordance with instructions of the program codes, and the functions of the present embodiment may be realized by the processing.
The present invention also includes a case where the program code read out from the storage medium is written into a memory provided in a function expansion board inserted into a computer or a function expansion unit connected to the computer, and then, in accordance with an instruction of the program code, a CPU or the like executes a part or all of actual processing by operating an expansion function provided in the expansion board or the expansion unit, and the functions of the present embodiment are realized by the processing.
The program code may be configured by, for example, an object code, a program code executed by a decoding program, script data supplied to an OS, or the like.

Claims (20)

1. A method for processing a substrate having an insulating film exposed by chemical mechanical polishing, comprising:
an insulating film exposing step of exposing the exposed insulating film to a mixed gas atmosphere containing ammonia and hydrogen fluoride under a predetermined pressure; and
and an insulating film heating step of heating the insulating film exposed to the mixed gas atmosphere to a predetermined temperature.
2. The substrate processing method according to claim 1, wherein the exposed insulating film is a low dielectric constant insulating film.
3. The substrate processing method according to claim 1 or 2, wherein in the insulating film exposing step, a plasma-free etching treatment is performed on the substrate.
4. The substrate processing method according to claim 1 or 2, wherein in the insulating film exposing step, a dry cleaning process is performed on the substrate.
5. The substrate processing method according to any one of claims 1to 4, wherein a volume flow ratio of the hydrogen fluoride to the ammonia in the mixed gas is 1to 1/2, and the predetermined pressure is 6.7 x 10-2～4.0Pa。
6. The substrate processing method according to any one of claims 1to 5, wherein the predetermined temperature is 80 to 200 ℃.
7. The substrate processing method according to any one of claims 1to 6, further comprising a product formation condition determining step of measuring a shape of the exposed insulating film and determining at least one of a volume flow rate ratio of the hydrogen fluoride to the ammonia in the mixed gas and the predetermined pressure based on the measured shape.
8. The substrate processing method according to any one of claims 1to 7, wherein the exposed insulating film has a cutting residue generated by the chemical mechanical polishing.
9. The substrate processing method according to any one of claims 1to 7, wherein the exposed insulating film has a reaction product caused by a polishing agent used in the chemical mechanical polishing.
10. The substrate processing method according to any one of claims 1to 7, wherein the insulating film has a surface damage layer with a reduced carbon concentration.
11. A cleaning method after chemical mechanical polishing, performed on a substrate after a conductive film formed on an insulating film formed on a surface of the substrate is polished by chemical mechanical polishing, the cleaning method comprising:
an insulating film exposing step of exposing the insulating film exposed by the chemical mechanical polishing to an atmosphere of a mixed gas containing ammonia and hydrogen fluoride under a predetermined pressure; and
an insulating film heating step of heating the insulating film exposed to the mixed gas atmosphere to a prescribed temperature.
12. The post-chemical mechanical polishing cleaning method according to claim 11, further comprising an insulating film drying step of drying a surface of the exposed insulating film before exposing the exposed insulating film to the mixed gas atmosphere.
13. A method for manufacturing an electronic device, comprising:
a wiring forming step of forming a wiring made of a first conductive material on a first insulating film formed on a surface of a semiconductor substrate;
a second insulating film forming step of forming a second insulating film covering the wiring on the first insulating film;
a photoresist layer forming step of forming a photoresist layer of a predetermined pattern on the formed second insulating film;
a plasma processing and forming step of processing and forming a connection hole reaching the wiring on the second insulating film by plasma treatment using the formed photoresist layer;
an ashing step of removing the photoresist layer;
a connection hole filling step of forming a conductive film made of a second conductive material on the second insulating film and filling the second conductive material in the connection hole;
a conductive film polishing step of polishing the formed conductive film by chemical mechanical polishing;
a second insulating film exposing step of exposing the second insulating film exposed by the chemical mechanical polishing to a mixed gas atmosphere containing ammonia and hydrogen fluoride under a predetermined pressure; and
a second insulating film heating step of heating the second insulating film exposed to the mixed gas atmosphere to a prescribed temperature.
14. The method for manufacturing an electronic device according to claim 13, comprising:
a connection hole surface exposure step of exposing the surface of the connection hole formed by machining to a mixed gas atmosphere containing ammonia and hydrogen fluoride under a predetermined pressure; and
and a junction hole surface heating step of heating the surface of the junction hole exposed to the mixed gas atmosphere to a prescribed temperature.
15. The method for manufacturing an electronic device according to claim 14, further comprising: and a connection hole covering step of covering the surface of the connection hole heated to the predetermined temperature with a conductive barrier.
16. A method for manufacturing an electronic device, comprising:
a wiring forming step of forming a wiring made of a first conductive material on a first insulating film formed on a surface of a semiconductor substrate;
a second insulating film forming step of forming a second insulating film covering the wiring on the first insulating film;
a photoresist layer forming step of forming a photoresist layer of a predetermined pattern on the formed second insulating film;
a plasma processing and forming step of processing and forming a connection hole reaching the wiring on the second insulating film by plasma treatment using the formed photoresist layer;
a connection hole filling step of forming a conductive film made of a second conductive material on the second insulating film and filling the second conductive material in the connection hole;
a conductive film polishing step of polishing the photoresist layer and the formed conductive film by chemical mechanical polishing;
a second insulating film exposing step of exposing the second insulating film exposed by the chemical mechanical polishing to a mixed gas atmosphere containing ammonia and hydrogen fluoride under a predetermined pressure; and
a second insulating film heating step of heating the second insulating film exposed to the mixed gas atmosphere to a prescribed temperature.
17. A program for running a method of processing a substrate having an insulating film exposed by chemical mechanical polishing in a computer, the program comprising:
an insulating film exposing module for exposing the exposed insulating film to a mixed gas atmosphere containing ammonia and hydrogen fluoride under a predetermined pressure; and
and an insulating film heating module for heating the insulating film exposed to the mixed gas atmosphere to a predetermined temperature.
18. A program for running a cleaning method after chemical mechanical polishing on a substrate after a conductive film formed on an insulating film formed on a surface of the substrate is polished by chemical mechanical polishing on a computer, the cleaning method comprising:
an insulating film exposing module for exposing the insulating film exposed by the chemical mechanical polishing to a mixed gas atmosphere containing ammonia and hydrogen fluoride under a predetermined pressure; and
and an insulating film heating module for heating the insulating film exposed to the mixed gas atmosphere to a predetermined temperature.
19. A program for executing a manufacturing method of an electronic device in a computer, comprising:
a wiring forming module for forming a wiring made of a first conductive material on a first insulating film formed on a surface of a semiconductor substrate;
a second insulating film forming module for forming a second insulating film covering the wiring on the first insulating film;
a photoresist layer forming module for forming a photoresist layer of a predetermined pattern on the formed second insulating film;
a plasma processing and forming module for processing and forming a connection hole reaching the wiring on the second insulating film by plasma processing using the formed photoresist layer;
an ashing module removing the photoresist layer;
a connection hole filling module for forming a conductive film made of a second conductive material on the second insulating film and filling the second conductive material into the connection hole;
a conductive film polishing module for polishing the formed conductive film by chemical mechanical polishing;
a second insulating film exposure module that exposes the second insulating film exposed by the chemical mechanical polishing to a mixed gas atmosphere containing ammonia and hydrogen fluoride under a predetermined pressure; and
a second insulating film heating module that heats the second insulating film exposed to the mixed gas atmosphere to a prescribed temperature.
20. A program for executing a manufacturing method of an electronic device in a computer, comprising:
a wiring forming module for forming a wiring made of a first conductive material on a first insulating film formed on a surface of a semiconductor substrate;
a second insulating film forming module for forming a second insulating film covering the wiring on the first insulating film;
a photoresist layer forming module for forming a photoresist layer of a predetermined pattern on the formed second insulating film;
a plasma processing module for processing and forming a connection hole reaching the wiring on the second insulating film by plasma processing using the formed photoresist layer;
a connection hole filling module for forming a conductive film made of a second conductive material on the second insulating film and filling the second conductive material into the connection hole;
a conductive film polishing module for polishing the photoresist layer and the formed conductive film by chemical mechanical polishing;
a second insulating film exposure module that exposes the second insulating film exposed by the chemical mechanical polishing to a mixed gas atmosphere containing ammonia and hydrogen fluoride under a predetermined pressure; and
a second insulating film heating module that heats the second insulating film exposed to the mixed gas atmosphere to a prescribed temperature.
CNB2006100074782A 2005-02-14 2006-02-14 Method of processing and cleaning substrate, and method of and program for manufacturing electronic device Expired - Fee Related CN100449709C (en)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
JP2005036717 2005-02-14
JP2005036717 2005-02-14
JP2005278841 2005-09-26

Publications (2)

Publication Number Publication Date
CN1822327A true CN1822327A (en) 2006-08-23
CN100449709C CN100449709C (en) 2009-01-07

Family

ID=36923529

Family Applications (1)

Application Number Title Priority Date Filing Date
CNB2006100074782A Expired - Fee Related CN100449709C (en) 2005-02-14 2006-02-14 Method of processing and cleaning substrate, and method of and program for manufacturing electronic device

Country Status (1)

Country Link
CN (1) CN100449709C (en)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102371525A (en) * 2010-08-19 2012-03-14 中芯国际集成电路制造(上海)有限公司 Polishing device
CN107275282A (en) * 2011-03-17 2017-10-20 美光科技公司 Semiconductor structure and the method for forming semiconductor structure
CN109216186A (en) * 2017-07-06 2019-01-15 东京毅力科创株式会社 Engraving method and residue minimizing technology
CN111712905A (en) * 2018-02-23 2020-09-25 索尼半导体解决方案公司 Semiconductor device and method for manufacturing semiconductor device

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6541351B1 (en) * 2001-11-20 2003-04-01 International Business Machines Corporation Method for limiting divot formation in post shallow trench isolation processes
US6656824B1 (en) * 2002-11-08 2003-12-02 International Business Machines Corporation Low resistance T-gate MOSFET device using a damascene gate process and an innovative oxide removal etch
US7877161B2 (en) * 2003-03-17 2011-01-25 Tokyo Electron Limited Method and system for performing a chemical oxide removal process
US6905941B2 (en) * 2003-06-02 2005-06-14 International Business Machines Corporation Structure and method to fabricate ultra-thin Si channel devices

Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102371525A (en) * 2010-08-19 2012-03-14 中芯国际集成电路制造(上海)有限公司 Polishing device
CN102371525B (en) * 2010-08-19 2014-09-24 中芯国际集成电路制造(上海)有限公司 Polishing device
CN107275282A (en) * 2011-03-17 2017-10-20 美光科技公司 Semiconductor structure and the method for forming semiconductor structure
US10862030B2 (en) 2011-03-17 2020-12-08 Micron Technology, Inc. Semiconductor devices comprising silver
CN109216186A (en) * 2017-07-06 2019-01-15 东京毅力科创株式会社 Engraving method and residue minimizing technology
CN109216186B (en) * 2017-07-06 2023-08-18 东京毅力科创株式会社 Etching method and residue removing method
CN111712905A (en) * 2018-02-23 2020-09-25 索尼半导体解决方案公司 Semiconductor device and method for manufacturing semiconductor device

Also Published As

Publication number Publication date
CN100449709C (en) 2009-01-07

Similar Documents

Publication Publication Date Title
CN1822326A (en) Method of processing substrate, method of and program for manufacturing an electronic device
CN1976003A (en) Semiconductor device manufacturing method and substrate processing system
CN1290197C (en) Process for producing semiconductor integrated circuit device
CN1828841A (en) Method of surface processing substrate, method of cleaning substrate, and programs for implementing the methods
CN100352016C (en) Semiconductor device and its manufacturing method
CN100347832C (en) Method of producing electronic device material
CN1187792C (en) Method for cleaning porous body and manufacture the same, non-porous film or keyed lining
CN100342518C (en) Processed object processing apparatus, processed object processing method, pressure control method, processed object transfer method, and transfer apparatus
CN103403852B (en) The elimination of double; two load locks configuration and lift-off processing chamber
US20060189138A1 (en) Method of processing substrate, post-chemical mechanical polishing cleaning method, and method of and program for manufacturing electronic device
CN101075577A (en) Method of manufacturing semiconductor device
CN101055832A (en) Method of manufacturing semiconductor device
CN1806315A (en) Method for forming ti film and tin film, contact structure, computer readable storing medium and computer program
CN1624871A (en) Substrate treating apparatus and substrate treating method
KR20090035578A (en) Cluster tool for advanced front-end processing
CN1263674C (en) Production device and production method for silicon-based structure
CN101047126A (en) Method of repairing damaged film having low dielectric constant, semiconductor fabricating device and storage medium
CN1516900A (en) Semiconductor integrated circuit apparatus and its manufacturing method
CN1873914A (en) Substrate processing method, substrate processing program and storage medium
CN1277289C (en) Semiconductor manufacturing device, semiconductor manufacturing system and substrate processing method
CN1929096A (en) Plasma ashing method
CN1619793A (en) Method for fabricating semiconductor device with fine patterns
CN101030525A (en) Substrate processing apparatus, method for modifying substrate processing conditions and storage medium
TWI398920B (en) Surface treatment of substrates
CN1822327A (en) Method of processing and cleaning substrate, and method of and program for manufacturing electronic device

Legal Events

Date Code Title Description
C06 Publication
PB01 Publication
C10 Entry into substantive examination
SE01 Entry into force of request for substantive examination
C14 Grant of patent or utility model
GR01 Patent grant
CF01 Termination of patent right due to non-payment of annual fee

Granted publication date: 20090107

Termination date: 20210214

CF01 Termination of patent right due to non-payment of annual fee