CN1819137A - Manufacture method for semiconductor device having field oxide film - Google Patents
Manufacture method for semiconductor device having field oxide film Download PDFInfo
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- CN1819137A CN1819137A CN 200610006799 CN200610006799A CN1819137A CN 1819137 A CN1819137 A CN 1819137A CN 200610006799 CN200610006799 CN 200610006799 CN 200610006799 A CN200610006799 A CN 200610006799A CN 1819137 A CN1819137 A CN 1819137A
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Abstract
To provide a method of forming a field oxide film capable of simply and accurately forming a channel stopper region separately from an element hole immediately under the field oxide film. On the principal surface of a silicon substrate, a side spacer made of silicon nitride is formed on the side wall of a lamination including a silicon oxide film, a silicon nitride film and a silicon oxide film. Thereafter, a channel stopper ion doped region is formed by implanting impurity ions by using as a mask the lamination, side spacer and resist layer. After the resist layer and side spacer are removed, a field oxide film is formed through selective oxidation using the lamination as a mask, and a channel stopper region corresponding to the ion doped region is formed. After the lamination is removed, a circuit device such as a MOS type transistor is formed in each device opening of the field oxide film.
Description
Technical field
The present invention relates to a kind of formation method that is applicable to the field oxide film (dielectric film) that metal-oxide semiconductor (MOS) (MOS) type integrated circuit (IC) is made, and more specifically, relate to the technology that a kind of formation only is positioned at below the field oxide film and the raceway groove that separates with device opening stops to distinguish.
Background technology
Known use Fig. 7 A is to form the conventional method (for example, with reference to JP-A-HEI-5-136123) with field oxide film that the raceway groove that only is positioned at below the field oxide film and separates with device opening stops to distinguish to the method for the side direction separator shown in the 7C.
In the technology shown in Fig. 7 A, on the surface of p type silicon substrate 1 by thermal oxidation with after forming silicon oxide film 2, on silicon oxide film 2, form silicon nitride film 3 by chemical vapor deposition (CVD), and on silicon nitride film 3, form silicon oxide film 4 by CVD.By adopting the dry etching of resist layer as mask, the lamination of silicon nitride film 3 and silicon oxide film 4 is patterned to the device opening pattern of expectation.
Then, on silicon oxide film 2, form silicon oxide film by CVD, cover the lamination of residual silicon nitride film 3 and silicon oxide film 4, and eat-back this silicon oxide film by anisotropic etching afterwards, to form side separator 4a on silicon oxide film, this side separator is formed and is covered with closed ring the sidewall of the lamination of silicon nitride film 3 and silicon oxide film 4 by the remainder of silicon oxide film.Lamination M by using silicon oxide film 2, silicon nitride film 3 and silicon oxide film 4 and the lamination of silicon oxide film 2 and side separator 4a are as mask, with boron ion B
+Inject the surface of substrate 1, stop ion doped region 5a in the external zones of side separator 4a, to form raceway groove.By the hydrofluoric acid etch that comprises chemical composition and remove silicon oxide film 4, side separator 4a and the zone (by the district shown in the dotted line) of the silicon oxide film 2 that do not covered by silicon nitride film 3.Therefore, the surface of substrate 1 that is not coated with the lamination of remaining silicon oxide film 2 and silicon nitride film 3 is exposed, and the surface of ion doped region 5a also is exposed.
In the technology shown in Fig. 7 B, the lamination by using silicon oxide film 2 and silicon nitride film 3 forms the field oxide film 6 with device opening 6A as the selective oxidation of mask on substrate 1 surface.Heat treatment formation in this technology and the corresponding to p type of ion doped region 5a raceway groove stop to distinguish 5.Raceway groove stops to distinguish 5 and is arranged on below the field oxide film 6 and with device opening 6A and separates.
In the technology shown in Fig. 7 C, silicon nitride film 3 and silicon oxide film 2 is by etching successively and remove to expose the surface portion of the substrate 1 among the device opening 6A.Silicon face among the device opening 6A by thermal oxidation to form by the film formed gate insulating film 7 of silica, the gate electrode layer of being made by doped polycrystalline silicon etc. 8 is formed on the gate oxidation films 7 subsequently, and by use field insulating membrane 6 and gate electrode layer 8 as the mask implanting impurity ion to form n+ type source/drain region 9S and 9D.Therefore in device opening 6A, form the MOS transistor npn npn.
According to above-mentioned field oxide film formation method, raceway groove stops to distinguish 5 and forms below field insulating membrane 6 and separate with device opening 6A.Therefore, because the MOS transistor npn npn is formed among the device opening 6A shown in Fig. 7 C, so (a) pn knot will can not be formed on source/drain region 9S and 9D and raceway groove and stop to distinguish between 5, thereby the pn junction breakdown voltage can be improved and junction capacitance can be reduced, (b) along perpendicular to raceway groove longitudinally the channel width of direction (direction that between source/drain region, flows along electric current) will can not stopped to distinguish 5 and dwindle by raceway groove, thereby favourable part is to avoid the variation (so-called shallow channel effect) by the caused transistor characteristic of channel width that narrows down.
Yet, according to above-mentioned field oxide film formation method, because the hydrofluoric acid etch by containing chemical composition in the technology shown in Fig. 7 A is also removed silicon oxide film 4, side separator 4a and the part of the silicon oxide film 2 that indicated by dotted line, so the silicon oxide film 2 below only being arranged in silicon nitride film 3 forms undercutting.For fear of like this, for example field oxide film formation method (for example, with reference to JP-A-HEI-5-136123) shown in Fig. 8 A and 8B has been proposed.
In the technology shown in Fig. 8 A, similar with according to above-mentioned Fig. 7 A, after silicon oxide film 2 and silicon nitride film 3 were formed on the p type silicon substrate 1 successively, silicon nitride film 3 was patterned to the device opening pattern of expectation.On silicon oxide film 2, form silicon oxide film 4A by CVD, cover residual silicon nitride film 3.Silicon oxide film 4A forms the closed ring part 4b of the sidewall of the silicon nitride film 3 that has on the capping oxidation silicon fiml 2.Afterwards, the lamination of lamination M ' by using silicon oxide film 2, silicon nitride film 3 and silicon oxide film 4A and silicon oxide film 2 and the closed ring part of silicon oxide film 4A is as mask, injects boron ion B via the lamination of silicon oxide film 2 and 4A
+To the superficial layer of substrate 1, form raceway groove with peripheral region and stop ion doped region 5a at the closed ring part 4b of silicon oxide film 4A.
In the technology shown in Fig. 8 B, carry out selective oxidation by the lamination that uses silicon oxide film 2, silicon nitride film 3 and silicon oxide film 4A as mask, on substrate 1 surface, to form field oxide film 6 with device opening 5a.Heat treatment formation in this technology and the corresponding to p type of ion doped region 5a raceway groove stop to distinguish 5.Raceway groove stops to distinguish 5 and is arranged on below the field oxide film 6 and with device opening 6A and is separated.Afterwards, silicon oxide film 4A, silicon nitride film 3 and silicon oxide film 2 are removed successively, thereby form the MOS transistor npn npn to be similar to the method shown in Fig. 7 C in device opening 6A.
According to reference Fig. 8 A and the described field oxide film of 8B formation method, because after the ion implantation technology shown in Fig. 8 A, do not eliminate deoxidation silicon fiml 2 and 4A, so can suppress increase and variation by the caused beak of the undercutting of silicon oxide film 2 (bird ' s break) length.
Known raceway groove stops to distinguish the formation method after forming field oxide film by thermal oxidation, the oxidation mask that is used for thermal oxidation by employing is as the ion injecting mask, carrying out ion via field oxide film injects, stop ion doped region (for example, with reference to JP-A-HEI-6-5588 and JP-A-HEI-6-85053) to form raceway groove.In this case, in order to suppress the formation of beak, on the oxide mask sidewall, form the sidewall (adopting so-called lateral seal localized oxidation of silicon (LOCOS) method) of making and having about 50nm thickness by silicon nitride.Yet,, be difficult to form the raceway groove that separates with the device opening of field oxide film and stop ion doped region owing to only have sidewall.
Stop to distinguish the formation method according to the described raceway groove of JP-A-HEI-6-5588, before ion implantation technology, be stacked in the sidewall of being made and being had about 50nm thickness on the silicon nitride sidewall by polysilicon by formation, raceway groove stops ion doped region and can form with device opening and separate.Stop to distinguish the formation method according to the described raceway groove of JP-A-HEI-6-85053, lamination by using silicon oxide film, polysilicon film and the silicon nitride film stack gradually from the bottom is as oxide-film, and by the side of the polysilicon film in the oxidation oxide-film in thermal oxidation technology, raceway groove stops ion doped region and can form with device opening and separate.
Another example of conventional field oxide film formation method be known as Fig. 9 A to the employing resist layer shown in the 9C as ion injecting mask (for example, with reference to JP-A-2000-12789).
In the technology shown in Fig. 9 A, after forming n type well region 1a and p type well region 1b on the silicon substrate first type surface, on this first type surface, form silicon oxide film 2 by thermal oxidation, and on silicon oxide film 2, form silicon nitride film 3 by CVD.By photoetching process, on the silicon nitride film on the well region 1a 3, form resist layer 4B according to the device opening pattern of expecting.After this, by using resist layer 4B as mask, by dry etching composition silicon nitride film 3, to stay the silicon nitride film 3 that has corresponding to the pattern of resist layer 4B.
Then, in the technology shown in Fig. 9 B, on silicon oxide film 2, form resist layer 4C, expose resist layer 4B and near silicon oxide film part, and cover p type well region 1b by photoetching process.By using resist layer 4B and 4C as mask, inject n type foreign ion to well region 1a, stop ion doped region 5b to form raceway groove.Remove resist layer 4B and 4C afterwards.
In the technology shown in Fig. 9 C, carry out selective oxidation by the lamination that uses silicon oxide film 2 and silicon nitride film 3 as mask, on the upper surface of substrate 1, to form field oxide film 6.Therefore field oxide film 6 forms the device opening 6A that has corresponding to silicon nitride film 3.Heat treatment in this process stops to distinguish 5B at the superficial layer formation n of well region 1a type raceway groove, and 5b is consistent with ion doped region.Raceway groove stops to distinguish 5B and forms and have the inner that is arranged in device opening 6A.After this, previous by adopting with reference to the described method of Fig. 7 C, in device opening 6A, form the MOS transistor npn npn.
According to reference Fig. 7 A to the field oxide film formation method shown in the 7C, with the technology shown in Fig. 7 A as injecting boron ion B with 100keV or above acceleration energy
+Common ion implantation technology, the mask functions of the lamination of silicon oxide film 2 and side separator 4a is not enough (may have ion penetration).Need the extra resist layer of covering lamination M and side separator 4a that forms to strengthen the ion injecting mask.This is because the ion resistance ability of the silicon oxide film of formation side separator 4a is low.Same in the ion implantation technology shown in Fig. 8 A, the mask functions of silicon oxide film 2 and closed ring part 4b is not enough.Need the extra resist layer of covering lamination M ' and closed ring part 4b that forms to strengthen the ion injecting mask.If additionally form Etching mask to strengthen the ion injecting mask, the problem that resist for example peeled off and hang down the manufacturing productive rate may take place so.
According to above-mentioned field oxide film formation method with reference to Fig. 8 A and 8B, except that above-mentioned with reference to Fig. 7 A to the field oxide film formation method shown in the 7C, because the thermal oxidation of the lamination by silicon oxide film 2 and 4A prolongs the process time.
As mentioned above, the raceway groove that carries out the ion injection via field oxide film after forming field oxide film stops to distinguish the formation method, because ion inject to be what the thick field oxide film by about 600nm carried out, so need use to have the ion implantor of 200keV or above costliness.
,, be formed among the device opening 6A and extend with reference to the field oxide film formation method of Fig. 9 A according to above-mentioned, so can not obtain aforesaid operations effect (a) and (b) because raceway groove stops to distinguish 5B though technology is simple to 9C.
Summary of the invention
An object of the present invention is to provide a kind of new method, semi-conductor device manufacturing method, it can be easily and forms accurately and only be positioned at below the field oxide film and the raceway groove that separates with device opening stops the district.
A technical problem that will solve according to the present invention provides first method, semi-conductor device manufacturing method, comprising:
The preparation silicon substrate, it has the district of at least one a kind of conduction type;
On the first type surface of described silicon substrate from the bottom according to mentioned sequential cascade first silicon oxide film, silicon nitride film and second silicon oxide film;
According to the device opening pattern of expectation, composition comprises the described silicon nitride film in described first silicon oxide film, described silicon nitride film and described second silicon oxide film and the lamination of described second silicon oxide film at least;
The side separator of described lamination one side is made and is covered in formation by silicon nitride;
By adopting described lamination and described side separator as mask, inject the first type surface of the foreign ion of described first kind of conduction type to described silicon substrate, stop ion doped region to form raceway groove; With
After removing described side separator, by adopting of the selective oxidation of described lamination as mask, formation has the field oxide film corresponding to the device opening of the described lamination on described silicon substrate first type surface, and the raceway groove of the described a kind of conduction type of formation stops the district on the basis of described ion doped region.
According to first method, semi-conductor device manufacturing method, lamination by adopting silicon nitride film and second silicon oxide film at least and the side separator that covers the silicon nitride of lamination side form raceway groove as the mask implanting impurity ion and stop ion doped region.After removing the side separator of lamination, form the field oxide film that has corresponding to the device opening of lamination by adopting lamination as the selective oxidation of mask, and stop the district by ion injection formation raceway groove.Owing to inject by adopting the side separator to carry out ion, so raceway groove stops to distinguish only to be formed on below the field oxide film and with device opening separating as mask.Like this because the side separator makes by having the silicon nitride that high ion suppresses ability, and the silicon nitride in the lamination when removing the side separator by lateral erosion, can make raceway groove stop the district and separate with device opening reliably.Therefore, do not need to adopt extraly resist layer and simplify technology.Since removing the side separator after by adopting lamination to select etching, so can in the short relatively process time, form field oxide film and raceway groove stops to distinguish as mask.
In first method, semi-conductor device manufacturing method, second silicon oxide film can be by the formed silicon oxide film of the thermal oxidation that is deposited on the polysilicon film on the silicon nitride film.The ion that therefore can improve second silicon oxide film suppresses ability, and prevents because the faulty goods that ion penetration caused.Like this, before polysilicon film is deposited on the silicon nitride film, can make the silicon nitride film densification by heat treatment.Therefore can improve the tight adhesion between polysilicon film and the silicon nitride film and prevent since polysilicon the faulty goods that causes such as peel off.
In first method, semi-conductor device manufacturing method, second silicon oxide film can be to be deposited on the silicon nitride film and by subsequently the heat treatment compact silicon oxide film that becomes.The faulty goods that therefore can improve the ion inhibition ability of second silicon oxide film and prevent to cause owing to ion penetration.
According to first method, semi-conductor device manufacturing method, the side separator of the silicon nitride of lamination by adopting silicon nitride film and second silicon oxide film at least and the side that covers lamination forms raceway groove as the mask implanting impurity ion and stops ion doped region.After removing the side separator of lamination, form the field oxide film that has corresponding to the device opening of lamination by adopting lamination as the selective oxidation of mask, and stop the district by ion injection formation raceway groove.Therefore, can be easily and form accurately the raceway groove that separates with device opening stop the district.
According to a further aspect in the invention, provide the manufacture method of second semiconductor device, comprised the steps:
The preparation silicon substrate, it has first type surface and has a kind of conduction type at least in device formation district;
On the first type surface of described silicon substrate, form and cover the oxidation mask material layer that described device forms the district;
The first device opening pattern according to form district's part corresponding to described device forms first resist layer on described oxide mask material layer;
By adopting described first resist layer to inject the first type surface of the foreign ion of described a kind of conduction type, be formed for first ion doped region that raceway groove stops to described silicon substrate as mask;
After described first ion doped region forms, described first resist layer of etching isotropically, thus reduce the thickness and the planar dimension of described first resist layer with scheduled volume;
After described isotropic etching, come the described oxide mask material layer of composition by adopting described first resist layer as the etching of mask, to form first oxide mask that forms by described oxide mask material layer; With
After removing described first resist layer, on the first type surface of described silicon substrate, form the field oxide film have corresponding to the device opening of described first oxidation mask by the selective oxidation of adopting described first oxide mask, and first raceway groove that forms corresponding to described a kind of conduction type of described first ion doped region stops the district.
According to second method, semi-conductor device manufacturing method, stop ion doped region as the foreign ion injection formation raceway groove of mask by adopting resist layer.At resist by after isotropically thereby etching reduces its thickness and lateral dimension with scheduled volume, by adopt resist layer as mask etching and composition oxide mask layer to form oxide mask.After removing resist layer, form the field oxide film that has corresponding to the device opening of oxide mask by the selective oxidation of adopting oxide mask, and stop the district by ion injection formation raceway groove.Preestablish scheduled volume by the distance between stopping to distinguish according to device opening and raceway groove, raceway groove stop that the district can accurately only be formed on below the field oxide film and with the device opening predetermined distance apart.
According to another aspect of the invention, provide the 3rd method, semi-conductor device manufacturing method, comprised the steps:
Preparation silicon substrate, its device with first type surface and a kind of conduction type form the district and with a kind of well region of conductivity type opposite conduction type;
On the first type surface of described silicon substrate, form oxide mask material layer and the well region that covering device forms the district;
According to the first device opening pattern of a part that forms the district corresponding to device with corresponding to the second device opening pattern of the part of well region, on the oxide mask material layer, form first and second resist layers;
By adopting first and second resist layers as mask, the foreign ion that injects a kind of conduction type via the oxidation mask material layer is to the first type surface of silicon substrate and be formed for first ion doped region that raceway groove stops;
After forming first ion doped region, thereby isotropically etching first and second resist layers reduce the thickness and the planar dimension of first and second resist layers with scheduled volume;
Form the 3rd resist layer that covering device forms the district and first resist layer, and formation does not cover and is present in the well region as the ion doped region of the part of first ion doped region and covers second oxidation mask and the 4th resist layer of a side of second resist layer;
By adopting third and fourth resist layer as mask, the foreign ion that injects films of opposite conductivity is to well region, is present in well region by compensation and is formed for second ion doped region that raceway groove stops as the ion doped region of the part of first ion doped region;
After removing the 3rd and the 4th resist layer and first and second resist layer, by adopting the selective oxidation of first and second oxidation masks, on the first type surface of silicon substrate, form the field oxide film that has corresponding to first and second device opening of first and second oxidation masks, first raceway groove stops the district and has a kind of conduction type and corresponding to first ion doped region, and second raceway groove stops that the district has films of opposite conductivity and corresponding to second ion doped region
In the 3rd method, semi-conductor device manufacturing method, when a kind of conduction type was the p type, preparation had the silicon substrate that p type device forms district and n type well region.Form in the district at p type device, similar with first method, semi-conductor device manufacturing method, comprise technology, the technology that forms first ion doped region, the technology that reduces the first resist layer thickness and planar dimension that form oxidation mask material layer technology, form first resist layer, form the technology of first oxidation mask and form the technology of the 3rd resist layer technology.In n type well region, carry out forming the common technology in district for the type device, comprise technology, the technology that forms second resist layer that forms the oxidation mask material layer, the technology that forms first ion doped region, the thickness that reduces by second resist layer and planar dimension technology, form the technology of second oxidation mask and form the technology of the 4th resist layer.
In the technology that forms third and fourth resist layer, the 3rd resist layer forms covering device and forms the district and first resist layer, wherein the 4th resist layer forms not cover and is present in the ion doped region of n type well region as first an ion doped region part, and covers the side of second oxidation mask and second resist layer.By using third and fourth resist layer as mask, inject n type foreign ion to n type well region, be present in the n type well region ion doped region by compensation as the part of first ion doped region, be formed for second ion doped region that raceway groove stops.
After removing third and fourth resist layer and first and second resist layers, by using the selective oxidation of first and second oxidation masks, on the first type surface of silicon substrate, form the field oxide film that has corresponding to first and second device opening of first and second oxidation masks, p type first raceway groove stops the district corresponding to first ion doped region, and n type second raceway groove stops the district corresponding to second ion doped region.First raceway groove stops to distinguish accurately only to be formed on below the field oxide film and with first device opening separating, and wherein second raceway groove stops to distinguish accurately only to be formed on below the field oxide film and with second device opening separating.
According to second method, semi-conductor device manufacturing method, form in the district at the device of first conduction type, raceway groove stops the district can be easily and only be formed on below the field oxide film and with device opening accurately and separate.Because number of processes is few, manufacturing output can improve and can realize that cost reduces.
According to the 3rd method, semi-conductor device manufacturing method, form in the well region of district and films of opposite conductivity at a kind of device of conduction type, raceway groove stops to distinguish can be easily and only be formed on below the field oxide film and with device opening accurately and separate.Because the increase of number of processes can be inhibited, manufacturing output can improve and can realize that cost reduces.
Description of drawings
Figure 1A is the sectional view that illustrates according to the MOS type IC manufacture method main technique of first embodiment of the invention to 1J;
Fig. 2 is the improved sectional view that side separator part is shown;
Fig. 3 A is the sectional view that illustrates according to the main technique of the manufacture method of the n channel MOS transistor npn npn of the CMOS type IC of second embodiment of the invention to 3H;
Fig. 4 is illustrated in the resist etch process shown in Fig. 3 C, the figure of relation between process time and the resist etch quantity (withdrawal amount);
Fig. 5 illustrates the figure that concerns between resist etch quantity and the drain junction puncture voltage;
Fig. 6 A is that the sectional view to the main technique of the manufacture method of the p channel MOS transistor npn npn of the described CMOS type of 3H IC with reference to Fig. 3 A is shown to 6H;
Fig. 7 A is the sectional view that the example of conventional field oxide film formation method is shown to 7C;
Fig. 8 A and 8B are the sectional views that another example of conventional field oxide film formation method is shown;
Fig. 9 A is the sectional view of an example again that conventional field oxide film formation method is shown to 9C.
Embodiment
Figure 1A shows the manufacture method of employing according to metal-oxide semiconductor (MOS) (MOS) the type integrated circuit (IC) of the field oxide film formation method of first embodiment of the invention to 1J.To the technology to 1J corresponding to Figure 1A be described successively.
In the technology shown in Figure 1A, p type well region 12, n type well region 14 and 16 are formed on the first type surface of p type silicon substrate 10 side by side by known method.N type well region 14 and 16 can form a well region around p type well region 12.After well region 12 to 16 forms, on the first type surface of substrate 10, form silicon oxide film (stress relaxation pad oxide film) 18 by thermal oxidation.The thickness of silicon oxide film 18 can be for example from 30nm in the 40nm scope.On silicon oxide film 18, form silicon nitride film 20 by CVD, and on silicon nitride film 20, form polysilicon film 22 by CVD.The thickness of polysilicon film 22 is determined by the thickness of considering ion implanting conditions and silicon nitride film 20.For example, if boron ion B
+Acceleration energy with 100keV injects, and the thickness of silicon nitride film 20 can be 170nm so, and the thickness of polysilicon film 22 can be that 200nm is to 300nm (preferred 250nm).
Before polysilicon film 22 is deposited on the silicon nitride film 20, preferably make silicon nitride film 22 densifications by the heat treatment under oxidizing atmosphere.This heat treatment makes the film quality densification of silicon nitride film 20, and forms very thin silicon oxide film on the surface of silicon nitride film 20.Therefore, when polysilicon film 22 is deposited on the silicon nitride film, can improve the tight adhesion between silicon nitride film 20 and the polysilicon film 22, therefore prevent owing to polysilicon peels off the defective that causes.
Then, in the technology shown in Figure 1B, the oxidation polysilicon film 22 by thermal oxidation is to form silicon oxide film 24.For example, can adopt vertical furnace at 950 ℃ of temperature and O
2/ H
2The gas flow rate of=13.3/7 (l/min) carries out thermal oxidation.Because polysilicon film 22 oxidations by thermal oxidation have the film quality that high ion suppresses ability and high compaction so silicon oxide film 24 can form.As silicon oxide film 24, can adopt by CVD and be deposited on silicon oxide film on the silicon nitride film 20.Perhaps, can adopt and be deposited on the silicon nitride film 20 and by the heat treatment compact silicon oxide film that becomes.If adopt by the CVD deposit and adopt the heat treatment compact silicon oxide film that becomes subsequently, this silicon oxide film has high ion and suppresses ability so.
In the technology shown in Fig. 1 C, device opening (the active area formation opening) pattern according to predetermined forms resist film 26 by photoetching process on silicon oxide film 24.In the technology shown in Fig. 1 D, by adopting resist film 26 as mask, by the stack membrane of etching composition silicon oxide film 24, silicon nitride film 20 and silicon oxide film 18, to form the mask stack 27 that forms by the remainder of stack membrane ( film 18,20 and 24 remainder).
Can adopt dry etching composition silicon oxide film 24.To this composition, can adopt under the condition of several mTorr pressure and adopt Cl
2/ O
2, CF
4Gas or SF
6The mist of gas is as the microwave plasma etching (2.45MHz frequency) or electron cyclotron resonace (ECR) plasma etching of etching gas.Can adopt dry etching composition silicon nitride film 20.To this composition, can adopt under the 160mTorr pressure conditions and adopt CF
4/ CHF
4Mist as radio frequency (RF) plasma etching of etching gas.Like this, RF power can be made as about 700W, and frequency can be made as 13.56MHz.
In the composition of silicon oxide film 18, preferred employing can keep the substrate surface cleaning and etching with respect to the high etching selection rate of silicon nitride film 20 and silicon substrate 10 is provided, and does not adopt absorption impurity or forming the etching that the substrate surface of the device of MOS transistor npn npn for example stays breakable layer.For example, can be by adopting dilute hydrofluoric acid (HF+NH
4F+ (H
2O)) etc. wet etching comes etching oxidation silicon fiml 18.Can stay silicon oxide film 18 and composition not.If stay silicon oxide film 18, the problem of being infected with on the silicon substrate can not take place so, and can be expected at the advantage of raceway groove protection in the ion implantation process.
After etching, pass through O
2Or O
3Resist layer 26 is removed in ashing (ashing).Adopt the chemical treatment and the pure water of sulfuric acid+hydrogen peroxide to handle successively, carry out drying then.In the technology shown in Fig. 1 E, form on substrate 10 surfaces by low pressure chemical vapor deposition etc. and to cover the silicon nitride film 28 that lamination 27 forms the side separators.The thickness of silicon nitride film 28 can be 100nm to 250nm (preferred 120nm to 180nm, more preferably 150nm).When forming silicon nitride film 28, can adopt to use to contain silane gas (SiH
4, Si
2H
8Deng) or the gas that contains tetraethoxysilane (TEOS) as source of the gas and oxygen (O
2) or ozone (O
3) and the mist of NOx as the mist pyrolysis-type CVD (pylolytic CVD) of reacting gas.Can adopt the plasma-enhanced CVD that uses these gases, perhaps can adopt for example ecr plasma of high-density plasma CVD.Adopt high-density plasma CVD, can form film at low temperatures fast.
Then, eat-back silicon nitride film 28, to form side separator 28a by anisotropic dry etch.Side separator 28a is formed by the remainder of silicon nitride film 28, and forms the closed ring of the side that covers substrate 10 lip-deep laminations 27.For anisotropic dry etch, can adopt CF with 1: 2 mixing ratio
4And CHF
3Mist as etching gas, under the pressure conditions of 160mTorr, carry out the RF plasma etching.Like this, RF power can be made as about 700W, and frequency can be made as 13.56MHz.Side separator 28a can be made as about 150nm along the thickness of the direction of the side of leaving lamination 27.As mentioned above, if stayed silicon oxide film 18 in the technology shown in Fig. 1 D, 18 of silicon oxide films remain in below the side separator 28a so.Like this, the only silicon oxide film 18 below side separator 28a outside the remainder can be removed or can stay (if stay silicon oxide film, the advantage that is obtained is same as described above so).
In the technology shown in Fig. 1 F, on the first type surface of substrate 10, form resist layer 30 by photoetching process, cover n type well region 14 and 16 and expose p type well region 12.By adopting resist layer 30, lamination 27 and side separator 28a as mask, boron ion B
+Be injected into the superficial layer of p type well region 12, stop ion doped region 32 to form raceway groove.Ion implanting conditions can be the acceleration energy and 1.5 * 10 of 100keV
13Cm
-2Dosage.Ion doped region 32 forms closed ring in the surrounding zone of side separator 28a, and separates the thickness (for example about 150nm) corresponding to side separator 28a with the side of lamination.
In the technology shown in Fig. 1 G, resist layer 30 and side separator 28a are removed.For example, can remove side separator 28a by adopting 160 ℃ hot phosphoric acid, about 50 minutes isotropism wet etching.The silicon nitride film 20 that constitutes lamination 27 is also bounced back by lateral erosion, thereby increases from the distance of ion doped region 32.In order to alleviate the influence of lateral erosion, by carrying out isotropic dry etch under the using plasma etching machine condition below:
Gas flow rate: CF
4/ O
2=100sccm is to 200sccm (preferred 150sccm)
Pressure: 0.5Torr is to 1Torr
RF power: 250W is to 500W
Cathode temperature: 80 ℃.
O
2With CF
4The volume ratio of comparing is 8% to 15%.O
2With CF
4The gas flow rate ratio of mist be that 100sccm is to 200sccm (preferred 150sccm).
Under these conditions, the etch-rate of silicon nitride is about 80nm/min.
In order to improve the side etching quantity controllability of silicon nitride film 20, in the dry etching of side separator 28a, at first carry out the anisotropic dry etching.The etched condition of anisotropic dry can be:
Gas flow rate: CHF
3/ CF
4/ N
2=60 to 100/60 to 100/10 to 20sccm (preferred 90/90/15sccm)
Pressure: 300mTorr is to 500mTorr
RF power: 500W is to 700W.
Can adopt parallel-plate plasma etching machine etc. as etching machine.When the thickness of side separator 28a during, carry out above-mentioned isotropic etching by anisotropic dry etching attenuation.Like this, because after the anisotropic dry etching, carry out isotropic etching, so the process time of isotropism dry etching shortens and the side etching quantity of silicon nitride film 20 diminishes.
Fig. 2 shows the example of the change of side partitioned portion.In Fig. 2, with components identical shown in Fig. 1 E etc. by same reference numerals and symbolic representation, and omitted its description.This exemplary characteristics is between side separator 28a and lamination 27 and p type well region 12 silicon oxide film 28b to be set.
In forming side separator shown in Figure 2, in the technology shown in Fig. 1 E, at silicon nitride film 28 in the technology shown in Fig. 1 E before the deposit, silicon oxide film 28b deposit for 30nm for example to 60nm (preferably 50nm) thickness.Afterwards, being similar to above-mentioned mode, silicon nitride film 28 deposits for 90nm for example to 120nm (preferred 100nm) thickness.Silicon nitride film 28 also as required deposit for 120nm for example to 150nm (preferred 130nm) thickness.Afterwards, to be similar to above-mentioned mode, the lamination of silicon oxide film 28b and silicon nitride film 28 is etched back to form side separator 28a and stay silicon oxide film 28b between side separator 28a and lamination 27 and p type well region 12.
According to side separator structures shown in Figure 2, though side separator 28a in the technology shown in Fig. 1 G by wet etching and by isotropically etching, so because the existence of silicon oxide film 28b, silicon nitride film 20 will can be by lateral erosion.Therefore improved dimensional controllability.After removing side separator 28a, be easy to only remove silicon oxide film 28b by wet etching etc.
In the technology shown in Fig. 1 H,, form the field oxide film 34 that has at substrate 10 lip-deep device opening 34A by adopting the selective oxidation of lamination 27 as mask.Heat treatment in this technology only is formed on below the field oxide film 34 and the p type raceway groove that separates with device opening 34A stops to distinguish 36, and is consistent with ion doped region 32.For example,, can under 1000 ℃ of temperature, adopt the horizontal proliferation stove to carry out means of wet thermal oxidation for selective oxidation, and can form have 350nm to the silicon oxide film of 1000nm (preferred 400nm to 600nm, more preferably 500nm) thickness as field oxide film 34.
In the technology shown in Fig. 1 I, the silicon oxide film 24, silicon nitride film 20 and the silicon oxide film 18 that constitute lamination 27 are removed successively.Can remove silicon oxide film 24 and 18 by the wet etching that adopts dilute hydrofluoric acid, and can adopt hot phosphoric acid about 60 minutes wet etching under 160 ℃ of temperature to remove silicon nitride film 20.
On the silicon face of the silicon oxide film 18 in removing device opening 34A, by thermal oxidation form have 30nm to the silicon oxide film of 50nm thickness as sacrifice oxide film.Can be at dried O
2Carry out thermal oxidation 950 ℃ of temperature in (or dry air).Adopting after hydrofluoric acid removes silicon oxide film as sacrifice oxide film, by forming silicon oxide film on the silicon face of thermal oxidation in device opening 34A as gate insulating film 38.Can be at dried O
2In under 950 ℃ of temperature, carry out thermal oxidation.As the thickness of the silicon oxide film of gate insulating film 38 can be 6.5nm to 35nm (preferred 12nm to 20nm, more preferably 15nm).
The mono-layer oxidized silicon fiml that gate insulating film 38 is not limited to form in the above described manner, but can be to be layered in the lamination of lamination, tantalum-oxide film (or high-k films) and the silicon oxide film of silicon oxide film on the silicon oxide film and silicon nitride film (or silicon oxynitride film) or silicon nitride film (or silicon oxynitride film) or to have the silicon nitride film (or silicon oxynitride film) that is inserted between the two-layer silica or the sandwich structure of high-k films.
In the technology shown in Fig. 1 J, after the layer of gate electrode material of for example doped polycrystalline silicon is deposited on the substrate top surface, by photoetching and dry etching patterned gate electrode material layer, on gate insulating film 38, to form gate electrode layer 40.By adopting field oxide film 34 and gate electrode layer 40 as mask, for example the n type foreign ion of phosphonium ion is injected into the superficial layer of p type well region 12 and is annealed, and with the foreign ion of activation injection, thereby forms n
+Type source/drain region 42 and 44.Therefore in device opening 34A, form n channel MOS transistor npn npn.The structure of MOS transistor npn npn and manufacture method are not limited to above-mentioned these, but can adopt various known structures and manufacture method.By using known method, also can in corresponding to the device opening of n type well region 14 and 16, form p channel MOS transistor npn npn.Can in device opening, form the circuit element of MOS transistor npn npn and for example MOS type capacitor and resistive element.
According to above-mentioned field oxide film formation method, be formed on below the field oxide film 34 owing to raceway groove stops to distinguish 36, and separate, shown in Fig. 1 H with device opening 34A; In source/drain region 42 and 44 and raceway groove stop to distinguish between 36 and can keep enough distance, delta L, shown in Fig. 1 J, thereby can realize the raising of junction breakdown voltage and reducing of junction capacitance.Because channel width will can not stopped to distinguish 36 by raceway groove and narrow down, so can prevent to reduce (threshold voltage increases and drain current reduces) by the caused transistor characteristic of narrow-channel effect.In addition, because having silicon nitride that macroion suppresses ability by employing, the technology shown in Fig. 1 E provides enough mask functions as the material of side separator 28a, and the technology lateral erosion silicon nitride film 20 shown in Fig. 1 G, so the technology shown in Fig. 1 H can make raceway groove stop to distinguish 36 to separate with device opening 34A reliably.In addition, the improvement of the mask functions by combination side separator 28a and the dense film quality of silicon oxide film 24, improved the mask functions of silicon oxide film 24, thereby in the ion implantation technology shown in Fig. 1 F, do not need to form the resist layer of extra covering lamination 27 and side separator 28a, cause technology of simplifying and the raising of making output.
Fig. 3 A shows manufacture method according to the n channel MOS transistor npn npn of compensation metal-oxide semiconductor (MOS) (CMOS) the type IC of second embodiment of the invention to 3H.To the technology to 3H corresponding to Fig. 3 A be described successively.
In the technology shown in Fig. 3 A, on the first type surface of p type silicon substrate 110, form p type well region 112 arranged side by side, n type well region 114 and 116 by known method.N type well region 114 and 116 can form a well region around p type well region 112.After well region 112 to 116 forms, on the first type surface of substrate 110, form silicon oxide film (stress relaxation pad oxide film) 118 by thermal oxidation.The thickness of silicon oxide film 118 can for 30nm for example to the 40nm scope.On silicon oxide film 118, form silicon nitride film 120 by CVD.The thickness of silicon nitride film 120 can arrive 150nm (preferred 100nm) for 75nm.
According to predetermined device opening (active area formation opening) pattern, on silicon nitride film 120, form resist layer 122a by photoetching process.The material of resist layer 122a can be based on the resist of promise volt lacquer (novolak), and its thickness can be that 700nm is to 1200nm (preferred 900nm).
Then, in the technology shown in Fig. 3 B, by using resist layer 122a as mask, p type foreign ion stops ion doped region 124 via the superficial layer of the lamination injection well region 112 to 116 of silicon oxide film 118 and silicon nitride film 120 with the raceway groove that forms closed ring in the peripheral region of resist layer 122a.For example, in ion implantation technology, at the acceleration energy and 1.5 * 10 of 100keV
13Cm
-2Condition under inject boron ion B
+
In the technology shown in Fig. 3 C, resist layer 122a is by isotropic dry etch, with thickness and the planar dimension of the resist layer 122a that reduces predetermined amount delta t.Therefore, the marginal position of resist layer 122a shrinks the amount corresponding to etch quantity Δ t from the inner of ion doped region 124.The dry etching condition can be:
Gas flow rate: O
2=100sccm
Pressure: 0.3Torr
RF power: 125W
Below table 1 show the relation between process time (s) and etch quantity (resist amount of recovery) Δ t (nm) under these conditions the resist etching process.In table 1, " etch quantity " is the mean value of the etch quantity measured of nine predetermined on wafer (substrate 110) surface measurement points.
Table 1
| Process time (s) | Etch quantity (nm) |
| 60 | 64.3 |
| 90 | 95.2 |
| 120 | 124.0 |
| 150 | 153.9 |
| 180 | 182.6 |
| 210 | 214.1 |
| 240 | 241.6 |
| 270 | 274.3 |
Fig. 4 illustrates the figure that concerns between process time shown in the table 1 and the etch quantity.Be appreciated that from table 1 and Fig. 4 etch quantity Δ t is almost proportional with the process time.Etch quantity Δ t in the technology shown in Fig. 3 C can be in being equal to or greater than the scope of 150nm.This will describe with reference to table 2 and Fig. 5 in the back.
Then, in the technology shown in Fig. 3 D, by using resist layer 122a, by anisotropic dry etch composition silicon nitride film 120, to form the oxide mask 120a that makes by the remainder of silicon nitride film 120 as mask.This etching can be by carrying out under the RF plasma etching condition below:
Etching gas: CF
4/ CHF
4
Pressure: 160mTorr
RF power: 700W (13.56MHz)
After oxide mask 120a formed, the lamination by adopting oxide mask 120a and resist layer 122a was as mask, can remove a part that silicon oxide film 118 not oxidized thing mask 120a the cover surface with exposed wall district 112 to 116.Yet, if silicon oxide film 118 is not capped but stays as shown in the figure, can prevent being infected with of surface of silicon, and can be expected at the raceway groove protection effect in the ion implantation process.
In the technology shown in Fig. 3 E, on silicon oxide film 118, form resist layer 126a by photoetching process, capping oxide mask 120a, resist layer 122a and p type well region 112, and do not cover n type well region 114 and 116.Because resist layer 126a is used as the ion injecting mask in ion implantation technology subsequently, its thickness can for about 900nm to 1500nm (preferably about 1100nm).Because resist layer 122a is applied in hardening process in the technology shown in Fig. 3 A, goes up and form so resist layer 126a can be layered in resist layer 122a.
Then, by using resist layer 126a as mask, n type foreign ion is injected into via silicon oxide film 118 in the superficial layer of n type well region 114 and 116, stops ion doped region 128 and 130 to form raceway groove respectively in n type well region 114 and 116.Ion doped region 128 and 130 all forms has the closed ring pattern.As representative, describe ion doped region 130 in detail with reference to Fig. 6 E.For example, this ion injection is by the acceleration energy and 4.8 * 10 at 50keV
12Cm
-2Dosage inject down phosphonium ion P
+Carry out.A part of 124a of ion doped region 124 remains in the p type well region 112.If the raceway groove that does not need to be used for the p channel MOS transistor in n type well region 114 and 116 stops district's (impurity doped region), then omit the resist layer shown in Fig. 3 E and form technology and ion implantation technology.
Then, in the technology shown in Fig. 3 F, pass through O
2Or O
3Ashing and remove resist layer 126a and 122a.Use the chemical treatment and the pure water of sulfuric acid+hydrogen peroxide to handle successively, carry out drying then.After this, be formed on the field oxide film 132 that has device opening 132A on substrate 110 surfaces by the selective oxidation of adopting oxide mask 120a.A part of 118a of silicon oxide film 118 remains in the bottom of oxide mask 120a.Adopt this heat treatment, stop to distinguish 134 corresponding to the p type raceway groove of ion doped region 124a and be formed on below the field oxide film 132 and separate, wherein stop to distinguish in 136 and 138 n type well regions 114 and 116 that are formed on below the field oxide film 132 corresponding to the n type raceway groove of ion doped region 128 and 130 with device opening 132A.For example,, can under 1000 ℃ of temperature, adopt the horizontal proliferation stove to carry out means of wet thermal oxidation for selective oxidation, and can form have 350nm to the silicon oxide film of 1000nm thickness (preferred 400nm to 600nm, more preferably 500nm) as field oxide film 132.
In the technology shown in Fig. 3 G, remove oxide-film (silicon nitride film) 120a and silicon oxide film 118a successively.Can remove oxidation mask 120a by about 60 minutes wet etching of hot phosphoric acid that under 160 ℃ of temperature, adopts, and can remove silicon oxide film 118a by the wet etching that adopts the hydrofluoric acid that dilutes.
On the silicon face of silicon oxide film 118a in removing device opening 132A, by thermal oxidation form have 30nm to the silicon oxide film of 50nm thickness as sacrifice oxide film.Can be at dried O
2Under 950 ℃ of temperature, carry out thermal oxidation in (or dry air).After the silicon oxide film of removing by hydrofluoric acid as sacrifice oxide film, by forming silicon oxide film on the silicon face of thermal oxidation in device opening 132A as gate insulating film 140A.Can be at dried O
2In under 950 ℃ of temperature, carry out thermal oxidation.As the thickness of the silicon oxide film of gate insulating film 140A can for 6.5nm to 35nm (preferred 12nm to 20nm, more preferably 15nm).
The mono-layer oxidized silicon fiml that gate insulating film 140A is not limited to form in the above described manner, but can be for the lamination of the lamination, tantalum-oxide film (or high-k films) and the silicon oxide film that are layered in oxidation film on the silicon oxide film and silicon nitride film (or silicon oxynitride) or silicon nitride film (or silicon oxynitride film) or have the silicon nitride film (or silicon oxynitride film) that is inserted between the two-layer silica or a sandwich structure of high-k films.
In the technology shown in Fig. 3 H, after the layer of gate electrode material of for example doped polycrystalline silicon is deposited on the substrate top surface,, thereby on gate insulating film 140A, form gate electrode layer 142A by photoetching and dry etching patterned gate electrode material layer.By adopting field oxide film 132 and gate electrode layer 142A as mask, for example the n type foreign ion of phosphonium ion is injected into the superficial layer of p type well region 112, and is annealed the foreign ion that injects to activate, thereby forms n
+Type source/drain region 144A and 146A.Therefore in device opening 132A, form n channel MOS transistor npn npn.
Following table 2 shows the etch quantity Δ t (nm) and the n shown in Fig. 3 H in the resist etch process shown in Fig. 3 C
+Relation between the junction breakdown voltage (V) of the pn knot between type drain region 146A and the p type well region 112.In table 2, " MAX " represents maximum, and " MIN " represents minimum value, and " AVG " expression mean value.
Table 2
| Etch quantity (nm) | Junction breakdown voltage (V) | ||
| | MAX | MIN | |
| 0 | 17.1 | 17.5 | 16.9 |
| 149.8 | 21.5 | 21.8 | 21.2 |
| 250.2 | 24.2 | 24.5 | 23.8 |
| 340.1 | 24.5 | 24.6 | 24 |
Fig. 5 is the figure that relation between etch quantity Δ t shown in the table 2 and the junction breakdown voltage (V) is shown.In Fig. 5, " R " expression 21V is to the junction breakdown voltage scope of the permission of 27V.From Fig. 5, be appreciated that by etch quantity being set in the scope that is equal to and greater than 150nm, the junction breakdown voltage that can obtain.
According to above-mentioned field oxide film formation method, shown in Fig. 3 F, only be formed on the following of field oxide film 132 and separate because raceway groove stops to distinguish 134 with device opening 132A, in the source/ drain region 144A and 146A and raceway groove stop to distinguish between 134 and can keep enough distance, delta L, shown in Fig. 3 H, thereby can realize the raising of junction breakdown voltage and reducing of junction capacitance.Because channel width will can not stopped to distinguish 134 by raceway groove and narrow down, can prevent the reduction (threshold voltage increases and drain current reduces) of the transistor characteristic that causes by narrow-channel effect.In addition, owing in the ion implantation technology shown in Fig. 3 B, adopt resist layer 122a,, cause a spot of technology number, the increase of manufacturing output and cost to reduce so do not need to adopt the technology that forms various dielectric films, side separator etc. as mask.
Fig. 6 A shows the manufacture method to the p channel MOS transistor npn npn of the described CMOS type of 3H IC with reference to Fig. 3 A to 6H., in 6H, pass through to adopt identical reference number and symbolic representation to the components identical shown in the 3H with Fig. 3 A, and omitted its detailed description at Fig. 6 A.
In the technology shown in Fig. 6 A, by carrying out technology, on the first type surface of p type silicon substrate 110, form p type well region 113 with reference to the formation p type trap 112 shown in the figure 3A, arranged side by side with n type well region 116.Form silicon oxide film 118 and silicon nitride film 120 by described thermal oxidation of reference Fig. 3 A and CVD.By carrying out technology, on silicon nitride film 120, form resist layer 122b corresponding to the device opening pattern of expectation with reference to the described formation resist layer of Fig. 3 A 122a.
In the technology shown in Fig. 6 B, carry out with reference to the ion implantation technology shown in Fig. 3 B.In this ion implantation technology, by adopt resist layer 122b with resist layer 122a as mask, in resist layer 122b surrounding zone, form the ion doped region 124 of the closed ring that comprises p type foreign ion.
In the technology shown in Fig. 6 C, by carrying out the described isotropic etching with reference to Fig. 3 C, the thickness of resist layer 122b and planar dimension have reduced predetermined amount delta t.Therefore, the marginal position of resist layer 122b is withdrawn corresponding to the amount of etch quantity Δ t from the inner of ion doped region 124.In the technology shown in Fig. 6 D, carry out described anisotropic dry etch with reference to Fig. 3 D.In this dry etching, by adopt resist layer 122b with resist layer 122a as mask, the oxidation film 120b that is formed by the remainder of silicon nitride film 120 also is formed on the bottom of resist layer 122b.Though can remove the part that silicon oxide film 118 not oxidized thing mask 120b cover, also can it be stayed to be similar to reference to the described mode of Fig. 3 D.
In the technology shown in Fig. 6 E, by carrying out forming resist layer 126b and 126c with reference to the technology of the described formation resist layer of Fig. 3 E 126a.Resist layer 126b forms the side of capping oxide mask 120b and resist layer 122b, and does not cover the ion doped region (with reference to Fig. 6 D) (being convenient to be injected in the ion technology below in the n type well region 116 that comprises the part ion doped region) that is present in the n type well region 116 as the part of ion doped region 124.Resist layer 126c forms and covers p type well region 113.
Then, carry out technology with reference to the described injection of Fig. 3 E n type foreign ion.In this ion implantation technology, by use resist layer 126b and 126c with resist layer 126a as mask, in the peripheral region of resist layer 126b, form the raceway groove that contains n type foreign ion and stop ion doped region 130.Therefore, be present in the n type well region 116 ion doped region, in the peripheral region of resist layer 126b, form ion doped region 130, shown in Fig. 6 D as the part of ion doped region 124 by compensation.A part of 124c of ion doped region 124 remains in the p type well region 113.
In the technology shown in Fig. 6 F, by carrying out removing resist layer 126b, 126c and 122b with reference to the technology of removing resist layer 126a and 122a shown in Fig. 3 F.The chemical treatment, the pure water that carry out successively with reference to the described use sulfuric acid+hydrogen peroxide of Fig. 3 F are handled and drying.After this, carry out described selective oxidation with reference to Fig. 3 F.Oxidation mask 120b and oxidation mask 120a are used in selective oxidation, thereby form field oxide film 132 on substrate 110 surfaces, have device opening 132A and 132B corresponding to oxidation mask 120a and 120b.A part of 118b of silicon oxide film 118 remains on the bottom of oxide mask 120b.Adopt this heat treatment, form p type raceway groove with reference to the described mode of Fig. 3 F and stop to distinguish 134, and stop to distinguish 138 corresponding to the n type raceway groove of ion doped region 130 and be formed on below the field oxide film 132 and separate, shown in Fig. 6 F with device opening 132B to be similar to.In p type well region 113, corresponding to the p type raceway groove of ion doped region 124c stop to distinguish 139 be formed on field oxide film 132 below.
In the technology shown in Fig. 6 G,, remove oxidation mask 120b and silicon oxide film 118a by carrying out described technology of removing oxidation mask 120a and silicon oxide film 118a with reference to Fig. 3 G.By carrying out, form expendable film, and be removed subsequently with reference to described thermal oxidation of Fig. 3 G and hydrofluoric acid treatment.After this, by carrying out in device opening 132B, forming gate insulating film 140B with reference to the technology of the described formation gate insulating film of Fig. 3 G or by adopting independently technology.
In the technology shown in Fig. 6 H, after the layer of gate electrode material of for example doped polycrystalline silicon is deposited on the substrate top surface, by photoetching and dry etching patterned gate electrode material layer, on gate insulating film 140B, to form gate electrode layer 142B.By using field oxide film 132 and gate electrode layer 142B as mask, BF for example
2The p type foreign ion of ion injects the into superficial layer of n type well region 116, and is annealed the foreign ion that injects to activate, thereby forms p
+Type source/drain region 144B and 146B.Therefore in device opening 132B, form p channel MOS transistor npn npn.
According to reference Fig. 6 A to the described field oxide film of 6H formation method, be formed on below the field oxide film 132 and and separate because raceway groove stops to distinguish 138 with device opening 132B, shown in Fig. 6 F, so can be in the source/drain region 144B and 146B and raceway groove stop to distinguish the enough distance, delta L of maintenance between 138, shown in Fig. 6 H, thereby can realize the raising of junction breakdown voltage and reducing of junction capacitance.Because channel width will can not stopped to distinguish 138 by raceway groove and narrow down, so can prevent reduction (reducing of the increase of threshold voltage and drain current) by the caused transistor characteristic of narrow-channel effect.In addition, only the technology of the formation resist layer shown in Fig. 6 E and ion implantation technology are used as the special technology that forms n type well region 116 by extra, thereby can prevent the increase of number of processes, have caused making the increase of output and the reduction of cost.
The structure of MOS transistor npn npn and manufacture method are not limited to above-mentioned those, but also can adopt various known structures and manufacture method.In device opening, not only the MOS transistor npn npn can be formed, for example circuit element of MOS type electric capacity and resistive element can also be formed.
Engage preferred embodiment and described the present invention.The present invention is not limited only to the foregoing description.It will be apparent to one skilled in the art that and to carry out various improvement, raising, combination etc.
Claims (7)
1, a kind of method, semi-conductor device manufacturing method comprises the steps:
The preparation silicon substrate, it has the district of at least one a kind of conduction type;
On the first type surface of described silicon substrate from the bottom according to mentioned sequential cascade first silicon oxide film, silicon nitride film and second silicon oxide film;
According to the device opening pattern of expectation, composition comprises the described silicon nitride film in described first silicon oxide film, described silicon nitride film and described second silicon oxide film and the lamination of described second silicon oxide film at least;
The side separator of described lamination one side is made and is covered in formation by silicon nitride;
By adopting described lamination and described side separator as mask, inject the first type surface of the foreign ion of described first kind of conduction type to described silicon substrate, stop ion doped region to form raceway groove; With
After removing described side separator, by adopting of the selective oxidation of described lamination as mask, formation has the field oxide film corresponding to the device opening of the described lamination on the described silicon substrate first type surface, and the raceway groove of the described a kind of conduction type of formation stops the district on the basis of described ion doped region.
2, method, semi-conductor device manufacturing method according to claim 1, wherein said second silicon oxide film is to be deposited on the silicon oxide film that the polysilicon film on the described silicon nitride film forms by thermal oxidation.
3, method, semi-conductor device manufacturing method according to claim 2 wherein before described polysilicon film is deposited on the described silicon nitride film, makes described silicon nitride film densification by heat treatment.
4, method, semi-conductor device manufacturing method according to claim 1, wherein said second silicon oxide film are to be deposited on the described silicon nitride film also to make silicon oxide film closely by heat treatment subsequently.
5, a kind of method, semi-conductor device manufacturing method comprises the steps:
(a) preparation silicon substrate, it has first type surface and has a kind of conduction type at least in device formation district;
(b) on the first type surface of described silicon substrate, form and cover the oxidation mask material layer that described device forms the district;
(c) according to the first device opening pattern that forms the part in district corresponding to described device, on described oxidation mask material layer, form first resist layer;
(d) by adopting described first resist layer, inject the first type surface of the foreign ion of described a kind of conduction type, be formed for first ion doped region that raceway groove stops to described silicon substrate via described oxidation mask material layer as mask;
(e) after described first ion doped region forms, described first resist layer of etching isotropically is to reduce the thickness and the planar dimension of described first resist layer according to scheduled volume;
(f) after described isotropic etching, come the described oxidation mask material layer of composition by adopting described first resist layer as the etching of mask, first oxidation mask that forms with the remainder that forms by described oxidation mask material layer; With
(g) after removing described first resist layer, by adopting the selective oxidation of described first oxidation mask, on the first type surface of described silicon substrate, form the field oxide film have corresponding to the device opening of described first oxidation mask, and first raceway groove that forms corresponding to described a kind of conduction type of described first ion doped region stops the district.
6, method, semi-conductor device manufacturing method according to claim 5, wherein
The well region of the conduction type of formation and described a kind of conductivity type opposite on the first type surface of described silicon substrate;
Described step (b) forms the described oxidation mask material layer that also covers described well region;
Described step (c) also forms second resist layer according to the second device opening pattern corresponding to the part of described well region;
Described step (d) also adopts described second resist layer to form described first ion doped region as mask;
Described step (e) is described second resist layer of etching isotropically also, thereby reduces the thickness and the planar dimension of described second resist layer with scheduled volume;
Described step (f) also adopts described second resist layer as the described oxidation mask material layer of mask composition, thereby forms second oxidation mask that is formed by the remainder corresponding to the described oxidation mask material layer of described second resist layer,
Described method, semi-conductor device manufacturing method also comprises, described step (f) afterwards with described step (g) step before:
(h) form to cover the 3rd resist layer that described device forms district and described first resist layer, form cover be present in described well region interior as described first an ion doped region part ion doped region and cover the 4th resist layer of the side of described second oxidation mask and described second resist layer; With
(i) adopt described third and fourth resist layer as mask, the foreign ion of the described conduction type of injection and described a kind of conductivity type opposite is to described well region, be present in the described well region ion doped region by compensation, and be formed for second ion doped region that raceway groove stops as described first an ion doped region part;
After described third and fourth resist layer and described first and second resist layers are removed, described step (g) is by adopting the selective oxidation of first and second oxide masks, on the first type surface of described silicon substrate, form the field oxide film that has corresponding to first and second device opening of described first and second oxide masks, first raceway groove stops the district and has described a kind of conduction type and corresponding to first ion doped region, and second raceway groove stop to distinguish have with in the described conduction type of described a kind of conductivity type opposite and corresponding to second ion doped region.
7, a kind of method, semi-conductor device manufacturing method comprises the steps:
The preparation silicon substrate, its device with first type surface and a kind of conduction type forms the district, and with the well region of the films of opposite conductivity of described a kind of conductivity type opposite;
On the first type surface of described silicon substrate, form and cover the oxide mask material layer that described device forms district and described well region;
On described oxide mask material layer, form first and second resist layers according to the first device opening pattern of a part that forms the district corresponding to described device with corresponding to the second device opening pattern of the part of described well region;
Adopt described first and second resist layers as mask, inject the first type surface of the foreign ion of described a kind of conduction type, be formed for first ion doped region that raceway groove stops to described silicon substrate through described oxide mask material layer;
After described first ion doped region forms, described first and second resist layers of etching isotropically, thus reduce the thickness and the planar dimension of described first and second resist layers with scheduled volume;
Form to cover the 3rd resist layer that described device forms district and described first resist layer, form cover be present in described well region interior as described first ion doped region ion doped region and cover the 4th resist layer of described second oxide mask and described second resist layer;
By adopting foreign ion that described third and fourth resist layer injects described films of opposite conductivity as mask to described well region, thereby the ion doped region that is present in the described well region as the part of described first ion doped region by compensation is formed for second ion doped region that raceway groove stops;
After described third and fourth resist layer and described first and second resist layers are removed, by adopting the selective oxidation of described first and second oxide masks, on the first type surface of described silicon substrate, form the field oxide film that has corresponding to first and second device opening of described first and second oxide masks, first raceway groove stops the district and has described a kind of conduction type and corresponding to first ion doped region, and second raceway groove stops that the district has described films of opposite conductivity and corresponding to second ion doped region.
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|---|---|---|---|
| JP2005028699A JP2006216815A (en) | 2005-02-04 | 2005-02-04 | Formation of field oxide film |
| JP028699/05 | 2005-02-04 | ||
| JP078628/05 | 2005-03-18 |
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| CN106981515A (en) * | 2016-01-19 | 2017-07-25 | 北大方正集团有限公司 | A kind of field-effect transistor and preparation method |
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| JP7209556B2 (en) * | 2019-02-05 | 2023-01-20 | 東京エレクトロン株式会社 | Substrate processing method and substrate processing apparatus |
| CN116848296A (en) * | 2021-02-05 | 2023-10-03 | 信越半导体株式会社 | Nitride semiconductor substrate and method for manufacturing same |
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| CN106981515A (en) * | 2016-01-19 | 2017-07-25 | 北大方正集团有限公司 | A kind of field-effect transistor and preparation method |
| CN106981515B (en) * | 2016-01-19 | 2019-11-08 | 北大方正集团有限公司 | A kind of field effect transistor and production method |
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| CN100543961C (en) | 2009-09-23 |
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