CN1815628B - 用于配置可编程设备的方法和电路 - Google Patents
用于配置可编程设备的方法和电路 Download PDFInfo
- Publication number
- CN1815628B CN1815628B CN2005101287616A CN200510128761A CN1815628B CN 1815628 B CN1815628 B CN 1815628B CN 2005101287616 A CN2005101287616 A CN 2005101287616A CN 200510128761 A CN200510128761 A CN 200510128761A CN 1815628 B CN1815628 B CN 1815628B
- Authority
- CN
- China
- Prior art keywords
- circuit
- programmable
- piece
- configuration
- programmable logic
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
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Classifications
-
- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F15/00—Digital computers in general; Data processing equipment in general
- G06F15/76—Architectures of general purpose stored program computers
- G06F15/78—Architectures of general purpose stored program computers comprising a single central processing unit
- G06F15/7867—Architectures of general purpose stored program computers comprising a single central processing unit with reconfigurable architecture
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
- H03K19/173—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components
- H03K19/177—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form
- H03K19/17724—Structural details of logic blocks
- H03K19/17732—Macroblocks
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
- H03K19/173—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components
- H03K19/177—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form
- H03K19/17748—Structural details of configuration resources
- H03K19/17758—Structural details of configuration resources for speeding up configuration or reconfiguration
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
- H03K19/173—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components
- H03K19/177—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form
- H03K19/17748—Structural details of configuration resources
- H03K19/1776—Structural details of configuration resources for memories
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
- H03K19/173—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components
- H03K19/177—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form
- H03K19/17748—Structural details of configuration resources
- H03K19/17768—Structural details of configuration resources for security
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
- H03K19/173—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components
- H03K19/177—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form
- H03K19/17748—Structural details of configuration resources
- H03K19/17772—Structural details of configuration resources for powering on or off
Landscapes
- Physics & Mathematics (AREA)
- Mathematical Physics (AREA)
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- General Engineering & Computer Science (AREA)
- Computing Systems (AREA)
- Theoretical Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Computer Security & Cryptography (AREA)
- Logic Circuits (AREA)
- Storage Device Security (AREA)
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US11/003,586 | 2004-12-02 | ||
| US11/003,586 US7242218B2 (en) | 2004-12-02 | 2004-12-02 | Techniques for combining volatile and non-volatile programmable logic on an integrated circuit |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN1815628A CN1815628A (zh) | 2006-08-09 |
| CN1815628B true CN1815628B (zh) | 2010-10-27 |
Family
ID=36078904
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN2005101287616A Expired - Fee Related CN1815628B (zh) | 2004-12-02 | 2005-12-02 | 用于配置可编程设备的方法和电路 |
Country Status (4)
| Country | Link |
|---|---|
| US (1) | US7242218B2 (enExample) |
| EP (1) | EP1667327A3 (enExample) |
| JP (1) | JP4249745B2 (enExample) |
| CN (1) | CN1815628B (enExample) |
Families Citing this family (57)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7190190B1 (en) * | 2004-01-09 | 2007-03-13 | Altera Corporation | Programmable logic device with on-chip nonvolatile user memory |
| US7689726B1 (en) * | 2004-10-01 | 2010-03-30 | Xilinx, Inc. | Bootable integrated circuit device for readback encoding of configuration data |
| US7442583B2 (en) * | 2004-12-17 | 2008-10-28 | International Business Machines Corporation | Using electrically programmable fuses to hide architecture, prevent reverse engineering, and make a device inoperable |
| US20080061817A1 (en) * | 2004-12-17 | 2008-03-13 | International Business Machines Corporation | Changing Chip Function Based on Fuse States |
| US20060136858A1 (en) * | 2004-12-17 | 2006-06-22 | International Business Machines Corporation | Utilizing fuses to store control parameters for external system components |
| US7919979B1 (en) | 2005-01-21 | 2011-04-05 | Actel Corporation | Field programmable gate array including a non-volatile user memory and method for programming |
| US20060194603A1 (en) * | 2005-02-28 | 2006-08-31 | Rudelic John C | Architecture partitioning of a nonvolatile memory |
| US8395426B2 (en) * | 2005-05-19 | 2013-03-12 | Broadcom Corporation | Digital power-on reset controller |
| US7538577B2 (en) * | 2005-06-29 | 2009-05-26 | Thomas Bollinger | System and method for configuring a field programmable gate array |
| US7403051B1 (en) * | 2006-01-26 | 2008-07-22 | Xilinx, Inc. | Determining voltage level validity for a power-on reset condition |
| JP2007251329A (ja) * | 2006-03-14 | 2007-09-27 | Matsushita Electric Ind Co Ltd | プログラマブルロジックデバイス |
| US7327595B2 (en) * | 2006-05-09 | 2008-02-05 | Analog Devices, Inc. | Dynamically read fuse cell |
| US7378873B1 (en) * | 2006-06-02 | 2008-05-27 | Lattice Semiconductor Corporation | Programmable logic device providing a serial peripheral interface |
| US7570078B1 (en) | 2006-06-02 | 2009-08-04 | Lattice Semiconductor Corporation | Programmable logic device providing serial peripheral interfaces |
| US7495970B1 (en) * | 2006-06-02 | 2009-02-24 | Lattice Semiconductor Corporation | Flexible memory architectures for programmable logic devices |
| US7375546B1 (en) | 2006-06-08 | 2008-05-20 | Xilinx, Inc. | Methods of providing performance compensation for supply voltage variations in integrated circuits |
| US7368940B1 (en) * | 2006-06-08 | 2008-05-06 | Xilinx, Inc. | Programmable integrated circuit with selective programming to compensate for process variations and/or mask revisions |
| US7365563B1 (en) | 2006-06-08 | 2008-04-29 | Xilinx, Inc. | Integrated circuit with performance compensation for process variation |
| US7362129B1 (en) | 2006-06-08 | 2008-04-22 | Xilinx, Inc. | Methods of providing performance compensation for process variations in integrated circuits |
| US7529993B1 (en) | 2006-06-08 | 2009-05-05 | Xilinx, Inc. | Method of selectively programming integrated circuits to compensate for process variations and/or mask revisions |
| US20080306723A1 (en) * | 2007-06-08 | 2008-12-11 | Luca De Ambroggi | Emulated Combination Memory Device |
| US7576561B1 (en) * | 2007-11-13 | 2009-08-18 | Xilinx, Inc. | Device and method of configuring a device having programmable logic |
| US7795909B1 (en) * | 2008-04-15 | 2010-09-14 | Altera Corporation | High speed programming of programmable logic devices |
| JP5273152B2 (ja) * | 2008-10-01 | 2013-08-28 | 富士通株式会社 | 半導体装置、情報処理装置及び半導体装置の構築方法 |
| WO2010070736A1 (ja) * | 2008-12-16 | 2010-06-24 | 株式会社島津製作所 | プログラマブルデバイス制御装置およびその方法 |
| US7888965B2 (en) * | 2009-01-29 | 2011-02-15 | Texas Instruments Incorporated | Defining a default configuration for configurable circuitry in an integrated circuit |
| EP2224344A1 (en) * | 2009-02-27 | 2010-09-01 | Panasonic Corporation | A combined processing and non-volatile memory unit array |
| US8433950B2 (en) * | 2009-03-17 | 2013-04-30 | International Business Machines Corporation | System to determine fault tolerance in an integrated circuit and associated methods |
| US8174287B2 (en) * | 2009-09-23 | 2012-05-08 | Avaya Inc. | Processor programmable PLD device |
| US8417874B2 (en) * | 2010-01-21 | 2013-04-09 | Spansion Llc | High speed memory having a programmable read preamble |
| US8358553B2 (en) * | 2010-06-07 | 2013-01-22 | Xilinx, Inc. | Input/output bank architecture for an integrated circuit |
| US9543956B2 (en) * | 2011-05-09 | 2017-01-10 | Intel Corporation | Systems and methods for configuring an SOPC without a need to use an external memory |
| US8625345B2 (en) * | 2011-07-27 | 2014-01-07 | Micron Technology, Inc. | Determining and transferring data from a memory array |
| US8611138B1 (en) | 2012-01-20 | 2013-12-17 | Altera Corporation | Circuits and methods for hardening volatile memory circuits through one time programming |
| US9830964B2 (en) * | 2012-09-10 | 2017-11-28 | Texas Instruments Incorporated | Non-volatile array wakeup and backup sequencing control |
| US9547034B2 (en) * | 2013-07-03 | 2017-01-17 | Xilinx, Inc. | Monolithic integrated circuit die having modular die regions stitched together |
| US10169618B2 (en) | 2014-06-20 | 2019-01-01 | Cypress Semiconductor Corporation | Encryption method for execute-in-place memories |
| US10192062B2 (en) * | 2014-06-20 | 2019-01-29 | Cypress Semiconductor Corporation | Encryption for XIP and MMIO external memories |
| US10691838B2 (en) | 2014-06-20 | 2020-06-23 | Cypress Semiconductor Corporation | Encryption for XIP and MMIO external memories |
| DE102015110729A1 (de) * | 2014-07-21 | 2016-01-21 | Dspace Digital Signal Processing And Control Engineering Gmbh | Anordnung zur teilweisen Freigabe einer Debuggingschnittstelle |
| CN109783435A (zh) * | 2014-10-27 | 2019-05-21 | 阿尔特拉公司 | 具有嵌入式可编程逻辑的集成电路器件 |
| EP3218827B1 (en) * | 2014-11-12 | 2020-05-27 | Xilinx, Inc. | Heterogeneous multiprocessor program compilation targeting programmable integrated circuits |
| US9847783B1 (en) * | 2015-10-13 | 2017-12-19 | Altera Corporation | Scalable architecture for IP block integration |
| GB2567215B (en) * | 2017-10-06 | 2020-04-01 | Advanced Risc Mach Ltd | Reconfigurable circuit architecture |
| US10956241B1 (en) | 2017-12-20 | 2021-03-23 | Xilinx, Inc. | Unified container for hardware and software binaries |
| KR102440799B1 (ko) * | 2019-04-23 | 2022-09-06 | 아르보 컴퍼니 엘엘엘피 | 이중 기능 셀 어레이를 재구성하기 위한 시스템 및 방법 |
| US10782759B1 (en) | 2019-04-23 | 2020-09-22 | Arbor Company, Lllp | Systems and methods for integrating batteries with stacked integrated circuit die elements |
| US10587270B2 (en) | 2019-06-12 | 2020-03-10 | Intel Corporation | Coarse-grain programmable routing network for logic devices |
| US10949204B2 (en) * | 2019-06-20 | 2021-03-16 | Microchip Technology Incorporated | Microcontroller with configurable logic peripheral |
| US12353846B2 (en) | 2019-07-09 | 2025-07-08 | MemryX | Matrix data reuse techniques in multiply and accumulate units of processing system |
| US10749528B2 (en) | 2019-08-20 | 2020-08-18 | Intel Corporation | Stacked programmable integrated circuitry with smart memory |
| US10992299B1 (en) * | 2020-03-09 | 2021-04-27 | Gowin Semiconductor Corporation | Method and system for providing word addressable nonvolatile memory in a programmable logic device |
| CN116097109B (zh) | 2020-06-29 | 2023-11-24 | 乔木有限责任合伙公司 | 使用3d管芯堆叠的可重新配置的处理器模块和独立于处理器的5g调制解调器的移动iot边缘装置 |
| US11662923B2 (en) | 2020-07-24 | 2023-05-30 | Gowin Semiconductor Corporation | Method and system for enhancing programmability of a field-programmable gate array |
| US11468220B2 (en) * | 2020-07-24 | 2022-10-11 | Gowin Semiconductor Corporation | Method and system for enhancing programmability of a field-programmable gate array via a dual-mode port |
| US11829480B2 (en) * | 2022-04-20 | 2023-11-28 | Quanta Computer Inc. | Remote access of system register configuration |
| US12361191B2 (en) * | 2022-09-22 | 2025-07-15 | Apple Inc. | Functional circuit block harvesting in computer systems |
Citations (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1144964A (zh) * | 1994-08-01 | 1997-03-12 | 精工电子工业株式会社 | 集成逻辑电路和电可擦可编程只读存储器 |
| US5784313A (en) * | 1995-08-18 | 1998-07-21 | Xilinx, Inc. | Programmable logic device including configuration data or user data memory slices |
| US6052309A (en) * | 1996-03-14 | 2000-04-18 | Altera Corporation | Nonvolatile configuration cells and cell arrays |
| US6107821A (en) * | 1999-02-08 | 2000-08-22 | Xilinx, Inc. | On-chip logic analysis and method for using the same |
| US20030020512A1 (en) * | 2001-07-30 | 2003-01-30 | Paul Mantey | System and method for in-system programming through an on-system JTAG bridge of programmable logic devices on multiple circuit boards of a system |
| CN1462945A (zh) * | 2003-06-18 | 2003-12-24 | 上海北大方正科技电脑系统有限公司 | 用可编程门阵列对打印机控制器进行硬件逻辑配置的方法 |
| CN1512591A (zh) * | 2002-12-30 | 2004-07-14 | ����ʿ�뵼������˾ | 非易失性存储器件 |
| CN1523510A (zh) * | 2003-02-18 | 2004-08-25 | 明基电通股份有限公司 | 可重复下载数据至现场可编程门阵列的方法及装置 |
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| US5548228A (en) * | 1994-09-28 | 1996-08-20 | Altera Corporation | Reconfigurable programmable logic device having static and non-volatile memory |
| US5734868A (en) * | 1995-08-09 | 1998-03-31 | Curd; Derek R. | Efficient in-system programming structure and method for non-volatile programmable logic devices |
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| US5970142A (en) * | 1996-08-26 | 1999-10-19 | Xilinx, Inc. | Configuration stream encryption |
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| US5874834A (en) * | 1997-03-04 | 1999-02-23 | Xilinx, Inc. | Field programmable gate array with distributed gate-array functionality |
| US6102963A (en) * | 1997-12-29 | 2000-08-15 | Vantis Corporation | Electrically erasable and reprogrammable, nonvolatile integrated storage device with in-system programming and verification (ISPAV) capabilities for supporting in-system reconfiguring of PLD's |
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| US7030646B1 (en) * | 2003-09-02 | 2006-04-18 | Altera Corporation | Functional pre-configuration of a programmable logic device |
| US20050102573A1 (en) * | 2003-11-03 | 2005-05-12 | Macronix International Co., Ltd. | In-circuit configuration architecture for embedded configurable logic array |
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-
2004
- 2004-12-02 US US11/003,586 patent/US7242218B2/en not_active Expired - Fee Related
-
2005
- 2005-11-22 JP JP2005336979A patent/JP4249745B2/ja not_active Expired - Fee Related
- 2005-11-22 EP EP05257191A patent/EP1667327A3/en not_active Withdrawn
- 2005-12-02 CN CN2005101287616A patent/CN1815628B/zh not_active Expired - Fee Related
Patent Citations (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1144964A (zh) * | 1994-08-01 | 1997-03-12 | 精工电子工业株式会社 | 集成逻辑电路和电可擦可编程只读存储器 |
| US5784313A (en) * | 1995-08-18 | 1998-07-21 | Xilinx, Inc. | Programmable logic device including configuration data or user data memory slices |
| US6263430B1 (en) * | 1995-08-18 | 2001-07-17 | Xilinx, Inc. | Method of time multiplexing a programmable logic device |
| US6052309A (en) * | 1996-03-14 | 2000-04-18 | Altera Corporation | Nonvolatile configuration cells and cell arrays |
| US6107821A (en) * | 1999-02-08 | 2000-08-22 | Xilinx, Inc. | On-chip logic analysis and method for using the same |
| US20030020512A1 (en) * | 2001-07-30 | 2003-01-30 | Paul Mantey | System and method for in-system programming through an on-system JTAG bridge of programmable logic devices on multiple circuit boards of a system |
| CN1512591A (zh) * | 2002-12-30 | 2004-07-14 | ����ʿ�뵼������˾ | 非易失性存储器件 |
| CN1523510A (zh) * | 2003-02-18 | 2004-08-25 | 明基电通股份有限公司 | 可重复下载数据至现场可编程门阵列的方法及装置 |
| CN1462945A (zh) * | 2003-06-18 | 2003-12-24 | 上海北大方正科技电脑系统有限公司 | 用可编程门阵列对打印机控制器进行硬件逻辑配置的方法 |
Also Published As
| Publication number | Publication date |
|---|---|
| US7242218B2 (en) | 2007-07-10 |
| EP1667327A3 (en) | 2010-05-19 |
| JP2006166430A (ja) | 2006-06-22 |
| EP1667327A2 (en) | 2006-06-07 |
| US20060119384A1 (en) | 2006-06-08 |
| JP4249745B2 (ja) | 2009-04-08 |
| CN1815628A (zh) | 2006-08-09 |
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| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| CF01 | Termination of patent right due to non-payment of annual fee | ||
| CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20101027 Termination date: 20181202 |