CN1811737A - Portable computer data enciphering device - Google Patents
Portable computer data enciphering device Download PDFInfo
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- CN1811737A CN1811737A CNA2006100572218A CN200610057221A CN1811737A CN 1811737 A CN1811737 A CN 1811737A CN A2006100572218 A CNA2006100572218 A CN A2006100572218A CN 200610057221 A CN200610057221 A CN 200610057221A CN 1811737 A CN1811737 A CN 1811737A
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Abstract
A portable computer data encryption device includes works mode configure module, clock source module, mainboard IDE interface module, inputting matched resistor, outputting matched resistor, voltage conversion module, and power supply filter circuit. Principal feature is said device also including ciphering chip, ciphering hard disk module, electronic key and status indication module, works mode configure module, clock source module, voltage conversion module, and electronic key respectively connected to ciphering chip, mainboard IDE interface module connected with ciphering chip through inputting matched resistor, ciphering chip part connected with ciphering hard disk module through outputting matched resistor, ciphering chip connected to status indication module, power supply filter circuit respectively connected with voltage conversion module and ciphering chip. Present invention has simple structure, easy manufacture with table technology.
Description
Technical field
The present invention relates to the electronic product in a kind of control or the field of adjusting, more particularly, the present invention is meant a kind of portable computer data enciphering device, and the present invention should be divided into the big class of G05 in International Patent Classification (IPC).
Background technology
At present, the data encryption of computing machine has two kinds, and it comprises that simple software mode encryption and software encrypts with the hardware mode of combining.Software cryptography is the form by software, cryptographic algorithm depicted with the form of software, and by Computing, with data input to be encrypted, encryption software output ciphertext.This cipher mode need take a large amount of cpu resources, and will ciphertext be reduced by certain means, and password also needs the user to remember.The cipher mode of software and combination of hardware, normally cryptographic algorithm is divided into two parts, on software, keep a part, on hardware, keep a part, data are encrypted to realize that software and hardware cooperates by software administration, the user wants prior installation administration software just can use in use, and need the user remember password.
Summary of the invention
The objective of the invention is to:, provide a kind of portable computer data enciphering device that does not influence computer speed that does not take cpu resource that adopts hardware-based cryptographic at the deficiency of prior art.
The objective of the invention is to be achieved through the following technical solutions:
Described data encryption device comprises: mode of operation is provided with module, clock source module, mainboard ide interface module, input build-out resistor, output build-out resistor, voltage transformation module and electric source filter circuit part.Principal feature is:
Described data encryption device also comprises: encryption chip, encipher hard disc module, electronic key and state indicating module part.
Described mode of operation is provided with module section and connects to described encryption chip part, and described clock source module partly connects to described encryption chip part.
Described mainboard ide interface module section and described input build-out resistor partly interconnect, described input build-out resistor part and described encryption chip partly interconnect, described encryption chip part and described output build-out resistor partly interconnect, and described output build-out resistor part and described encipher hard disc module section interconnect.
Described voltage transformation module partly connects to described encryption chip part.
Described electric source filter circuit part partly interconnects with described voltage transformation module part, described encryption chip respectively.
Described encryption chip partly connects to described state indicating module part.
Described electronic key partly connects to described encryption chip part.
Described input build-out resistor partly comprises RP1, RP2, RP3, RP4, RP5, RP6 and RP7, also comprises resistance R
8And R
9
Described encryption chip partly comprises circuit U 1, resistance R
1And resistance R
2
Described output build-out resistor partly comprises RP8, RP9, RP10, RP11, RP12, RP13, RP14 and resistance R
13, R
14, R
15, R
16, R
17And R
18
Described encipher hard disc module section comprises CN2 and resistance R
10, R
11And R
12
The 1-4 leg of the RP1 of described input build-out resistor part is received H DD0 to the H DD3 leg of described mainboard ide interface module section respectively, and the 5-8 leg of the RP1 of described input build-out resistor part is received the MH DD[3 of the circuit U 1 of described encryption chip part respectively] to MH DD[0] leg.
The 1-4 leg of the RP2 of described input build-out resistor part is received H DD4 to the H DD7 leg of described mainboard ide interface module section respectively, and the 5-8 leg of the RP2 of described input build-out resistor part is received the MH DD[7 of the circuit U 1 of described encryption chip part respectively] to MH DD[4] leg.
The 5th leg of the RP2 of described input build-out resistor part connects described resistance R
9An end, described resistance R
9The other end receive GND-POWER.
The 1-4 leg of the RP3 of described input build-out resistor part is received H DD8 to the H DD11 leg of described mainboard ide interface module section respectively, and the 5-8 leg of the RP3 of described input build-out resistor part is received the MH DD[11 of the circuit U 1 of described encryption chip part respectively] to MH DD[8] leg.
The 1-4 leg of the RP4 of described input build-out resistor part is received H DD12 to the HDD15 leg of described mainboard ide interface module section respectively, and the 5-8 leg of the RP4 of described input build-out resistor part is received the MH DD[15 of the circuit U 1 of described encryption chip part respectively] to MH DD[12] leg.
The 8-5 leg of the RP5 of described input build-out resistor part is received H DMACK-, H DIOW-, H DIOR and the H DA2 leg of described mainboard ide interface module section respectively, and the 1-4 leg of the RP5 of described input build-out resistor part is received MH DMACKi, MH DIOWi, MH DIORi and the MH DA[2 of the circuit U 1 of described encryption chip part respectively] leg.
The 8-5 leg of the RP6 of described input build-out resistor part is received H DA1, H DA0, H CS1 and the H CS0 leg of described mainboard ide interface module section respectively, and the 1-4 leg of the RP6 of described input build-out resistor part is received the MH DA[1 of the circuit U 1 of described encryption chip part respectively], MH DA[0], MH CSi[1] and MH CSi[2] leg.
The 8-6 leg of the RP7 of described input build-out resistor part is received H INTRQ, H DMARQ, the H IORDY leg of described mainboard ide interface module section respectively, and the 1-3 leg of the RP7 of described input build-out resistor part is received MHINTRQ, MH DMARQ, the MH IORDY leg of the circuit U 1 of described encryption chip part respectively.
Described resistance R
8A H REST-leg that terminates to described mainboard ide interface module section, the other end is received the MH RESTi leg of the circuit U 1 of described encryption chip part.
2,19,22,24,26,30 and 40 leg of the CN1 of described mainboard ide interface module section are received on the GND simultaneously.
The resistance R of described encipher hard disc module section
10A H CSEL leg that terminates to the CN1 of described mainboard ide interface module section, its other end is received on the D CSEL leg of described encipher hard disc module section CN2.
The resistance R of described encipher hard disc module section
11A H PDIAG-leg that terminates to the CN1 of described mainboard ide interface module section, its other end is received on the D PDIAG-leg of described encipher hard disc module section CN2.
The resistance R of described encipher hard disc module section
12A H DASP-leg that terminates to the CN1 of described mainboard ide interface module section, its other end is received on the D DASP-leg of described encipher hard disc module section CN2.
The 1-4 leg of described output build-out resistor part RP8 is received D DD0 to the D DD3 leg of the CN2 of described encipher hard disc module section respectively, and the 5-8 leg of described output build-out resistor part RP8 is received the MD DD[3 of the circuit U 1 of described encryption chip part respectively] to MD DD[0] on the leg.
The 1-4 leg of described output build-out resistor part RP9 is received D DD4 to the D DD7 leg of the CN2 of described encipher hard disc module section respectively, and the 5-8 leg of described output build-out resistor part RP9 is received the MD DD[7 of the circuit U 1 of described encryption chip part respectively] to MD DD[4] on the leg.
The 5th leg of described output build-out resistor part RP9 is received described resistance R
18An end.Described resistance R
18The other end receive on the GND-POWER.
The 1-4 leg of described output build-out resistor part RP10 is received D DD8 to the D DD11 leg of the CN2 of described encipher hard disc module section respectively, and the 5-8 leg of described output build-out resistor part RP10 is received the MD DD[11 of the circuit U 1 of described encryption chip part respectively] to MD DD[8] on the leg.
The 1-4 leg of described output build-out resistor part RP11 is received D DD12 to the D DD15 leg of the CN2 of described encipher hard disc module section respectively, and the 5-8 leg of described output build-out resistor part RP11 is received the MD DD[15 of the circuit U 1 of described encryption chip part respectively] to MD DD[12] on the leg.
The 8-5 leg of described output build-out resistor part RP12 is received D CS0-, D CS1-, D DA0, the D DA1 leg of the CN2 of described encipher hard disc module section respectively, and the 1-4 leg of described output build-out resistor part RP12 is received the MD CSi[0 of the circuit U 1 of described encryption chip part respectively], MD CSi[1], MD DA[0], MD DA[1] on the leg.
The 8-6 leg of described output build-out resistor part RP13 is received D DIOR-, D DIOW-, the D DMACK-leg of the CN2 of described encipher hard disc module section respectively, and the 1-3 leg of described output build-out resistor part RP13 is received respectively on MDDIORi, MD DIOWi, the MD DMACKi leg of the circuit U 1 of described encryption chip part.
The 8-6 leg of described output build-out resistor part RP14 is received D IORDY, D DMARQ, the D INTRQ leg of the CN2 of described encipher hard disc module section respectively, and the 1-3 leg of described output build-out resistor part RP14 is received respectively on MDIORDY, MD DMARQ, the MD INTRQ leg of the circuit U 1 of described encryption chip part.
Described output build-out resistor part resistance R
13An end connect the D RESET-leg of described encipher hard disc module CN2, its other end is received the MDRESETi leg of the circuit U 1 of described encryption chip part.
Described output build-out resistor part resistance R
14An end connect the D DA2 leg of described encipher hard disc module CN2, its other end is received the MD DA[2 of the circuit U 1 of described encryption chip part] leg.
Described output build-out resistor part resistance R
15An end connect the D IORDY leg of described encipher hard disc module CN2, its another termination VCC.
Described output build-out resistor part resistance R
16An end connect the D DMARQ leg of described encipher hard disc module CN2, its another termination GND.
Described output build-out resistor part resistance R
17An end connect the D INTRQ leg of described encipher hard disc module CN2, its another termination GND.
2,19,22,24,26,30,40 leg that meet described encipher hard disc module CN2 are received on the GND simultaneously.
The described resistance R of described encryption chip part
1An end connect the PH1 leg of described circuit U 1, its another termination VDD3.
The described resistance R of described encryption chip part
2An end connect the PH2 leg of described circuit U 1, its another termination VDD3.
Described voltage transformation module partly comprises circuit U 2, capacitor C 1 and C2.
Described circuit U 2 the 3rd leg connects the VCC power supply, and the 1st leg connects VDD3, and the 2nd leg meets GND.
One end of described capacitor C 1 connects VCC power supply, its another termination GND.
One end of described capacitor C 2 connects VDD3, its another termination GND.
Described electric source filter circuit partly comprises capacitor C 5-C20 in parallel.
The end of described capacitor C 5-C20 connects VCC power supply, its another termination GND POWER.
Described clock source module partly comprises crystal oscillator SYS, resistance R 3, capacitor C 3 and C4.
Described crystal oscillator SYS and resistance R 3 parallel connections, an one common port connects the XIN leg of described encryption chip circuit U 1 partly and an end of described capacitor C 3, and its another common port connects the XOUT leg of described encryption chip circuit U 1 partly and an end of described capacitor C 4; The other end of the other end of described capacitor C 3 and described capacitor C 4 is ground connection simultaneously.
Described electronic key partly comprises E-KEY, diode D1 and resistance R 4.The the 1st to 6 leg of described E-KEY connects respectively: SEEPROM-DO, SEEPROM-DI, SEEPROM-SK, the SEEPROM-CS leg of the circuit U 1 of described diode D1 negative pole, GND POWER and encryption chip part; The positive pole of described diode D connects VCC by described resistance R 4.
Described state indicating module partly comprises power supply indication POW-LED, mistake indication ERR-LED, read-write indication RW-LED and resistance R 5, R6 and R7.One termination VDD3 of described resistance R 5, the positive pole of the described RW-LED of another termination of described resistance R 5, the negative pole of described RW-LED connect the D DASP-leg of the CN2 of described encipher hard disc module.One end of described resistance R 6 connects the KEY-ERR leg of the circuit U 1 of described encryption chip part, the positive pole of the described ERR-LED of another termination of described resistance R 6, and the negative pole of described ERR-LED connects GND-POWER.One termination VDD3 of described resistance R 7, the positive pole of the described POW-LED of another termination of described resistance R 7, the negative pole of described POW-LED connects GND-POWER.
Described mode of operation is provided with module section and comprises JP1, JP2, JP3, JP4 and RP15.
The 1st leg of described JP1, JP2, JP3, JP4 connects DES-ENA, DEV-SEL, CLK-MODE0, the CLK-MODE1 of the circuit U 1 of described encryption chip part respectively, and receives the 8th to 5 leg of described RP15 simultaneously respectively.Described JP1, JP2, JP3, JP4 the 2nd leg be ground connection simultaneously.The the 1st to 4 leg of described RP15 is received on the VDD3 simultaneously.
The model of described RP1-RP4 is RP4-33, the model of RP8-RP12 is RP4-33, the model of RP5, RP6, RP14 is RP4-82, the model of RP7, RP13 is RP4-68, the model of RP15 is RP4-10K, the model of E-KEY is 93C46, and the model of JP1-JP4 is CON2, and the model of CN1-CN2 is FKV40SN.
Because the present invention adopted above-mentioned technical scheme, the present invention adopts hardware-based cryptographic, by circuit the data stream of hard disk is encrypted, need not the software support; Be suitable for all and have the motherboard at Standard PC I South Bridge chip and IDE interface; Transfer rate 〉=1.5Gbps/s, key length 〉=2
112Each piece hard disk can only corresponding password; Hard disc data stream is encrypted, do not taken cpu resource, do not influence the speed of computing machine; When encryption device breaks down, can not make loss of data or damage on the hard disk; If hard disk is stolen, hard disk is put into does not have the key can not sense data on other computing machine.
Description of drawings
Below accompanying drawing is described, wherein:
Accompanying drawing 1 is a circuit block diagram of the present invention.
Accompanying drawing 2 is wiring diagrams of mainboard ide interface module section of the present invention.
Accompanying drawing 3 is wiring diagrams of input build-out resistor part of the present invention.
The wiring diagram of accompanying drawing 4 encryption chip parts of the present invention.
The wiring diagram of accompanying drawing 5 output build-out resistor parts of the present invention.
The wiring diagram of accompanying drawing 6 encipher hard disc module sections of the present invention.
The wiring diagram of accompanying drawing 7 voltage transformation module parts of the present invention.
The wiring diagram of accompanying drawing 8 electric source filter circuit parts of the present invention.
The wiring diagram of accompanying drawing 9 clock source module parts of the present invention.
The wiring diagram of accompanying drawing 10 electronic key parts of the present invention.
The wiring diagram of accompanying drawing 11 state indicating module parts of the present invention.
Accompanying drawing 12 mode of operations of the present invention are provided with the wiring diagram of module section.
Embodiment
The present invention is further described below in conjunction with drawings and Examples, and wherein: accompanying drawing 1 is a circuit block diagram of the present invention.Can see from this figure: described data encryption device comprises: mode of operation is provided with module, clock source module, mainboard ide interface module, input build-out resistor, output build-out resistor, voltage transformation module and electric source filter circuit part.Principal feature is: described data encryption device also comprises: encryption chip, encipher hard disc module, electronic key and state indicating module part.Can see its annexation from this figure: mode of operation is provided with module section and connects to the encryption chip part, and the clock source module partly connects to the encryption chip part.Mainboard ide interface module section and input build-out resistor partly interconnect, input build-out resistor part and encryption chip partly interconnect, encryption chip part and output build-out resistor partly interconnect, and output build-out resistor part and encipher hard disc module section interconnect.Voltage transformation module partly connects to the encryption chip part.The electric source filter circuit part partly interconnects with described voltage transformation module part and encryption chip respectively.Encryption chip partly connects to state indicating module part.Electronic key partly connects to the encryption chip part.
Accompanying drawing 2-12 has provided the concrete circuit connecting relation of the embodiment of the invention.
Wherein: from accompanying drawing 3-6, can see:
Described input build-out resistor partly comprises RP1, RP2, RP3, RP4, RP5, RP6 and RP7, also comprises resistance R
8And R
9Described encryption chip partly comprises circuit U 1, resistance R
1And resistance R
2Described output build-out resistor partly comprises RP8, RP9, RP10, RP11, RP12, RP13, RP14 and resistance R
13, R
14, R
15, R
16, R
17And R
18Described encipher hard disc module section comprises CN2 and resistance R
10, R
11And R
12
The 1-4 leg of the RP1 of described input build-out resistor part is received H DD0 to the H DD3 leg of described mainboard ide interface module section respectively, and the 5-8 leg of the RP1 of described input build-out resistor part is received the MH DD[3 of the circuit U 1 of described encryption chip part respectively] to MH DD[0] leg.The 1-4 leg of the RP2 of described input build-out resistor part is received H DD4 to the H DD7 leg of described mainboard ide interface module section respectively, and the 5-8 leg of the RP2 of described input build-out resistor part is received the MH DD[7 of the circuit U 1 of described encryption chip part respectively] to MH DD[4] leg.The 5th leg of the RP2 of described input build-out resistor part connects described resistance R
9An end, described resistance R
9The other end receive GND-POWER.The 1-4 leg of the RP3 of described input build-out resistor part is received H DD8 to the H DD11 leg of described mainboard ide interface module section respectively, and the 5-8 leg of the RP3 of described input build-out resistor part is received the MH DD[11 of the circuit U 1 of described encryption chip part respectively] to MH DD[8] leg.The 1-4 leg of the RP4 of described input build-out resistor part is received H DD12 to the HDD15 leg of described mainboard ide interface module section respectively, and the 5-8 leg of the RP4 of described input build-out resistor part is received the MH DD[15 of the circuit U 1 of described encryption chip part respectively] to MH DD[12] leg.The 8-5 leg of the RP5 of described input build-out resistor part is received H DMACK-, H DIOW-, H DIOR and the H DA2 leg of described mainboard ide interface module section respectively, and the 1-4 leg of the RP5 of described input build-out resistor part is received MH DMACKi, MH DIOWi, MH DIORi and the MH DA[2 of the circuit U 1 of described encryption chip part respectively] leg.The 8-5 leg of the RP6 of described input build-out resistor part is received HDA1, H DA0, H CS1 and the H CS0 leg of described mainboard ide interface module section respectively, and the 1-4 leg of the RP6 of described input build-out resistor part is received the MH DA[1 of the circuit U 1 of described encryption chip part respectively], MH DA[0], MH CSi[1] and MH CSi[2] leg.The 8-6 leg of the RP7 of described input build-out resistor part is received H INTRQ, H DMARQ, the H IORDY leg of described mainboard ide interface module section respectively, and the 1-3 leg of the RP7 of described input build-out resistor part is received MH INTRQ, MH DMARQ, the MH IORDY leg of the circuit U 1 of described encryption chip part respectively.One of described resistance R 8 terminates to the H REST-leg of described mainboard ide interface module section, and the other end is received the MH RESTi leg of the circuit U 1 of described encryption chip part.
2,19,22,24,26,30 and 40 leg of the CN1 of described mainboard ide interface module section are received on the GND simultaneously.
The resistance R of described encipher hard disc module section
10A H CSEL leg that terminates to the CN1 of described mainboard ide interface module section, its other end is received on the D CSEL leg of described encipher hard disc module section CN2.The resistance R of described encipher hard disc module section
11A H PDIAG-leg that terminates to the CN1 of described mainboard ide interface module section, its other end is received on the D PDIAG-leg of described encipher hard disc module section CN2.The resistance R of described encipher hard disc module section
12A H DASP-leg that terminates to the CN1 of described mainboard ide interface module section, its other end is received on the D DASP-leg of described encipher hard disc module section CN2.
The 1-4 leg of described output build-out resistor part RP8 is received D DD0 to the D DD3 leg of the CN2 of described encipher hard disc module section respectively, and the 5-8 leg of described output build-out resistor part RP8 is received the MD DD[3 of the circuit U 1 of described encryption chip part respectively] to MD DD[0] on the leg.The 1-4 leg of described output build-out resistor part RP9 is received D DD4 to the D DD7 leg of the CN2 of described encipher hard disc module section respectively, and the 5-8 leg of described output build-out resistor part RP9 is received the MD DD[7 of the circuit U 1 of described encryption chip part respectively] to MD DD[4] on the leg.The 5th leg of described output build-out resistor part RP9 is received described resistance R
18An end.Described resistance R
18The other end receive on the GND-POWER.The 1-4 leg of described output build-out resistor part RP10 is received D DD8 to the D DD11 leg of the CN2 of described encipher hard disc module section respectively, and the 5-8 leg of described output build-out resistor part RP10 is received the MD DD[11 of the circuit U 1 of described encryption chip part respectively] to MD DD[8] on the leg.The 1-4 leg of described output build-out resistor part RP11 is received D DD12 to the D DD15 leg of the CN2 of described encipher hard disc module section respectively, and the 5-8 leg of described output build-out resistor part RP11 is received the MD DD[15 of the circuit U 1 of described encryption chip part respectively] to MD DD[12] on the leg.The 8-5 leg of described output build-out resistor part RP12 is received D CS0-, D CS1-, D DA0, the D DA1 leg of the CN2 of described encipher hard disc module section respectively, and the 1-4 leg of described output build-out resistor part RP12 is received the MD CSi[0 of the circuit U 1 of described encryption chip part respectively], MD CSi[1], MD DA[0], MD DA[1] on the leg.The 8-6 leg of described output build-out resistor part RP13 is received D DIOR-, D DIOW-, the D DMACK-leg of the CN2 of described encipher hard disc module section respectively, and the 1-3 leg of described output build-out resistor part RP13 is received respectively on MD DIORi, MD DIOWi, the MD DMACKi leg of the circuit U 1 of described encryption chip part.The 8-6 leg of described output build-out resistor part RP14 is received D IORDY, D DMARQ, the D INTRQ leg of the CN2 of described encipher hard disc module section respectively, and the 1-3 leg of described output build-out resistor part RP 14 is received respectively on MD IORDY, MD DMARQ, the MD INTRQ leg of the circuit U 1 of described encryption chip part.Described output build-out resistor part resistance R
13An end connect the D RESET-leg of described encipher hard disc module CN2, its other end is received the MD RESETi leg of the circuit U 1 of described encryption chip part.Described output build-out resistor part resistance R
14An end connect the D DA2 leg of described encipher hard disc module CN2, its other end is received the MD DA[2 of the circuit U 1 of described encryption chip part] leg.Described output build-out resistor part resistance R
15An end connect the D IORDY leg of described encipher hard disc module CN2, its another termination VCC.Described output build-out resistor part resistance R
16An end connect the D DMARQ leg of described encipher hard disc module CN2, its another termination GND.Described output build-out resistor part resistance R
17An end connect the D INTRQ leg of described encipher hard disc module CN2, its another termination GND.
2,19,22,24,26,30,40 leg that meet described encipher hard disc module CN2 are received on the GND simultaneously.
The described resistance R of described encryption chip part
1An end connect the PH1 leg of described circuit U 1, its another termination VDD3.The described resistance R of described encryption chip part
2An end connect the PH2 leg of described circuit U 1, its another termination VDD3.
Described voltage transformation module partly comprises circuit U 2, capacitor C 1 and C2.Described circuit U 2 the 3rd leg connects the VCC power supply, and the 1st leg connects VDD3, and the 2nd leg meets GND.One end of described capacitor C 1 connects VCC power supply, its another termination GND.One end of described capacitor C 2 connects VDD3, its another termination GND.
Described electric source filter circuit partly comprises capacitor C 5-C20 in parallel.The end of described capacitor C 5-C20 connects VCC power supply, its another termination GND POWER.
Described clock source module partly comprises crystal oscillator SYS, resistance R 3, capacitor C 3 and C4.Described crystal oscillator SYS and resistance R 3 parallel connections, an one common port connects the XIN leg of described encryption chip circuit U 1 partly and an end of described capacitor C 3, and its another common port connects the XOUT leg of described encryption chip circuit U 1 partly and an end of described capacitor C 4; The other end of the other end of described capacitor C 3 and described capacitor C 4 is ground connection simultaneously.
Described electronic key partly comprises E-KEY, diode D1 and resistance R 4.The the 1st to 6 leg of described E-KEY connects respectively: SEEPROM-DO, SEEPROM-DI, SEEPROM-SK, the SEEPROM-CS leg of the circuit U 1 of described diode D1 negative pole, GND POWER and encryption chip part; The positive pole of described diode D connects VCC by described resistance R 4.
Described state indicating module partly comprises power supply indication POW-LED, mistake indication ERR-LED, read-write indication RW-LED and resistance R 5, R6 and R7.One termination VDD3 of described resistance R 5, the positive pole of the described RW-LED of another termination of described resistance R 5, the negative pole of described RW-LED connect the D DASP-leg of the CN2 of described encipher hard disc module.One end of described resistance R 6 connects the KEY-ERR leg of the circuit U 1 of described encryption chip part, the positive pole of the described ERR-LED of another termination of described resistance R 6, and the negative pole of described ERR-LED connects GND-POWER.One termination VDD3 of described resistance R 7, the positive pole of the described POW-LED of another termination of described resistance R 7, the negative pole of described POW-LED connects GND-POWER.
Described mode of operation is provided with module section and comprises JP1, JP2, JP3, JP4 and RP15.The 1st leg of described JP1, JP2, JP3, JP4 connects DES-ENA, DEV-SEL, CLK-MODE0, the CLK-MODE1 of the circuit U 1 of described encryption chip part respectively, and receives the 8th to 5 leg of described RP15 simultaneously respectively.Described JP1, JP2, JP3, JP4 the 2nd leg be ground connection simultaneously.The the 1st to 4 leg of described RP15 is received on the VDD3 simultaneously.
The model of described RP1-RP4 is RP4-33, the model of RP8-RP12 is RP4-33, the model of RP5, RP6, RP14 is RP4-82, the model of RP7, RP13 is RP4-68, the model of RP15 is RP4-10K, the model of E-KEY is 93C46, and the model of JP1-JP4 is CON2, and the model of CN1-CN2 is FKV40SN.
When mainboard ide interface module is input to data to be encrypted in the encryption chip by the input build-out resistor,,, ciphertext is saved in the encipher hard disc module by the output build-out resistor with expressly being converted into the form of ciphertext by the encrypting conversion of encryption chip.In reading of data, send out reading command to data encryption device, when passing through encryption chip, the data that read are converted into expressly form by original ciphertext form.Described voltage transformation module is the voltage that the voltage transitions of VCC is become VDD3, uses for whole data encryption device.Described electric source filter circuit is the Filtering Processing of the voltage after the conversion being carried out high and low frequency, makes it obtain the galvanic current source.Electronic key is the key of store data encryption device password, and it separates with data encryption device.The state indicating module is the working indicating of data encryption device, comprises mistake indication, power supply indication and disk read-write indication.It is the circuit that is provided with to the duty of data encryption device that mode of operation is provided with module, can whether encrypt being provided with etc. of setting, data transfer mode of setting, principal and subordinate's dish.The clock source module is to provide the clock source for encryption chip.In the encapsulation of electronic key the inside is a storage chip, its internal storage one group of key that is generated by tandom number generator (RandomGenerator), the length of its key is according to the difference of the secret grade of encryption chip and difference, and key length of the present invention is 2
112When portable computer hard disc not being encrypted, mainboard IDE data cable is directly received the FPDP of hard disk, can normally use.When by encryption device the time, receive earlier on the mainboard ide interface module from the IDE data cable that mainboard comes out, be connected on the encrypted hard disk by the output build-out resistor, that is to say can be the present invention as being an IDE lock road, and the write-read of data all comes encryption and decryption by it.
The principle of work of its encryption and decryption is: when detecting when powering on Power-on or Reset signal, the state that is provided with that the interceptor of encryption chip inside (Interceptor) can be differentiated on encrypted card earlier is By Pass, Master or Slave, this is the function of selecting by wire jumper (Jumper) that encryption chip provides.When wire jumper (Jumper) though be exactly data encryption device to be arranged but the function that do not have to encrypt when being transferred to By Pass, when if wire jumper (Jumper) is transferred to Master or Slave, encrypt to Primary Hard Drive (Master HDD) or from hard disk (Slave HDD) exactly, can have the user to decide in its sole discretion.Being determined to is Primary Hard Drive or during from the state of hard disk, data encryption device will send the requirement of " password conveying " to electronic key (Security Key).When receiving from the password of encryption chip, carries when requiring electronic key, just this can be organized password sends inner working storage to and transfers to the crypto-operation engine again, calculate out secret value by DES (Data Encryption Standard)/TDES (Three Data Encryption Standard) algorithm that the crypto-operation engine is possessed according to this group password, do the 0th track that is written to hard disk when distinguishing at hard disk, when the hard disk differentiation was finished, the encrypting and authenticating function had also been finished thereupon.To plug electronic key just when later on the user uses a computer and to find encipher hard disc, just key can be pulled out after ending machine.After computing machine is turned off power supply, again during the promptly hard start of start, need plug key again,, then not need to plug again electronic key if Windows " start again " or " withdrawing from the user " logins when being soft start more again.
Experiment showed, that structure of the present invention is simple relatively, be convenient to make that process stabilizing is fit to popularize and produces.
Claims (9)
1. portable computer data enciphering device, described data encryption device comprises: mode of operation is provided with module, clock source module, mainboard ide interface module, input build-out resistor, output build-out resistor, voltage transformation module and electric source filter circuit part; It is characterized in that:
Described data encryption device also comprises: encryption chip, encipher hard disc module, electronic key and state indicating module part;
Described mode of operation is provided with module section and connects to described encryption chip part, and described clock source module partly connects to described encryption chip part;
Described mainboard ide interface module section and described input build-out resistor partly interconnect, described input build-out resistor part and described encryption chip partly interconnect, described encryption chip part and described output build-out resistor partly interconnect, and described output build-out resistor part and described encipher hard disc module section interconnect;
Described voltage transformation module partly connects to described encryption chip part;
Described electric source filter circuit part partly interconnects with described voltage transformation module part, described encryption chip respectively;
Described encryption chip partly connects to described state indicating module part;
Described electronic key partly connects to described encryption chip part.
2. data encryption device according to claim 1 is characterized in that:
Described input build-out resistor partly comprises RP1, RP2, RP3, RP4, RP5, RP6 and RP7, also comprises resistance R
8And R
9
Described encryption chip partly comprises circuit U 1, resistance R
1And resistance R
2
Described output build-out resistor partly comprises RP8, RP9, RP10, RP11, RP12, RP13, RP14 and resistance R
13, R
14, R
15, R
16, R
17And R
18
Described encipher hard disc module section comprises CN2 and resistance R
10, R
11And R
12
The 1-4 leg of the RP1 of described input build-out resistor part is received H DD0 to the H DD3 leg of described mainboard ide interface module section respectively, and the 5-8 leg of the RP1 of described input build-out resistor part is received the MH DD[3 of the circuit U 1 of described encryption chip part respectively] to MH DD[0] leg;
The 1-4 leg of the RP2 of described input build-out resistor part is received H DD4 to the H DD7 leg of described mainboard ide interface module section respectively, and the 5-8 leg of the RP2 of described input build-out resistor part is received the MH DD[7 of the circuit U 1 of described encryption chip part respectively] to MH DD[4] leg;
The 5th leg of the RP2 of described input build-out resistor part connects described resistance R
9An end, described resistance R
9The other end receive GND-POWER;
The 1-4 leg of the RP3 of described input build-out resistor part is received H DD8 to the H DD11 leg of described mainboard ide interface module section respectively, and the 5-8 leg of the RP3 of described input build-out resistor part is received the MH DD[11 of the circuit U 1 of described encryption chip part respectively] to MH DD[8] leg;
The 1-4 leg of the RP4 of described input build-out resistor part is received H DD12 to the HDD15 leg of described mainboard ide interface module section respectively, and the 5-8 leg of the RP4 of described input build-out resistor part is received the MH DD[15 of the circuit U 1 of described encryption chip part respectively] to MH DD[12] leg;
The 8-5 leg of the RP5 of described input build-out resistor part is received H DMACK-, H DIOW-, H DIOR and the H DA2 leg of described mainboard ide interface module section respectively, and the 1-4 leg of the RP5 of described input build-out resistor part is received MH DMACKi, MH DIOWi, MH DIORi and the MH DA[2 of the circuit U 1 of described encryption chip part respectively] leg;
The 8-5 leg of the RP6 of described input build-out resistor part is received H DA1, H DA0, H CS1 and the H CS0 leg of described mainboard ide interface module section respectively, and the 1-4 leg of the RP6 of described input build-out resistor part is received the MHDA[1 of the circuit U 1 of described encryption chip part respectively], MH DA[0], MH CSi[1] and MH CSi[2] leg;
The 8-6 leg of the RP7 of described input build-out resistor part is received H INTRQ, H DMARQ, the H IORDY leg of described mainboard ide interface module section respectively, and the 1-3 leg of the RP7 of described input build-out resistor part is received MHINTRQ, MH DMARQ, the MH IORDY leg of the circuit U 1 of described encryption chip part respectively;
Described resistance R
8A H REST-leg that terminates to described mainboard ide interface module section, the other end is received the MH RESTi leg of the circuit U 1 of described encryption chip part;
2,19,22,24,26,30 and 40 leg of the CN1 of described mainboard ide interface module section are received on the GND simultaneously;
The resistance R of described encipher hard disc module section
10A H CSEL leg that terminates to the CN1 of described mainboard ide interface module section, its other end is received on the D CSEL leg of described encipher hard disc module section CN2;
The resistance R of described encipher hard disc module section
11A H PDIAG-leg that terminates to the CN1 of described mainboard ide interface module section, its other end is received on the D PDIAG-leg of described encipher hard disc module section CN2;
The resistance R of described encipher hard disc module section
12A H DASP-leg that terminates to the CN1 of described mainboard ide interface module section, its other end is received on the D DASP-leg of described encipher hard disc module section CN2;
The 1-4 leg of described output build-out resistor part RP8 is received D DD0 to the D DD3 leg of the CN2 of described encipher hard disc module section respectively, and the 5-8 leg of described output build-out resistor part RP8 is received the MD DD[3 of the circuit U 1 of described encryption chip part respectively] to MD DD[0] on the leg;
The 1-4 leg of described output build-out resistor part RP9 is received D DD4 to the D DD7 leg of the CN2 of described encipher hard disc module section respectively, and the 5-8 leg of described output build-out resistor part RP9 is received the MD DD[7 of the circuit U 1 of described encryption chip part respectively] to MD DD[4] on the leg;
The 5th leg of described output build-out resistor part RP9 is received described resistance R
18An end.Described resistance R
18The other end receive on the GND-POWER;
The 1-4 leg of described output build-out resistor part RP10 is received D DD8 to the D DD11 leg of the CN2 of described encipher hard disc module section respectively, and the 5-8 leg of described output build-out resistor part RP10 is received the MD DD[11 of the circuit U 1 of described encryption chip part respectively] to MD DD[8] on the leg;
The 1-4 leg of described output build-out resistor part RP11 is received D DD12 to the D DD15 leg of the CN2 of described encipher hard disc module section respectively, and the 5-8 leg of described output build-out resistor part RP11 is received the MD DD[15 of the circuit U 1 of described encryption chip part respectively] to MD DD[12] on the leg;
The 8-5 leg of described output build-out resistor part RP12 is received D CS0-, D CS1-, D DA0, the D DA1 leg of the CN2 of described encipher hard disc module section respectively, and the 1-4 leg of described output build-out resistor part RP12 is received the MD CSi[0 of the circuit U 1 of described encryption chip part respectively], MD CSi[1], MD DA[0], MD DA[1] on the leg;
The 8-6 leg of described output build-out resistor part RP13 is received D DIOR-, D DIOW-, the D DMACK-leg of the CN2 of described encipher hard disc module section respectively, and the 1-3 leg of described output build-out resistor part RP13 is received respectively on MDDIORi, MD DIOWi, the MD DMACKi leg of the circuit U 1 of described encryption chip part;
The 8-6 leg of described output build-out resistor part RP14 is received D IORDY, D DMARQ, the D INTRQ leg of the CN2 of described encipher hard disc module section respectively, and the 1-3 leg of described output build-out resistor part RP14 is received respectively on MDIORDY, MD DMARQ, the MD INTRQ leg of the circuit U 1 of described encryption chip part;
Described output build-out resistor part resistance R
13An end connect the D RESET-leg of described encipher hard disc module CN2, its other end is received the MDRESETi leg of the circuit U 1 of described encryption chip part;
Described output build-out resistor part resistance R
14An end connect the D DA2 leg of described encipher hard disc module CN2, its other end is received the MD DA[2 of the circuit U 1 of described encryption chip part] leg;
Described output build-out resistor part resistance R
15An end connect the D IORDY leg of described encipher hard disc module CN2, its another termination VCC;
Described output build-out resistor part resistance R
16An end connect the D DMARQ leg of described encipher hard disc module CN2, its another termination GND;
Described output build-out resistor part resistance R
17An end connect the D INTRQ leg of described encipher hard disc module CN2, its another termination GND;
2,19,22,24,26,30,40 leg that meet described encipher hard disc module CN2 are received on the GND simultaneously;
The described resistance R of described encryption chip part
1An end connect the PH1 leg of described circuit U 1, its another termination VDD3;
The described resistance R of described encryption chip part
2An end connect the PH2 leg of described circuit U 1, its another termination VDD3.
3. data encryption device according to claim 1 is characterized in that:
Described voltage transformation module partly comprises circuit U 2, capacitor C 1 and C2;
Described circuit U 2 the 3rd leg connects the VCC power supply, and the 1st leg connects VDD3, and the 2nd leg meets GND;
One end of described capacitor C 1 connects VCC power supply, its another termination GND;
One end of described capacitor C 2 connects VDD3, its another termination GND.
4. data encryption device according to claim 1 is characterized in that:
Described electric source filter circuit partly comprises capacitor C 5-C20 in parallel;
The end of described capacitor C 5-C20 connects VCC power supply, its another termination GND POWER.
5. data encryption device according to claim 1 is characterized in that:
Described clock source module partly comprises crystal oscillator SYS, resistance R 3, capacitor C 3 and C4;
Described crystal oscillator SYS and resistance R 3 parallel connections, an one common port connects the XIN leg of described encryption chip circuit U 1 partly and an end of described capacitor C 3, and its another common port connects the XOUT leg of described encryption chip circuit U 1 partly and an end of described capacitor C 4; The other end of the other end of described capacitor C 3 and described capacitor C 4 is ground connection simultaneously.
6. data encryption device according to claim 1 is characterized in that:
Described electronic key partly comprises E-KEY, diode D1 and resistance R 4;
The the 1st to 6 leg of described E-KEY connects respectively: SEEPROM-DO, SEEPROM-DI, SEEPROM-SK, the SEEPROM-CS leg of the circuit U 1 of described diode D1 negative pole, GNDPOWER and encryption chip part; The positive pole of described diode D connects VCC by described resistance R 4.
7. data encryption device according to claim 1 is characterized in that:
Described state indicating module partly comprises power supply indication POW-LED, mistake indication ERR-LED, read-write indication RW-LED and resistance R 5, R6 and R7; One termination VDD3 of described resistance R 5, the positive pole of the described RW-LED of another termination of described resistance R 5, the negative pole of described RW-LED connect the D DASP-leg of the CN2 of described encipher hard disc module; One end of described resistance R 6 connects the KEY-ERR leg of the circuit U 1 of described encryption chip part, the positive pole of the described ERR-LED of another termination of described resistance R 6, and the negative pole of described ERR-LED connects GND-POWER; One termination VDD3 of described resistance R 7, the positive pole of the described POW-LED of another termination of described resistance R 7, the negative pole of described POW-LED connects GND-POWER.
8. data encryption device according to claim 1 is characterized in that:
Described mode of operation is provided with module section and comprises JP1, JP2, JP3, JP4 and RP15;
The 1st leg of described JP1, JP2, JP3, JP4 connects DES-ENA, DEV-SEL, CLK-MODE0, the CLK-MODE1 of the circuit U 1 of described encryption chip part respectively, and receives the 8th to 5 leg of described RP15 simultaneously respectively; Described JP1, JP2, JP3, JP4 the 2nd leg be ground connection simultaneously; The the 1st to 4 leg of described RP15 is received on the VDD3 simultaneously.
9. data encryption device according to claim 1 is characterized in that: the model of described RP1-RP4 is RP4-33; The model of RP8-RP12 is RP4-33; The model of RP5, RP6, RP14 is RP4-82; The model of RP7, RP13 is RP4-68; The model of RP15 is RP4-10K; The model of E-KEY is 93C46; The model of JP1-JP4 is CON2; The model of CN1-CN2 is FKV40SN.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNA2006100572218A CN1811737A (en) | 2006-03-09 | 2006-03-09 | Portable computer data enciphering device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNA2006100572218A CN1811737A (en) | 2006-03-09 | 2006-03-09 | Portable computer data enciphering device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN1811737A true CN1811737A (en) | 2006-08-02 |
Family
ID=36844667
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CNA2006100572218A Pending CN1811737A (en) | 2006-03-09 | 2006-03-09 | Portable computer data enciphering device |
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| Country | Link |
|---|---|
| CN (1) | CN1811737A (en) |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN100403281C (en) * | 2006-09-01 | 2008-07-16 | 西安交通大学 | Dynamic key based hardware data enciphering method and device thereof |
| CN102236751A (en) * | 2010-04-22 | 2011-11-09 | 研华股份有限公司 | Computer system with safety lock and method for implementing safety lock |
| CN102508794A (en) * | 2011-11-09 | 2012-06-20 | 山东惠影科技传媒股份有限公司 | Encryption system for digital program hard disk |
| CN102522062A (en) * | 2011-12-01 | 2012-06-27 | 深圳市洲明科技股份有限公司 | Encryption system of light emitting diode (LED) display screen |
-
2006
- 2006-03-09 CN CNA2006100572218A patent/CN1811737A/en active Pending
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN100403281C (en) * | 2006-09-01 | 2008-07-16 | 西安交通大学 | Dynamic key based hardware data enciphering method and device thereof |
| CN102236751A (en) * | 2010-04-22 | 2011-11-09 | 研华股份有限公司 | Computer system with safety lock and method for implementing safety lock |
| CN102508794A (en) * | 2011-11-09 | 2012-06-20 | 山东惠影科技传媒股份有限公司 | Encryption system for digital program hard disk |
| CN102508794B (en) * | 2011-11-09 | 2014-04-02 | 山东惠影科技传媒股份有限公司 | Encryption system for digital program hard disk |
| CN102522062A (en) * | 2011-12-01 | 2012-06-27 | 深圳市洲明科技股份有限公司 | Encryption system of light emitting diode (LED) display screen |
| CN102522062B (en) * | 2011-12-01 | 2013-12-04 | 深圳市洲明科技股份有限公司 | Encryption system of light emitting diode (LED) display screen |
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