CN1808909A

CN1808909A - Sampling and charge transfer circuit with supply voltage as common mode input voltage

Info

Publication number: CN1808909A
Application number: CN 200510132082
Authority: CN
Inventors: 李福乐; 谭年熊; 刘力源
Original assignee: Wangong Sci & Tech Co Ltd Beijing
Current assignee: Hangzhou Vango Science & Technology Co., Ltd.; Wangong Sci. & Tech. Co., Ltd., Beijing
Priority date: 2005-12-23
Filing date: 2005-12-23
Publication date: 2006-07-26

Abstract

This invention relates to input common mode voltage as power voltage sampling and charge transferring circuit, which belongs to integration circuit design technique field and comprises one outer input voltage maximum power, more than one outer voltage maximum to get maximum power; static protective circuit by two transistors; sampling and charge transfer circuit composed of four transistors, sampling capacitors and clock circuits; integrator circuit composed one computation amplifier and one integral capacitor.

Description

Common mode input is the sampling and the charge transfer circuit of supply voltage

Technical field

The present invention relates to sampling and charge transfer circuit that a kind of common mode input is a supply voltage, belong to the integrated circuit (IC) design technical field.

Background technology

Switched-capacitor circuit is a kind of widely used circuit design technique.In switched-capacitor circuit, generally between the discrete signal treatment circuit of signal continually varying analog input end and internal clocking control, provide an interface, this interface comprises the sample circuit that input signal is adopted, i.e. turning on and off by one group of switch, on sampling capacitance, obtain turn-offing the directly proportional electric charge of input voltage constantly with switch, in addition, also comprise charge transfer circuit, promptly, the electric charge that keeps on the sampling capacitance is transferred to internal circuit by the shutoff and the connection of other one group of switch.For example, in the oversampling analog-to-digital converter circuit, input end of analog signal and inner the quantification need such sampling and charge transfer circuit as interface between the change-over circuit, by sampling and electric charge transfer operation the continually varying analog input signal is converted to discrete signal, then, Nei Bu change-over circuit is quantified as corresponding digital code with each value of this discrete signal.

One example can be with reference to United States Patent (USP) 5,134 more specifically, 401 content, and its interface circuit is as shown in Figure 1.Wherein, sampling capacitance CS and four transistor m1, m2, m, m4 and the interconnection line between them have constituted sampling and charge transfer circuit, and control signal PH1 that oxide-semiconductor control transistors turns on and off and the sequential relationship of PH2 are as shown in Figure 2.In the sampling phase, PH2 is that height and PH1 are low, and transistor m1 and m3 connect, and m2 and m4 turn-off, and like this, the voltage at capacitor C S two ends is for equaling input voltage VIN, and correspondingly the electric charge on the capacitor C S is (VIN-VREF) * CS; Shifting phase, Ph1 is that height and PH2 are low, and transistor m2 and m4 connect, and m1 and m3 turn-off, like this, under the effect of the integrating circuit that amplifier A1 and integrating capacitor CI are constituted, capacitor C S goes up electric charge (VIN-VREF) the * CS that preserves and is transferred on the integrating capacitor CI.

Be pointed out that, Fig. 1 has just provided the circuit that single-ended signal is handled, this is based on the needs of concise description circuit working principle, actual application might be that the internal signal treatment circuit is the fully differential structure, (end that is signal was fixed as a direct current voltage and input signal both can be single-ended signal, the other end is that the center changes up and down with it, this direct voltage is called common mode input), also can be differential signal (is that all to center on a direct current voltage be that the center changes up and down for the two ends of signal, and change in the opposite direction, the direct voltage here is called common mode input).Consider this point, the reference voltage VREF that transistor m2 among Fig. 1 need be connected to, its value should be common mode input, and the positive input terminal of transistor m3 and amplifier A1 also need be connected to a reference voltage, this reference voltage can be identical with the reference voltage that transistor m2 connects, i.e. VREF.Under the single ended power supply electric power thus supplied, generally between supply voltage and ground, typically, its value can be 1/2 of supply voltage to the value of reference voltage.

It should be noted that the angle from system design, the general requirement outputs to chip exterior with a reference voltage of chip internal, is used for determining the common mode electrical level of input signal.In design shown in Figure 1, the value of reference voltage VREF is between supply voltage and ground, therefore need the pin of a special use that reference voltage VREF is outputed to the external definite input common mode electrical level of sheet, and, reference voltage VREF produces circuit must have stronger driving force, to guarantee importing the stable of common mode electrical level, obviously, these 2 all is disadvantageous to the cost of chip and the control of power consumption.A way of head it off is that input common-mode is set to ground voltage, and like this, internal reference voltage VREF need not output to outside the sheet, has saved a pin, and, reduce the driving requirement that reference voltage VREF is produced circuit.Yet, for circuit shown in Figure 1, when the input common mode is ground, the situation of ground voltage just may appear being lower than in the value of input signal VIN, in the case, the N type substrate of N type MOS transistor (MOS transistor) m1 ground connection and the just possible conducting of PN junction that is connected between the P type source end (or drain terminal) of importing VIN, thus the voltage of input VIN is caused the clamper effect.United States Patent (USP) 5,872,469 have proposed a kind of improved sampling and charge transfer circuit, can be used to head it off, concrete method is, transistor m1 and m2 are revised as P type MOS transistor, is input VIN clamper effect under the ground voltage situation to solve input common mode voltage; Then, that introduces that two level shift circuits adjust switch controlling signal on transistor m1 and the m2 respectively turns on and off control voltage, still can normally turn on and off near signal is ground voltage to guarantee the PMOS transistor switch.

Although U.S. Patent No. 5; 872; 469 import the clamper effect by solution makes common mode input can be ground voltage; thereby can be used to save a pin and the requirement that reduces generating circuit from reference voltage; yet; this order input common mode may be conflicted with the design of at present known chip electro-static discharge (hereinafter to be referred as ESD) protective circuit mutually for the processing method on ground, thereby brings the new problem of esd protection circuit design, or increases the design difficulty of esd protection circuit.This be because; pointed as this patent itself; for chip design based on complementary metal oxide semiconductors (CMOS) (hereinafter to be referred as CMOS) technology; the single ended power supply power supply is more suitable; so; under the single ended power supply power supply; the applied signal voltage that the esd protection circuit of at present known CMOS chip generally requires to be inserted on its pad (hereinafter to be referred as PAD) is between ground and supply voltage; otherwise just might bring the voltage clamp effect to input signal; and the input common mode for when ground applied signal voltage can be lower than ground, this has exceeded ground and the included scope of supply voltage.

In fact, there is the different single ended power supply of a plurality of voltages in the present chip more and more, this be because, integrated circuit (IC) design forward SOC (system on a chip) (SOC) direction develops, increasing chip is integrated into chip internal with the power circuit that originally is placed on outside the sheet in design, that is to say, system provides a power supply to chip, chip is that one or more voltages are lower by inner power circuit (for example linear voltage-stabilizing circuit) with this outside access power source conversion, but the internal electric source of more stable (for example ripple is littler) powers to internal circuit, simultaneously, these internal electric sources also will be connected with the sheet lotus root electric capacity that goes outward by pin separately, to reduce the noise on the internal electric source.In view of the situation, can consider to utilize the power supply of different voltages to be used as importing the power supply of common mode and esd protection circuit, when obtaining the advantage of U.S. Patent No. 5,872,469, solve its aforesaid esd protection circuit problem.

Summary of the invention

The objective of the invention is to propose sampling and the charge transfer circuit that a kind of common mode input is a supply voltage; to have the power supply of the power supply of ceiling voltage as known esd protection circuit; power supply with low voltage is used for determining common mode input; and guarantee its operate as normal with charge transfer circuit by improving sampling, to save chip pin and to reduce the requirement that sheet internal reference voltage VREF is produced circuit.

The common mode input that the present invention proposes is the sampling and the charge transfer circuit of supply voltage, comprises first, second, third, fourth transistor, sampling capacitance and clock circuit; In the source electrode of described the first transistor or the drain electrode one very is sampled the input of signal, the drain electrode of the first transistor or another utmost point in the source electrode are connected with an end and the drain electrode of transistor seconds or the utmost point in the source electrode of described sampling capacitance simultaneously, the substrate of the first transistor is connected with the highest power supply of the substrate of described transistor seconds while and described external voltage, and the grid of the first transistor is connected with the reverse second clock holding wire of described clock circuit output; One in the drain electrode of transistor seconds or another utmost point in the source electrode and the lower power supply of described voltage is connected, and the grid of transistor seconds is connected with reverse first clock cable of described clock circuit output; Utmost point in a utmost point in the 3rd transistor drain or the source electrode and the 4th transistor drain or the source electrode is connected with the other end of described sampling capacitance simultaneously, the 3rd transistorized substrate and the described the 4th transistorized substrate be ground connection simultaneously, the 3rd transistorized grid is connected with the forward second clock holding wire of described clock circuit output, and another utmost point in the 3rd transistor drain or the source electrode links to each other with this circuit reference voltage signal line outward; Another utmost point in the 4th transistor drain or the source electrode is as the output of this circuit.

Above-mentioned sampling and charge transfer circuit can also comprise:

The power supply that the voltage of (1) outside input is the highest, one or more are by outside input or the lower power supply of voltage that obtained by the highest power source conversion of described external voltage;

(2) the 5th, the 6th transistor and resistance, in order to constitute ESD protection circuit, the described the 5th transistorized grid, source electrode and substrate are connected with the highest power supply of described external voltage simultaneously, the 6th transistorized grid, source electrode and substrate be ground connection simultaneously, be connected with an end of described resistance after the 5th transistor AND gate the 6th transistor drain is connected, the other end of described resistance is connected with the sampled signal input of charge transfer circuit with described sampling;

(3) operational amplifiers and an integrating capacitor, in order to constitute integrator circuit, one end of the negative input end of described operational amplifier and described integrating capacitor is connected with the output of charge transfer circuit with described sampling simultaneously, the positive input terminal of operational amplifier links to each other with described circuit reference voltage signal line outward, and the output of operational amplifier is connected with the other end of integrating capacitor.

The common mode input that the present invention proposes is the sampling and the charge transfer circuit of supply voltage, and its advantage is:

1, saves chip pin, therefore reduced chip area, reduced circuit cost.

2, reduced the requirement that sheet internal reference voltage VREF is produced the output driving force of circuit, thereby reduced chip power-consumption and reduce the circuit design difficulty.

3, therefore the applied signal voltage of circuit can directly adopt known ESD protection circuit between the power supply and ground of ESD protection circuit, need not circuit is redesigned.

Description of drawings

Fig. 1 is existing sampling and charge transfer circuit.

Fig. 2 is the signal timing diagram of circuit shown in Figure 1.

Fig. 3 is sampling and the charge transfer circuit figure that the present invention proposes.

Fig. 4 is the signal timing diagram of circuit shown in Figure 3.

Embodiment

The common mode input that the present invention proposes be supply voltage sampling and charge transfer circuit an embodiment as shown in Figure 3, comprise an outside the highest power supply of importing of voltage; One or more are by outside input or the lower power supply of voltage that obtained by the highest power source conversion of described external voltage; The ESD protection circuit that constitutes by the 5th transistor MP, the 6th transistor MN and resistance R 1; The sampling and the charge transfer circuit that constitute by the first transistor MP1, transistor seconds MP1, the 3rd transistor MN1, the 4th transistor MN2, sampling capacitance CS and clock circuit; And by an operational amplifier A 1 and the integrator circuit that integrating capacitor CI constitutes.

In the foregoing circuit, the grid of the 5th transistor MP, source electrode and substrate are connected with the highest power supply of external voltage simultaneously, the grid of the 6th transistor MN, source electrode and substrate be ground connection simultaneously, be connected with an end of resistance R 1 after the 5th transistor MP is connected with the drain electrode of the 6th transistor MN, the other end of resistance R 1 is connected with the sampled signal input of charge transfer circuit with sampling.Utmost point in the source electrode of the first transistor MP1 or the drain electrode is connected with the other end of resistance R 1, as the input that is sampled signal, the drain electrode of the first transistor or another utmost point in the source electrode are connected with an end and the drain electrode of transistor seconds MP2 or the utmost point in the source electrode of sampling capacitance CS simultaneously, the substrate of the substrate of the first transistor MP1 and transistor seconds MP2 is connected with the highest power supply of external voltage simultaneously, and the grid of the first transistor MP1 is connected with the reverse second clock holding wire NPH2 that clock circuit is exported.One in the drain electrode of transistor seconds MP2 or another utmost point in the source electrode and the lower power supply of voltage is connected, and the grid of transistor seconds MP2 is connected with the reverse first clock cable NPH1 of clock circuit output.Utmost point in a utmost point in the drain electrode of the 3rd transistor MN1 or the source electrode and the drain electrode of the 4th transistor MN2 or the source electrode is connected with the other end of sampling capacitance CS simultaneously, the substrate of the substrate of the 3rd transistor MN1 and the 4th transistor MN2 is ground connection simultaneously, the grid of the 3rd transistor MN1 is connected with the forward second clock holding wire PH2 of clock circuit output, and another utmost point in the 3rd transistor drain or the source electrode links to each other with circuit reference voltage signal line outward.The drain electrode of the 4th transistor MN2 or another utmost point in the source electrode are as the output of sampling with charge transfer circuit.The end of the negative input end of operational amplifier A 1 and integrating capacitor CI is connected with the output of charge transfer circuit with sampling simultaneously, the positive input terminal of operational amplifier A 1 links to each other with circuit reference voltage signal line outward, and the output of operational amplifier A 1 is connected with the other end of integrating capacitor CI.

In the embodiment of the invention, the highest power supply of voltage of outside input is 5 volts, and the lower power supply of voltage of being imported or being obtained by the highest power source conversion of described external voltage by the outside is one, is 3 volts.

From the circuit diagram of present embodiment as can be seen, the present invention is that to make sampling and charge transfer circuit be operate as normal under the situation of chip internal supply voltage at common mode input, at first, change the transistor m1 and the m2 of circuit shown in Figure 1 in the prior art into P-type mos (hereinafter to be referred as PMOS) transistor, these two switches can normally turn on and off when changing near internal power source voltage with the assurance input signal; Secondly, the substrate of PMOS transistor m1 and m2 and the power end of esd protection circuit are connected to the higher power supply of voltage, when being higher than internal power source voltage, the clamper effect can occur to guarantee input voltage.

Below in conjunction with Fig. 3, introduce the operation principle and the course of work of the above embodiment of the present invention in detail.

In Fig. 3, system is a single power supply, supply voltage is 5V, chip internal is integrated power circuit, with the 5V power source conversion of sending into chip is the 3V power supply, this 3V power supply is on-chip circuit power supply, and delivers to that sheet is outer to be connected with removing lotus root electric capacity, determines the common mode electrical level of input signal and powers to external circuit under the situation of needs.

For technical characterstic of the present invention is described, embodiments of the invention give the known esd protection circuit on the PAD that analog input signal inserts when giving the sampling and charge transfer circuit that make new advances.PMOS transistor MP; N type metal oxide semiconductor (hereinafter to be referred as NMOS) transistor MN; resistance R 1 and the interconnection line between them have constituted known esd protection circuit; wherein; PMOS transistor MP receives the higher 5V power supply of voltage; like this, can guarantee that in the input common mode be 3V, input signal VIN when changing up and down at 3V, itself can not cause clamper to input signal VIN this known esd protection circuit.

Sampling capacitance CS and four transistor MP1, MP2, MN1, MN2 and being connected to each other between them have constituted sampling and charge transfer circuit, wherein, the substrate of the first transistor MP1 and transistor seconds MP2 is connected to 5V with N trap independently, can guarantee that like this in the input common mode be 3V, when input signal VIN changes up and down at 3V, the PN junction that the P type source electrode of the first transistor MP1 and transistor seconds MP2 (or drain electrode) and N type substrate are constituted can forward conduction, promptly can not cause clamper to input signal VIN; The high level voltage of the grid control signal of the first transistor MP1 and transistor seconds MP2 reverse second clock signal NPH2 and the reverse first clock signal NPH1 is set to 5V, can guarantee like this when applied signal voltage VIN surpasses 3V, be in the situation that the first transistor MP1 under the off state and transistor seconds MP2 can not occur misleading.Transistor seconds MP2 is equivalent to and is connected to 3V but not reference voltage Vref among Fig. 1, and the positive input terminal of the 3rd transistor MN1 and amplifier A1 is connected to inner reference voltage VREF jointly, and the representative value of VREF is 1/2 of internal power source voltage, i.e. 1.5V here.The reverse second clock signal of switch controlling signal NPH2, the reverse first clock signal NPH1, forward second clock signal PH2 and the forward first clock signal PH1 of control the first transistor MP1, transistor seconds MP2, the 3rd transistor MN1 and the 4th transistor MN2 are produced by clock circuit, and its high-low level voltage and mutual sequential relationship are as shown in Figure 4.Sampling and charge transfer circuit shift alternation between the phase in sampling phase and electric charge respectively, in the sampling phase, oppositely second clock signal NPH2 is low level (0V), second clock signal PH2 is high level (3V), the reverse first clock signal NPH1 is high level (5V), the first clock signal PH1 is low level (0V), the first transistor MP1 and the 3rd transistor MN1 connect, transistor seconds MP2 and the 4th transistor MN2 turn-off, like this, voltage on the sampling capacitance CS equals input voltage VIN, and correspondingly the electric charge on the sampling capacitance CS is (VIN-VREF) * CS; Shifting phase, oppositely second clock signal NPH2 is high level (5V), forward second clock signal PH2 is low level (0V), the reverse first clock signal NPH1 is low level (0V), the forward first clock signal PH1 is high level (3V), the first transistor MP1 and the 3rd transistor MN1 turn-off, transistor seconds MP2 and the 4th transistor MN2 connect, like this, under the effect of the integrating circuit that amplifier A1 and integrating capacitor CI are constituted, sampling capacitance CS goes up the electric charge of preserving and is transferred on the integrating capacitor CI, the quantity of electric charge that is shifted is (VIN-VREF-3+VREF) * CS=(VIN-3) * CS, here, because the input common mode is 3V, VIN-3 is the signal voltage that will sample.

Claims

1, a kind of common mode input is the sampling and the charge transfer circuit of supply voltage, it is characterized in that this circuit comprises: first, second, third, fourth transistor, sampling capacitance and clock circuit;

In the source electrode of described the first transistor or the drain electrode one very is sampled the input of signal, the drain electrode of the first transistor or another utmost point in the source electrode are connected with an end and the drain electrode of transistor seconds or the utmost point in the source electrode of described sampling capacitance simultaneously, the substrate of the first transistor is connected with the highest power supply of the substrate of described transistor seconds while and described external voltage, and the grid of the first transistor is connected with the reverse second clock holding wire of described clock circuit output; One in the drain electrode of transistor seconds or another utmost point in the source electrode and the lower power supply of described voltage is connected, and the grid of transistor seconds is connected with reverse first clock cable of described clock circuit output; Utmost point in a utmost point in the 3rd transistor drain or the source electrode and the 4th transistor drain or the source electrode is connected with the other end of described sampling capacitance simultaneously, the 3rd transistorized substrate and the described the 4th transistorized substrate be ground connection simultaneously, the 3rd transistorized grid is connected with the forward second clock holding wire of described clock circuit output, and another utmost point in the 3rd transistor drain or the source electrode links to each other with this circuit reference voltage signal line outward; Another utmost point in the 4th transistor drain or the source electrode is as the output of this circuit.

2, sampling as claimed in claim 1 and charge transfer circuit is characterized in that this circuit also comprises: