CN101047381A - Voltage level conversion circuit, method and method for providing initial voltage - Google Patents
Voltage level conversion circuit, method and method for providing initial voltage Download PDFInfo
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- CN101047381A CN101047381A CN 200710091109 CN200710091109A CN101047381A CN 101047381 A CN101047381 A CN 101047381A CN 200710091109 CN200710091109 CN 200710091109 CN 200710091109 A CN200710091109 A CN 200710091109A CN 101047381 A CN101047381 A CN 101047381A
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Abstract
A voltage-electric level conversion circuit consists of an input buffer unit being connected between the first voltage source and a grounding voltage source and being used to receive input signal, an output buffer unit being connected between the second voltage source and a grounding voltage source and being used to output an output signal, a level processing unit being connected between input buffer unit and output buffer unit and being biased between the second voltage source and grounding voltage source for converting input signal to be output signal, a voltage drop unit connected to level processing unit and used to receive bias.
Description
Technical field
The present invention is a voltage level converting, and You Zhiyi has the voltage level converting of auto-initiation function.
Background technology
Voltage level converting (level shifter) places Circuits System in order to the changing voltage level usually.
See also Fig. 1, it is the function block schematic diagram of a voltage level converting 10 of using always.Voltage level converting 10 comprises: an input buffer cell 102 (input buffer) is biased between one first voltage source V DD and the ground voltage supplies GND, input buffer cell 102 is in order to receiving an input signal Vin, and wherein the voltage level range of input signal Vin is between the VDD to GND; One output buffer cell (output buffer) 106 is biased between one second voltage source V PP and the ground voltage supplies GND, output buffer cell 106 is in order to exporting an output signal Vout, and wherein the voltage level range of output signal Vout is between the VPP to GND; An and level processing unit 104, be electrically connected between input buffer cell 102 and the output buffer cell 106, be biased in the second voltage source V PP and ground voltage supplies GND, in order to the voltage level of input signal Vin is converted to voltage level VPP～GND of output signal Vout by VDD～GND.Wherein VPP is greater than VDD.
As shown in Figure 1, when a voltage level is after the input signal Vin of VDD～GND inputs to input buffer cell 102, processing via level processing unit 104, input signal Vin will be converted to the output signal Vout that a voltage level is VPP～GND, and, so can reach the purpose of conversion one voltage signal level via 106 outputs of output buffer cell.
In the foregoing circuit system,, therefore, can not guarantee that the first voltage source V DD and the second voltage source V PP can open simultaneously because the first voltage source V DD and the second voltage source V PP are two independently voltage sources.When the 2nd VPP has opened and the first voltage source V DD when not opening as yet, rely on the input buffer cell 102 of first voltage source V DD work can't normal operation, therefore the voltage of input buffer cell 102 outputs may be in a unknown state, the voltage signal of related output (being the output of the voltage level converting 10) output that influences next stage output buffer cell 106 is undesired, and may cause the system can't normal operation.
Summary of the invention
The invention provides a kind of voltage level converting, in order to change input signal to an output signal.Voltage level converting of the present invention includes: an input buffer cell is connected between one first voltage source and a ground voltage supplies, in order to receiving inputted signal; One output buffer cell is connected between one second voltage source and ground voltage supplies, in order to output signal output; One level processing unit is connected between input buffer cell and output buffer cell, is biased between second voltage source and ground voltage supplies, becomes this output signal in order to change this input signal; An and pressure drop unit, be connected to the level processing unit, receive the bias voltage of first voltage source and second voltage source, wherein do not open and second voltage source when having opened when first voltage source, the pressure drop unit provides an initial voltage to the level processing unit according to second voltage source.
The method that the present invention provides a kind of initial voltage to provide in addition, in order to the initial voltage of a voltage level converting to be provided, wherein voltage level converting operates between one first voltage source and one second voltage source.The method that initial voltage of the present invention provides comprises: open as yet and second voltage source when not opened when first voltage source, make the second voltage source step-down become initial voltage.
The present invention provides a kind of method of voltage level conversion in addition, converts an input signal to an output signal in order to utilize one first voltage source and one second voltage source.The method of voltage level conversion of the present invention includes: when first voltage source and second voltage source are all opened, utilize first voltage source and second voltage source to make input signal convert output signal to; And open as yet and second voltage source when not opened when first voltage source, provide an initial voltage to make input signal convert output signal to.
The method that voltage level converting of the present invention, method and initial voltage provide, can solve voltage level converting commonly used when high and low voltage level voltage source is not opened simultaneously, the voltage signal of voltage level converting output is undesired to cause the problem that system can't normal operation and produce.
Description of drawings
Fig. 1 is the function block schematic diagram for a voltage level converting of using always.
Fig. 2 is the function block schematic diagram for voltage level converting of the present invention.
Fig. 3 is the block schematic diagram for pressure drop of the present invention unit.
Fig. 4 is the examples of circuits figure for voltage level converting of the present invention.
Embodiment
The present invention must can get a more deep understanding by following graphic and explanation:
The present invention proposes a kind of voltage level converting makes voltage source V DD and voltage source V PP to reach opening synchronously, makes that voltage level converting can normal operation.
Fig. 2 is the function block schematic diagram of voltage level converting 20 of the present invention.Voltage level converting 20 is biased in one first voltage source V DD, one second voltage source V PP, and between a ground voltage supplies GND, wherein the voltage level of the second voltage source V PP is greater than the voltage level of the first voltage source V DD.Voltage level converting 20 comprises: an input buffer cell 302, receive an input signal Vin, and wherein the voltage level range of input signal Vin is VDD～GND; One output buffer cell 306, in order to export an output signal Vout, wherein the voltage level range of output signal Vout is VPP～GND; One level processing unit 304 is electrically connected between input buffer cell 302 and the output buffer cell 306, level processing unit 304 is biased between the second voltage source V PP and the ground voltage supplies GND, in order to being that the input signal Vin of VDD～GND converts the output signal Vout that voltage level range is VPP～GND to voltage level range.In addition, voltage level converting 20 of the present invention more comprises a pressure drop unit 308 and is electrically connected to level processing unit 304, and the bias voltage of the first voltage source V DD and the second voltage source V PP is accepted in pressure drop unit 308.In the present invention, when the first voltage source V DD did not open, pressure drop unit 308 can provide an initial voltage to level processing unit 304 according to the second voltage source V PP, makes voltage level converting 20 can not produce misoperation.
The present invention makes by pressure drop unit 308 and has opened and the first voltage source V DD when not opening as yet as the second voltage source V PP, provides an initial voltage to level processing unit 304.Thus, even cause the input buffer cell 302 that relies on first voltage source V DD work can't normal operation the time because the first voltage source V DD does not open as yet, level processing unit 304 still can be according to initial voltage and operate as normal, makes output buffer cell 306 can export a normal voltage signal.
See also Fig. 3, it is pressure drop unit 308 schematic diagrames according to an embodiment of the invention.In the present invention, pressure drop unit 308 includes a pressure drop element 3085 and a switch element 3087 serial connections.Wherein pressure drop element 3085 receives the bias voltage of the second voltage source V PP, and switch element 3087 receives the bias voltage of the first voltage source V DD and is connected to level processing unit 304.
As shown in Figure 3, suppose that the second voltage source V PP is for opening, and the first voltage source V DD is not for opening as yet, then make switch element 3087 open (ON), the element of pressure drop simultaneously 3085 can make the second voltage source step-down become an initial voltage, wherein the level of initial voltage afterwards, exports initial voltage to this level processing unit 304 via the switch element 3087 of opening (ON) again near the level of the first voltage source V DD.In addition, after the first voltage source V DD opens (that is the level of working as first voltage source reaches VDD), this moment, switch element 3087 can be closed (OFF), and voltage level converting 20 will be returned to normal operating state.That is voltage level converting 20 utilizes the first voltage source V DD to make input buffer cell 302 normal operations.
Please refer to Fig. 2 and Fig. 4, Fig. 4 is a circuit embodiments figure of the voltage level converting 20 according to the present invention.
As shown in Figure 4, input buffer cell 302 includes one the one P transistor npn npn Mp1, one the 2nd P transistor npn npn Mp2, one the one N transistor npn npn Mn1 and one the 2nd N transistor npn npn Mn2.Wherein the source electrode of a P transistor npn npn Mp1 and the 2nd P transistor npn npn Mp2 is connected to the first bias generator VDD respectively; The source electrode of the one N transistor npn npn Mn1 and the 2nd N transistor npn npn Mn2 is connected to ground connection bias generator GND respectively; The grid of the one P transistor npn npn Mp1 and one the one N transistor npn npn Mn1 is receiving inputted signal Vin respectively, and the drain electrode of a P transistor npn npn Mp1 is connected to the drain electrode of a N transistor npn npn Mn1 via a first node N1 (that is input buffer cell 302 first outputs); The grid of the 2nd P transistor npn npn Mp2 and one the 2nd N transistor npn npn Mn2 is connected to first node N1 respectively, and the drain electrode of the 2nd P transistor npn npn Mp2 is connected to the drain electrode of the 2nd N transistor npn npn Mn2 via a Section Point N2 (that is input buffer cell 302 second outputs).Input buffer cell 302 is connected to level processing unit 304 by a first node N1 and Section Point N2 in addition.
As shown in Figure 4, level processing unit 304 includes: one the 3rd P transistor npn npn Mp3, one the 4th P transistor npn npn Mp4, one the 3rd N transistor npn npn Mn3 and one the 4th N transistor npn npn Mn4.Wherein the source electrode of the 3rd P transistor npn npn Mp3 and the 4th P transistor npn npn Mp4 is connected to the second voltage source V PP respectively; The source electrode of the 3rd N transistor npn npn Mn3 and the 4th N transistor npn npn Mn4 is connected to ground voltage supplies VDD respectively; The grid of the 3rd N transistor npn npn Mn3 is connected to first node N1, and drain electrode is connected to the drain electrode of the 3rd P transistor npn npn Mp3 and the grid of the 4th P transistor npn npn Mp4 via one the 3rd node N3; The grid of the 4th N transistor npn npn Mn4 is connected to Section Point N2, and drain electrode is connected to the drain electrode of the 4th P transistor npn npn Mp4 and the grid of the 3rd P transistor npn npn Mp3 via one the 4th node N4 (that is output of level processing unit 304).In addition, Mn4 grid of the 4th N transistor npn npn is connected to pressure drop unit 308 in addition; And level processing unit 304 is connected to output buffer cell 306 via the 4th node N4.
As shown in Figure 4, output buffer cell 306 includes one the 5th P transistor npn npn Mp5 and one the 5th N transistor npn npn Mn5.Wherein the grid of the 5th P transistor npn npn Mp5 and the 5th N transistor npn npn Mn5 is connected to the 4th node N4 respectively; The source electrode of the 5th P transistor npn npn Mp5 is connected to the second voltage source V PP; The source electrode of the 5th N transistor npn npn Mn5 is connected to ground voltage supplies GND; The drain electrode of the 5th P transistor npn npn Mp5 is connected to the drain electrode of the 5th N transistor npn npn Mn5 via output.And voltage level converting 20 of the present invention is exported an output signal Vout by output.
As shown in Figure 3, Figure 4, pressure drop element 3085 of the present invention can be a plurality of diode D1～DN serial connection, and switch element 3087 can be a switching transistor Mps (being assumed to be a P transistor npn npn).Wherein the grid of switching transistor Mps is connected to the first voltage source V DD, and source electrode is connected to the diode D1～DN of serial connection, and drain electrode is connected to the grid of the 4th N transistor npn npn Mn4.
The operation principle of voltage level converting 20 of the present invention is described below.When the first voltage source V DD and second voltage source are opened simultaneously, suppose input signal Vin be high level (for example: VDD), then Mn1 can conducting, not conducting of Mp1, first node N1 be low level (for example: GND).Mp2 conducting this moment, not conducting of Mn2, Section Point N2 be high level (for example: VDD).Because first node N1 is a low level, and Section Point N2 is high level, so not conducting of Mn3, the Mn4 conducting, the 4th node N4 be low level (for example: GND), the Mp3 conducting, the 3rd node N3 be high level (for example: VPP), not conducting of Mp4.Since the 4th node N4 be low level (for example: GND), so not conducting of Mn5, the Mp5 conducting, output signal Vout be high level (for example: VPP).Suppose input signal Vin by high level change into low level (for example: GND), then not conducting of Mn1, the Mp1 conducting, first node N1 be high level (for example: VDD).Mp2 not conducting this moment, the Mn2 conducting, Section Point N2 be low level (for example: GND).Because first node N1 is a high level, and Section Point N2 is low level, so the Mn3 conducting, not conducting of Mn4, the 3rd node N3 be low level (for example: GND), the Mp4 conducting, the 4th node N4 be high level (for example: VPP), not conducting of Mp3.Since the 4th node N4 be high level (for example: VPP), so the Mn5 conducting, not conducting of Mp5, output signal Vout be low level (for example: GND).
As mentioned above, suppose under normal operating state, that is suppose that the first voltage source V DD and the second voltage source V PP are all when opening, not conducting of switch element Mps, that is pressure drop of the present invention unit 38 does not act on.
Suppose to open but the first voltage source V DD unlatching as yet as the second voltage source V PP, this moment, input buffer cell 302 can't act on.Pressure drop unit 308 among the present invention utilizes the second voltage source V PP that has opened to produce an initial voltage to the level processing unit, but makes voltage level converting 20 operate as normal.As shown in Figure 4, that is, suppose that the second voltage source V DD does not open as yet, this moment, Mps was for opening, and the second voltage source V PP produces voltage range near the initial voltage of VDD and input to the grid of Mn4 via serial connection diode D1～DN, made the Mn4 conducting, the 4th node N4 be low level (for example: GND), make Mp5 conducting, not conducting of Mn5, output signal Vout be high level (for example: VPP).
As mentioned above, even voltage level converting of the present invention 20 uses a pressure drop unit 308 to make that (for example: VDD) open as yet, voltage level converting 20 still can operate as normal because of low level voltage source.In addition, when the low level voltage source (for example: VDD) open after, that is the level of voltage source is when reaching VDD, pressure drop unit 308 is closed, and voltage level converting 20 can be returned to normal operating state, but that is input buffer cell 302 normal operations.
In sum, see through voltage level converting of the present invention can solve voltage level converting commonly used the high-voltage level voltage source (for example: VPP) opened and the low voltage level voltage source (for example: when VDD) not opening as yet, the voltage signal of voltage level converting output is undesired to cause the problem that system can't normal operation and produce.
The above only is preferred embodiment of the present invention; so it is not in order to limit scope of the present invention; any personnel that are familiar with this technology; without departing from the spirit and scope of the present invention; can do further improvement and variation on this basis, so the scope that claims were defined that protection scope of the present invention is worked as with the application is as the criterion.
Being simply described as follows of symbol in the accompanying drawing:
Voltage level converting: 10,20
Input buffer cell: 102,302
Level processing unit: 104,304
Output buffer cell: 106,306
Pressure drop unit: 308
Pressure drop element: 3085
Switch element: 3087
Claims (13)
1. a voltage level converting becomes an output signal in order to change an input signal, it is characterized in that this voltage level converting includes:
One input buffer cell is connected between one first voltage source and a ground voltage supplies, in order to receive this input signal;
One output buffer cell is connected between one second voltage source and this ground voltage supplies, in order to export this output signal;
One level processing unit is connected between this input buffer cell and this output buffer cell, is biased between this second voltage source and this ground voltage supplies, becomes this output signal in order to change this input signal; And
One pressure drop unit, be connected to this level processing unit, receive the bias voltage of this first voltage source and this second voltage source, wherein do not open and this second voltage source when having opened when this first voltage source, this pressure drop unit provides an initial voltage to this level processing unit according to this second voltage source.
2. voltage conversion circuit according to claim 1 is characterized in that, this pressure drop unit comprises:
One pressure drop element is connected to this second voltage source, makes this second voltage source pressure drop form this initial voltage; And
One switch element is connected to this pressure drop element, and wherein when this first voltage source was not opened, this switch element conducting made this initial voltage provide to this level processing unit.
3. voltage level converting according to claim 2 is characterized in that, this pressure drop element is a plurality of serial connection diodes, and wherein the input of this serial connection diode is connected to this second voltage source, and output is connected to this switch element.
4. voltage level converting according to claim 2, it is characterized in that this switch element is a switching transistor, wherein the grid of this switching transistor is connected to this first voltage source, source electrode is connected to this pressure drop element, and drain electrode is connected to this level processing unit.
5. voltage level converting according to claim 1 is characterized in that, wherein the level of this first voltage source is less than the level of this second voltage source, and the level of this initial voltage is near the level of this first voltage source.
6. voltage level converting according to claim 1, it is characterized in that, the voltage level range of this input signal is between the level of the level of this first voltage source and this ground voltage supplies, and the voltage level range of this output signal is between the level of the level of this second voltage source and this earthed voltage.
7. voltage level converting according to claim 1 is characterized in that, this input buffer cell comprises: one the one P transistor npn npn, one the 2nd P transistor npn npn, one the one N transistor npn npn and one the 2nd N transistor npn npn; Wherein the source electrode of a P transistor npn npn and the 2nd P transistor npn npn is connected to this first voltage source respectively; The source electrode of the one N transistor npn npn and the 2nd N transistor npn npn is connected to this ground voltage supplies respectively; The grid of the one a P transistor npn npn and a N transistor npn npn receives this input signal respectively; The drain electrode of the one P transistor npn npn is connected to the drain electrode of a N transistor npn npn via a first node; The grid of the 2nd P transistor npn npn and the 2nd N transistor npn npn is connected to this first node respectively; The drain electrode of the 2nd P transistor npn npn is connected to the drain electrode of the 2nd N transistor npn npn via a Section Point.
8. voltage level converting according to claim 1 is characterized in that, this level processing unit comprises: one the 3rd P transistor npn npn, one the 4th P transistor npn npn, one the 3rd N transistor npn npn and one the 4th N transistor npn npn; Wherein the source electrode of the 3rd P transistor npn npn and the 4th P transistor npn npn is connected to this second voltage source respectively; The source electrode of the 3rd N transistor npn npn and the 4th N transistor npn npn is connected to this ground voltage supplies respectively; The grid of the 3rd N transistor npn npn is connected to a first input end of this input buffer cell; The grid of the 4th N transistor npn npn is connected to one second input and this pressure drop unit of this input buffer cell; The drain electrode of the 3rd N transistor npn npn is connected to the drain electrode of the 3rd P transistor npn npn and the grid of the 4th P transistor npn npn; The drain electrode of the 4th N transistor npn npn is connected to the drain electrode of the 4th P transistor npn npn and the grid of the 3rd P transistor npn npn.
9. voltage level converting according to claim 1 is characterized in that, this output buffer cell comprises: one the 5th P transistor npn npn and one the 5th N transistor npn npn; Wherein the source electrode of the 5th P transistor npn npn is connected to this second voltage source; The source electrode of the 5th N transistor npn npn is connected to this ground voltage supplies; The grid of the grid of the 5th P transistor npn npn and the 5th N transistor npn npn is connected to the output of this level processing unit respectively; The drain electrode of the 5th P transistor npn npn and the 5th N transistor npn npn is connected to each other and exports this output signal.
10. the method that initial voltage provides in order to the initial voltage of a voltage level converting to be provided, is characterized in that, this voltage level converting operates between one first voltage source and one second voltage source, and this method comprises:
Open as yet and this second voltage source when not opened when this first voltage source, make the second voltage source step-down become this initial voltage.
11. the method that initial voltage according to claim 10 provides is characterized in that, the voltage level range of this first voltage source is less than the voltage level of this second voltage source, and the voltage level of this initial voltage is near the voltage level of this first voltage source.
12. the method for a voltage level conversion converts an input signal to an output signal in order to utilize one first voltage source and one second voltage source, it is characterized in that this method includes:
When this first voltage source and this second voltage source are all opened, utilize this first voltage source and this second voltage source to make this input signal convert this output signal to; And
Open as yet and this second voltage source when not opened when this first voltage source, provide an initial voltage to make this input signal convert this output signal to.
13. the method for voltage level conversion according to claim 12 is characterized in that, more comprises to make this second voltage source step-down become this initial voltage.
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| Application Number | Priority Date | Filing Date | Title |
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| CN2007100911090A CN101047381B (en) | 2007-04-02 | 2007-04-02 | Voltage level conversion circuit, method and method for providing initial voltage |
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| CN2007100911090A CN101047381B (en) | 2007-04-02 | 2007-04-02 | Voltage level conversion circuit, method and method for providing initial voltage |
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Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7804327B2 (en) | 2007-10-12 | 2010-09-28 | Mediatek Inc. | Level shifters |
| CN105099437A (en) * | 2014-05-16 | 2015-11-25 | 华邦电子股份有限公司 | Logic circuit |
| CN105262474A (en) * | 2014-07-08 | 2016-01-20 | 力旺电子股份有限公司 | Level shift driver circuit |
| CN113285707A (en) * | 2020-02-19 | 2021-08-20 | 圣邦微电子（北京）股份有限公司 | Voltage level conversion circuit |
-
2007
- 2007-04-02 CN CN2007100911090A patent/CN101047381B/en active Active
Cited By (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7804327B2 (en) | 2007-10-12 | 2010-09-28 | Mediatek Inc. | Level shifters |
| CN102394628A (en) * | 2007-10-12 | 2012-03-28 | 联发科技股份有限公司 | Level shifters and the related input/output buffers |
| CN102394628B (en) * | 2007-10-12 | 2014-08-13 | 联发科技股份有限公司 | Level shifters and the related input/output buffers |
| CN105099437A (en) * | 2014-05-16 | 2015-11-25 | 华邦电子股份有限公司 | Logic circuit |
| CN105099437B (en) * | 2014-05-16 | 2018-07-24 | 华邦电子股份有限公司 | Logic circuit |
| CN105262474A (en) * | 2014-07-08 | 2016-01-20 | 力旺电子股份有限公司 | Level shift driver circuit |
| CN105262474B (en) * | 2014-07-08 | 2018-05-25 | 力旺电子股份有限公司 | Level shift driving circuit |
| CN113285707A (en) * | 2020-02-19 | 2021-08-20 | 圣邦微电子（北京）股份有限公司 | Voltage level conversion circuit |
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| CN101047381B (en) | 2010-04-14 |
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