CN1801265A - Integrated drive circuit for filed emission display capable of displaying color video frequency image - Google Patents
Integrated drive circuit for filed emission display capable of displaying color video frequency image Download PDFInfo
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- CN1801265A CN1801265A CN 200410103216 CN200410103216A CN1801265A CN 1801265 A CN1801265 A CN 1801265A CN 200410103216 CN200410103216 CN 200410103216 CN 200410103216 A CN200410103216 A CN 200410103216A CN 1801265 A CN1801265 A CN 1801265A
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Abstract
The invention relates to a field emission display driving circuit for displaying colorful video image which comprises: a video receiving unit, a video A/D converting unit, a data buffer unit and a power module, an integrated gray grade modulation driving unit, a line rear integrated driving unit, a FPGA control module. The invention has the advantages of being able to display real-time colorful video image on FED display screen and of having high reliability.
Description
Technical field
Patent of the present invention belongs to the display fabrication techniques field, the video driver circuit that particularly a kind of field emission display device is used.
Background technology
Field-emitter display (FED) is comparatively novel a kind of in the flat-panel monitor, is the flat-panel monitor of new generation that the another kind after LCD (LCD), plasma scope (PDP), electroluminescent display (ELD) etc. has future most.The large tracts of land printing-type FED that our company researched and developed adopts low work function FED cathode material of exclusive low-cost large-area and cathode slurry thereof, has independent intellectual property right.Different with the FED of other kind, large tracts of land printing-type FED cost is low, and technology is simple, and institute's materials used has low work function characteristics, can reduce emission voltage required among the FED, makes external circuit oversimplify.We have developed 25 inches large color screen printing-type field-emitter displays at present, belong to initiative at home and abroad.The application number of being applied for by our company in February, 2003 is 03115390.9 patent of invention " field-emitter display (FED) video driver circuit ", this patent has been introduced a kind of drive circuit system of realizing that the field-emitter display video image shows, this patent adopts discrete component to realize the amplification of the pulse width modulating signal of gray scale modulator output, reached the purpose that drives the demonstration of FED display video image, and be applied among the FED of 20 inches monochromes 320 * 240.But the image driver circuitry in the above-mentioned FED drive circuit system is the gray modulation signal generator separates separately with pulse amplifier, and pulse amplifier is to adopt discrete driving circuit structure mode, the discrete device that uses is many, exist circuit structure complexity, loaded down with trivial details, the circuit volume is big, power attenuation reaches the not high shortcoming of stability greatly, and above-mentioned FED driving circuit can only be realized monochromatic video image.
Summary of the invention
In order to overcome above-mentioned deficiency, the video integrated drive electronics that the purpose of this invention is to provide a kind of improved field-emitter display (FED), but particularly a kind of integrated drive circuit for filed emission display of display color video image, it will simplify available circuit greatly, dwindle its volume, can also on the FED display screen, realize the demonstration of real-time color video image simultaneously.
The objective of the invention is to realize by following technical proposals.
The present invention comprises video reception unit, video a/d converting unit, data buffer storage unit, and power module part, it is characterized in that it also comprises integrated gray modulation driver element, the integrated driver element of row back level, FPGA control module unit, circuit carries out the image video signal of pal mode to send into data buffer storage unit after A/D gathers conversion, realizes the zone intercepting of image simultaneously; The row back integrated driver element of level is pressed row-by-row system scanning then, correspondingly view data is sent to integrated gray modulation driver element and finishes the reduction of gradation of image and produce corresponding FED screen row driving pulse, finish the driving of FED display screen ranks, demonstrate video image; FPGA is by the control of programming realization to data buffer unit, integrated gray modulation driver element, the integrated driver element of row back level; Power module provides required voltage for the each part mentioned above circuit.
Described integrated gray modulation driver element comprises gradation of image modulating driver (its chip model is HV632), and level integrated driver element in row back comprises horizontal pulse driver (its chip model is STV7697).
Described gradation of image modulating driver is finished by the HV632PG chip cascade, and the gradation of image modulation of each primary colours is according to some HV632PG chip cascades of the corresponding employing of image resolution ratio.
The cascade of described HV632PG chip is to be connected with reception data enable input end CSI with its contiguous following chip piece by the reception data enable output terminal CSO of preceding chip piece; It all is that each chip is shared that other Data Input Interface, shifted data clock SC, counting clock CC, counting enable input end LC.
Described horizontal pulse driver can adopt the STV7697 chip cascade to constitute, according to some STV7697 chip cascades of the corresponding employing of image resolution ratio.
The cascade of described STV7697 chip is that other data shift clock CLK, barnyard output terminal BLK, polarity selecting side POL, latch data output terminal/STB are that all row chips are shared by the serial data output terminal SOUT of preceding chip piece with the serial data input end SIN cascade of its contiguous following chip piece.
Described FPGA control circuit is a complete machine timing sequence generating control circuit, and it is controlled data buffer unit, integrated gray modulation driver element, the integrated driver element of row back level respectively by producing required unit controls signal.
Described FPGA control circuit is to realize by producing the row, column intercept signal to the control of data buffer unit; Under the control of address signal, FPGA presses the programming in logic capable intercept signal of 512 clock period of output, and preceding 512 data that intercept each line of input data deposit buffer memory in, realizes row intercepting function; Under the control of the reference signal of being expert at and parity field distinguishing signal, the FPGA circuit produces the field intercept signal of 256 interlacing reference pulses, intercepts 256 line data of incoming frame data and in the buffer memory of depositing, and realizes row intercepting function.
Described FPGA control circuit is to realize by gray modulation Load Count (LC) signal, the reception data enable input end CSI signal that produce HV632 to the control of integrated gray modulation driver element.
Described FPGA control circuit is to realize by serial input SIN, the barnyard output terminal BLK, polarity selecting side POL, the latch data output terminal/STB signal that produce STV7697 to the control of the integrated driver element of row back level.
The present invention is the acquisition process video image in real time, and offers the FED display screen exactly, realizes the difficult problem that the real-time color video image shows thereby solved on the FED display screen; The integrated complicacy that also reduces circuit structure widely, it is original 1/3 that whole driving circuit volume is reduced to, and weight is reduced to 1/5.Except above advantage, the present invention also has the following advantages: 1. adopt integrated gray scale modulator HV632 to realize gray modulation and drive output, exportablely be up to 80 volts, 4mA
P-PPulse signal, and horizontal drive circuit sweep signal amplitude can reach the high-voltage signal of volt more than 170, peak drive current can reach 200mA
P-P, the mode of the integrated driving of this employing, convenient and easy, the reliability height makes circuit that very wide redundant space be arranged, even when the display screen parameter changes greatly, still can satisfy the pulsed drive requirement of FED display screen; 2. simultaneously because driving circuit integrated improves circuit working efficient, the output power of circuit power module, dissipated power are all dwindled greatly, the power module volume is reduced to original 1/3; 3. in addition, use FPGA and realize the accurate mapping of buffer memory physical address and display addressing, control signal that image-region intercepts and the timing control signal of integrated gray modulation chip for driving HV632 etc., control flexiblely, extensibility is strong; 4. and with former printing-type FED compare, the FED panel that the present invention can drive is long-pending bigger, reaches 25 inches, and resolution is also higher; 5. the present invention can also realize and compunication, with the display of FED as computing machine, and can intercept one vision signal in real time and is sent to computing machine, and this also helps the debugging to circuit.
Description of drawings
Fig. 1 is a whole block scheme of the present invention.
Fig. 2 is the circuit theory diagrams of Fig. 1.
Fig. 3 is the main signal timing diagram of data buffer storage unit.
Fig. 4 is integrated gray scale modulator HV632PG chip cascade circuit diagram.
Fig. 5 is the application system sequential chart of integrated gray modulation driver element.
Fig. 6 is a row integrated drive STV7697 chip cascade circuit diagram.
Fig. 7 is the application system sequential chart of the integrated driver element of row back level.
Fig. 8 is the overview flow chart of the control signal of FPGA generation.
Embodiment
Extremely shown in Figure 7 as Fig. 1, the present invention is by video reception unit, the video a/d converting unit, data buffer storage unit, integrated gray modulation driver element, the integrated driver element of row back level, FPGA control module unit and power module etc. are partly formed, after being received by video reception unit, vision signal send the video a/d converting unit to carry out the A/D conversion, after then sending data buffer storage unit storage and intercepting, taking-up send integrated gray modulation driver element to finish gray modulation and amplification, being sent to the FED screen then shows, capable signal after the integrated driver element of row back level will amplify is simultaneously sent to driving FED and is shielded, and FPGA is to wherein data buffer storage unit, integrated gray modulation driver element, level integrated driver element in row back is controlled.The principle of work of its circuit is that the analog video image signals of the pal mode that provides with the pal mode television receiver or by video reception unit such as VCD, DVD is sent into the A/D that carries out video among the video input processor SAA7111A and gathered and be transformed to 24 colorful digital picture intelligences, deposits the zone intercepting that Data Buffer Memory is realized image simultaneously then under the control of metadata cache write address generator in.The mode that employing is lined by line scan is sent the view data of every some 8bits in the three primary colours buffer memory in strange, the even field into the integrated gray modulation chip for driving of image HV632 respectively and is carried out the reduction of gradation of image, the width of its output pulse is directly proportional with the size of view data numerical value, and the pattern pulse of output is directly used in and drives the FED display screen.Wherein the reception of video reception unit realization TV signal or VCD, DVD signal belong to conventional module, do not repeat them here.The vision signal that the video a/d conversion portion is sent video reception unit here is converted to three primary colours 24 R, G, each digital video signal of 8 of B, and therefrom isolates parity field distinguishing signal, the pulse of 13.5MHz sampling clock, field system chronizing impulse, row reference signal, systematic reset signal etc.Concrete operations to it are to I by single-chip microcomputer
2C bus corresponding registers is carried out write operation from the address, realize 256 grades of adjustment of brightness, contrast, colourity.Power module provides the each several part circuit required DC voltage.According to FED display screen display requirement, provide the DC voltage of 80V, 150V, 1200V and 5V respectively.
We are example with the FED display screen of 25 inches colours 480 * 3 * 240, and specific implementation process of the present invention is described, wherein the function of FPGA control module unit is implemented in to incorporate in the description of each unit and illustrates:
1, data buffer storage unit, its function are the digital video image data that the store video receiving element is sent here, and carry out the zone intercepting of image.This partial circuit is mainly by metadata cache read/write address generator (74HC161), Data Buffer Memory formations such as (A617308S).In storing process, because the needs of FED screen, we also need to intercept local signal, and both the needs according to display format 480 * 3 * 240 intercepted out 512 * 3 * 256 signal, and its intercepting control signal is produced by the FPGA programming.At first metadata cache read/write address generator produces from 0000H to 2 under the control of corresponding read-write time clock, and the address of 0000H is convenient to choose each storage unit of Data Buffer Memory to carry out read-write operation.Under the sequential control of address signal, FPGA presses the programming in logic capable intercept signal of 512 clock period of output then, and preceding 512 data that intercept each line of input data deposit buffer memory in, realizes row intercepting function thus.Under the control of the reference signal of being expert at and parity field distinguishing signal, the FPGA circuit produces the field intercept signal of 256 interlacing reference pulses, intercepts 256 line data of incoming frame data and in the buffer memory of depositing, and realizes row intercepting function thus.Can be clear that the relation of above-mentioned ranks intercepting from the sequential synoptic diagram of Fig. 3.And vision signal is that odd field R, G, each view data of 8 of B are write strange buffer memory during for odd field, and the data of taking out even field output to the back level; Otherwise then, be to write an idol buffer memory during for even field, take out odd field data and output to the back level.The switching of read-write triggers by A/D part isolated parity field distinguishing signal from vision signal.This FPGA intercepting control circuit can be adjusted the carry-out bit ranks position of output data and taking out row, take out the format conversion function of capable compress mode whole secondary output image arbitrarily.The post-stage drive circuit that video data is then sent into is the input of integrated gray modulation driver HV632.
2, integrated gray modulation driver element, its function be will input 8 bit data directly be modulated into the grey scale signal that pulsewidth is represented, i.e. pulse width modulation (PWM mode), and carry out power amplification.The high-voltage pulse signal of its output is to deliver to the corresponding R of FED display screen, G, the demonstration of B three primary colours pixel lead-in wire electrode drive.The core devices of gray modulation circuit is integrated gray scale modulator, can select the HV632PG of U.S. Supertexic company or HV633, HV621 chip for use.Every of HV632PG has 32 tunnel outputs, vedio data to every frame 480 * 3 * 240, the modulation of the gradation of image of each primary colours adopts 15 integrated gray scale modulator HV632PG chip cascades to finish, circuit diagram as shown in Figure 4, core number also can change according to different column split rates.The reception data enable input end CSI of first chip block is controlled by extraneous control signal, and the every chip block CSI in back end all is connected with the CSO end of preceding chip piece, the following chip piece work that is close to its by the reception data enable end CSO notice of preceding chip piece; It all is that each chip is shared that other Data Input Interface, shifted data clock SC, counting clock CC, counting enable input end LC, and control signal CSI, LC are produced by the FPGA programming.The Enable Pin ground connection that allows gray scale modulator earlier makes chip always be in and enables duty.Send digital video signal here Deng front end, begin to receive data by receiving data enable input end CSI notice gray scale modulator, deposit the first order latch of gray scale modulator inside in, as shown in Figure 5,480 data need 480 shift clock in the present embodiment, and data begin transmission under CSI starts; Wait then imported data line after, under the effect of gray modulation Load Count (LC) input signal, modulator will be sent in the latch of the second level simultaneously in the data in the first order latch, start the internal comparator unit simultaneously, under the effect of Count Clock (CC) signal, carry out exporting after the gray modulation.At this moment, first order latch begins to latch the digital image signal of next line again under Shift Clock (SC) effect.In this course, the input of data, modulation and output are separate, do not disturb mutually.Delegation connects data line and is latched, squeezes into comparer width modulation, pulse amplification output in proper order like this, goes round and begins again, and the data in buffer memory are output in one and finish.Integrated gray modulation driver element can satisfy following parameters: data rate is 12MByte/s, and the modulation counting clock is 6MHz, outputting drive voltage 12V
P-P-80V
P-P, electric current is not less than 4mA
P-PThereby, make display video image stable, brightness of display screen height, the screen of compatible different parameters more broadly; In addition, integrated gray modulation driver element has the function to the capacity load compensation, makes circuit follow display screen can obtain good coupling.
3, the integrated driver element of row back level, its function are to be used for the line scanning pulse signal is deciphered and finished the circuit of power gain, and this circuit module is finished the parameter matching that realizes driving circuit and FED display screen when voltage, current amplitude amplify.The high-voltage pulse signal of lining by line scan of its output is to deliver to the corresponding line lead electrode drive of FED display screen to show.Use row integrated drive STV7697 or HV57908, STV7699 chip to constitute the row post-stage drive circuit among the present invention.Every of STV7697 integrated chip has 64 tunnel outputs, and the present invention can adopt 4 STV7697 chip cascades to constitute.Row integrated drive electronics figure as shown in Figure 6.The serial data input end SIN cascade of last chip serial data output terminal SOUT and back chip piece, data serial transfer in each chip; Other data shift clock CLK, barnyard output terminal BLK, polarity selecting side POL, latch data output terminal/STB are that all row chips are shared, control signal SIN ,/STB, POL, BLK produce by FPGA.As shown in Figure 7, its principle of work is: a line period high level active data is imported from the SIN end of first STV7697 earlier, remaining chip is by the SOUT of last chip and the SIN end cascade transmission signal of back one chip then, like this 240 line scanning pulse CLK signals promptly the effective scan-data level of the next line period of effect of a field time be displaced to the 240th output terminal successively from first output terminal, each signal is through the scanning impulse of internal power amplifier gain output corresponding line.Level integrated driver element in row back satisfies following parameters: voltage 60V
P-P-150V
P-P, electric current is not less than 200mA
P-PThereby, make this unit to provide bigger power parameter, more broadly the screen of compatible different parameters for screen; Level integrated driver element in row back also has the function to the capacity load compensation, makes circuit follow display screen can obtain good coupling.
Claims (10)
1. but the integrated drive circuit for filed emission display of a display color video image, it comprises video reception unit, video a/d converting unit, data buffer storage unit, and power module part, it is characterized in that it also comprises integrated gray modulation driver element, the integrated driver element of row back level, FPGA control module unit, circuit carries out the image video signal of pal mode to send into data buffer storage unit after A/D gathers conversion, realizes the zone intercepting of image simultaneously; The row back integrated driver element of level is pressed row-by-row system scanning then, correspondingly view data is sent to integrated gray modulation driver element and finishes the reduction of gradation of image and produce corresponding FED screen row driving pulse, finish the driving of FED display screen ranks, demonstrate video image; FPGA is by the control of programming realization to data buffer unit, integrated gray modulation driver element, the integrated driver element of row back level; Power module provides required voltage for the each part mentioned above circuit.
2. but the integrated drive circuit for filed emission display of a kind of display color video image according to claim 1, it is characterized in that described integrated gray modulation driver element comprises gradation of image modulating driver (its chip model is HV632), level integrated driver element in row back comprises horizontal pulse driver (its chip model is STV7697).
3. but the integrated drive circuit for filed emission display of a kind of display color video image according to claim 1 and 2, it is characterized in that described gradation of image modulating driver finished by the HV632PG chip cascade, the gradation of image modulation of each primary colours is according to some HV632PG chip cascades of the corresponding employing of image resolution ratio.
4. but the integrated drive circuit for filed emission display of a kind of display color video image according to claim 3, the cascade that it is characterized in that described HV632PG chip are to be connected with reception data enable input end CSI with its contiguous following chip piece by the reception data enable output terminal CSO of preceding chip piece; It all is that each chip is shared that other Data Input Interface, shifted data clock SC, counting clock CC, counting enable input end LC.
5. but the integrated drive circuit for filed emission display of a kind of display color video image according to claim 1 and 2, it is characterized in that described horizontal pulse driver can adopt the STV7697 chip cascade to constitute, according to some STV7697 chip cascades of the corresponding employing of image resolution ratio.
6. but the integrated drive circuit for filed emission display of a kind of display color video image according to claim 5, the cascade that it is characterized in that described STV7697 chip is that other data shift clock CLK, barnyard output terminal BLK, polarity selecting side POL, latch data output terminal/STB are that all row chips are shared by the serial data output terminal SOUT of preceding chip piece with the serial data input end SIN cascade of its contiguous following chip piece.
7. but the integrated drive circuit for filed emission display of a kind of display color video image according to claim 1, it is characterized in that described FPGA control circuit is a complete machine timing sequence generating control circuit, it is controlled data buffer unit, integrated gray modulation driver element, the integrated driver element of row back level respectively by producing required unit controls signal.
8. but the integrated drive circuit for filed emission display of a kind of display color video image according to claim 7 is characterized in that the control of described FPGA control circuit to the data buffer unit, is to realize by producing the row, column intercept signal; Under the control of address signal, FPGA presses the programming in logic capable intercept signal of 512 clock period of output, and preceding 512 data that intercept each line of input data deposit buffer memory in, realizes row intercepting function; Under the control of the reference signal of being expert at and parity field distinguishing signal, the FPGA circuit produces the field intercept signal of 256 interlacing reference pulses, intercepts 256 line data of incoming frame data and in the buffer memory of depositing, and realizes row intercepting function.
9. but the integrated drive circuit for filed emission display of a kind of display color video image according to claim 7, it is characterized in that the control of described FPGA control circuit to integrated gray modulation driver element, is to realize by gray modulation Load Count (LC) signal, the reception data enable input end CSI signal that produce HV632.
10. but the integrated drive circuit for filed emission display of a kind of display color video image according to claim 7, it is characterized in that the control of described FPGA control circuit to the integrated driver element of row back level, is to realize by serial input SIN, the barnyard output terminal BLK, polarity selecting side POL, the latch data output terminal/STB signal that produce STV7697.
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| CN 200410103216 CN1801265A (en) | 2004-12-31 | 2004-12-31 | Integrated drive circuit for filed emission display capable of displaying color video frequency image |
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2011076071A1 (en) * | 2009-12-23 | 2011-06-30 | 北京联想软件有限公司 | Computer, monitor and computer display method |
| CN105719588A (en) * | 2014-12-22 | 2016-06-29 | 三星显示有限公司 | Scanline driver chip and display device including the same |
| WO2023093138A1 (en) * | 2021-11-26 | 2023-06-01 | 海信视像科技股份有限公司 | Backlight module and display device |
-
2004
- 2004-12-31 CN CN 200410103216 patent/CN1801265A/en active Pending
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2011076071A1 (en) * | 2009-12-23 | 2011-06-30 | 北京联想软件有限公司 | Computer, monitor and computer display method |
| US8907960B2 (en) | 2009-12-23 | 2014-12-09 | Beijing Lenovo Software Ltd. | Computer, monitor and computer display method |
| CN102109899B (en) * | 2009-12-23 | 2015-06-24 | 联想(北京)有限公司 | Computer, displayer, and display method of computer |
| CN105719588A (en) * | 2014-12-22 | 2016-06-29 | 三星显示有限公司 | Scanline driver chip and display device including the same |
| WO2023093138A1 (en) * | 2021-11-26 | 2023-06-01 | 海信视像科技股份有限公司 | Backlight module and display device |
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