CN100390840C - Display apparatus and method for controlling the same - Google Patents
Display apparatus and method for controlling the same Download PDFInfo
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- CN100390840C CN100390840C CNB2005100818285A CN200510081828A CN100390840C CN 100390840 C CN100390840 C CN 100390840C CN B2005100818285 A CNB2005100818285 A CN B2005100818285A CN 200510081828 A CN200510081828 A CN 200510081828A CN 100390840 C CN100390840 C CN 100390840C
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Abstract
A display apparatus includes a control circuit for outputting a timing signal for determining a predetermined time period and a clock signal counted to determine the length of a modulation signal. The display apparatus is capable of switching between a first state in which a first timing signal and a first clock signal are output, and a second state in which a second timing signal and a second clock signal are output. The first time period is shorter than the second time period, wherein the first time period is the predetermined time period determined by the first timing signal and the second time period is the predetermined time period determined by the second timing signal. The frequency of the first clock signal is higher than the frequency of the second clock signal.
Description
Technical field
The method that the present invention relates to a kind of display device and control this display device.
Background technology
Jap.P. discloses and discloses a kind of structure that can will switch to the control signal of gate drivers and source electrode driver according to the type of the picture signal that is input to Thin Film Transistor-LCD (TFT-LCD) in 2000-338925 number.The picture signal of mentioning in this document meets NTSC system (NTSC), Phase Alternate Line (PAL) or high-definition television (HDTV) standard, the wherein frame frequency of picture signal (Fig. 7) inequality.
Summary of the invention
According to display device of the present invention display image admirably.
Display device according to one aspect of the present invention comprises: display board, and it contains a plurality of matrix of display elements that are connected with many modulation distributions by plurality of scanning wirings; Sweep circuit is used to scan described plurality of scanning wirings, in the given time sweep signal is applied to plurality of scanning wirings simultaneously; Modulation circuit, the modulation signal that is used for will having the modulating time width synchronously with predetermined amount of time is applied to many modulation distributions; And control circuit, being used to export timing signal and clock signal, timing signal is used for determining predetermined amount of time, clock signal will be counted to determine the length of modulation signal.Control circuit can switch between first state and second state, wherein first state is that control circuit is exported first timing signal as timing signal and export the state of first clock signal as clock signal, and second state is a control circuit output second timing signal as timing signal and the output second clock signal state as clock signal.And very first time section is shorter than second time period, and wherein very first time section is the predetermined amount of time of being determined by first timing signal, and second time period was the predetermined amount of time of being determined by second timing signal.In addition, the frequency of first clock signal is higher than the frequency of second clock signal.
Can adopt the structure that is used to carry out width modulation, have the modulation signal of modulating time width with generation.This structure is not restricted to the structure that is used to carry out single width modulation.For example, the present invention can adopt disclosed structure in the U.S. Patent application 20020195966, and the waveform of modulation signal has different wave height values in this structure, and modulated corresponding to the time width of at least one wave height value.
For first clock signal, can use clock signal with fixed frequency, for the second clock signal, can use clock signal with fixed frequency different with first clock signal.But clock signal is not limited to such clock signal with fixed frequency, can use first and second clock signals that have according to the variable frequency of predetermined condition.In the case, the frequency of clock signal of the present invention is the mean value of variable frequency.
Be used for determining the modulation signal controlling value of non-application period according to the output of the control circuit of one aspect of the present invention, non-application period of modulation signal from predetermined amount of time initial extends to the moment that modulation signal is employed.At this, control circuit is exported first controlling value as the controlling value in first state, and control circuit is exported second controlling value as the controlling value in second state.The first and second non-application periods and first and second predetermined amount of time have following relation:
First non-application period/non-application period/the second time period of very first time section＞second
Wherein the first non-application period was the modulation signal non-application period of being determined by first controlling value, and the second non-application period was the modulation signal non-application period of being determined by second controlling value.
Integrated circuit can be used as this control circuit.Needn't be from same integrated circuit output timing signal, clock signal and controlling value.Can be from discrete circuit output timing signal, clock signal and controlling value.In the case, circuit bank will constitute control circuit of the present invention.
Determined for the first non-application period by counting first clock signal until quantity, determined for the second non-application period until the quantity of corresponding second controlling value by counting second clock signal corresponding to first controlling value.
For counting clock signal until quantity corresponding to controlling value, can adopt to be used for the relatively structure of this count value and controlling value.And, can at first set controlling value, and synchronously count down with clock signal.
Control circuit is exported first timing signal and first clock signal when the picture signal with first frame per second is imported into display device, output second timing signal and second clock signal when the picture signal with second frame per second that is lower than first frame per second is imported into display device.
Another aspect of the present invention provides a kind of method that is used to drive display device, and display device comprises the display board with a plurality of matrix of display elements that are connected with many modulation distributions by plurality of scanning wirings.This method may further comprise the steps: scan described plurality of scanning wirings, in the given time sweep signal is applied to each bar in the plurality of scanning wirings simultaneously; The modulation signal that synchronously will have the modulating time width with predetermined amount of time is applied to many modulation distributions; And between first state and second state, switch.Herein, first state is that control circuit is exported first timing signal is used for first controlling value of definite modulation signal non-application period as clock signal and output as timing signal, output first clock signal state, wherein timing signal is used for determining predetermined amount of time, clock signal is counted determining the length of modulation signal, and non-application period of modulation signal from predetermined amount of time initial extends to the moment that modulation signal is employed.Second state is that control circuit output second timing signal is used for determining the non-state of using second controlling value of period of modulation signal as timing signal, output second clock signal as clock signal and output, wherein timing signal is used for determining predetermined amount of time, clock signal is counted determining the length of modulation signal, and non-application period of modulation signal from predetermined amount of time initial extends to the moment that modulation signal is employed.Very first time section is shorter than second time period, and wherein very first time section is the predetermined amount of time of being determined by first timing signal, and second time period was the predetermined amount of time of being determined by second timing signal.By counting first clock signal, determine modulation signal non-application period in second state until the quantity of corresponding second controlling value by counting second clock signal until the modulation signal non-application period of determining corresponding to the quantity of first controlling value in first state.When second state switches to first state, controlling value is switched to first controlling value from second controlling value, stops applying step simultaneously.
Comprise according to the present invention's display device on the other hand: display board, it contains a plurality of matrix of display elements that are connected with many modulation distributions by plurality of scanning wirings; Sweep circuit is used to scan described plurality of scanning wirings, in the given time sweep signal is applied to plurality of scanning wirings simultaneously; Modulation circuit, the modulation signal that is used for synchronously will having a modulating time width with predetermined amount of time is applied to many modulation distributions; And control circuit, be used to export timing signal and clock signal, timing signal is used for determining predetermined amount of time, clock signal will be counted to determine the length of modulation signal, and control circuit is used to export and is used for determining the modulation signal controlling value of non-application period, and non-application period of modulation signal from predetermined amount of time initial extends to the moment that modulation signal is employed.Control circuit can have the state that picture signal is transfused to and first timing signal, first clock signal and first controlling value are output of first frame per second therein, and wherein has between the state that picture signal is transfused to and second timing signal, second clock signal and second controlling value are output of second frame per second that is lower than first frame per second and switch.Very first time section is shorter than second time period, wherein very first time section is the predetermined amount of time of being determined by first timing signal, second time period was the predetermined amount of time of being determined by second timing signal, and the average frequency of first clock signal is higher than the average frequency of second clock signal.Second controlling value is that wherein the first and second non-application periods and first and second predetermined amount of time have the value of following relation:
First non-application period/non-application period/the second time period of very first time section＞second.
Herein, the first non-application period was the modulation signal non-application period of being determined by first controlling value, and the second non-application period was the modulation signal non-application period of being determined by second controlling value.
Provide a kind of method that is used to control display device according to another aspect of the present invention, display device comprises the display board with a plurality of matrix of display elements that are connected with many modulation distributions by plurality of scanning wirings.This method may further comprise the steps: scan described plurality of scanning wirings, in the given time sweep signal is applied to plurality of scanning wirings simultaneously; The modulation signal that synchronously will have the modulating time width with predetermined amount of time is applied to many modulation distributions; And export timing signal, clock signal and be used for determining the modulation signal controlling value of non-application period, wherein timing signal is used for determining predetermined amount of time, clock signal is counted determining the length of modulation signal, and non-application period of modulation signal from predetermined amount of time initial extends to the moment that modulation signal is employed.In the output step, have the state that picture signal is transfused to and first timing signal, first clock signal and first controlling value are output of first frame per second therein, and wherein have between the state that picture signal is transfused to and second timing signal, second clock signal and second controlling value are output of second frame per second that is lower than first frame per second and switch.Very first time section is shorter than second time period, wherein very first time section is the predetermined amount of time of being determined by first timing signal, second time period was the predetermined amount of time of being determined by second timing signal, and the average frequency of first clock signal is higher than the average frequency of second clock signal.Second controlling value is that wherein the first and second non-application periods and first and second predetermined amount of time have the value of following relation:
First non-application period/non-application period/the second time period of very first time section＞second.
Herein, the first non-application period was the modulation signal non-application period of being determined by first controlling value, and the second non-application period was the modulation signal non-application period of being determined by second controlling value.
Provide a kind of method that is used to control display device according to another aspect of the present invention, display device comprises the display board with a plurality of matrix of display elements that are connected with many modulation distributions by plurality of scanning wirings.This method may further comprise the steps: scan described plurality of scanning wirings, in the given time sweep signal is applied to each bar in the plurality of scanning wirings simultaneously; The modulation signal that will have the modulating time width with predetermined amount of time is applied to many modulation distributions; And export timing signal, clock signal and be used for determining the modulation signal controlling value of non-application period, wherein timing signal is used for determining predetermined amount of time, clock signal is counted determining the length of modulation signal, and non-application period of modulation signal from predetermined amount of time initial extends to the moment that modulation signal is employed.In the output step, have the state that picture signal is transfused to and first timing signal, first clock signal and first controlling value are output of first frame per second therein, and wherein have between the state that picture signal is transfused to and second timing signal, second clock signal and second controlling value are output of second frame per second that is lower than first frame per second and switch.In this method that is used for controlling display device, when being switched, frame per second carries out following steps: stop frequency, the change controlling value that applies modulation signal, changes clock signal and begin to apply modulation signal once more.
Other features and advantages of the present invention will become clearer in the explanation of exemplary embodiments (with reference to accompanying drawing) below.
Description of drawings
Fig. 1 has shown the display device according to the embodiment of the invention;
Fig. 2 has shown the sweep circuit according to the embodiment of the invention;
Fig. 3 has shown the modulation circuit according to the embodiment of the invention;
Fig. 4 has shown the timing pulse generator circuit according to the embodiment of the invention;
Fig. 5 has shown the timing pulse generator circuit according to the embodiment of the invention;
Fig. 6 has shown the sequence of operation according to embodiment of the invention driving timing pulse-generator circuit;
Fig. 7 has shown prior art;
Fig. 8 has shown the structure according to the television equipment of the embodiment of the invention.
Embodiment
The method that the following describes the details of display device and drive this display device, display device comprise the display board with display device matrix.
With reference to the details of Fig. 1 explanation according to the display device of the embodiment of the invention, display device comprises the surface conductive electron emitter as display device.
Fig. 1 shows display board 1, and it comprises the display device with the arranged of scan wiring and modulation distribution.Display device can be cold cathode device, electroluminescence (EL) device or light emitting diode (LED).These devices expect because they can according to modulation signal be provided for the length of time period of this device and the time modulated and that their responses are luminous very fast.
The picture signal that is input to display board shown in Figure 11 can meet PAL, NTSC or HDTV.But picture signal is not limited to meet the signal of these standards, also can be the picture signal that for example is used for computing machine, and it meets VESA (VESA) standard.
The picture signal that is used for personal computer has many different frame per second.The picture signal of these types also can be used for according to display device of the present invention.
Display device according to first embodiment of the invention is described below with reference to accompanying drawings.The size of parts, material, shape and relative position are not restricted among the embodiment, except as otherwise noted.
First embodiment
In Fig. 1, display board 1 comprises a plurality of electron beam sources with surface conductive electron emitter matrix and can be by receiving from the electron beam of a plurality of electron beam sources and luminous video screen.When the little film surface that is provided on electric current and the surface conductive electron emitter applied abreast, from this film emitting electrons, image was displayed on the display board 1, and this surface conductive electron emitter is electron emission device (cold cathode device).The high-voltage power supply of display board 1 (not showing among the figure) applies HVB high voltage bias to video screen, so that surface conductive electron emitter ejected electron is quickened.
Substrate is installed on the backboard.Be provided with N * M surface conductive electron emitter on substrate, wherein N and M are the positive integers more than or equal to 2.Determine the quantity of surface conductive electron emitter according to the display resolution of expectation.For example, for the display device that is used for the high resolution displayed TV, the gratifying setting value of N and M is at least N=3000 and M=1000.N * M surface conductive electron emitter is arranged in single matrix, and horizontal distribution of M bar (scan wiring) and N bar vertical wires (modulation distribution) have wherein interconnected.Substrate, surface conductive electron emitter and level and vertical wires have constituted a plurality of electron beam sources.
Has the lower surface that fluoroscopic fluorescence membrane is arranged on panel.Fluorescence membrane according to present embodiment is coated with the trichromatic phosphor of the red, green and blue of using in the cathode ray tube (CRT) technical field so that can coloredly show.On fluorescence membrane, apply the phosphor of three kinds of colors with strip form.The black conductor is set between the striped of phosphor.Even being set, the black conductor when position divergent bundle out of position, also can prevent the display color distortion, can avoid showing decrease of contrast by the reflection that prevents extraneous light, and avoid because the fluorescence membrane that electron beam causes is recharged.The black conductor mainly is made of graphite.As long as but can realize above-mentioned functions, the material of any kind can be used as the black conductor.
The side relative with backboard that metal backing in the CRT technical field is arranged on fluorescence membrane will be used in usually.The utilization that metal backing has improved the direct reflection part light of the light that fluorescence membrane is launched is set, prevented that fluorescence membrane is subjected to the bump of negative ion, the electrode that is used to apply beam voltage is provided, and provides conducting path for the electronics that is used for the fluorescence excitation film.By fluorescence membrane is arranged on the display panel substrate, the surface of level and smooth fluorescence membrane and vacuum deposition aluminium and constitute metal backing on fluorescence membrane.When the fluorescent material of low-voltage is used for fluorescence membrane, then do not need metal backing.
Although do not mention among this embodiment, the transparency electrode that indium tin oxide (ITO) constitutes also can be arranged between display panel substrate and the fluorescence membrane, is used to the conductivity that applies accelerating potential and improve fluorescence membrane.
Because disclosing, Jap.P. disclosed the method that is used to prepare display board in 11-185599 number, so will omit its explanation in the present embodiment.
Disclose described in 11-185599 number as Jap.P., can adopt several methods that are used to control the brightness step of the light that display board 1 launched, wherein display board 1 comprises the surface conductive electron emitter.According to the modulation circuit 8 as modulating device of this embodiment, the potential pulse that will have corresponding to the pulsewidth of importing modulating data (D1 to DN in the accompanying drawing) imposes on distribution XD1 to XDN.Sweep circuit 2 will select voltage to be applied to the line that will be lighted, and non-selected voltage is applied to non-selected line.Selection wire by order is carried out scanning.In this way, display board 1 display image.The modulation signal of modulation circuit output is applied to a plurality of surface conductive electricity of being connected with selected scan wiring in emitter.Thus sweep signal and modulation signal are applied to the surface conductive electron emitter that is connected with selected scan wiring.In other words, display board 1 of the present invention adopts line order drive system and variable duration impulse system.
Input block 3 comprises decoding circuit, analog to digital (A/D) translation circuit and synchronizing separator circuit.Input block 3 output component picture signals (component image signal) Y, U and V, horizontal-drive signal HD and vertical synchronizing signal VD.
The picture format detecting unit receives synchronizing signal HD and VD from input block 3, and the format information and the frame per second information FR of output input signal.At this moment, can determine form by the counting synchronizing signal.Be used for determining that the method for form can be the method that Jap.P. discloses 2000-338925 number disclosure.
The timing pulse generator circuit is with reference to frame per second information FR, and the Dot Clock DCLK that produces synchronizing signal HS and VS and use as benchmark when driving display board 1 according to frame per second.
Image signal processing unit 4 is transformed to the rgb signal corresponding one by one with the pixel of display board 1 according to synchronizing signal HS and VS and Dot Clock DCLK from the timing pulse generator circuit with received image signal Y, U and V, keeps frame per second constant simultaneously.Image signal processing unit 4 is carried out conversion of resolution and color matrix conversions, and output needle is to trichromatic three set of image data R, G and B then.
Oppositely three set of image data R, G and the B of 7 pairs of generations of γ processing unit carry out reverse gamma-corrected conversion.Therefore, image data set R, G and B are transformed into and the proportional data set Ra of the brightness requirement data value of each pixel, Ga and Ba.
Data set Ra, Ga and Ba are rearranged serial image data Dout at R, G and B at data array converter unit 9.Then, for sweep time of certain line in the section with the image data transmission of a horizontal distribution to shift register 5, make that the selected scan-synchronized ground with horizontal distribution to be shown shows this horizontal distribution.
Shift register 5 is as the storer that arrives each vertical wires of display board 1 connected in series.Shift register 5 is from timing pulse generator circuit 11 received signals, for example Dot Clock DCLK and data enable signal Xsft_en, and after the view data of order displacement, storing this view data from data array converter unit 9.
Shift register 5 receives load pulse XIoad, and before the view data that receives scanning subsequently, read in shift register 5 at the loaded with image data of a scan wiring to latch cicuit 6.Latch cicuit 6 latchs the view data (modulating data) that is used for this sweep trace.
Modulation circuit 8 outputs to vertical wires XD1 to XDN according to big young pathbreaker's modulation signal (XD1 to XDN) of the modulating data D1 to DN that receives from latch cicuit 6.
The details of the modulation circuit 8 of present embodiment is described with reference to Fig. 3 A.Modulation circuit 8 comprises counter, comparer, switch and OR door.Come reset counter according to the PwmStart signal that receives from driving timing pulse-generator circuit 12.After counter reset, counter begins the Pwmclk signal that receives from driving timing pulse-generator circuit 12 is counted, and the Pwmclk signal is a clock signal, and it is counted and is used for determining modulation signal length.Modulation circuit 8 comprises the comparer that is used for every vertical wires.Each comparer is count value and modulating data (one of D1 to DN) at every vertical wires relatively.The output of comparer is set to low level at first according to the PwmStart signal, and is set to high level when view data and count value coupling.In other words, till mating, the value of count value and view data can determine pulsewidth by counting Pwmclk signal as the length of modulation signal.Provide the OR door to be used to stop, and do not consider to import modulating data from the output of the modulation signal of comparer output.
In this way, when the output enable signal XOE that sends when described driving timing pulse-generator circuit 12 is in high level, close modulation circuit 8 output and no matter the input modulating data.
On the other hand, if output enable signal XOE is in low level, then for the each switching that provides of every modulation distribution is short-circuited to ground (GND) voltage with every vertical wires, is in low spot from the output signal of comparer simultaneously and puts down, voltage VPwm is in high level.As the result of this circuit operation, its rising edge and PwmStart signal rising edge synchronously and the modulation signal that has with the pulsewidth that is in proportion of view data be provided for every vertical wires.
Fig. 3 B has shown the example of this pulse-width signal.Fig. 3 B has shown the pulsewidth of 8 input image datas when view data is 128d and 255d.
Clock signal outputs to modulation circuit 8 from driving timing pulse-generator circuit 12.Next sweep circuit 2 is described.For example, sweep circuit 2 has structure shown in Figure 2.Sweep circuit 2 has the Y shift register that comprises switch and trigger circuit, and it is used to produce horizontal time-base.The quantity of switch is identical with the quantity of the horizontal distribution of display board 1.The quantity of trigger circuit is identical with the quantity of the horizontal distribution of display board 1.
The Y shift register is by receiving as the Ydata of input shifted data and the circuit that comes shifted data as the Ysft of clock signal from described driving timing pulse-generator circuit 12.
Switch receives the sweep signal of expression " selection " or " unselected " from shift register.When sweep signal is represented " selection ",, when representing " unselected ", non-selected voltage Vus is offered the horizontal distribution of display board 1 in sweep signal with selecting voltage Vs to offer the horizontal distribution of display board 1.
Next driving timing pulse-generator circuit 12 according to the embodiment of the invention will be described.
As mentioned above, driving timing pulse-generator circuit 12 outputs to modulation circuit 8 and sweep circuit 2 with control signal and is used for control regularly.Driving timing pulse-generator circuit 12 is with reference to the frame per second information FR from the picture format detecting unit, and produces the driving timing pulse generating signal according to frame per second.
Fig. 4 has shown driving timing pulse-generator circuit 12, and comprises oscillator (OSC) 40, controller 41, counter 42, phaselocked loop (PLL) 43, the PwmStart register 44, YCLK register 45 and comparer 46 and 47 that are used to export controlling value.
When Counter Value with from the Signal Matching of PwmStart register the time, comparer 46 output high level signals, and when Counter Value and signal from the PwmStart register do not match the output low level signal.The output of comparer 47 is timing signals, is used to scanning to set predetermined amount of time.
Fig. 5 has shown the control details of driving timing pulse-generator circuit 12.Fig. 5 aim at and compared when first frame per second be driving timing signal, the output of sweep circuit 2 and the output of modulation circuit 8 when being 50Hz of the 60Hz and second frame per second.The output of modulation circuit 8 shown in Figure 5 is the modulation signals (modulating pulse) that produce when modulating data is represented maximal value.
When importing the picture signal with different frame per second by setting driving timing pulse-generator circuit 12, the operation of driving timing pulse-generator circuit 12 expections is as described below.
Be driven in the frame per second of 60Hz with display board 1 and compare,, reduce with the brightness that prevents display board 1 when the oscillation frequency of display board 1 PLL 43 when the frame per second of 50Hz is driven descends.Simultaneously, 43 oscillation frequency can and 60Hz and 50Hz between the proportional change of difference.But, in this embodiment of the present invention, for the expection operation according to the oscillation frequency that is provided with as described below.Change the predetermined amount of time that is used for sweep signal is applied to continuously scan wiring by changing frame per second.As mentioned above, modulation circuit 8 is determined the pulsewidth of modulation signal by counting clock signal (Pwmclk).Consider two predetermined amount of time herein: very first time section and greater than second time period of very first time section.If for the identical clock signal of first and second time periods counting, then the maximum ladder number in grade will be obviously different.Therefore, according to this embodiment, the clock signal that is used for very first time section (first clock signal) has the frequency less than the clock signal that is used for second time period (second clock signal).
Expectation is provided with a time period, wherein in the application that does not have the application of modulation signal from (modulate non-use the period) between each time period of the application that is applied to modulation signal of sweep signal.By this modulation non-application period is set, can reduce the maximal value of the self-vibration voltage (ringing voltage) that is applied to display element.For the modulation of the present invention non-application period is set, during width modulation, clock signal (Pwmclk) is counted predetermined times.In other words, not the application of modulation signal up to obtaining predetermined count value.Because having clock signals of different frequencies is used for above-mentioned first and second time periods, so the length of non-application period of modulation can be obviously different in first and second periods.Below a kind of optimum length by setting the modulation non-application period of explanation is suppressed at method under the predetermined voltage with self-vibration voltage, for example, sets the modulation optimum length of non-application period according to the predetermined control value by counting first clock signal.For second time period, if set the modulation non-application period by counting second clock signal according to identical controlling value, then the non-application period of the modulation of second time period is greater than the modulation of the very first time section non-application period, because the frequency of second clock signal is greater than the frequency of first clock signal.Therefore, can shorten the time span of the modulation signal that will be employed.But according to this embodiment, it is inequality that expression is used to set the controlling value of counts of non-application period of modulation of first and second time periods, so that suppress the difference in the modulation of first and second time periods length of non-application period.In this way, with modulation non-application periods of first and second time periods of identical length setting.In other words, PwmStart register 44 output needles are to the different controlling value of first and second time periods, and the value of the clock signal of being counted up to counter 42 controlling value that equals 44 outputs of PwmStart register just applies the application of modulation signal then.
Constant from the time period between the application that is applied to modulation voltage of selecting voltage (that is, (using " Ta " expression in the accompanying drawings) forbidden the period in modulation) maintenance, even changing it, frame per second also remains unchanged.In this way, can prevent in specific grade characteristic the inefficacy of for example disturbing or because the superpotential that the waveform self-vibration of sweep signal causes is applied to display element, and can avoid because the brightness reduction of the display board 1 that the length of the time modulation signal that shortening is employed causes.
More specifically, by applying from time scan circuit 2 that the time span of selecting voltage deducts Ta and definite time period is defined as revising the period.The counts of Pwmclk signal equated for each modification period.
According to this embodiment, driving the non-application period is from the finish time based on the modulating pulse with peaked modulating data, switches to the time span in the moment of non-selected voltage to the output of sweep circuit 2 from selecting voltage, and remains unchanged.
The clock signal frequency that can represent width modulation by following formula:
fpwmclk＝Npclk/(Ts-Ta-Tb)
Wherein to apply and select the time span of voltage be Ts to sweep circuit 2, and the maximum clock that is used to modulate (being equivalent to maximum grade ladder) is Npclk.If (Npclk is 8 PWM, and then fpwmclk is 255d, if Npclk is 10 PWM, then fpwmclk is 1023d.)
Therefore, if the greatest level ladder Ta of first and second time periods is set to identical value with Tb, the frequency difference of first and second clock signals then is because Ts is different for first and second time periods.
Although above-mentioned frequency is an optimum frequency, very difficult accurately synchronous for 43 of PLL with these frequencies, because there are the various restrictions that comprise multiplication and division ratio.Do not expect frequency is dropped under the said frequencies,, and reduce the time span of time period Ta and Tb thus because will increase the application time of modulation signal.
Therefore, expectation selects to be higher than the frequency of said frequencies.
In other words, expect to set multiplication and the formula of division ratio below satisfying for PLL 43:
fpwmclk≥Npclk/(Ts-Ta-Tb)
Set the PwmStart register of driving timing pulse-generator circuit 12 and the register value of Yclk register, it is constant to make that Ta and Tb keep, as mentioned above.
At this moment, controller can change the setting value of register, perhaps this value can be switched to the value of calculating according to a plurality of frame per second in advance.
In this way, change is used for determining PwmStart register and the controlling value of Yclk register and the clock frequency of the driving timing pulse-generator circuit 12 of definite modulation signal duration, and is constant to keep the driving non-application period.
Therefore, the following describes the control of being undertaken by driving timing pulse-generator circuit 12.
Satisfy following formula by the control that driving timing pulse-generator circuit 12 carries out:
f1＞f2
Wherein f1 represents the frequency of the Pwmclk of the first frame per second F1, and f2 represents the frequency of the Pwmclk of the second frame per second F2.
Formula below relation between f1, F1, f2 and the F2 satisfies:
f1/F1＞f2/F2
Very Qi Wang operation can when driving timing pulse-generator circuit 12, provide satisfy below the control of formula:
B1/H1＞B2/H2
Wherein H1 represents the application period (corresponding to the Ts among Fig. 5) of the selection voltage that sweep circuit 2 applies at the first frame per second F1, B1 represents the non-application of above-mentioned driving period (corresponding to Ta among Fig. 5 or Ta+Tb), H2 represents the application period of the selection voltage that sweep circuit 2 applies at the second frame per second F2, and B2 represents the non-application period of above-mentioned driving.
When the first frame per second F1 is dynamically switched (that is, being switched) to the second frame per second F2 when image is presented on the display board 1, the process described in driving timing generator circuit 12 execution graphs 6.
Fig. 6 has shown when detecting the frame per second variation by the performed process of the controller of picture format detecting unit.Controller is forbidden the output enable signal XOE that is provided to modulation circuit 8, and closes the output of modulation circuit 8.In order to obtain above-mentioned setting, set multiplication and the division ratio of PLL 43, change the value of PwmStart register and Yclk register, activate output enable signal XOE then.
Fig. 6 has shown to have only the controlled situation of output enable signal XOE.But the output of sweep circuit 2 also is can be controlled.
After setting PLL 43, expectation obtains time enough and is used for stablizing PLL 43.When the clock of PLL 43 output was counted in the section at the fixed time, the time of the scheduled volume that can consume by the stabilization process of waiting for enough PLL43 was perhaps by waiting for that reaching predetermined value up to clock value determines whether PLL 43 is stabilized.
Therefore, display device according to the embodiment of the invention does not have to make us extremely satisfied aspect the disturbance at input picture, even when a frame per second dynamically switched to another frame per second, image shows also can be avoided because the disturbance that the driving timing change causes at input picture.
By aforesaid controlling and driving regularly, display device according to the embodiment of the invention has the following advantages: apply from the timing of the selection voltage of sweep circuit 2 output and apply from the difference between the timing of the modulation voltage pulse of modulation circuit 8 outputs by keeping, stable driving is provided; Kept identical grade ladder; Make the application time maximization of modulation signal; And the brightness reduction of display device is minimized.
In addition, when the frame per second of input picture is dynamically switched, can there be to obtain under the situation of disturbance the demonstration of expectation at display screen yet.
Fig. 8 has shown television equipment 804, and it comprises display device shown in Figure 1.Television equipment 804 shown in Fig. 8 comprises the tuner 802 that is used for the tv tuner broadcast singal and display device 803 shown in Figure 1.Television broadcasting signal 801 is input to tuner 802.Tuner 802 extracts the signal of expection from input signal, and the signal of expection is sent to display device 803.Display device 803 is according to the signal display of television programmes that comes self-tuner 802.
Second embodiment
But modulating device is not limited to this modulating device, can adopt the modulating device of any kind, as long as can be according to the length of modulating data modulating pulse.For example, the present invention can expect to be used in Jap.P. and discloses the structure that discloses in 2003-173159 and 2003-316312 number.
Although the present invention has been described, should be appreciated that to the invention is not restricted to disclosed embodiment with reference to exemplary embodiments.On the contrary, the present invention is intended to contain essence and interior various modifications and the equivalent arrangements of scope that is included in appended claim.Below the scope of claim will be consistent with the explanation of its wide region so that comprise modification and equivalent construction and the function that all are such.
The application requires the right of priority of the Japanese patent application submitted on June 30th, 2004 2004-193475 number, and its content is incorporated this paper into way of reference.
Claims (9)
1. display device comprises:
Display board, it contains a plurality of matrix of display elements that are connected with many modulation distributions by plurality of scanning wirings;
Sweep circuit is used to scan described plurality of scanning wirings, sweep signal is applied in the section simultaneously each bar in the plurality of scanning wirings at the fixed time;
Modulation circuit, the modulation signal that is used for synchronously will having a modulating time width with described predetermined amount of time is applied to described many modulation distributions; And
The driving timing pulse-generator circuit is used to export timing signal and clock signal, and described timing signal is used for determining described predetermined amount of time, and described clock signal will be counted to determine the length of modulation signal;
Wherein said driving timing pulse-generator circuit can switch between first state and second state, first state is that described driving timing pulse-generator circuit is exported first timing signal as described timing signal and export the state of first clock signal as described clock signal, second state is a described driving timing pulse-generator circuit output second timing signal as described timing signal and the output second clock signal state as described clock signal
Wherein very first time section is shorter than second time period, and very first time section is the predetermined amount of time of being determined by first timing signal, and second time period was the predetermined amount of time of being determined by second timing signal, and
Wherein the frequency of first clock signal is higher than the frequency of second clock signal.
2. display device as claimed in claim 1,
Wherein said driving timing pulse-generator circuit output is used for determining the modulation signal controlling value of non-application period, and the initial moment of non-application period of described modulation signal from described predetermined amount of time extends to the moment that modulation signal is employed,
Wherein said driving timing pulse-generator circuit is exported first controlling value as the controlling value in first state,
Wherein said driving timing pulse-generator circuit is exported second controlling value as the controlling value in second state, and
Wherein the first and second non-application periods and first and second time periods have following relation:
First non-application period/non-application period/the second time period of very first time section＞second,
The first non-application period was the modulation signal non-application period of being determined by first controlling value, and the second non-application period was the modulation signal non-application period of being determined by second controlling value.
3. display device as claimed in claim 2,
Wherein the first non-application period was by counting first clock signal until definite corresponding to the quantity of first controlling value, and
Wherein the second non-application period was until definite corresponding to the quantity of second controlling value by counting second clock signal.
4. display device as claimed in claim 1,
Wherein said driving timing pulse-generator circuit is exported first timing signal and first clock signal when the picture signal with first frame per second is imported into this display device, and
Wherein said driving timing pulse-generator circuit is exported second timing signal and second clock signal when the picture signal with second frame per second that is lower than first frame per second is imported into this display device.
5. television equipment comprises:
Tuner is used for the tv tuner broadcast singal; And
Display device is used for coming display image according to the signal from described tuner output, and described display device comprises:
Display board, it contains a plurality of matrix of display elements that are connected with many modulation distributions by plurality of scanning wirings;
Sweep circuit is used to scan described plurality of scanning wirings, sweep signal is applied in the section simultaneously each bar in the plurality of scanning wirings at the fixed time;
Modulation circuit, the modulation signal that is used for synchronously will having a modulating time width with described predetermined amount of time is applied to described many modulation distributions; And
The driving timing pulse-generator circuit is used to export timing signal and clock signal, and timing signal is used for determining described predetermined amount of time, and clock signal will be counted to determine the length of modulation signal;
Wherein said driving timing pulse-generator circuit can switch between first state and second state, first state is that described driving timing pulse-generator circuit is exported first timing signal as described timing signal and export the state of first clock signal as described clock signal, second state is a described driving timing pulse-generator circuit output second timing signal as described timing signal and the output second clock signal state as described clock signal
Wherein very first time section is shorter than second time period, and very first time section is the predetermined amount of time of being determined by first timing signal, and second time period was the predetermined amount of time of being determined by second timing signal, and
Wherein the frequency of first clock signal is higher than the frequency of second clock signal.
6. television equipment as claimed in claim 5,
Wherein said driving timing pulse-generator circuit output is used for determining the modulation signal controlling value of non-application period, and the initial moment of non-application period of described modulation signal from described predetermined amount of time extends to the moment that modulation signal is employed,
Wherein said driving timing pulse-generator circuit is exported first controlling value as the controlling value in first state,
Wherein said driving timing pulse-generator circuit is exported second controlling value as the controlling value in second state, and
Wherein the first and second non-application periods and first and second time periods have following relation:
First non-application period/non-application period/the second time period of very first time section＞second,
The first non-application period was the modulation signal non-application period of being determined by first controlling value, and the second non-application period was the modulation signal non-application period of being determined by second controlling value.
7. television equipment as claimed in claim 6,
Wherein the first non-application period was by counting first clock signal until definite corresponding to the quantity of first controlling value, and
Wherein the second non-application period was until definite corresponding to the quantity of second controlling value by counting second clock signal.
8. television equipment as claimed in claim 5,
Wherein said driving timing pulse-generator circuit is exported first timing signal and first clock signal when the picture signal with first frame per second is imported into this display device, and
Wherein said driving timing pulse-generator circuit is exported second timing signal and second clock signal when the picture signal with second frame per second that is lower than first frame per second is imported into this display device.
9. method that is used to drive display device, this display device comprise the display board with a plurality of matrix of display elements that are connected with many modulation distributions by plurality of scanning wirings, and this method may further comprise the steps:
Scan described plurality of scanning wirings, sweep signal is applied in the section simultaneously each bar in the plurality of scanning wirings at the fixed time;
The modulation signal that synchronously will have the modulating time width with described predetermined amount of time is applied to described many modulation distributions; And
Between first state and second state, switch, first state is that the driving timing pulse-generator circuit is exported first timing signal, first clock signal and the state that is used for first controlling value of definite non-application period of modulation signal, wherein first timing signal is used for determining described predetermined amount of time, first clock signal is counted to determine the length of modulation signal, the initial moment of non-application period of modulation signal from predetermined amount of time extends to the moment that modulation signal is employed, second state is a driving timing pulse-generator circuit output second timing signal, second clock signal and the state that is used for second controlling value of definite non-application period of modulation signal, wherein second timing signal is used for determining described predetermined amount of time, the second clock signal is counted to determine the length of modulation signal, and the initial moment of non-application period of described modulation signal from predetermined amount of time extends to the moment that modulation signal is employed;
Wherein very first time section is shorter than second time period, and wherein very first time section is the predetermined amount of time of being determined by first timing signal, and second time period was the predetermined amount of time of being determined by second timing signal;
Wherein by counting first clock signal, by counting the second clock signal until the modulation signal non-application period of determining corresponding to the quantity of second controlling value in second state until the modulation signal non-application period of determining corresponding to the quantity of first controlling value in first state; And
Wherein when when second state switches to first state, controlling value switches to first controlling value from second controlling value, stops applying step simultaneously.
Applications Claiming Priority (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2004193475 | 2004-06-30 | ||
| JP2004193475 | 2004-06-30 | ||
| JP2005173880 | 2005-06-14 |
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| Publication Number | Publication Date |
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| CN1716356A CN1716356A (en) | 2006-01-04 |
| CN100390840C true CN100390840C (en) | 2008-05-28 |
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| Application Number | Title | Priority Date | Filing Date |
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| CNB2005100818285A Expired - Fee Related CN100390840C (en) | 2004-06-30 | 2005-06-30 | Display apparatus and method for controlling the same |
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| CN (1) | CN100390840C (en) |
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| CN107004395A (en) * | 2014-12-08 | 2017-08-01 | 夏普株式会社 | Display control unit, display control method and display control program |
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| TWI406233B (en) * | 2008-01-31 | 2013-08-21 | Innolux Corp | Liquid crystal display panel, liquid crystal display apparatus and control method thereof |
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| CN1716356A (en) | 2006-01-04 |
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