CN1801129A - Selection circuit for selecting slave module in accordance with connection sequence and control mode thereof - Google Patents

Abstract

The invention discloses a circuit selection and control pattern according to the connection sequence of mode selection, which is characterized by the following: setting the selected circuit of mode as D trigger; connecting each mode D trigger serially to form shift register; transmitting only one effective selection signal of main mode in the secondary mode according to the serial connection sequence; paralleling the clock signal of main mode to clock signal end of the secondary mode; paralleling the clear signal of main mode to the clear end of secondary mode. The invention accomplishes the mode selection of serial connection according to the connection sequence without setting address, which connects secondary mode first then main mode sequently and selects utility of serial connection mode according to the connection sequence.

Description

Selection circuit and control mode thereof that slave module in accordance with connection sequence is selected

Technical field:

The present invention relates to a kind of by the selection circuit and the control mode thereof of primary module to selecting from module.

Background introduction:

Have a lot of electronic products all to adopt modular design now, make the configuration of product more flexible, the user can select easily.Generally, the module of this product can be divided into primary module (as: main control module, CPU module etc.) and from module (as: switching value input/output module, analog quantity input/output module etc.).Each module is connected in series.Each all has the address of oneself from module.The address signal that primary module transmits by the logical circuit on module, produces corresponding module select signal, thereby control is to the visit from module.The user can change the address from module by modes such as wire jumpers.Adopt this connected mode, before using product will to product from module the address is set, and must guarantee that the address do not repeat, cumbersome.And when increasing new module, also to be provided with one with current all from module address inequality, not too convenient.

Summary of the invention:

The present invention is for avoiding above-mentioned existing in prior technology weak point, and a kind of selection circuit that can select by the order of connection is provided.

The present invention provides the control mode of this circuit simultaneously.

The technical scheme that technical solution problem of the present invention is adopted is:

The present invention selects the design feature of circuit to be: it is characterized in that single selection circuit from module is a d type flip flop, each d type flip flop from module is connected in series each other, constitute shift register, primary module unique one effectively select signal CS_Input by sequence delivery connected in series to selected from module, primary module clock signal C S_Clock is in parallel to insert respectively clock signal terminal CLK from module, and primary module reset signal CS_Clear is in parallel to insert respectively clear terminal CLR from module.

The characteristics of control mode of the present invention are to work in the following order:

A, primary module CS_Clear be output " low " level earlier, and the Q end of all d type flip flops all is set to " low " level, and output " height " level again makes all d type flip flops can the normal delivery signal;

B, primary module CS_Input export " height " level, and from CS_Clock output " low " level;

C, individual from module if will visit n, earlier from CS_Clock output " height " level, then from CS_Clock and CS_Input output " low " level, so repeat n time, produce n rising edge at the CS_Clock end, unique " height " level is moved on to the Q end of n d type flip flop from module, thereby make this selection signal from module effective, primary module can conduct interviews from module to this;

D, after visit finishes, from CS_Clear output " low " level, the Q end of all d type flip flops all is set to " low " level, make all invalid from the selection signal of module.

The present invention utilizes shift register, and unique of primary module is effectively selected signal, by sequence delivery connected in series to selected from module, make primary module to conduct interviews from module to this.

Compared with the prior art, beneficial effect of the present invention is embodied in:

The present invention selects circuit can realize by the order of connection module connected in series being selected, and need not to be provided with the address.During use, only needing will be connected in series one by one from module, receive primary module at last again, by the order of connection module connected in series be selected to use.

Description of drawings:

Fig. 1 is that the present invention is from module syndeton block diagram.

Fig. 2 is that the present invention is from module connecting circuit structural representation.

Fig. 3 is the master and slave module of a present invention formation shift-register circuit connected in series structural representation.

Below by embodiment the present invention is further described:

Embodiment:

Primary module is with connected in series from module, as shown in Figure 1 in the present embodiment.Primary module output 3 control signal wire: CS_Clear, CS_Clock, CS_Input.From the connecting circuit of module as shown in Figure 2.Wherein P1 is an input socket, and P2 is an accessory power outlet, and chip SN74HC74N is a d type flip flop.

The principle of work of this connecting circuit: master and slave module is connected in series, enough become a shift-register circuit, by primary module whole shift circuit is controlled.As shown in Figure 3.

In the present embodiment, when the CS_Clear signal of primary module output was " low " level, the Q end of all d type flip flops all was " low " level; When the CS_Clear signal of primary module output was " height " level, the rising edge of each CS_Clock signal all can pass to the level signal of d type flip flop D end the Q end, thus the displacement that produces signal.The output terminal Q (or Q) of the d type flip flop from the module connecting circuit is as the selection signal from module.

The scope of application of this connecting circuit: be applicable to " one main many from " structure, module and circuit board connected in series.Particularly need by the product of the order of connection conducting interviews from module.

In concrete the enforcement: when using this connecting circuit, be not to use chip SN74HC74N.As long as several chip blocks couple together and can constitute shift register.For effective selection signal be " height " level from module, can obtain the selection signal from the Q end of d type flip flop; For effective selection signal be " low " level from module, can obtain the selection signal from the Q end of d type flip flop.

Claims (2)

1, a kind of selection circuit of slave module in accordance with connection sequence selection, it is characterized in that single selection circuit from module is a d type flip flop, each d type flip flop from module is connected in series each other, constitute shift register, primary module unique one effectively select signal CS_Input by sequence delivery connected in series to selected from module, primary module clock signal C S_Clock is in parallel to insert respectively clock signal terminal CLK from module, and primary module reset signal CS_Clear is in parallel to insert respectively clear terminal CLR from module.

2, the control mode of the described selection circuit of claim 1 is characterized in that following steps carry out:

A, primary module CS_Clear be output " low " level earlier, and the Q end of all d type flip flops all is set to " low " level, and output " height " level again makes all d type flip flops can the normal delivery signal;

B, primary module CS_Input export " height " level, and from CS_Clock output " low " level;

C, individual from module if will visit n, earlier from CS_Clock output " height " level, then from CS_Clock and CS_Input output " low " level, so repeat n time, produce n rising edge at the CS_Clock end, unique " height " level is moved on to the Q end of n d type flip flop from module, thereby make this selection signal from module effective, primary module can conduct interviews from module to this;

D, after visit finishes, from CS_Clear output " low " level, the Q end of all d type flip flops all is set to " low " level, make all invalid from the selection signal of module.

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