CN1798470A - T type topological wiring architecture for transmission line - Google Patents
T type topological wiring architecture for transmission line Download PDFInfo
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- CN1798470A CN1798470A CN 200410091891 CN200410091891A CN1798470A CN 1798470 A CN1798470 A CN 1798470A CN 200410091891 CN200410091891 CN 200410091891 CN 200410091891 A CN200410091891 A CN 200410091891A CN 1798470 A CN1798470 A CN 1798470A
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- transmission line
- connector slot
- wiring architecture
- topological wiring
- type topological
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Abstract
The invention is used for connecting a chip between a first connector slot and a second connector slot. The first connector slot and the second connector slot are respectively connected to the two ends in one side of the invention. The chip is connected to the other end of the invention. The transmission lines of first and second connector slot are connected to the chip after they are joined together in same impedance at a connection point. The invention can effectively solve the problem of transmission effects such as cross talk and overshoot existed in traditional wiring structure.
Description
[technical field]
The present invention relates to a kind of topological wiring architecture for transmission line, particularly relate to a kind of topological wiring architecture for transmission line that north bridge chips and DDR connector interconnect in high speed circuit on motherboard.
[background technology]
Development of electronic technology makes that the operating rate of IC (integrated circuit) is more and more faster, frequency is more and more higher, when the interconnect delay of signal greater than the edge signal turn threshold time 20% the time, PCB (printed circuit board (PCB)) goes up holding wire will present transmission line effect, be online no longer be the simple lead that shows lumped parameter, but present the parameter effect of distribution, high speed design that Here it is.
Development along with semiconductor technology, high speed design becomes an important step in the product design, compare with traditional design, high speed design will be considered problems of Signal Integrity more, and the overshoot that high speed design faced (overshoot), down dash problems of Signal Integrity such as (under shoot), ring (ringing), delay and monotonicity, will become a bottleneck of traditional design.On high-speed printed circuit board, a lead no longer has been simple lead, treats and must be used as transmission line, handles according to transmission line theory.Do not match when signal runs into impedance during in High-Speed PCB upper edge transmission line, will have portion of energy to pass back along transmission line, cause reflex from the impedance discontinuity point.
Fig. 1 is the north bridge chips of existing daisy chain (Daisy Chain) type topological wiring architecture and the schematic diagram of two DDR slots interconnection, north bridge chips 10 is connected to the 21 DDR slot 30 after being connected to a DDR slot 20 earlier by a transmission lines 12 again, wherein, the 2nd DDR slot 30 with respect to a DDR slot more than 20 one section transmission line 14, if the length long enough of transmission line 14, when signal then transmission line effect can occur during in High-Speed PCB upper edge transmission line, cause impedance not distinguish the problem of joining.Do not distinguish the situation of joining for solving this impedance, prior art is general to adopt end at the 2nd DDR slot 30 tie points to be provided with a terminal resistance 40 that is connected to power supply VTT, so no doubt can solve the unmatched situation of signal impedance, but increase a terminal resistance 40 can make motherboard under originally the very meagre situation of the profit margin of present motherboard whole cost rising.
Therefore, how to provide a kind of design that can effectively solve the Wiring architecture of transmission line effect and whole cost is risen to become the problem of people's research.
[summary of the invention]
The object of the present invention is to provide a kind of topological wiring architecture for transmission line that under endless resistance situation, still can effectively reduce transmission line effect.
In order to solve the above-mentioned technical problem of prior art, according to a scheme of the present invention, a kind of T type topological wiring architecture for transmission line, be applied to being connected of north bridge chips and one first connector slot and one second connector slot, described first connector slot and the described second connector slot are connected to two ends on same one side of T type topological wiring architecture for transmission line, described chip is connected in the end of T type topological wiring architecture for transmission line another side, is connected in the chip after being connected in a tie-point to the impedances such as transmission line of the described first connector slot and the second connector slot.
Adopt the embodiment of above-mentioned T type topological wiring architecture for transmission line, can reach and under the situation of endless resistance, still can effectively solve crosstalking and transmission line effect problem such as overshoot in the traditional wiring framework, improve the transmission quality of signal, and reduce the quantity of element, reduce cost.
[description of drawings]
Fig. 1 is the north bridge chips of existing chrysanthemum chain topological wiring architecture and the schematic diagram of two DDR slots interconnection.
Fig. 2 is the north bridge chips of T type topological wiring architecture for transmission line of the present invention and the schematic diagram of two DDR slots interconnection.
Fig. 3 is according to the T type topological wiring architecture for transmission line of Fig. 2 and address wire simulation waveform comparison diagram according to the chrysanthemum chain topological wiring architecture of Fig. 1.
Fig. 4 is according to the T type topological wiring architecture for transmission line of Fig. 2 and write data simulation waveform comparison diagram according to the chrysanthemum chain topological wiring architecture of Fig. 1.
Fig. 5 is according to the T type topological wiring architecture for transmission line of Fig. 2 and read data simulation waveform comparison diagram according to the chrysanthemum chain topological wiring architecture of Fig. 1.
[embodiment]
The present invention is described in further detail below in conjunction with drawings and the specific embodiments.
Please refer to Fig. 2, it is the schematic diagram of the north bridge chips of T type topological wiring architecture for transmission line of the present invention and the interconnection of two DDR slots.Among the figure, north bridge chips 100 is by a transmission line 112,114,116 respectively with one the one DDR slot 120, one the 2nd DDR slot 130 is connected, wherein, transmission line 112,114,116 one-tenth T type Wiring architectures, the one DDR connector slot 120 and the 2nd DDR connector slot 130 lay respectively at two ends on same one side of T type topological wiring architecture for transmission line, the one DDR connector slot 120 is connected with transmission line 114, the 2nd DDR connector slot 130 is connected with transmission line 116, chip 100 is positioned at T type topological wiring architecture for transmission line another side end, be connected with transmission line 112, transmission line 112,114,116 intersect at a tie-point 160 respectively, promptly a DDR connector slot 120 is through being connected in a tie-point 160 with the 2nd DDR connector slot 130 behind the transmission line 114 behind transmission line 116, and the transmission line 116 of a DDR connector slot 120 to transmission line 114 distances of 160 of tie-points and the 2nd DDR connector slot 130 to 160 of tie-points is apart from equating the integrality of inhibit signal.The one DDR connector slot 120 equates with the impedance of the second connector slot 130 to the transmission line 116 of 160 of tie-points to the impedance of the transmission line 114 of 160 of tie-points, and equal the twice of tie-point 160 to the impedance of the transmission line 112 of 100 of chips, it is discontinuous that the elimination interlink is put 160 impedances.
Please in the lump with reference to figure 3, it is according to the T type topological wiring architecture for transmission line of figure and address wire simulation waveform comparison diagram according to the chrysanthemum chain topological wiring architecture of Fig. 1.Among the figure, what waveform 1 was represented is the waveform that adopts T type topological wiring architecture for transmission line, and what waveform 2 was represented is the waveform that adopts chrysanthemum chain topological wiring architecture.As seen from Figure 3, under the situation of endless resistance, adopt the DDR connector slot of T type topological wiring architecture for transmission line of the present invention comparing aspect the address wire signal with the transmission line signals of north bridge chips with the DDR slot of traditional chrysanthemum chain topological wiring architecture with the transmission line signals of north bridge chips, the effect that both reached is basic identical.
Please in the lump with reference to figure 4, it is according to the T type topological wiring architecture for transmission line of Fig. 2 and write data simulation waveform comparison diagram according to the chrysanthemum chain topological wiring architecture of Fig. 1.Among the figure, what waveform 3 was represented is the waveform that adopts T type topological wiring architecture for transmission line, and what waveform 4 was represented is the waveform that adopts chrysanthemum chain topological wiring architecture.As seen from Figure 4, under the situation of endless resistance, adopt the DDR connector slot of T type topological wiring architecture for transmission line of the present invention to compare aspect the write data with the transmission line signals of north bridge chips with the DDR slot of traditional chrysanthemum chain topological wiring architecture with the transmission line signals of north bridge chips, the effect that both reached is basic identical.
Please in the lump with reference to figure 5, it is according to the T type topological wiring architecture for transmission line of Fig. 2 and read data simulation waveform comparison diagram according to the chrysanthemum chain topological wiring architecture of Fig. 1.Among the figure, what waveform 5 was represented is the waveform that adopts T type topological wiring architecture for transmission line, and what waveform 6 was represented is the waveform that adopts chrysanthemum chain topological wiring architecture.As seen from Figure 5, under the situation of endless resistance, adopt the DDR connector slot of T type topological wiring architecture for transmission line of the present invention to compare aspect the data read with the transmission line signals of north bridge chips with the DDR slot of traditional chrysanthemum chain topological wiring architecture with the transmission line signals of north bridge chips, the connected mode of employing T type topological wiring architecture for transmission line then slightly is inferior to the connected mode of traditional chrysanthemum chain topological wiring architecture for transmission line, but also within the requirement of former design specification.
In sum, the DDR connected mode that adopts T type topological wiring architecture for transmission line keeps and the original allomeric function that adopts the DDR connected mode of chrysanthemum chain topological wiring architecture for transmission line under the situation of endless resistance basically.
Execute in the example above, in the connected mode of north bridge chips and a DDR connector slot, the 2nd DDR connector slot, adopt T type transmission line topology cabling architecture, but the present invention never only only limits to this, and the Wiring architecture of this printed circuit board (PCB) can also be applied to other single driver in the circuit framework of multiple collector.
Claims (5)
1. T type topological wiring architecture for transmission line, be applied to being connected of north bridge chips and one first connector slot and one second connector slot, it is characterized in that: described first connector slot and the described second connector slot are connected to two ends on same one side of T type topological wiring architecture for transmission line, described chip is connected in T type topological wiring architecture for transmission line another side end, is connected in the chip after being connected in a tie-point to the impedances such as transmission line of the described first connector slot and the second connector slot.
2. T type topological wiring architecture for transmission line as claimed in claim 1 is characterized in that: describedly be connected to the first connector slot and the second connector slot is the twice of tie-point to the transmission line impedance of chip chamber to the transmission line impedance between tie-point.
3. T type topological wiring architecture for transmission line as claimed in claim 1 is characterized in that: the described first connector slot is to equate with the second connector slot to the distance between tie-point to the distance between tie-point.
4. T type topological wiring architecture for transmission line as claimed in claim 2 is characterized in that: the described first connector slot and the second connector slot are the DDR memory bank.
5. T type topological wiring architecture for transmission line as claimed in claim 2 is characterized in that: the described first connector slot and the second connector slot are the DDR memory bank.
Priority Applications (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 200410091891 CN1798470A (en) | 2004-12-25 | 2004-12-25 | T type topological wiring architecture for transmission line |
| US11/291,756 US20060132577A1 (en) | 2004-12-04 | 2005-12-01 | Circuit topology for high-speed printed circuit board |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 200410091891 CN1798470A (en) | 2004-12-25 | 2004-12-25 | T type topological wiring architecture for transmission line |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN1798470A true CN1798470A (en) | 2006-07-05 |
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Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN 200410091891 Pending CN1798470A (en) | 2004-12-04 | 2004-12-25 | T type topological wiring architecture for transmission line |
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| Country | Link |
|---|---|
| CN (1) | CN1798470A (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102573269A (en) * | 2010-12-09 | 2012-07-11 | 鸿富锦精密工业（深圳）有限公司 | Printed circuit board |
| CN106776420A (en) * | 2016-11-11 | 2017-05-31 | 郑州云海信息技术有限公司 | A kind of mainboard structure for lifting DDR signal transmission quality |
| CN113316319A (en) * | 2021-05-08 | 2021-08-27 | 珠海全志科技股份有限公司 | Intelligent device, readable storage medium, printed circuit board and using method thereof |
-
2004
- 2004-12-25 CN CN 200410091891 patent/CN1798470A/en active Pending
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102573269A (en) * | 2010-12-09 | 2012-07-11 | 鸿富锦精密工业（深圳）有限公司 | Printed circuit board |
| CN106776420A (en) * | 2016-11-11 | 2017-05-31 | 郑州云海信息技术有限公司 | A kind of mainboard structure for lifting DDR signal transmission quality |
| CN113316319A (en) * | 2021-05-08 | 2021-08-27 | 珠海全志科技股份有限公司 | Intelligent device, readable storage medium, printed circuit board and using method thereof |
| CN113316319B (en) * | 2021-05-08 | 2022-11-11 | 珠海全志科技股份有限公司 | Intelligent device, readable storage medium, printed circuit board and using method thereof |
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Open date: 20060705 |