CN1797997A - Transmission system of parallel 12 routes 10Gb/s very short distance - Google Patents
Transmission system of parallel 12 routes 10Gb/s very short distance Download PDFInfo
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- CN1797997A CN1797997A CN 200410098997 CN200410098997A CN1797997A CN 1797997 A CN1797997 A CN 1797997A CN 200410098997 CN200410098997 CN 200410098997 CN 200410098997 A CN200410098997 A CN 200410098997A CN 1797997 A CN1797997 A CN 1797997A
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Abstract
The system includes parts and operating flow: an OC-192 framer generates 16 routes of STM-4 signal, which are converted to 10 routes of signal, 1 route of parity check signal, and 1 route CRC check signal generated through decommutator; then, the said signals are adjustment in a transmission controller to make each route of channel transfer data; being transferred to a 8B/10B encoder, data are converted to serial signal after passing through a parallel/serial convertor; reception controller recovers 10 routes of data signal, 1 route of parity check signal, and 1 route CRC check signal from 12 route mixed signal, and the controller realizes function of cable symmetrical cross detection and frame synchronization; after passing through debugging and correcting unit, data are converted to 16 routes of STM-4 signals, which are transferred to OC-192 framer; the system converts signals received to 12 route of mixed channel for transmitting data, debugging and correcting signal in parallel.
Description
Technical field
The present invention relates to transmit the very short distance transmission system that digit rate is 10Gb/s, particularly the very short distance transmission system of a kind of 12 tunnel parallel 10Gb/s.
Background technology
Along with the paces of global IT application process constantly quicken, network technology obtains fast development, and is also increasing to the demand of Network Transmission bandwidth.The present a kind of 10Gb/s very short distance transmission system that exists, use 12 tunnel vertical-cavity surface-emitting laser array with and parallel light transceiving module 300 meters transfer of data that realize 10Gb/s apart from the lining, but it adopts 10 path channels transmission payload user data, the scheme of 2 path channels transmitting control datas exists channel resource waste, the problem that efficiency of transmission is not high.
Summary of the invention
The purpose of this invention is to provide a kind of 12 tunnel novel parallel 10Gb/s very short distance transmission systems, have more high efficiency, bigger flexibility, 12 tunnel parallel very short distance transmission systems of employing VCSEL and 12 road multimode fiber bands.
The present invention's a kind of 12 tunnel parallel 10Gb/s very short distance transmission systems is characterized in that, comprising:
An OC-192 framer, generate 16 road STM-4 signals, this frame signal is this 16 tunnel conversion of signals that 10 road signals generate 1 tunnel parity signal and 1 tunnel CRC check signal simultaneously by a decommutator, 10 road signals after the conversion and 1 tunnel parity signal are adjusted sequential by a buffer memory, import into simultaneously in the transmission control unit (TCU) with 1 tunnel CRC check signal then, transmission control unit (TCU) is adjusted the data of 12 road signals of input, make all transmitting data information and control informations on every path channels, do not transmitted the dedicated channel of parity signal and CRC check signal this moment, this 12 road signal enters a parallel/serial transducer after importing a 8B/10B encoder encodes into, be converted to serial signal, by a parallel optical transmission module transmission, signal passes to a parallel Optical Receivers, be received the back and be converted to parallel signal by a serial/parallel transducer, parallel signal passes through to import a reception controller after the 8B/10B decoder for decoding, receive controller 12 tunnel mixed signals are reverted to 10 circuit-switched data signals and 1 tunnel parity signal, 1 tunnel CRC check signal, realize cable symmetrical chiasma measuring ability simultaneously, frame synchronization function, realize cable symmetrical chiasma measuring ability simultaneously, frame synchronization function, signal is undertaken importing Jian Cuo ﹠amp after the bit aligned by a buffer queue then; Error-corrector is carried out EDC error detection and correction, and being converted to 16 road STM-4 signals through the data-signal behind the EDC error detection and correction, 16 road STM-4 signals are passed to an OC-192 framer at last;
12 tunnel parallel 10Gb/s very short distance transmission systems become 12 road mixed channels that transmit data and error correcting and detecting signal simultaneously, parallel transmission data to 10 circuit-switched data transmission channels, 1 road error-correcting channel and 1 tunnel error detection channel.
Wherein this transmission system is 12 tunnel parallel very short distance transmission systems of a kind of VCSEL of employing and 12 road multimode fiber bands.
Wherein the defeated device of transmission control is the controller that 16 road STM-4 signals are reset, it is converted to 12 channel parallel data pieces to a STM-64 frame of being made up of 16 road STM-4 frames, its 12969 row bytes that begin are data and the error correction of STM-64,12961 to be listed as 14040 row bytes be the error detection byte, and error correction is inserted in the 12960 row bytes of beginning.
Wherein receiving controller is that 12 tunnel mixed signals that receive are reverted to 10 circuit-switched data signals and 1 tunnel parity signal, 1 tunnel CRC check signal, the signal that receives a frame of controller reception 14040 is listed as totally, from wherein extracting data-signal, be mapped as 10 road parallel signals, extract parity signal and CRC check signal again, be mapped as 1 road signal respectively, 12 road signal parallels transmission of generation.
Wherein receive controller to 12 the bit signals detections of first row of totally 14040 row of first frame signal, normal condition is the 1 the road to the 6 the tunnel to be the A1 byte, the the 7 the road to the 12 the tunnel is the A1 byte, the the 1 the road to the 6 the tunnel is the A1 byte if cable is instead inserted, the the 7 the road to the 12 the tunnel is the A1 byte, can judge the situation that cable connects by this species diversity, realize that the cable symmetrical chiasma detects, avoid cable instead to insert.
Wherein receiving controller by first frame the 3rd row A1 that receives is detected, is A1 in conjunction with 6 bytes of the 1st row, and 6 bytes are the situation of A1, determine frame head, and achieve frame is synchronous.
The present invention adopts the method for transmitting payload user data and control data in 12 tunnel transmission channels simultaneously, has strengthened the harmony of transfer of data, has reduced the bandwidth waste on original 2 tunnel control data transmission channels, is improved on performance and efficient.
Description of drawings
For further specifying concrete technology contents of the present invention, below in conjunction with embodiment and accompanying drawing describes in detail as after, wherein:
Fig. 1 is 12 tunnel novel parallel 10Gb/s very short distance transmission system structure charts;
Fig. 2 is the channel rearrangement figure of novel 12 tunnel parallel 10Gb/s very short distance transmission systems;
Fig. 3 is the transmission frame-form figure of novel 12 tunnel parallel 10Gb/s very short distance transmission systems;
Fig. 4 is the 12 tunnel novel parallel 10Gb/s very short distance transmission system frame assumption diagrams that contain error correction;
Fig. 5 is the 12 tunnel novel parallel 10Gb/s very short distance transmission system frame assumption diagrams that contain error correction and error detection byte.
Embodiment
Of the present invention 12 tunnel parallel 10Gb/s very short distance transmission systems, as shown in Figure 1, it comprises transmission and receives two parts.Sending part is to send an OC-192 frame by an OC-192 framer 101, and this frame is 16 road STM-4 signals, and every road frequency is 622MHz.By a decommutator 102 is this 16 tunnel conversion of signals 10 road signals, generate 1 tunnel parity signal and 1 tunnel CRC check signal simultaneously, every road signal takies a channel, wherein 10 circuit-switched data signals take 1～10 channel, parity signal takies the 11st channel, and the CRC check signal takies the 12nd channel.10 road signals after the conversion and 1 tunnel parity signal are adjusted sequential by a buffer memory 103, import in the transmission control unit (TCU) 104 with 1 tunnel CRC check signal then.The data of 12 road signals of 104 pairs of inputs of transmission control unit (TCU) are adjusted, and make all transmitting data information and control informations on every path channels, comprise the 11 road and the 12nd path channels, have not transmitted the dedicated channel of parity signal and CRC check signal this moment.This 12 road signal enters a parallel/serial transducer 106 after importing a 8B/10B encoder 105 codings into, is converted to serial signal, by parallel optical transmission module 107 transmission.Receiving unit is that a parallel Optical Receivers 108 receives the signal that parallel optical transmission module 107 transmits, and is converted to parallel signal by a serial/parallel transducer 109, by reception controller 111 of a 8B/10B decoder 110 decoding back inputs.Receive controller 111 12 tunnel mixed signals are reverted to 10 circuit-switched data signals and 1 tunnel parity signal, 1 tunnel CRC check signal.Undertaken importing Jian Cuo ﹠amp after the bit aligned by a buffer queue 112 then; Error-corrector 113 is carried out EDC error detection and correction, is 10 circuit-switched data conversion of signals that 16 road STM-4 signals are passed to an OC-192 framer 114 at last, has finished the process that sends to reception from data.
The present invention has a transmission control unit (TCU) 104 and a reception controller 111.The major function of transmission control unit (TCU) 104 is to be 10 circuit-switched data signals and 1 tunnel parity signal, 1 tunnel CRC check conversion of signals 12 tunnel mixed signals, and receiving controller 111 mainly is that 12 tunnel mixed signals are reverted to 10 circuit-switched data signals and 1 tunnel parity signal, 1 tunnel CRC check signal.
One, the course of work of transmission control unit (TCU) 104 as shown in Figure 2, it need realize that 16 road STM-4 signals reset to the channel of 12 road parallel signals, is implemented as follows:
1,16 to 12 tunnel parallel conversion is finished by SERDES.Be the mode of mapping equally.Every road STM-4 signal sequence is mapped in 1～12 channel successively, first byte of the first via is from channel 1 transmission, first byte of the second tunnel is shone upon into second channel, the 13rd byte of the first via returns channel 1, according to such order, mapping up to entire frame is finished, and carries out the operation of next frame again.
2, go tiltedly to move, frame synchronization and cable symmetrical chiasma measuring ability can have two kinds of implementation methods, the one, the frame first byte is replaced, and realizes in the 8B/10B cataloged procedure.The 2nd, in last figure, the 7th～12 tunnel first frame A1 byte negate obtains the A1 byte, realizes cable symmetrical chiasma measuring ability, the whole negates of the 3rd row A1 byte is obtained the A1 byte, with the achieve frame synchronizing function.
3, the realization of fault monitoring function.Each road of previous " block frame " is carried out after BIP-8 calculates, and 12 BC bytes that obtain are inserted the 18th row of this frame successively, promptly after the first row A2 byte.Receiving terminal to each road of this frame carry out BIP-8 calculate after and the 18th row byte of next frame compare, to find whether error code has appearred in a certain road.Do not carry out error correction, the frame structure that transmission control unit (TCU) 104 sends during error detection as shown in Figure 3.
Through after the above-mentioned processing, this 12 road parallel scheme has been realized frame synchronization and cable symmetrical chiasma measuring ability and channel error monitoring function, but not error correction.Behind the 8B/10B coding, every road speed is 1.0368Gb/s.
4, the realization of error correction, this function is optional.Realize error correction, must add more redundant information, can adopt FEC, but the complexity of realization needs special module to design realization.
(1) generation of error correction as shown in Figure 4: on 1,2 basis, 12960 row of each the STM-64 frame among Fig. 3 are carried out vertical bit XOR, obtained the error correction P of 12960 bytes altogether, laterally insert the last of these frame data in turn.Each STM-64 frame expands to 14040 * 12 bytes like this, wherein is listed as 14040 from 12961 and classifies 1080 * 12 error correction as.
The generation of (2) error detection byte is as shown in Figure 5: each road is that unit is divided into one " dummy data block " with 1080 bytes, successively this data block is carried out the CRC check of CCITT CRC 16 generator polynomials (X16+X12+X5+1), each rood is to the verification redundancy of 26 bytes like this, and wherein the 26th byte is the CRC check to error correction.This 26 byte is carried out the CRC check of CCITT CRC 16 once more, 2 bytes that obtain adding, each road obtains the redundant CRC check byte of 28 bytes altogether like this.A block frame obtains the CRC check of 336 bytes altogether.4～16 (A1) of the next frame first via, 18～32 (A2) byte are inserted in 28 byte verifications of the first via in turn.
Two, receive controller 111 and carry out following work:
1), carries out frame synchronization and the monitoring of cable symmetrical chiasma according to the parallel 3 row bytes of first frame.Receiving controller 111 passes through 12 the bit signals detections of first row of 14040 row of first frame signal totally, normal condition is the 1 the road to the 6 the tunnel to be the A1 byte, the the 7 the road to the 12 the tunnel is the A1 byte, the the 1 the road to the 6 the tunnel is the A1 byte if cable is instead inserted, the the 7 the road to the 12 the tunnel is the A1 byte, can judge the situation that cable connects by this species diversity, realize that the cable symmetrical chiasma detects, avoid cable instead to insert.Receiving controller 111 by first frame the 3rd row A1 that receives is detected, is A1 in conjunction with 6 bytes of the 1st row, and 6 bytes are A1, determine frame head, and achieve frame is synchronous.
2), latter two byte by CRC check carries out verification to the CRC on each road of this frame, if CRC is correct, then changes next step over to, otherwise thinks that mistake appears in CRC, do not carry out the EDC error detection and correction function, directly changes for the 5th step over to.
3), error correction 12961～14040 row on each road of previous frame are carried out CRC check respectively, compare, judge whether error correction mistake occurs, does not have mistake to change next step over to, go on foot otherwise directly change the 5th over to CRC 26 bytes of this frame.
4), all do not have on the wrong basis picking up mistake and error correction, respectively each road of previous frame is carried out carrying out CRC check according to the size of 1080 bytes " dummy data block ", if occur 1 tunnel mistake in 12 the tunnel, then recover by the corresponding error correction in the previous frame.If the above mistake of two-way then changed for the 5th step over to.
5), do not carry out EDC error detection and correction, the beginning data rearrangement recovers 16 road parallel signals.
The very short distance transmission system of the novel 12 tunnel parallel 10Gb/s that the present invention produces has been compared following difference with the very short distance transmission system of the 12 tunnel parallel 10Gb/s of VSR4-1.0:
One, the 12 tunnel all is used for data information, at the check information of the last additional redundancy of block frame.The size of whole block frame is 14040 * 12 bytes, and the size of a block frame of OIF-VSR 4-1.0 is 15552 * 12 bytes, has reduced by 1512 * 12 bytes.
Two, utilized A1 and the A2 byte that repeats in the next frame, carried out the CRC check of this frame, OIF-VSR 4-1.0 then is that additional parallel two-way carries out verification, and is redundant big.After this programme was encoded through 8B/10B, redundancy was 35%.
Three, because error correction is optional, for channel situation preferably, can carry out error correction, then error correction 12961～14040 row can not add, and in this case, do not have additional redundancy.Behind the 8B/10B coding, every road speed is 1.0368Gb/s.Even and OIF-VSR 4-1.0 does not adopt additional two-way, the link rate on each road still is 1.25Gb/s.
Claims (6)
1, a kind of 12 tunnel parallel 10Gb/s very short distance transmission systems is characterized in that, comprising:
An OC-192 framer, generate 16 road STM-4 signals, this frame signal is this 16 tunnel conversion of signals that 10 road signals generate 1 tunnel parity signal and 1 tunnel CRC check signal simultaneously by a decommutator, 10 road signals after the conversion and 1 tunnel parity signal are adjusted sequential by a buffer memory, import into simultaneously in the transmission control unit (TCU) with 1 tunnel CRC check signal then, transmission control unit (TCU) is adjusted the data of 12 road signals of input, make all transmitting data information and control informations on every path channels, do not transmitted the dedicated channel of parity signal and CRC check signal this moment, this 12 road signal enters a parallel/serial transducer after importing a 8B/10B encoder encodes into, be converted to serial signal, by a parallel optical transmission module transmission, signal passes to a parallel Optical Receivers, be received the back and be converted to parallel signal by a serial/parallel transducer, parallel signal passes through to import a reception controller after the 8B/10B decoder for decoding, receive controller 12 tunnel mixed signals are reverted to 10 circuit-switched data signals and 1 tunnel parity signal, 1 tunnel CRC check signal, realize cable symmetrical chiasma measuring ability simultaneously, frame synchronization function, signal is undertaken importing Jian Cuo ﹠amp after the bit aligned by a buffer queue then; Error-corrector is carried out EDC error detection and correction, and being converted to 16 road STM-4 signals through the data-signal behind the EDC error detection and correction, 16 road STM-4 signals are passed to an OC-192 framer at last;
12 tunnel parallel 10Gb/s very short distance transmission systems become 12 road mixed channels that transmit data and error correcting and detecting signal simultaneously, parallel transmission data to 10 circuit-switched data transmission channels, 1 road error-correcting channel and 1 tunnel error detection channel.
According to claim 1 said 12 tunnel parallel 10Gb/s very short distance transmission systems, it is characterized in that 2, wherein this transmission system is 12 tunnel parallel very short distance transmission systems of a kind of VCSEL of employing and 12 road multimode fiber bands.
3, according to claim 1 12 tunnel parallel 10Gb/s very short distance transmission systems, it is characterized in that, wherein the defeated device of transmission control is the controller that 16 road STM-4 signals are reset, it is converted to 12 channel parallel data pieces to a STM-64 frame of being made up of 16 road STM-4 frames, its 12969 row bytes that begin are data and the error correction of STM-64,12961 to be listed as 14040 row bytes be the error detection byte, and error correction is inserted in the 12960 row bytes of beginning.
4, according to claim 1 12 tunnel parallel 10Gb/s very short distance transmission systems, it is characterized in that, wherein receiving controller is that 12 tunnel mixed signals that receive are reverted to 10 circuit-switched data signals and 1 tunnel parity signal, 1 tunnel CRC check signal, the signal that receives a frame of controller reception 14040 is listed as totally, from wherein extracting data-signal, be mapped as 10 road parallel signals, extract parity signal and CRC check signal again, be mapped as 1 road signal respectively, 12 road signal parallels transmission of generation.
5, according to claim 1 12 tunnel parallel 10Gb/s very short distance transmission systems, it is characterized in that, wherein receive controller to 12 the bit signals detections of first row of totally 14040 row of first frame signal, normal condition is the 1 the road to the 6 the tunnel to be the A1 byte, the the 7 the road to the 12 the tunnel is the A1 byte, the the 1 the road to the 6 the tunnel is the A1 byte if cable is instead inserted, the the 7 the road to the 12 the tunnel is the A1 byte, can judge the situation that cable connects by this species diversity, realize that the cable symmetrical chiasma detects, avoid cable instead to insert.
6, according to claim 1 12 tunnel parallel 10Gb/s very short distance transmission systems, it is characterized in that, wherein receive controller by first frame the 3rd row A1 that receives is detected, in conjunction with 6 bytes of the 1st row is A1,6 bytes are the situation of A1, determine frame head, achieve frame is synchronous.
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101523312B (en) * | 2006-08-08 | 2011-08-03 | 西门子工业公司 | Devices, systems, and methods for assigning a plc module address |
| CN103023518A (en) * | 2012-12-26 | 2013-04-03 | 中国科学院微电子研究所 | Cyclic Hamming code correction method based on parallel encoding and decoding- |
| WO2022179407A1 (en) * | 2021-02-26 | 2022-09-01 | 华为技术有限公司 | Data encoding method, data decoding method and related device |
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Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101523312B (en) * | 2006-08-08 | 2011-08-03 | 西门子工业公司 | Devices, systems, and methods for assigning a plc module address |
| CN101501586B (en) * | 2006-08-08 | 2012-06-27 | 西门子工业公司 | Devices, systems, and methods for initializing a plc module |
| CN103023518A (en) * | 2012-12-26 | 2013-04-03 | 中国科学院微电子研究所 | Cyclic Hamming code correction method based on parallel encoding and decoding- |
| CN103023518B (en) * | 2012-12-26 | 2016-04-27 | 中国科学院微电子研究所 | A kind of error correction method of the circulation Hamming code based on parallel encoding decoding |
| WO2022179407A1 (en) * | 2021-02-26 | 2022-09-01 | 华为技术有限公司 | Data encoding method, data decoding method and related device |
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