CN1797900A - Input / output module of inner communication through serial synchronous communication bus - Google Patents
Input / output module of inner communication through serial synchronous communication bus Download PDFInfo
- Publication number
- CN1797900A CN1797900A CN 200410093515 CN200410093515A CN1797900A CN 1797900 A CN1797900 A CN 1797900A CN 200410093515 CN200410093515 CN 200410093515 CN 200410093515 A CN200410093515 A CN 200410093515A CN 1797900 A CN1797900 A CN 1797900A
- Authority
- CN
- China
- Prior art keywords
- circuit
- data
- serial
- bus
- microprocessor
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Images
Abstract
Being setup inside terminal of power load management system, the input / output module includes serial synchronous communication bus, serial main board connected to the bus, remote controlled sub boards, and remote communication pulse sub boards. XCK ends and XDA ends of the serial main board, remote controlled sub boards and remote communication pulse sub boards are connected to clock line XCK, data line XDA of the bus in parallel respectively. Connecting to each sub board, serial main board transfers message data in bothway. The serial main board connected to CAN interface carries out transmission of data and commands with main control boards in terminals. Connecting to external trip devices, each remote controlled sub board controls operation of trip. Connecting to external measuring units, each remote communication pulse sub board collects pulsed quantity/ quantity of state. Features are: easy of expanding new function, adding number of input/output and debugging etc.
Description
Technical field
The present invention relates to a kind of input/output module that is used for the electric power load monitoring and control management system of electrical network, relate in particular to a kind of input/output module that is arranged on the usefulness inner communication through serial synchronous communication bus that is used to control outside trip device and read external pulse amount/quantity of state in the terminal of electric power load monitoring and control management system.
Background technology
See also shown in Figure 1, at present, the prior art input/output module circuit that is provided with in the terminal of power load management system is made up of chip microprocessor MCU, watchdog circuit A1, oscillating circuit A2, communication serial port A3, tri-state gate circuit A4, latch A5, tri-state gate circuit A6, photoelectric isolating circuit A7, photoelectric isolating circuit A8, insulating power supply A9 and power circuit A10; Microprocessor MCU is connected with watchdog circuit A1 with reset line RES by control line WDI; Microprocessor MCU is connected with oscillating circuit A2 with OSC2 by clock cable OSC1; Microprocessor MCU is connected with communication serial port A3 with control line by data/address bus, and communication serial port A3 is connected with master control borad W1 in the terminal; Microprocessor MCU is connected with tri-state gate circuit A4 by data/address bus AD7-0, reading signal lines RD and chip selection signal line CS1; Microprocessor MCU is connected by data/address bus AD7-0, write signal line WR and chip selection signal line CS2 and latch A5's; Tri-state gate circuit A4 is connected with photoelectric isolating circuit A7 by lead with latch A5; Photoelectric isolating circuit A7 is connected with outside trip device W2 by lead, and microprocessor MCU is connected with tri-state gate circuit A6 by data/address bus AD7-0 and chip selection signal line CS3; Tri-state gate circuit A6 is connected with photoelectric isolating circuit A8, and photoelectric isolating circuit A8 is connected with external measurement devices W3 by lead, and insulating power supply A9 is connected with photoelectric isolating circuit A8 with photoelectric isolating circuit A7 respectively.Power circuit A10 is connected with each circuit in the module, and power circuit A10 is connected with each circuit by the POWER line, for input/output module provides dc supply.Microprocessor MCU is connected with communication serial port A3 with control line by data/address bus, and communication serial port A3 is connected with master control borad W1 in the terminal.
The prior art input/output module is arranged in the terminal equipment of power load management system, and to be used to gather this be with the external pulse amount/quantity of state data of the input/output module of inner communication through serial synchronous communication bus and control outside trip device.The operation principle of following this input/output module of example explanation is, adopt the microprocessor MCU of the chip microprocessor AT89C52 (also can with other microprocessor) of atmel corp, by the work of all circuit in the microprocessor MCU distribution module as input/output module.
Watchdog circuit A1 in the input/output module regularly produces pulse in program operation process, remove the counter of watchdog circuit A1, makes watchdog circuit A1 not have reset signal RES output; If program is because unexpected situation enters an endless loop, and in official hour, control line WD does not produce pulse, and watchdog circuit A1 will export reset signal RES, microprocessor MCU resets calling program can be re-executed.
Oscillating circuit A2 in the input/output module provides a sinusoidal wave clock signal for microprocessor MCU, and microprocessor MCU is according to the beat work of this clock, and structure is comparatively simple.Microprocessor MCU is by the same sine wave signal of OSC1 line output, and this signal can drive ancillary equipment.
The status data of outside trip device directly leaves the input port CTR4-1 of tri-state gate circuit A4 in by photoelectric isolating circuit A7, and microprocessor MCU can read the status data of outside trip device W2 at any time by data/address bus AD7-0.The process that will read tri-state gate circuit A4 data as microprocessor MCU is: microprocessor MCU exports to tri-state gate circuit A4 chip selection signal CS1, choose tri-state gate circuit A4, microprocessor MCU is to tri-state gate circuit A4 output read signal RD, and tri-state gate circuit A4 gives microprocessor MCU by the status data that data/address bus AD7-0 exports outside trip device W2.
When microprocessor MCU will operate outside trip device W2: at first give latch A5 by microprocessor MCU output CS2 chip selection signal, microprocessor MCU produces by the WR line and writes latch A5 data command, and microprocessor MCU gives latch A5 by data/address bus AD7-0 output tripping operation data then; Microprocessor MCU latched data appears in latch A5 on delivery outlet, this latch data outputs to photoelectric isolating circuit A7 by the YK4-1 line, and latched data remains to next microprocessor MCU always and revises the tripping operation data once more.
Prevent that the high voltage in the outside trip device W2 circuit from might directly enter inside modules by circuit, and be provided with photoelectric isolating circuit A7, thus the reliability of raising system.Photoelectric isolating circuit A7 reads the status data of outside trip device W2 by the WCTR4-1 line, outputs to tri-state gate circuit A4 by the CTR4-1 line.Latch A5 gives photoelectric isolating circuit A7 by YK4-1 line output tripping operation data, and photoelectric isolating circuit A7 passes through the MYK4-1 dateout to outside trip device W2, thereby reaches the control to outside trip device W2.
Outside measurement data is placed directly in input port MC4-1, the YX4-1 of tri-state gate circuit A6 by photoelectric isolating circuit A8, and microprocessor MCU can read pulsed quantity/quantity of state data of external equipment W3 at any time by data/address bus.The data procedures that will read tri-state gate circuit A6 as microprocessor MCU is: microprocessor MCU is to tri-state gate circuit A6 output chip selection signal CS3, choose tri-state gate circuit A6, export to tri-state gate circuit A6 pulsed quantity/state quantity signal MC4-1 and YX4-1 by photoelectric isolating circuit A8.Microprocessor MCU reads pulsed quantity/quantity of state data of tri-state gate circuit A6 by data/address bus AD7-0.
For preventing that the high voltage in the external measurement devices W3 circuit from might directly enter inside modules by circuit, and be provided with photoelectric isolating circuit A8, thereby improve the reliability of system.Photoelectric isolating circuit A8 reads external pulse amount/quantity of state data by PI4-PI1 line and DI4-DI1 line, outputs to tri-state gate circuit A6 by MC4-1 line and YX4-1.Photoelectric isolating circuit A8 is connected with two groups of power supplys: an end that is connected with tri-state gate circuit A6 is to be provided by " POWER " by inside modules power circuit A10, and that end that is connected with external measurement devices W3 is to be provided by insulating power supply A9.
Insulating power supply A9 is specially for photoelectric isolating circuit A7, A8 provide power supply, by the power supply of different mutual isolation is provided, thereby improves the reliability of system.
Communication serial port A3 adopts 485 interface circuits, and 485 interface circuits are communication interfaces that input/output module is connected with master control borad in the terminal.485 interface circuits are connected with microprocessor MCU with the 485C line by TXD line, RXD line, and 485 interface circuits pass through 485A1 line and 485B1 line and are connected with master control borad W1 in the terminal, and the transmitted in both directions differential signal can direct transfer and deliver to 485 communication networks of terminal.
Existing input/output module adopts chip microprocessor MCU by tri-state gate circuit direct read switch amount data or operation external equipment, though simple in structure, the input and output way of module is all fixed, and generally is designed to 4 the road or 8 the tunnel.Input and output way if desired surpasses the design way, and the expansion way is very difficult.Together, wherein part of functions also might only be used in the scene, and does not use other functions, causes function waste among all input/output function complete or collected works of this module.In actual use, the input and output circuit also has various configuration requirement, and the prior art input/output module is not easy to according to on-the-spot needs various input and output circuits be disposed flexibly.
Summary of the invention
The object of the present invention is to provide a kind of input/output module with inner communication through serial synchronous communication bus, this module is easily expanded, on the distant serial synchronous telecommunications bus, can and connect the quantity that increases remote control daughter board or remote signalling pulse daughter board, realize the expansion of input and output circuit on way; Can select different daughter board allocation plans, satisfy on-the-spot various requirement, and maintain easily; Software is easily revised, and can only revise software programming and debugging separately at corresponding daughter board or serial mainboard; Use the distant serial synchronous telecommunications bus communication, can also expand new function.
Technical scheme of the present invention is achieved in that
A kind of input/output module with inner communication through serial synchronous communication bus, this module is arranged in the terminal of power load management system, be characterized in that this module comprises the distant serial synchronous telecommunications bus, is attempted by the serial mainboard on the distant serial synchronous telecommunications bus, some remote control daughter boards and some remote signalling pulse daughter boards; Described distant serial synchronous telecommunications bus comprises a clock lines XCK, another data wire XDA; The XCK of described serial mainboard, some remote control daughter boards, some remote signalling pulse daughter boards end is respectively with the clock line XCK of distant serial synchronous telecommunications bus and connect, and the XDA end of described serial mainboard, some remote control daughter boards, some remote signalling pulse daughter boards is respectively with the data wire XDA of distant serial synchronous telecommunications bus and connect; Described serial mainboard is by distant serial synchronous telecommunications bus and each remote control daughter board and the two-way transmission message data of remote signalling pulse daughter board.
Above-mentioned input/output module with inner communication through serial synchronous communication bus, wherein, described serial mainboard is made up of microprocessor MCU, watchdog circuit, oscillating circuit and CAN interface; Microprocessor MCU is connected with watchdog circuit with reset line RES by control line WDI, and microprocessor MCU is connected with oscillating circuit with OSC2 by clock cable OSC1; Microprocessor MCU is connected with the CAN interface with control line by data wire; The XCK of microprocessor MCU end and XDA end are held with the clock line XCK end of distant serial synchronous telecommunications bus and data wire XDA respectively and are connect; The serial mainboard is connected with the CAN interface, by master control borad bi-directional transfer of data and the control command in CAN interface and the terminal.
Above-mentioned input/output module with inner communication through serial synchronous communication bus, wherein, described remote control daughter board is made up of microprocessor MCU, watchdog circuit, oscillating circuit, tri-state gate circuit, latch, photoelectric isolating circuit and insulating power supply; Microprocessor MCU is connected with watchdog circuit with reset line RES by control line WDI; Microprocessor MCU is connected with oscillating circuit with OSC2 by clock cable OSC1; Microprocessor MCU is connected with tri-state gate circuit by data/address bus AD7-0, reading signal lines RD and chip selection signal line CS1; Microprocessor MCU is connected with latch by data/address bus AD7-0, write signal line WR and chip selection signal line CS2; Tri-state gate circuit is connected with photoelectric isolating circuit respectively by lead with latch; Insulating power supply is connected with photoelectric isolating circuit; The XCK of microprocessor MCU end and XDA end are held with the clock line XCK end of distant serial synchronous telecommunications bus and data wire XDA respectively and are connect; Described each remote control daughter board is connected with corresponding outside trip device with control line by data wire; The serial mainboard reads the status data of outside trip device by each remote control daughter board, and controls the tripping operation action of outside trip device.
Above-mentioned input/output module with inner communication through serial synchronous communication bus, wherein, described remote signalling pulse daughter board is made up of microprocessor MCU, watchdog circuit, oscillating circuit, tri-state gate circuit, photoelectric isolating circuit and insulating power supply; Microprocessor MCU is connected with watchdog circuit with reset line RES by control line WDI; Microprocessor MCU is connected with oscillating circuit with OSC2 by clock cable OSC1; Microprocessor MCU is connected with tri-state gate circuit by data/address bus AD7-0 and chip selection signal line CS1; Tri-state gate circuit is connected with photoelectric isolating circuit by lead; Insulating power supply is connected with photoelectric isolating circuit; The XCK of microprocessor MCU end and XDA end are held with the clock line XCK end of distant serial synchronous telecommunications bus and data wire XDA respectively and are connect; Described each remote signalling pulse daughter board is connected with corresponding external measurement devices with control line by data wire; The serial mainboard reads the pulsed quantity/quantity of state data of external measurement devices by each remote signalling pulse daughter board.
The above-mentioned input/output module with inner communication through serial synchronous communication bus, wherein, described photoelectric isolating circuit is made up of some groups of identical photoelectricity isolated location circuit.
The present invention, makes it compared with prior art owing to adopted above-mentioned technical scheme with the input/output module of inner communication through serial synchronous communication bus, has following advantage and good effect:
1. the present invention is owing to adopt the distant serial synchronous telecommunications bus, and expansion only needs to increase the quantity of remote control daughter board or remote signalling pulse daughter board easily, just can realize the expansion of input and output circuit on way easily.
2. the present invention is owing to can and connect several remote control daughter boards or remote signalling pulse daughter board on the distant serial synchronous telecommunications bus, and configuration is convenient, can select different daughter board allocation plans according to the needs at scene, to satisfy on-the-spot various requirement.
3. easy maintenance of the present invention when breaking down, needn't be changed a whole set of input/output module, only needs out of order daughter board or serial mainboard are changed separately.
4. the present invention can only revise separately at corresponding daughter board or serial mainboard when needs carry out the technical scheme modification.
5. the present invention constitutes microprocessor MCU system owing to be equipped with microprocessor MCU in serial mainboard and each daughter board, is convenient to software programming and debugging.
6. the present invention has the new function of expansion, and the serial mainboard is by the distant serial synchronous telecommunications bus communication, and the I/O mouth that takies in the time of can saving parallel communications utilizes the I/O mouth of saving, and can expand new function easily.
Description of drawings
By following to the present invention with an embodiment of the input/output module of inner communication through serial synchronous communication bus description in conjunction with its accompanying drawing, can further understand purpose of the present invention, specific structural features and advantage.Wherein, accompanying drawing is:
Fig. 1 is the input/output module circuit block diagram of prior art.
Fig. 2 is the present invention with in the input/output module of inner communication through serial synchronous communication bus and connect the circuit block diagram of some daughter boards.
Fig. 3 is the input/output module circuit block diagram of the present invention with inner communication through serial synchronous communication bus.
Fig. 4 is the serial mainboard workflow block diagram of the present invention with the input/output module of inner communication through serial synchronous communication bus.
Fig. 5 is the remote control daughter board workflow block diagram of the present invention with the input/output module of inner communication through serial synchronous communication bus.
Fig. 6 is the remote signalling pulse daughter board workflow block diagram of the present invention with the input/output module of inner communication through serial synchronous communication bus.
Fig. 7 is the circuit theory diagrams of the present invention with the serial mainboard of the input/output module of inner communication through serial synchronous communication bus.
Fig. 8 is the circuit theory diagrams of the present invention with the remote control daughter board of the input/output module of inner communication through serial synchronous communication bus.
Fig. 9 is the circuit theory diagrams of the present invention with the remote signalling pulse daughter board of the input/output module of inner communication through serial synchronous communication bus.
Figure 10 is the input/output module distant serial synchronous telecommunications bus communication sequential chart of the present invention with inner communication through serial synchronous communication bus.
Figure 11 is the main frame distant serial synchronous telecommunications bus communication software flow pattern of the present invention with the input/output module of inner communication through serial synchronous communication bus.
Figure 12 is the input/output module slave distant serial synchronous telecommunications bus communication software flow pattern of the present invention with inner communication through serial synchronous communication bus.
Embodiment
See also shown in Figure 2, input/output module with inner communication through serial synchronous communication bus, this module is arranged in the terminal of power load management system, and this module comprises serial mainboard 10, some remote control daughter boards 20, some remote signalling pulse daughter boards 30, distant serial synchronous telecommunications bus 40 (also can abbreviate serial XT2 bus as).
Distant serial synchronous telecommunications bus 40 comprises a clock lines XCK41, another data wire XDA42.The XCK of serial mainboard 10, some remote control daughter boards 20, some remote signalling pulse daughter boards 30 end is respectively with the clock line XCK41 of distant serial synchronous telecommunications bus 40 and connect, and the XDA end of serial mainboard 10, some remote control daughter boards 20, some remote signalling pulse daughter boards 30 is respectively with the data wire XDA42 of distant serial synchronous telecommunications bus 40 and connect; Serial mainboard 10 sends address dates by distant serial synchronous telecommunications bus 40 to each remote control daughter board 20 and remote signalling pulse daughter board 30, and with each remote control daughter board 20 and remote signalling pulse daughter board 30 two-way transmission message datas.
Please cooperate referring to shown in Figure 3, input/output module with inner communication through serial synchronous communication bus, this module is arranged in the power load management system terminal, and this module comprises serial mainboard 10, some remote control daughter boards 20, some remote signalling pulse daughter boards 30, distant serial synchronous telecommunications bus 40.Connect the power circuit 50 of serial mainboard 10 and each remote control daughter board 20 and remote signalling pulse daughter board 30 and be connected remote control daughter board 20 and the insulating power supply 60 of remote signalling pulse daughter board 30.
Remote control daughter board 20 is made up of microprocessor MCU21, watchdog circuit 22, oscillating circuit 23, tri-state gate circuit 24, latch 25 and photoelectric isolating circuit 26; Microprocessor MCU21 is connected with watchdog circuit 22 with reset line RES by control line WDI; Microprocessor MCU21 is connected with oscillating circuit 23 with OSC2 by clock cable OSC1; Microprocessor MCU11 is connected with tri-state gate circuit 24 inputs by data/address bus AD7-0, reading signal lines RD and chip selection signal line CS1; Microprocessor MCU21 is connected with the input of latch 25 by data/address bus AD7-0, write signal line WR and chip selection signal line CS2; Tri-state gate circuit 24 is by the CTR4-1 line, and latch 25 is connected with photoelectric isolating circuit 26 respectively by the YK4-1 line; Insulating power supply 60 is connected with photoelectric isolating circuit 26; The XCK of microprocessor MCU21 end and XDA end are held with the XDA of the XCK end of the clock line 41 of distant serial synchronous telecommunications bus 40 and data wire 42 respectively and are connect.Photoelectric isolating circuit 26 is connected with outside trip device W2 by lead.Remote control daughter board 20 is connected with corresponding outside trip device 80 with control line by data wire; Serial mainboard 10 reads the status data of outside trip device 70 by each remote control daughter board 20, and controls the tripping operation action of outside trip device 70.
Remote signalling pulse daughter board 30 is made up of microprocessor MCU31, watchdog circuit 32, oscillating circuit 33 tri-state gate circuits 34 and photoelectric isolating circuit 35; Microprocessor MCU31 is connected with watchdog circuit 32 with reset line RES by control line WDI; Microprocessor MCU31 is connected with oscillating circuit 33 with OSC2 by clock cable OSC1; Microprocessor MCU31 is connected with tri-state gate circuit 34 by data/address bus AD7-0 and chip selection signal line CS1; Tri-state gate circuit 34 is connected with photoelectric isolating circuit 35 by lead; Insulating power supply 60 is connected with photoelectric isolating circuit 35; The XCK of microprocessor MCU31 end and XDA end are held with the XDA of the XCK end of the clock line 41 of distant serial synchronous telecommunications bus 40 and data wire 42 respectively and are connect.Photoelectric isolating circuit 35 is connected with external measurement devices W3 by lead.Remote signalling pulse daughter board 30 is connected with corresponding external measurement devices 90 by data wire; Serial mainboard 10 reads the pulsed quantity/quantity of state data of external measurement devices 90 by each remote signalling pulse daughter board 30.
Circuit theory of the present invention is, all is provided with microprocessor MCU in serial mainboard 10, remote control daughter board 20 and the remote signalling pulse daughter board 30, and microprocessor MCU can adopt 8,16,32 chip microprocessor of any company.With software two I/O mouths of microprocessor MCU are modeled as the distant serial synchronous telecommunications interface.
Microprocessor MCU on serial mainboard 10, remote control daughter board 20, remote signalling pulse daughter board 30 connects a watchdog circuit separately.In order to prevent program unexpected interruption in running, and increased watchdog circuit, the interface of watchdog circuit and microprocessor MCU is made up of a control line WDI and a reset line RES, control line WDI is the I/O line traffic control of microprocessor MCU, control line regularly produces pulse in program operation process, remove the counter of watchdog circuit, make watchdog circuit not have reset signal RES output; If program is because unexpected fault enters an endless loop, and in the time of setting, control line WD does not produce pulse, and watchdog circuit will be exported reset signal RES, microprocessor MCU resets, and calling program can be re-executed.
Microprocessor MCU on serial mainboard 10, remote control daughter board 20 and the remote signalling pulse daughter board 30 connects an oscillating circuit separately.Oscillating circuit provides microprocessor MCU a clock signal, and microprocessor MCU is according to the beat work of this clock, and structure is comparatively simple.Oscillating circuit gives microprocessor MCU input a sine wave signal by the OSC2 line, and microprocessor MCU exports same sine wave signal by the OSC1 line, and this signal can drive ancillary equipment.
The status data of outside trip device 80 directly leaves the input port CTR4-1 of tri-state gate circuit 24 in by photoelectric isolating circuit 26, and microprocessor MCU21 can read the status data of outside trip device 80 at any time by data/address bus.The process that microprocessor MCU21 will read tri-state gate circuit 24 data is: microprocessor MCU21 at first chooses tri-state gate circuit 24, by microprocessor MCU21 chip selection signal CS1 is exported to tri-state gate circuit 24; By the order of microprocessor MCU21 issue read data, microprocessor MCU21 gives tri-state gate circuit 24 reading of data by output read signal RD again; Microprocessor MCU21 reads the status data of the outside trip device 80 of tri-state gate circuit 24 storages by data/address bus AD7-0.
When microprocessor MCU21 will operate outside trip device 80, at first to give latch 25 by microprocessor MCU21 output chip selection signal CS2, microprocessor MCU21 produces by the WR line and writes the latch data instruction, and microprocessor MCU21 gives latch 25 by data wire AD7-0 output tripping operation data then; Microprocessor MCU21 latched data appears in latch 25 on delivery outlet, this latch data outputs to photoelectric isolating circuit 26 by the YK4-1 line, and the data of latch 25 remain to next microprocessor MCU21 always and revise the tripping operation data once more.
For the high voltage that prevents outside trip device 80 circuit might directly enter inside modules by circuit, and be provided with photoelectric isolating circuit 26, thereby improve the reliability of system.
Photoelectric isolating circuit 26 reads the status data of outside trip device 80 by the MCTR4-1 line, outputs to tri-state gate circuit by the CTR4-1 line.Latch 25 is given photoelectric isolating circuit 26 by YK4-1 line output tripping operation data, and photoelectric isolating circuit 26 passes through MYK4-1 line dateout to outside trip device, thereby reaches the control to outside trip device 80.Photoelectric isolating circuit 26 is connected with two groups of power supplys, and one group is to be provided by " POWER " by inside modules power circuit 50, and another group insulating power supply 60 provides.
Outside pulsed quantity/quantity of state data directly leave input port MC4-1, the YX4-1 of tri-state gate circuit 34 in by photoelectric isolating circuit 35, and microprocessor MCU31 can read external measurement devices pulsed quantity/quantity of state data by data/address bus AD7-0 at any time.To read the data of tri-state gate circuit 34 as microprocessor MCU31, microprocessor MCU output chip selection signal CS1 give tri-state gate circuit 34, choose tri-state gate circuit 34 earlier, read pulsed quantity/state quantity signal MC4-1 and the YX4-1 that exports to tri-state gate circuit 34 by photoelectric isolating circuit 35 by microprocessor MCU31 again.
For the high voltage that prevents external measurement devices 90 might directly enter inside modules by circuit, and be provided with photoelectric isolating circuit 35, thereby improve the reliability of system.Photoelectric isolating circuit 35 reads external pulse amount/quantity of state data by PI4-PI1 line and DI4-DI1 line, outputs to tri-state gate circuit 34 by MC4-1 line and YX4-1 line.Photoelectric isolating circuit 35 is connected with two groups of power supplys respectively: one group is to be provided by the POWER line by inside modules power circuit 50, and another group is provided by insulating power supply 60.
Insulating power supply 60 is specially for photoelectric isolating circuit 35 provides power supply, improves the reliability of system by the power supply that different mutual isolation is provided.
Microprocessor MCU11 adopts CAN interface 14, and this CAN interface is made up of CAN controller model (model is SJA1000) and CAN transceiver (model is P82C250), and microprocessor MCU11 is by the master control borad bi-directional transfer of data in CAN interface and the terminal.
Microprocessor MCU11 and CAN interface 14 are by data/address bus AD7-0 bi-directional transfer of data; Microprocessor MCU11 output chip selection signal CS is to the CAN interface; Microprocessor MCU11 output reads to allow signal RD to CAN interface 14; Microprocessor MCU11 output written allowance signal WR is to CAN interface 14; CANRST is to CAN interface 14 for microprocessor MCU11 output reset signal; Finish when sending or receive message, the terminal signaling INT that 14 outputs of CAN interface send or the reception message is finished is to microprocessor MCU11.
See also shown in Figure 4,
The present invention is that serial mainboard 10 begins " initialization " program with the input/output module workflow of inner communication through serial synchronous communication bus after the terminal opening power; After initialization was finished, serial mainboard 10 was checked the communications reception message flag position of CAN interface 14; If received message, carry out CAN communications reception message and handle, enter next step again, if 14 communications of CAN interface do not receive message, directly enter next step; Detection will send CAN interface 14 communication message flag bits, sends message if desired, can directly send message, enters next step when sending message.If there are not CAN interface 14 communication messages to send, then check distant serial synchronous telecommunications bus communication message flag position, if prepared communication, carrying out distant serial synchronous telecommunications bus communication message handles, enter next step again,, directly enter next step if do not prepare communication; Turn back to " checking CAN communications reception message flag position "; Restart to take turns new circulation.
See also shown in Figure 5,
Remote control daughter board 20 begins " initialization " program after the terminal opening power; After initialization was finished, the remote control daughter board detected on the distant serial synchronous telecommunications bus whether the initial conditions of distant serial synchronous telecommunications are arranged, if initial conditions are arranged, just carried out " XT2 receives and dispatches handling procedure ", carried out message and handled, if there are not initial conditions, carried out next step; Inquiry having tripping operation action flag bit, if the tripping operation action is arranged then the handling procedure that trips enters next step after finishing, if the action request that do not trip directly enters next step; Turn back to " whether initial conditions are arranged "; Restart to take turns new circulation.
See also shown in Figure 6,
Remote signalling pulse daughter board 30 begins " initialization " program after the terminal opening power; After initialization is finished, remote signalling pulse daughter board 30 detects the initial conditions whether distant serial synchronous telecommunications is arranged on the distant serial synchronous telecommunications bus, if initial conditions are arranged, just carry out " XT2 receives and dispatches handling procedure ", receive the distant serial synchronous telecommunications message, send data to serial mainboard 10,, carry out next step if there are not initial conditions; Carry out " reading pulsed quantity/quantity of state data ", upgrade the data field; Turn back to " whether initial conditions are arranged "; Restart to take turns new circulation.
See also Fig. 7, Fig. 8, shown in Figure 9,
2 I/O mouth 21P, the 22P of microprocessor MCU on serial mainboard and each daughter board are used for doing the distant serial synchronous telecommunications bus interface, and connect together with the distant serial synchronous telecommunications interface, communicate with master-slave mode.Working power in the input/output module is provided by " VCC " and " GND " line by power circuit 50.
Please cooperate referring to shown in Figure 7,
Serial mainboard 10 comprises microprocessor MCU11 (model is 89C52), be watchdog circuit (MAX706) 12, oscillating circuit 13, the CAN interface 14 that connects and composes by controller 141 (model is SJA1000) and transceiver 142 (model is P82C250).The 6P of microprocessor MCU11 (WDI) is connected with the 6P (WDI) of watchdog circuit 12, and the 7P of watchdog circuit 12 (RESET) is connected with the 9P (RESET) of microprocessor MCU11.Microprocessor MCU11 regularly produces pulse signal by control line WDI in program running, interrupt in program running, and watchdog circuit 12 output reset signals re-execute calling program to the 9P (RESET) of microprocessor MCU11.The 18P of microprocessor MCU11 is connected one and connects the oscillating circuit 13 that capacitor C 1 and C2 form respectively by crystal oscillator G1 two ends with 19P, oscillating circuit 13 is by sine wave signal of 19P " X1 " input of microprocessor MCU11, microprocessor MCU11 is by the same signal of 18P " X2 " output, and this signal can drive ancillary equipment.The corresponding connection of P23 to P28, P1, P2 of the P39 to P32 of microprocessor MCU11 and the controller 141 of CAN interface 14 is by data/address bus AD7-0 bi-directional transfer of data; The P5 of microprocessor MCU11 is connected with the P4 of controller 141, and microprocessor MCU11 output chip selection signal CS is to controller 141; The P17 of microprocessor MCU11 is connected with the P5 of controller 141, and microprocessor MCU11 output reads to allow signal RD to controller 141; The P16 of microprocessor MCU11 is connected with the P6 of controller 141, and microprocessor MCU11 output written allowance signal WR is to controller 141; The P7 of microprocessor MCU11 is connected with the P17 of controller 141, and CANRST is to controller 141 for microprocessor MCU11 output reset signal; The P13 of microprocessor MCU11 is connected with the P16 of controller 141, finishes when sending or receive message, and the terminal signaling INT that controller 141 outputs send or the reception message is finished of CAN interface 14 is to microprocessor MCU11.The P13 of controller 141, P19 are connected with P1, the P4 of transceiver 142 respectively, bi-directional transfer of data, and the P6 of transceiver 142, P7 are connected with CAN bus in the terminal, transmit CANL, CANH differential signal.
See also shown in Figure 8,
Remote control daughter board 20 comprises microprocessor MCU21 (model is 89C52), watchdog circuit 22 (model is MAX706), oscillating circuit 23, tri-state gate circuit 24 (model is 74HC573), latch circuit 25 (model is 74HC377), photoelectric isolating circuit 26, and this photoelectric isolating circuit 26 is made up of eight groups of identical photoelectricity isolated location circuit 261,262,263,264,265,266,267,278.This photoelectricity isolated location circuit is by photoelectrical coupler and be connected a resistance at the 1P of photoisolator respectively with 4P and constitute.(model of photoisolator is TLP181).
The 6P of microprocessor MCU21 (WDI) is connected with the 6P (WDI) of watchdog circuit 22, and the 7P of watchdog circuit 22 (RESET) is connected with the 9P (RESET) of microprocessor MCU21.Microprocessor MCU21 regularly produces pulse signal by control line WDI in program running, interrupt in program running, and watchdog circuit 22 output reset signals re-execute calling program to the 9P (RESET) of microprocessor MCU21.The 18P of microprocessor MCU21 is connected one and connects the oscillating circuit 23 that capacitor C 11 and C12 form respectively by crystal oscillator G11 two ends with 19P, oscillating circuit 23 is by sine wave signal of 19P " X1 " input of microprocessor MCU21, microprocessor MCU21 is by the same signal of 18P " X2 " output, and this signal can drive ancillary equipment.
The outside trip device state quantity signal that remote control daughter board 20 collects can not directly link to each other (if directly hang over pulse/state quantity signal on the data/address bus with the data/address bus of microprocessor MCU22, may hang the data/address bus of microprocessor MCU22), therefore, when design circuit, increased tri-state gate circuit 24.The 19P-16P of tri-state gate circuit 24 is by the 39P-36P corresponding connection of data/address bus AD3-0 with microprocessor MCU21; The 4P of microprocessor MCU21 (CS1) is connected with the 1P (CS1) of tri-state gate circuit 24, by the chip selection signal CS1 of microprocessor MCU21 to tri-state gate circuit 24 inputs; The 17P of microprocessor MCU21 (RD) is connected with the 11P (RD) of tri-state gate circuit 24, by the read control signal of microprocessor MCU21 to tri-state gate circuit 24 inputs.The 2P of tri-state gate circuit 24 (CTR1), 3P (CTR2), 4P (CTR2), 5P (CTR4) respectively with the 4P (CTR1) of photoelectricity isolated location circuit 265,266 4P (CTR2), 267 4P (CTR3), 268 the corresponding connection of 4P (CTR4).By photoelectric isolating circuit 26 to tri-state gate circuit 24) input outside trip device status signal.
The control signal that remote control daughter board 20 outputs to outside trip device can not directly link to each other with the data/address bus of microprocessor MCU, has increased latch 25 when design circuit.The corresponding connection of 39P to 36P of the 3P of latch 25,4P, 7P, 8P and microprocessor MCU21, microprocessor MCU21 by data/address bus AD3-0 to latch 25 transmission data; The 1P (YK1) of the 2P of latch 25 (YK1), 5P (YK2), 6P (YK3), 9P (YK4) and photoelectricity isolated location circuit 261,262 1P (YK2), 263 1P (YK3), 264 the corresponding connection of 1P (YK4) are by the tripping operation control signal of microprocessor MCU21 by the outside trip device of latch 25 outputs.The 1P of latch 25 (CS2) is connected with the 3P (CS2) of microprocessor MCU21, by the chip selection signal CS2 of microprocessor MCU21 to latch 25 inputs.The 11P of latch 25 (WR) is connected with the 16P (WR) of microprocessor MCU21, allows control signal WR by microprocessor MCU21 to writing of latch 25 inputs.
Outside trip device may comprise high-tension composition, and signal can not be introduced directly into the logical circuit in the remote control daughter board, designs photoelectric isolating circuit for the reliability that improves system.
Photoelectric isolating circuit 26 is made up of eight groups of identical photoelectricity isolated location circuit 261,262,263,264,255,266,267,268; This photoelectricity isolated location circuit is by photoisolator and be connected a resistance at the 1P of photoisolator respectively with 4P and constitute.Wherein four groups of photoelectricity isolated location circuit 261,262,263,264 are serially connected in respectively between the control end of the output of latch 25 control signals and outside trip device 80, microprocessor 21 transmits control signal by latch 25 and photoelectricity isolated location circuit 261,262,263,264, controls the action of outside trip device; Other four groups of photoelectricity isolated location circuit 265,266,267,268 are serially connected in respectively between the state output end of the data input pin of tri-state gate circuit 24 and outside trip device 80; Microprocessor 21 reads the status data of outside trip device 80 by tri-state gate circuit 24, photoelectric isolating circuit 26.
The 4P of the photoisolator of photoelectricity isolated location circuit 261 is connected by the control end of lead with outside trip device 80, and 261 output control signal MYK1 give outside trip device 80 by photoelectricity isolated location circuit; The 4P of the photoisolator of photoelectricity isolated location circuit 262 is connected by the control end of lead with outside trip device 80, and 262 output control signal MYK2 give outside trip device 80 by photoelectricity isolated location circuit; The 4P of the photoisolator of photoelectricity isolated location circuit 263 is connected by the control end of lead with outside trip device 80, and 263 output control signal MYK3 give outside trip device 80 by photoelectricity isolated location circuit; The 4P of the photoisolator of photoelectricity isolated location circuit 264 is connected by the control end of lead with outside trip device 80, and 264 output control signal MYK4 give outside trip device 80 by photoelectricity isolated location circuit.
The 1P of the photoisolator of photoelectricity isolated location circuit 265 is connected with the status signal end of outside trip device 80 by lead, gives photoelectricity isolated location circuit 265 by outside trip device 80 output tripped condition MCTR1 signals; The 1P of the photoisolator of photoelectricity isolated location circuit 266 is connected with the status signal end of outside trip device 80 by lead, gives photoelectricity isolated location circuit 266 by outside trip device 80 output tripped condition signal MCTR2; The 1P of the photoisolator of photoelectricity isolated location circuit 267 is connected with the status signal end of outside trip device 80 by lead, gives photoelectricity isolated location circuit 267 by outside trip device 80 output tripped condition signal MCTR3; The 1P of the photoisolator of photoelectricity isolated location circuit 268 is connected with the status signal end of outside trip device 80 by lead, gives photoelectricity isolated location circuit 288 by outside trip device 80 output tripped condition signal MCTR4.
Be provided with two groups of power supplys in the photoelectric isolating circuit 26, provide by insulating power supply 60 at the power supply of photoelectric isolating circuit 26 inputs; Provide by " VCC " and " GND " at the output end power of photoelectric isolating circuit 26 power circuit 50 by inside modules.
See also shown in Figure 9,
The sub-piece 30 of pulse remote signalling comprises microprocessor MCU31 (model is 89C52) watchdog circuit 32 (model is MAX706), oscillating circuit 33, tri-state gate circuit 34 (model is 74HC573); Photoelectric isolating circuit 35 is made up of eight groups of identical photoelectricity isolated location circuit 351 to 358.This photoelectricity isolated location circuit is by photoisolator and be connected a resistance at the 1P of photoisolator respectively with 4P and constitute.(model of photoisolator is TLP181).
The 6P of microprocessor MCU31 (WDI) is connected with the 6P (WDI) of watchdog circuit 32, and the 7P of watchdog circuit 32 (RESET) is connected with the 9P (RESET) of microprocessor MCU31.Microprocessor MCU31 regularly produces pulse signal by control line WDI in program running, interrupt in program running, and watchdog circuit 32 output reset signals re-execute calling program to the 9P (RESET) of microprocessor MCU31.The 18P of microprocessor MCU31 is connected one and connects the oscillating circuit 33 that capacitor C 31 and C32 form respectively by crystal oscillator G31 two ends with 19P, oscillating circuit 33 is by sine wave signal of 19P " X1 " input of microprocessor MCU31, microprocessor MCU31 is by the same signal of 18P " X2 " output, and this signal can drive ancillary equipment.
Pulse/state quantity signal that remote signalling pulse daughter board 30 collects can not directly link to each other (if directly hang over the switching value signal on the data/address bus with the data/address bus of microprocessor MCU31, may hang the data/address bus of MCU), when design circuit, increased tri-state gate circuit 34.The 19P-16P of tri-state gate circuit 34 is by the 39P-36P corresponding connection of data/address bus AD3-0 with microprocessor MCU31; The 4P of microprocessor MCU31 (CS1) is connected with the 1P (CS1) of tri-state gate circuit 34, and this line is the control line that microprocessor MCU31 reads tri-state gate circuit 34 data, by the chip selection signal CS1 of microprocessor MCU31 to tri-state gate circuit 34 inputs.The 2P of tri-state gate circuit 34 (MC1), 3P (MC2), 4P (MC3), 5P (MC4) respectively with the 4P (MC1) of photoelectricity isolated location circuit 351,352 4P (MC2), 353 4P (MC3), 354 the corresponding connection of 4P (MC4), by photoelectric isolating circuit 35 to tri-state gate circuit 34 input pulse amount signals.The 4P (YX1) of the 6P of tri-state gate circuit 34 (YX1), 7P (YX2), 8P (YX3), 9P (YX4) and photoelectricity isolated location circuit 355,356 4P (YX2), 357 4P (YX3), 358 the corresponding connection of 4P (YX4), by photoelectric isolating circuit 35 to tri-state gate circuit 34 input state amount signals.
External measurement devices 90 may comprise high-tension composition, and signal can not be introduced directly into the logical circuit in the remote signalling pulse daughter board 30, designs photoelectric isolating circuit for the reliability that improves system.The first via that 351 P1 of photoelectric isolating circuit 35 and P2 connect external measurement devices 90 (PI1+, PI1-); PI1+ and PI1-are the pulsed quantity signals that external measurement devices is input to photoelectricity isolated location circuit 351; The P1 of photoelectricity isolated location circuit 352 and P2 connect external measurement devices 90 the second the tunnel (PI2+, PI2-); PI2+ and PI2-are the pulsed quantity signals that external measurement devices is input to photoelectricity isolated location circuit 352; The P1 of photoelectricity isolated location circuit 353 and P2 connect external measurement devices 90 Third Road (PI3+, PI3-); PI3+ and PI3-are the pulsed quantity signals that external measurement devices is input to photoelectricity isolated location circuit 353; The P 1 of photoelectricity isolated location circuit 354 and P2 connect external measurement devices 90 the four the tunnel (PI4+, PI4-); PI4+ and PI4-are the pulsed quantity signals that external measurement devices 90 is input to photoelectricity isolated location circuit 354; The P1 of photoelectricity isolated location circuit 355 meets the five tunnel (DI1+) of external measurement devices 90; DI1+ is the state quantity signal that external measurement devices 90 is input to photoelectricity isolated location circuit 355; The P1 of photoelectricity isolated location circuit 356 meets the six tunnel (DI2+) of external measurement devices; DI2+ is the state quantity signal that external measurement devices 90 is input to photoelectricity isolated location circuit 356; 357 P1 of photoelectricity isolated location circuit meets the seven tunnel (DI3+) of external measurement devices 90; DI3+ is the state quantity signal that external measurement devices 90 is input to photoelectricity isolated location circuit 357; The P8 of photoelectricity isolated location circuit 358 meets the eight tunnel (DI4+) of external measurement devices 90; DI4+ is the state quantity signal that external measurement devices 90 is input to photoelectricity isolated location circuit 358.
The power supply of photoelectric isolating circuit 35, is provided by insulating power supply 60 at the power supply of photoelectric isolating circuit 35 inputs by two groups; At the output end power of photoelectric isolating circuit 35, provide by " VCC " and " GND " by the power circuit 50 of inside modules.
Distant serial synchronous telecommunications bus 40 is two wire serial bus, and this bus 40 is made up of clock line XCK and data wire XDA, communicates with master-slave mode, has only by main frame and calls together when surveying, and slave just sends to main frame.In input/output module, as main frame, remote control daughter board 20, pulse remote signalling daughter board 30 are as slave serial mainboard 10.Clock line XCK41 is used for main frame tranmitting data register signal, and data wire XDA42 is used for data signal.High level is a logical one, and low level is a logical zero.The bus idle hour is a high level according to line XDA42, and clock line XCK41 is a high level.When communication, main frame is put low level to data wire XDA42 earlier, produces initial conditions, and slave receives initial conditions, produces and interrupts, and enters CIP, begins to receive the message that main frame sends.
The hardwood form of distant serial synchronous telecommunications bus comprises with the lower part: initial conditions, slave addresses, R/W position, parity check bit, ACK position, order and data, stop condition.
When XCK was high level, XDA was by high step-down, and expression has produced initial conditions, and main frame is ready for sending.When XCK was high level, XDA was uprised by low, and expression has produced a stop condition, and main frame finishes to send.Except under initial or stop condition, XDA should keep stable at XCK during for high level, only should change during for low level at XCK.
Each XCK cycle comprises interval and 1 the high level interval of 1 low level.The low level interval in 9 XCK cycles after initial conditions, main frame write 9 bit data successively on XDA, this 9 bit data comprises 7 bit address and R/W position+parity check bit.
Daughter board address: 7 bit address.
The R/W position: 1 expression main frame will be from from machine-readable data, and 0 expression main frame will be to the slave write data.
Parity check bit: to 8 additions before the parity check bit and lowest order be the value of parity check bit.
If slave sends data to main frame, write the ACK position by main frame.After main frame is received data, write 1, produce stop condition then in the ACK position.
Main frame is order to what slave was sent out, slave to main frame send out for data.
After the address met, slave was according to the R/W position, and decision takes orders or the transmission data.
Order and data can be byte, also can be multibytes.
The byte form:
Main frame is to the slave write order
Main frame is from from machine-readable data.
Main frame sends to slave
Slave sends to main frame
S: initial conditions P: stop condition
R/W: read-write is selected, and writes in=0 o'clock, reads in=1 o'clock
The A:ACK position, response=0
/ A:ACK position, response=1
N: parity check bit, to 8 bit data additions before the parity check bit.
The multibyte form: if M byte command or data are arranged,
The form of order and data is that (8 bit data+1 bit parity check position+ACK position) repeat M time.
Main frame is from from machine-readable data.
Main frame sends to slave
Slave sends to main frame
S: initial conditions P: stop condition
R/W: read-write is selected, and writes in=0 o'clock, reads in=1 o'clock
The A:ACK position, response=0
/ A:ACK position, response=1
N: parity check bit, to 8 bit data additions before the parity check bit.
Seeing also shown in Figure 10ly, is the communication sequential chart of distant serial synchronous telecommunications bus.
When XCK=1, main frame jumps to 0 with XDA by 1, produces initial conditions, and slave detects initial conditions, begin to accept message, main frame begins to export a string XCK pulse, and the corresponding one digit number certificate of each pulse is in the low level interval of XCK, main frame writes data to the XDA bus, in the high level interval of back to back XCK, slave reads the data on the XDA, like this data of main frame is sent to slave.
8 bit data after the initial conditions are that 7 bit address add the R/W position, R/W=1, and next expression is the data that main frame receives slave; R/W=0, next expression is that main frame sends order to slave.The 9th is parity check bit.The 10th is the ACK position, and 7 bit address of getting off conform to and the parity check bit checking is correct if the address of slave sends with main frame, and slave writes 0 to the XDA bus, otherwise write 1, main frame reads the data of XDA bus, if be read as 1, illustrate not from the message of function response main frame, withdraw from communication; If be read as 0.The message of slave preparation response main frame is described.
If the message of slave response main frame is arranged, judge that according to the value of R/W if R/W=1, main frame receives 8 bit data and the parity check bit of slave in the pulse period at ensuing 9 XCK; R/W=0, main frame sends 8 order of the bit and parity check bit to slave in ensuing 9 XCK the pulse period.The 10th XCK pulse period is the ACK position, the check parity check bit, and when R/W=1, if parity check bit is correct, main frame writes 1 on the XDA bus, otherwise writes 0; When R/W=0, if parity check bit is correct, slave writes 0 on the XDA bus, otherwise writes 1.If data or order are multibyte, repeat above-mentioned steps.If the parity check bit-errors then withdraws from communication.
After main frame sends order or receives data, when XCK=1, XDA is jumped to 1 by 0, produce stop condition, finish communication.
Distant serial synchronous telecommunications bus software flow is described main frame distant serial synchronous telecommunications software flow and slave distant serial synchronous telecommunications software flow respectively.
See also shown in Figure 11,
Main frame distant serial synchronous telecommunications software flow comprises: the processing of initialization, transmission distant serial synchronous telecommunications message, reception distant serial synchronous telecommunications message and message.When main frame need send order or reading of data to slave, produce initial conditions during communication earlier, send 7 bit address+R/W position+parity check bit then, then at the ACK place reading according to line, if ACK=0, then slave addresses meets, and can continue to send or accept message; ACK=1 does not then have the slave response, withdraws from communication.
During write order, R/W=0, main frame sends order, sends the end back and finishes communication.
During read data, R/W=1, host receiving data, check parity check bit and ACK position, communication is finished in correct back, handles the data of accepting.
See also shown in Figure 12,
Slave distant serial synchronous telecommunications software flow comprises: initialization, detection initial conditions, receive the distant serial synchronous telecommunications message, and send the processing of synchronous communication message and message.Slave is checked initial conditions on the distant serial synchronous telecommunications bus, prepare to receive message, receives 7 bit address+R/W position+parity check bit earlier, the address meet and parity check correct after, in ACK position response 0, according to the value of R/W, determine next step again.During R/W=0, slave receives message, the order that the sign off reprocessing is received; During R/W=1, slave sends data, sends the back that finishes and finishes communication.
In sum, the present invention is owing to adopt the distant serial synchronous telecommunications bus, expansion easily, only need to increase the quantity of remote control daughter board or remote signalling pulse daughter board, just can realize the expansion of input and output circuit on way easily, can satisfy onsite user's requirement, carrying out technical scheme revises, programming and debugging safeguard that replacing is easy, can expand new function easily.
Claims (5)
1. input/output module with inner communication through serial synchronous communication bus, this module is arranged in the terminal of power load management system,
It is characterized in that:
This module comprises the distant serial synchronous telecommunications bus, is attempted by the serial mainboard on the distant serial synchronous telecommunications bus, some remote control daughter boards and some remote signalling pulse daughter boards; Described distant serial synchronous telecommunications bus comprises a clock lines XCK, the XCK of the described serial mainboard of another data wire XDA, some remote control daughter boards, some remote signalling pulse daughter boards end is respectively with the clock line XCK of distant serial synchronous telecommunications bus and connect, and the XDA end of described serial mainboard, some remote control daughter boards, some remote signalling pulse daughter boards is respectively with the data wire XDA of distant serial synchronous telecommunications bus and connect; Described serial mainboard is by distant serial synchronous telecommunications bus and each remote control daughter board and the two-way transmission message data of remote signalling pulse daughter board.
2. the input/output module with inner communication through serial synchronous communication bus according to claim 1,
It is characterized in that:
Described serial mainboard is made up of microprocessor MCU, watchdog circuit, oscillating circuit and CAN interface; Microprocessor MCU is connected with watchdog circuit with reset line RES by control line WDI, and microprocessor MCU is connected with oscillating circuit with OSC2 by clock cable OSC1; Microprocessor MCU is connected with the CAN interface with control line by data wire; The XCK of microprocessor MCU end and XDA end are held with the clock line XCK end of distant serial synchronous telecommunications bus and data wire XDA respectively and are connect; The serial mainboard is connected with the CAN interface, by master control borad bi-directional transfer of data and the control command in CAN interface and the terminal.
3. the input/output module with inner communication through serial synchronous communication bus according to claim 1,
It is characterized in that:
Described remote control daughter board is made up of microprocessor MCU, watchdog circuit, oscillating circuit, tri-state gate circuit, latch, photoelectric isolating circuit and insulating power supply; Microprocessor MCU is connected with watchdog circuit with reset line RES by control line WDI; Microprocessor MCU is connected with oscillating circuit with OSC2 by clock cable OSC1; Microprocessor MCU is connected with tri-state gate circuit by data/address bus AD7-0, reading signal lines RD and chip selection signal line CS1; Microprocessor MCU is connected with latch by data/address bus AD7-0, write signal line WR and chip selection signal line CS2; Tri-state gate circuit is connected with photoelectric isolating circuit respectively by lead with latch; Insulating power supply is connected with photoelectric isolating circuit; The XCK of microprocessor MCU end and XDA end are held with the clock line XCK end of distant serial synchronous telecommunications bus and data wire XDA respectively and are connect; Described each remote control daughter board is connected with corresponding outside trip device with control line by data wire; The serial mainboard reads the status data of outside trip device by each remote control daughter board, and controls the tripping operation action of outside trip device.
4. the input/output module with inner communication through serial synchronous communication bus according to claim 1,
It is characterized in that:
Described remote signalling pulse daughter board is made up of microprocessor MCU, watchdog circuit, oscillating circuit, tri-state gate circuit, photoelectric isolating circuit and insulating power supply; Microprocessor MCU is connected with watchdog circuit with reset line RES by control line WDI; Microprocessor MCU is connected with oscillating circuit with OSC2 by clock cable OSC1; Microprocessor MCU is connected with tri-state gate circuit by data/address bus AD7-0 and chip selection signal line CS1; Tri-state gate circuit is connected with photoelectric isolating circuit by lead; Insulating power supply is connected with photoelectric isolating circuit; The XCK of microprocessor MCU end and XDA end are held with the clock line XCK end of distant serial synchronous telecommunications bus and data wire XDA respectively and are connect; Described each remote signalling pulse daughter board is connected with corresponding external measurement devices with control line by data wire; The serial mainboard reads the pulsed quantity/quantity of state data of external measurement devices by each remote signalling pulse daughter board.
5. according to the described input/output module of claim 3 and claim 4 with inner communication through serial synchronous communication bus,
It is characterized in that:
Described photoelectric isolating circuit is made up of some groups of identical photoelectricity isolated location circuit.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB2004100935157A CN100338845C (en) | 2004-12-24 | 2004-12-24 | Input / output module of inner communication through serial synchronous communication bus |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB2004100935157A CN100338845C (en) | 2004-12-24 | 2004-12-24 | Input / output module of inner communication through serial synchronous communication bus |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN1797900A true CN1797900A (en) | 2006-07-05 |
| CN100338845C CN100338845C (en) | 2007-09-19 |
Family
ID=36818746
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CNB2004100935157A Expired - Fee Related CN100338845C (en) | 2004-12-24 | 2004-12-24 | Input / output module of inner communication through serial synchronous communication bus |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN100338845C (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101692220B (en) * | 2009-10-28 | 2012-05-09 | 广东威创视讯科技股份有限公司 | Method for managing equipment numbers of distributed system |
| CN107959348A (en) * | 2017-12-27 | 2018-04-24 | 上海欣能信息科技发展有限公司 | A kind of modular distribution power automation terminal |
| CN112684848A (en) * | 2020-12-11 | 2021-04-20 | 广西电网有限责任公司电力科学研究院 | Method and device for timing chain type redundant board level clock |
Family Cites Families (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH096725A (en) * | 1995-06-14 | 1997-01-10 | Kofu Nippon Denki Kk | Asynchronous data transfer receiver |
| JPH09305535A (en) * | 1996-05-15 | 1997-11-28 | Nec Corp | Asynchronous multiplexing system for control system serial bus |
| KR100230451B1 (en) * | 1997-04-08 | 1999-11-15 | 윤종용 | Method of transceiving asynchronous serial data of digital signal processor |
| CN2770200Y (en) * | 2004-12-20 | 2006-04-05 | 上海协同科技股份有限公司 | Inputting and outputting module for electric loading monitoring terminal |
-
2004
- 2004-12-24 CN CNB2004100935157A patent/CN100338845C/en not_active Expired - Fee Related
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101692220B (en) * | 2009-10-28 | 2012-05-09 | 广东威创视讯科技股份有限公司 | Method for managing equipment numbers of distributed system |
| CN107959348A (en) * | 2017-12-27 | 2018-04-24 | 上海欣能信息科技发展有限公司 | A kind of modular distribution power automation terminal |
| CN112684848A (en) * | 2020-12-11 | 2021-04-20 | 广西电网有限责任公司电力科学研究院 | Method and device for timing chain type redundant board level clock |
Also Published As
| Publication number | Publication date |
|---|---|
| CN100338845C (en) | 2007-09-19 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN1108574C (en) | Peripheral unit selection system | |
| CN1760839A (en) | Apparatus, system, and method for facilitating port testing of a multi-port host adapter | |
| CN101060412A (en) | Ethernet power supply system, control unit, master control module and Ethernet power supply method | |
| CN1804799A (en) | SCM online loading and updating method and system | |
| CN101060457A (en) | Optical fiber-based high speed serial industrial real-time communication bus system and its control method | |
| CN1591377A (en) | Apparatus and methods for communicating with programmable logic devices | |
| CN1862512A (en) | Single board read/writ system and method for information | |
| CN1904842A (en) | Apparatus and method of CMOS parameter setting and maintaining | |
| CN100338845C (en) | Input / output module of inner communication through serial synchronous communication bus | |
| CN2770200Y (en) | Inputting and outputting module for electric loading monitoring terminal | |
| CN101067925A (en) | Adaptive method for display screen to different interface type | |
| CN1897594A (en) | USB-CAN bus adapter based on microcontroller | |
| CN101277198B (en) | High speed communication chip capable of resisting irradiation interference in rigor surroundings | |
| CN110809002A (en) | Method for protocol conversion between robot and welding equipment and protocol conversion module | |
| CN1859155A (en) | Link state self consulting method | |
| CN1374592A (en) | Terminal equipment for maintaining clock/calender information and high read out speed and its real-time clock control method | |
| CN1684467A (en) | Control method of plug-in and plug-out end of interface plate and plug-in and plug-out end device of interface plate | |
| CN103838587A (en) | Control system remote upgrading method and device based on GPRS | |
| CN1645852A (en) | Agreement converting method and device between MODBUS/TCP industrial Ethernet and PROFIBUS-DP bus on-the-spot | |
| CN1956540A (en) | Control system of audio-video transmission based on optical fibre transmission | |
| CN204706031U (en) | Serial peripheral equipment interface SPI bus circuit and electronic equipment | |
| CN209842365U (en) | Signal processing system | |
| CN102591688B (en) | Electrocardiograph plug-in access method and system | |
| CN1190925C (en) | Universal serial bus synthesizer and synthesis method | |
| CN203883862U (en) | PROFIBUS communication module for connecting frequency converter with host computer |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20070919 Termination date: 20191224 |
|
| CF01 | Termination of patent right due to non-payment of annual fee |