CN1797761A - Power core devices and methods of making thereof - Google Patents

Abstract

The present invention relates to a power core comprising: at least one embedded surface mount technology (SMT) discrete chip capacitor layer comprising at least one embedded SMT discrete chip capacitor; and at least one planar capacitor laminate; wherein at least one planar capacitor laminate serves as a low inductance path to supply a charge to at least one embedded SMT discrete chip capacitor; and wherein said embedded SMT discrete chip capacitor is connected in parallel to said planar capacitor laminate.

Description

Power supply core devices and manufacture method thereof

Technical field

The present technique field relates to the device with low inductance value and two kinds of functions of high capacity, and these devices are incorporated into method in organic dielectric layered product and the printed substrate.

Background technology

When the semiconductor device that comprises integrated circuit (IC) is worked under upper frequency, higher data rate and lower voltage, noise in power line and ground connection (returning) line, and enough electric currents are provided, and circuit is switching to more and more important problem to adapt to faster, requires to have low inductance value in this power distribution system.For low noise and stabilized power supply are provided to IC, reduce impedance in the traditional circuit by additional surface mounting technique (SMT) electric capacity that uses interconnection in parallel.Higher operating frequency (higher IC switch speed) is meant that voltage must be than comparatively fast to response time of IC.Lower operating voltage requirement permission change in voltage (ripple) and noise ratio are less.For example, when microprocessor IC switched and starts working, it required to provide power supply to support this commutation circuit.If the response time of voltage source is too slow, then this microprocessor can experience a voltage drop or a power supply decline that surpasses permission ripple voltage and noise margin, and IC can break down.In addition, when the IC power supply raise, the slow-response time can cause the power supply overshoot.Must be by using enough near the electric capacity of this IC, in the suitable response time, provide or absorb power supply, power supply is descended and the power supply overshoot is controlled in the tolerance limit.

Usually being used for that impedance reduces and suppressing that power supply descends or the SMT electric capacity of power supply overshoot is placed on circuit board surface as far as possible near the place of IC, to improve circuit performance.Traditional design has to be surface mounted in clusters round the electric capacity on every side at IC on the printed substrate (PWB).Big value electric capacity is placed near the power supply, the electric capacity of medium range value between IC and power supply, the very close IC of little value electric capacity.Accompanying drawing 1 is a power supply 2, the schematic diagram of IC10 and electric capacity 4,6,8, and electric capacity 4,6,8 represent high value respectively, and medium range value and little value electric capacity are used for above-mentioned impedance reduction and suppress power supply descending or the power supply overshoot.Accompanying drawing 2 is representative section figure of positive apparent direction, expresses SMT electric capacity 50,60 and IC40 being connected of voltage plane and ground plane in the PWB substrate.Weld tabs 44 is connected to welded disc 41 with IC device 40.Circuitry lines 72 and 73 is connected to the through hole path pad of the plating of path 90 and 100 with welded disc 41.The path pad generally is represented as 82.Path 90 is electrically connected with conducting surface 120, and path 100 is electrically connected with conducting surface 122.Conducting surface 120 and one of 122 is connected to the mains side of power supply, and another is connected to ground connection (returning) side of power supply.Little value electric capacity 50 and 60 is electrically connected to path and conducting surface 120 and 122 similarly, and its connected mode is to be electrically connected with IC40 with parallel way.IC is placed on module, and when plate or encapsulation were gone up, big value and intermediate value electric capacity can be positioned at link block, on the printed wire motherboard of plate or encapsulation.

In order to reduce the impedance of the power-supply system that needs the complicated circuit wiring, generally need a large amount of SMT electric capacity of interconnection in parallel.This causes improving the loop inductance value, thereby improves impedance, suppresses electric current, thereby reduces the beneficial effect of mounted on surface electric capacity.Along with frequency increases and the lasting reduction of operating voltage, must provide the power supply of increase to require the more and more lower very fast speed of inductance and impedance level.

Expended sizable effort impedance has been reduced to minimum.People's such as Howard United States Patent (USP) 5161086 provides a kind of minimum approach has been reduced in impedance and " noise ".People such as Howard provide a kind of capacitive character printed circuit board (PCB), in a plurality of layers of laminated sheet, comprise capacitor lamination body (plane capacitance), there is device such as a large amount of integrated circuits to be mounted or to be formed on circuit board, to install or form devices such as a large amount of integrated circuits, and, provide to comprise and using or the capacitive function of shared electric capacity with capacitor lamination body (or a plurality of capacitor lamination body) coupling connection work.But this approach differs and improves voltage response surely.Improving voltage response requires this electric capacity near IC.It may be not enough simply capacitor lamination body being placed on than the place near IC, because resulting total capacitance value may be inadequate.

The United States Patent (USP) 6611419 of Chakravorty provides another kind of embedded capacitance to reduce the approach of switching noise, wherein, and the corresponding end coupling of at least one electric capacity that embeds in the power end of integrated circuit modules and multi-layered ceramic substrate connection.

Therefore, the present inventor is desirable to provide the method for a kind of manufacturing and designing power supply heart yearn, and this power supply heart yearn is used to integrated circuit encapsulation or other interconnection plates, in structure or the element, can obtain superior power distribution impedance and reduce, and the voltage response that adapts to the improvement of higher IC switch speed.The method that the invention provides a kind of like this device and make this device.

Summary of the invention

An embodiment of the invention relate to the power supply heart yearn, comprising: at least one embedded surface mounting technique (SMT) discrete monolithic capacitor layer, comprising at least one embedded SMT discrete monolithic capacitor; With at least one planar capacitor lamination body; Wherein at least one planar capacitor lamination body provides electric charge as low inductance path at least one embedded SMT discrete monolithic capacitor; And wherein said embedded SMT monolithic capacitor is connected with described planar capacitor lamination body with parallel way.

Another execution mode of the present invention provides the method for making the power supply core structure, comprising: a kind of method of making the power supply core structure comprises: the planar capacitor lamination body with the first Butut side and second Butut side is provided; Metal forming is provided; Described metal foil layer is depressed into a described Butut side of described planar capacitor lamination body; On described metal forming, form welded disc and path pad; At least one SMT discrete monolithic capacitor is fixed on the welded disc of described metal forming; And at least one SMT discrete monolithic capacitor is parallel on the described planar capacitor lamination body.

Also at a kind of method of making device and comprising the device of above-mentioned power supply core structure, wherein said power supply heart yearn is interconnected at least one signals layer in the present invention.

Brief Description Of Drawings

Be specifically described with reference to the following drawings, wherein like adopted similar Reference numeral, wherein:

Fig. 1 is used for the schematic diagram that inductance value reduces and the inhibition power supply descends or the typical prior art of the electric capacity of power supply overshoot is used; Fig. 2 is the profile of printed wire assembly in positive apparent direction, and mounted on surface (SMT) electric capacity that has traditional prior art in this printed wire assembly is used for the impedance reduction and suppresses power supply descending or the power supply overshoot;

Fig. 3 is according to the power supply core structure of first execution mode profile in positive apparent direction;

The method of planar capacitor lamination body is made in Fig. 4 A-4B explanation;

Fig. 5 A-5B represents to be used to make according to the planar capacitor lamination body of the power supply core structure of first execution mode and initially prepares;

Fig. 6 is the profile of power supply core structure subdivision on positive apparent direction according to first execution mode;

Fig. 7 is according to the profile of the power supply core structure subdivision of first execution mode after further handling on positive apparent direction;

Fig. 8 is the profile of power supply core structure on positive apparent direction according to first execution mode;

Fig. 9 is that the power supply heart yearn is attached to printed circuit board (PCB), module (comprising multi-chip module), plate or encapsulation (comprising encapsulation in the encapsulation and system in zone battle array array packages, the system) when forming the power supply core devices, at the power supply core structure of the next stage profile on apparent direction just.

Figure 10 is the A type discrete capacitor design of seeing from the paper tinsel side.

Figure 11 is the Type B discrete capacitor design of seeing from the paper tinsel side.

Figure 12 is the C type discrete capacitor design of seeing from the paper tinsel side.

Embodiment

Embodiments of the present invention relate to can be embedded in printed substrate (PWB) substrate, module, the power supply core structure in plate or the encapsulation.Consider PWB, module, the low inductance value of power supply heart yearn and high capacity function have kept PWB in plate or the enclosed chip, module, valuable surperficial resource is gone up in plate or encapsulation, compares with traditional SMT capacitance arrangement, needs less solder joint.

According to first execution mode, the method for a kind of design and manufacturing power supply core structure is disclosed, wherein the SMT discrete monolithic capacitor of high capacity is pressed body to be connected with parallel way with planar capacitor layers and is embedded in the laminate structure formation power supply core structure.SMT discrete monolithic capacitor is electrically connected on the metal solder dish by welding or other proper method.Usually, metal is a metal forming.Though we use term " paper tinsel " here, should be realized that, paper tinsel comprises common metal layer, plated metal, splash-proofing sputtering metal etc.The SMT discrete monolithic capacitor of high capacity is placed and be interconnected in the power supply heart yearn as far as possible near the power end of IC, be used for IC is produced the quick voltage response, switch at a high speed supporting.Can also provide low inductance value to connect near the placement of IC power end as much as possible SMT discrete monolithic capacitor.Planar capacitor lamination body is as power supply-ground plane, and power supply-ground plane is separated very thin, to reduce the high-frequency resistance in the encapsulation.

Accompanying drawing 3 is power supply core devices 600 of the present invention profiles on positive apparent direction.Above-mentioned execution mode allows paper tinsel 210 is laminated to planar capacitor lamination body 340, forms welded disc 220, circuit conductor 230 and path pad 240 on paper tinsel, and with bonding pad 250 SMT discrete monolithic capacitor 410 is welded to welded disc.Such SMT discrete monolithic capacitor is that industry is commonly used, and can obtain from for example MurataManufacturing Co., Ltd, Syfer a Dover company and Johanson Dielectrics Co., Ltd.Can adopt the laminating method of standard printed circuit board, the paper tinsel that is used for forming the described welded disc of fixing described SMT discrete monolithic capacitor is laminated on the planar capacitor lamination body, form the subdivision of power supply core structure.

Above-mentioned execution mode also allows to use various materials to form plane capacitance.These materials can comprise metal forming-dielectric material-metal foil layer laminated structure, and dielectric material wherein can comprise organic layer, the organic layer that pottery is filled, or ceramic layer.When using a plurality of layers, these layers can be different materials.The thickness of these dielectric materials can be thin to reduce impedance.Can adopt standard printed substrate laminating method that planar capacitor is laminated to and be used for forming on the paper tinsel of the described welded disc of fixing described SMT discrete monolithic capacitor, form the subdivision of power supply core devices.

By solder paste being put on welded disc, be placed on the solder paste position and use Reflow Soldering technology fusing solder paste can fix described SMT discrete monolithic capacitor, for example, form the power supply core devices to SMT discrete monolithic capacitor.For example, can use the high temperature fluxes thickener, such as the Indalloy No.241 that obtains from IndiumCorporation of America, to prevent solder fusing at printed substrate hot-air solder leveling or follow-up weld period.

According to above-mentioned execution mode, two kinds of functions of Low ESR and high capacity can both be integrated in the single power supply core structure, this structure can also further be integrated in another laminate structure, allows to carry out High Speed ICs work with the voltage ripple that reduces under low voltage.The power supply core structure is combined in printed substrate, module, in the time of in plate or the encapsulation, valuable resource becomes available.And, can cancel being connected in parallel on the relevant solder joint of lip-deep single SMT capacitor, thereby improve reliability.Can adopt printed substrate method processing power source core structure commonly used, further reduce manufacturing cost.

By reading specifying and the following accompanying drawing of reference of these execution modes, those skilled in the art can understand the above-mentioned of each execution mode of the present invention and other advantages and benefit.

According to general custom, the various piece of accompanying drawing is not necessarily proportional.The size of each several part can be amplified or dwindle, thereby is illustrated more clearly in embodiments of the present invention.

Fig. 3 is the end view according to the power supply core devices 600 of first execution mode, comprises planar capacitor lamination body 340 and SMT discrete monolithic capacitor 410 in this device.

Fig. 4 A-4B is an end view of making the conventional method of planar capacitor lamination body.

Fig. 4 A is the end view of the phase I of the planar capacitor lamination body 320 shown in the shop drawings 4B, and a metal forming 310 wherein is provided.Paper tinsel 310 can be from for example copper, and copper-based material and other metal are made.Preferred paper tinsel comprises the paper tinsel of mainly being made up of copper, the Copper Foil handled of reverse side for example, the Copper Foil of double treatment, the Copper Foil of mill-annealed and be usually used in other Copper Foils in the multilayer board industry.The example of some suitable copper foil is those products from Olin Brass (Somers Thin Strip) and Gould Electronics acquisition.The thickness of paper tinsel 310 can be for example approximately in the scope of 1-100 micron, and preferably the 3-75 micron most preferably is the 12-36 micron, corresponding to the Copper Foil between about 1/3 and 1 ounce.

Slurry or solution can be cast or are coated on the paper tinsel 310, and dry and curing forms first dielectric layer 312, forms the metal forming 300 through coating.One or more dielectric layers of layered product can be selected from organic, pottery, and it is organic that pottery is filled, and the layer of their mixture.If polymer has thermoplasticity, then solidifying can be by realizing for example curing under 200-350 ℃.If polymer is a thermosets, then can use higher curing temperature.If it is partly solidified and form the polymer of " B " stage condition that polymer tends to, then solidifies and to realize by for example under 120-200 ℃, carrying out drying.

The solution that is used to form dielectric layer 312 can comprise, for example is dissolved in the polymer in the solvent.Slurry can comprise for example having the polymer-solvent solution of high-k (" high K ") filler/ceramic packing or function thing phase.Be suitable for to include, but are not limited to, for example epoxy or polyimide resin as the polymer of slurry or solution.High K function thing can be defined as dielectric constant mutually greater than 500 material, can comprise that general formula is ABO ₃Perovskite-type compounds.The filler that is suitable for comprises for example crystalline barium titanate (BT), barium strontium (BST), lead zirconate titanate (PZT), load lanthanium titanate, lead lanthanum zirconate titanate (PLZT), lead magnesium niobate (PMN) and calcium titanate copper.Filler can be a powder type.A kind of suitable high K filler is from FerroCorporation, the barium titanate that Tam Ceramics or Fuji Titanium obtain.

For other reasons, dielectric constant is lower than 500 function thing and also may be suitable for mutually.These materials can comprise titanium, tantalum, the oxide of hafnium and niobium.

If dielectric material 312 is thermoplastic, perhaps be partly solidified, then can be under heat and pressure that two metal formings 300 through coating are laminated together with direction shown in the arrow among Fig. 4 A, form the laminar structure 320 shown in Fig. 4 B.

If dielectric material 312 is heat cured, then the adherent coating can be put on one or two dielectric layer 312.Commercial thermosetting dielectric material comprises the polyimides level product that obtains from E.I.du Pont de Nemours and Company.

Referring to Fig. 4 B, form single dielectric material 324 from layer 312 lamination.For example, the dielectric material 324 that makes can be a thin layer, about 4-25 micron after the lamination.An execution mode of planar capacitor lamination body is copper-dielectric material-copper layered product.Can be used for forming that the material of embedded capacitance of metal-dielectric material-metal structure and method comprise that Vantico licenses to Probelec 81 CFP of Motorola and through resin-coated paper tinsel product, the MCF6000E that obtains from Hitachi Chemical Company for example, from Mitsui Metal and Smelting Co., Ltd. the MR-600 of Huo Deing, from MatsushitaElectric Works, Ltd. the R-0880 of Huo Deing, with from Sumitomo Bakelite Co., the APL-4000 that Ltd. obtains.

The method of another kind of formation dielectric material 324 can be, in the filling of paper tinsel 310 top castings process or without the thermoplastic polymer of filling, with the thermoplastic polymer of the uncoated second paper tinsel contact laminating to the process filling.And another kind of manufacture method comprises with single film and forms dielectric layer 324 independently, and uses heat and pressure that it is laminated to first paper tinsel 310 and second paper tinsel 310.Another kind of manufacture method comprises with single film and forms dielectric layer 324 independently, and at the both sides splash-proofing sputtering metal crystal seed layer of the described independent dielectric layer that forms, adopts chemical plating or metallide technology then, other metals of plating on this crystal seed layer.The capacitor lamination body that is suitable for comprises the Interra that obtains from E.I.du Pont de Nemours and Company ^TMHK04 series is from the Interra of E.I.du Pont de Nemours and Company acquisition ^TMHK 11 series, BC-2000 and BC-1000 layered product that Sanmina-SCI Corporation authorizes are from the FaradFlex series of Oak-MitsuiTechnologies acquisition, from the InSite of Rohm and Haas Electronic Materials acquisition ^TMEmbedded capacitance series is from the TCC of Gould Electronics acquisition ^TMAnd the C-Ply that obtains from 3M.

Fig. 5 A-5B illustrates that in the end view mode preparation is used to make the universal method of the planar capacitor lamination body of power supply core devices.

Fig. 5 A has represented the planar capacitor lamination body 320 of Fig. 4 B in the end view mode.On each paper tinsel 310 (not shown in Fig. 5 A) with photoresist.But, have only a photoresist imaging and development, therefore paper tinsel 310 of an etching forms foil electrode part 314 and interlock circuit.Adopt standard printed substrate processing conditions to peel off all remaining photoresists then.A kind of example of suitable photoresist is the Riston that obtains from E.I.du Pontde Nemours and Company ^Photoresist.

Fig. 5 B with the end view mode represented to make through overetched layered product 340, a side of layered product is etched among the figure has removed part paper tinsel 310, and other paper tinsels 310 are kept perfectly.

Referring to Fig. 6, paper tinsel 210 is laminated to the Butut side of planar capacitor layers 340.For example, can adopt standard printed substrate processing method to carry out lamination with FR4 epoxy prepreg 360.In one embodiment, can use epoxy prepreg type 106.The lamination that is suitable for can be that in the vacuum chamber that is evacuated to 28 inches of mercury, with 185 ℃, 208 pounds/square inch (gauge pressure) handled 1 hour.The glass stripping film of silicon rubber pressure pad and level and smooth filling PTFE can contact with 310 with paper tinsel 210, prevents that epoxy resin is bonded together laminate.Dielectric prepreg and laminated material can be the dielectric materials of any kind of, standard epoxy for example, high Tg epoxy resin, polyimides, polytetrafluoroethylene, cyanate ester resin, the potting resin system, BT epoxy resin and other resins and the layered product of insulation can be provided.Stripping film can contact foil, in case the stop ring epoxy resins is bonded together laminate.Subdivision 400 1 sides that make have paper tinsel 210, and opposite side has paper tinsel 310.

Referring to Fig. 7, after the lamination, photoresist (not shown in Fig. 7) is applied to paper tinsel 210 and plane condenser foil 310.Photoresist is developed by imaging, and the etching metal paper tinsel, adopts standard printed substrate processing conditions stripping photoresist.Be etched in and form foil electrode part 314 and interlock circuit in the planar capacitor paper tinsel 310.Etching also produces welded disc 220, circuit conductor 230 and path pad 240 from paper tinsel 210.Also produce all interlock circuits by paper tinsel 210.Form subdivision 500.

Referring to Fig. 8, SMT discrete monolithic capacitor 410 is fixed to finishes power supply core devices 600 on the subdivision 500.Fixedly a kind of method of SMT capacitor is to apply high temperature fluxes thickener such as IndalloyNo.241 (can obtain from Indium Corporation of America Indium) to welded disc 220.After applying solder paste, by SMT discrete monolithic capacitor being placed on the welded disc of this thickener covering from picking up and place apparatus that the printed circuit board (PCB) assembly industry obtains.

Be to be understood that, can form the power supply heart yearn by the lamination of other orders, for example at first the imaging side of the lamination of planar capacitor shown in Fig. 6 body 340 is laminated to other printed wire flaggies, on the paper tinsel 310 of not imaging, apply photoresist, etched foil, stripping photoresist is laminated to paper tinsel 210 on the structure of formation then.

Shown in Figure 9 is the end view that the power supply heart yearn is attached to the another stage in the processing of printed circuit board (PCB), module, plate or encapsulation.Power supply core devices 600 can adopt standard printed substrate processing method to be laminated to other circuit layer with for example FR4 epoxy prepreg 710 and 730.Prepreg 710 can be a pre-punched hole, forms perforate 720.Metal forming 740 also can with prepreg 710 laminations and suitably imaging, form required circuit.Perforate 720 is used for reducing the pressure on SMT discrete monolithic capacitor 410 in the lamination process.During lamination, the epoxy resin in the prepreg flows around capacitor 410, they is sealed (unclear in the figure marking).Can also the other circuit layer of lamination.Another kind method can be used the metal forming of coating resin, and its dielectric layer does not contain fiberglass reinforcement.Only partly solidified resin flows around SMT discrete monolithic capacitor 410 in lamination process.

Other method of using always by boring and the through hole path that plate or employing printed circuit board industry is electrically connected to path pad 240 with the foil electrode part 312 and 314 of planar capacitor.Fig. 9 illustrates the expression of the part of the through hole path 750 that plated and 760.The through hole path 750 that plated is electrically connected on the paper tinsel of end of SMT discrete monolithic capacitor 410 and planar capacitor 340.The through hole path 760 that plated is electrically connected on the relative paper tinsel of the opposing ends of SMT discrete monolithic capacitor 410 and planar capacitor 340.This representative situation is presented at the parallel electrical connection between SMT discrete monolithic capacitor 410 and the planar capacitor layers pressure body 340.

Figure 9 shows that a kind of execution mode of power supply core devices.This power supply core devices comprises the power supply heart yearn, and the power supply heart yearn comprises: at least one embedded surface mounting technique (SMT) the discrete monolithic capacitor layer that comprises at least one embedded SMT discrete monolithic capacitor; With at least one planar capacitor lamination body; Wherein at least one planar capacitor lamination body provides electric charge as low inductance path at least one embedded SMT discrete monolithic capacitor; And wherein said embedded SMT monolithic capacitor is connected with described planar capacitor lamination body with parallel way; Described power supply heart yearn is interconnected at least one signals layer.

The SMT discrete monolithic capacitor of device comprises at least the first electrode and second electrode.First electrode and second electrode are connected at least one power tip of semiconductor device.This semiconductor device can be an integrated circuit.

In addition, the power supply core devices can comprise more than one signals layer, and described signals layer connects by conductive path.Described device can be selected in plate, printed circuit board (PCB), multi-chip module, area array package, system to encapsulate in encapsulation and the system.

The power supply core devices can adopt the whole bag of tricks manufacturing, comprises a kind of method of making device, and this method comprises: the body of the planar capacitor lamination with at least one Butut side is provided; Metal forming is provided; Described metal foil layer is depressed into the Butut side of described planar capacitor lamination body; On described metal forming, form welded disc and path pad; At least one SMT discrete monolithic capacitor is fixed on the welded disc of described metal forming; And at least one SMT discrete monolithic capacitor is parallel on the described planar capacitor lamination body, form the power supply heart yearn; On described power supply heart yearn, form at least one signals layer.

The another kind of method of making device may further comprise the steps: the planar capacitor lamination body with the first Butut side and second Butut side is provided; Metal forming is provided; Described metal foil layer is depressed into a described Butut side of described planar capacitor lamination body; On described metal forming, form welded disc and path pad; At least one SMT discrete monolithic capacitor is fixed on the welded disc of described metal forming; And at least one SMT discrete monolithic capacitor is parallel on the described planar capacitor lamination body, form the power supply heart yearn; On described power supply heart yearn, form at least one signals layer.

These signals layers can adopt following method to form, and promptly the one or both sides at described power supply heart yearn apply dielectric layer; On described dielectric layer, form the circuit that comprises one or more holding wires; And comprise described holding wire the layer between form conductive interconnection.Interconnection between the layer can be a conductive path.In addition, passive component is connected to and is external to described power supply heart yearn.

Embodiment

Design has also been tested a kind of structure that comprises planar capacitor lamination body and discrete embedded ceramic condenser.Planar capacitor lamination body forms the power distribution face, and embedded capacitance is designed to be placed on two interior metal layers.Have three kinds of different capacitor design: A type, Type B and C type.For every type, have 1 square millimeter, a plurality of electric capacity of 4 square millimeters and 9 square millimeters of effective capacitance sizes (area) are placed on each of two interior metal layers.The difference of capacitor design is relative position and foil electrode size, the size of the copper electrode of dielectric material size and silk screen printing.Their design distinguished also is, the design in the gap (spacing) of isolated two copper foil electrodes, and their difference also to be embedded capacitance is connected to the via positions and the quantity of next metal level top also inequality.For example, in the electric capacity of 9 square millimeters of sizes, A type design characteristic is to have 4 paths to connect, and Type B has 28 paths, and the C type has 52 paths.For all three types, the conductor of silk screen printing forms a capacitance electrode, by the paper tinsel of the conductor of dielectric material and silk screen printing separation as another capacitance electrode.

The design of as shown in Figure 10 A type discrete capacitor when the paper tinsel side is observed, has square profiles, and the foil electrode (900) of connection screen-printed conductor extends through the electric capacity width.This electrode is separated by 250 microns spacing (920) and second foil electrode (910) as another capacitance electrode.This spacing extends through the electric capacity width.Second foil electrode that extends through the electric capacity width has the length for this electric capacity length about 4/5.The formation diameter is 150 microns path connection (930) on the next metal level above the electric capacity, when the paper tinsel side of each from two electrodes is observed, finds that this path connection is placed in the upper right corner.For all sizes, in each electrode, use two paths.

The design of as shown in Figure 11 Type B discrete capacitor when the paper tinsel side is observed, has square profiles, and two foil electrodes (1000,1005) are connected to the conductor of silk screen printing.Each electrode all extends through the electric capacity width at capacitive head and bottom, and the length of each is respectively about 1/5 of electric capacity length.These electrodes are extended by 250 micron pitch (1020) of electric capacity width and second foil electrode (1010) as another capacitance electrode and separate.The length of this second electrode (1010) is 3/5 more smaller than electric capacity length.The path that forms diameter in the next metal level above electric capacity and be 150 microns connects (1030), and is evenly arranged into row, by the width of capacitance electrode, is connected to the conductor of silk screen printing in capacitive head and bottom.Second electrode of electric capacity has the path that a row distributes along the every side of electric capacity.For 9 square millimeters of sizes, use 28 paths.

The design of as shown in Figure 12 C type discrete capacitor when the paper tinsel side is observed, has square profiles.The foil electrode (1100) that is connected to screen-printed conductor forms square " frame " shape parts that center on second capacitance electrode (1100).This second capacitance electrode also is square, is separated by 250 microns continuous spacings (1120) and first electrode that centers on.The 150 micron diameter paths that arrive the next metal level in electric capacity top connect (1130) and are evenly distributed on all 4 sides of first capacitance electrode that is connected to screen-printed conductor, have 32 paths altogether for 9 square millimeters of sizes.For 9 square millimeters of sizes, second electrode of electric capacity has 20 paths, is evenly distributed on around the electrode.

Measurement has the electrical quantity (capacitance, resistance value, inductance value) of single electric capacity when not having path to be connected.The impedance of measuring single electric capacity is to frequency response, and the curve that the response that records and simulation model are made compares.Use a model the then impedance of a plurality of capacitor arrays of simulation, to the embedded capacitance arrayed applications conservative with the design rule advanced person.

Conclusion:

The two-port method of measurement of utilizing the Vector network analyzer and using SOLT to calibrate, measurement do not have the A of 1,4 and 9 square millimeter of size of path connection, capacitance, resistance value and the inductance value of B and C type electric capacity.Use has the parameter of coaxial ground connection-signal probe measurement electric capacity S in 500 microns gaps, calculates the reality and the empty impedance component of electric capacity.In table 1 (not having path) and table 2 (having path), electric capacity 1,4,9th, the design of A type, electric capacity 2,5 and 8 is Type B designs, electric capacity 3,6 and 7 is the designs of C type.Electric capacity 1 to 3 is 1 millimeter * 1 mm sizes, and electric capacity 4-6 is 2 millimeters * 2 mm sizes, and electric capacity 7 to 9 is 3 millimeters * 3 mm sizes.

Table 1 does not have path

	Capacitance	ESR (resistance value)	Inductance value
				Electric capacity 1	1.26 nanofarad	36 milliohms	48 skin henries
Electric capacity 2	1.17 nanofarad	50 milliohms	47.3 skin henry
				Electric capacity 3	1.63 nanofarad	34 milliohms	41.6 skin henry
Electric capacity
	4	5.15 nanofarad	8 milliohms	33.7 skin henry
Electric capacity 5					5.16 nanofarad	10.7 milliohm	35.07 skin henry
	Electric capacity
6		6.16 nanofarad	10.7 milliohm	35.48 skin henry
	Electric capacity 9				10.6 nanofarad	7.9 milliohm	35.44 skin henry
Electric capacity
	8	11 nanofarads	10 milliohms	40 skin henries
Electric capacity 7					13.6 nanofarad	8.9 milliohm	33.8 skin henry

This explanation, as desirable, capacitance is along with size increases, can great changes have taken place because of kind of design.All inductance value of three types are very approaching when not having path to connect.A when using identical equipment and method to measure to have path to be connected, the identical parameters of B and C type electric capacity.

Table 2 has path

	Capacitance	ESR (resistance value)	Inductance value
				Electric capacity 1	1.05 nanofarad	89 milliohms	382 skin henries
Electric capacity 2	1.20 nanofarad	86.5 milliohm	125 skin henries
				Electric capacity 3	1.7 nanofarad	37.1 milliohm	74.6 skin henry
Electric capacity
	4	6.49 nanofarad	50.1 milliohm	308 skin henries
Electric capacity 5					5.28 nanofarad	128 milliohms	120.5 skin henry
	Electric capacity
6		6.6 nanofarad	20.9 milliohm	65.17 skin henry
	Electric capacity 9				15.3 nanofarad	100 milliohms	218.2 skin henry
Electric capacity
	8	13.26 nanofarad	15.4 milliohm	115 skin henries
Electric capacity 7					13.2 nanofarad	17.3 milliohm	79.39 skin henry

These data declarations, capacity type and number of passages and position influence the resistance value and the inductance value of electric capacity to a great extent.

Measurement has impedance with two C type electric capacity that do not have path to be connected to frequency response.For electric capacity 3 listed above, the result shows, has and the impedance when not having path is about 30 milliohms about 500 megahertzes of about 900 megahertzes of the resonant frequency shift that this electric capacity produces because path connects during for path never when having path.For electric capacity 6, the result when not having path shows that the impedance when resonance frequency is about 350 megahertzes is about 10 milliohms, and when having path, the impedance when resonance frequency is about 200 megahertzes is about 20 milliohms.

Observe between the response of measured frequency response of the electric capacity of two kinds of different sizes and simulation and have good correlation.

The plane capacitance that has and do not have the through hole inductance to distribute is carried out the simulation of plane capacitance impedance to frequency response.The through-hole interconnection area is about 1% of the gross area.The frequency response that does not have a plane capacitance of through hole inductance has about 80 milliohms under the resonance frequency of about 300 megahertzes a impedance, and two frequency response with plane capacitance of through hole inductance has about 30 milliohms under the resonance frequency of about 250 megahertzes impedances.

According to the analog result of result who records and various independent capacitances, the minimum clearance between the application electric capacity is that 500 microns conservative design rule is simulated 64 discrete embedded capacitance arrays.Select the electric capacity of different size and different resonant frequencies, make the impedance response of capacitor array provide low impedance value quite uniformly.The impedance that obtains in the 1 gigahertz scope at 100 megahertzes is less than about 40 milliohms.

According to recording and Simulation result, in 1 gigahertz frequencies scope, every side is of a size of the harsher gap design rule of capacitance applications of 1.15 to 2.5 millimeters array at 100 megahertzes, obtain the impedance of 0.7 milliohm.

For being arranged in on-chip 100 the coupling connection transmission line design simulation models not of 38 micron thickness, the relative dielectric constant of this substrate is 3.8, and substrate separates with voltage plane.Transmission line is spaced apart 10 mils, and is long 15 millimeters, wide 2.82 mils, and every line is all being that 99 ohm resistance stops (50 ohm line terminals) to voltage plane and ground plane.Under a kind of situation, voltage plane is positioned on the 14 micron thickness substrates relative with ground plane.The relative dielectric constant of substrate is 3.8, and loss angle tangent is 0.02.In another case, voltage plane is positioned on the 14 micron thickness substrates relative with ground plane, and relative dielectric constant is 11, and loss angle tangent is 0.02.Use to produce 5 gigahertz square wave bit streams, 80 picopulse width, 20 psecs rise and the output driver of fall time drives all 100 transmission lines, obtain " eye " shape pattern response of meta transmission line.For the eye shape pattern of first kind of situation, the dielectric constant of voltage plane substrate is 3.8, and the eye shape open height of acquisition is 2.4799 volts.For the response of second kind of situation, the dielectric constant of the same terms and voltage plane substrate is 11 o'clock, and eye shape open height is 2.6929 volts, than first kind of situation tangible increase is arranged.Gap between the transmission line is adjusted into 3 mils, produces 50 pairs of coupling on lines.It is identical that other all conditions keep, and obtains the response of eye shape pattern.For the eye shape pattern of first kind of coupling on line situation, the dielectric constant of voltage plane substrate is 3.8 o'clock, and the open height of eye shape pattern is 2.5297 volts.For the response of under the same conditions second kind of coupling on line situation, the dielectric constant of voltage plane substrate is 11 o'clock, and the open height of eye shape pattern is 2.6813 volts, increases to some extent than first kind of situation.The eye shape pattern that the voltage plane substrate of high dielectric constant causes again improving responds.

The configuration that also comprises discrete decoupling capacitor except smooth voltage plane substrate is made up the simulation model that carries out Switching Noise (SSN) analysis.This simulation model has 50 pairs of coupling connection transmission lines on 38 micron thickness substrates, the relative dielectric constant of substrate is 3.8, and substrate separates with voltage plane.Transmission line is 3 mils at interval, and long 15 millimeters, wide 2.82 Mills, every line is all being that 99 ohm resistance stops (50 ohm line terminals) to voltage plane and ground plane.In some cases, voltage plane is positioned on the 14 micron thickness substrates relative with ground plane.The relative dielectric constant of substrate is 3.8, and loss angle tangent is 0.02.In other cases, voltage plane is positioned on the 14 micron thickness substrates relative with ground plane, and the relative dielectric constant of substrate is 11, and loss angle tangent is 0.02.With producing 5 gigahertz square wave bit streams, 80 picopulse width, the rising of 20 psecs and all 100 transmission lines of output driver driven in synchronism of fall time, the noise voltage that produces on the acquisition voltage plane.To variety classes, SMT or embedded discrete capacitor and electric capacity quantity are analyzed.Electric capacity is positioned at the somewhere of driver or the end of close transmission line.

In one case, will have 50 pairs of coupling on lines (100 transmission lines altogether), the configuration of 25 SMT electric capacity is placed in the driver tip place of transmission line, online to 1 beginning every a line to locating, next online to 3 beginnings, onlinely finish 50.The dielectric constant of smooth voltage plane substrate is 3.8.Each SMT electric capacity has the capacitance of 100 nanofarads, the equivalent series inductance value (ESL) of about 205 skin henries and the equivalent series impedance (ESR) of 100 milliohms.Use 80 picopulse width, 20 psecs rise and the 5 gigahertz square wave bit streams of fall time come all 100 transmission lines of driven in synchronism, and measure the noise voltage on the voltage plane.Each electric capacity is had 1 nanofarad capacitance, and the embedded discrete capacitor of prosperous equivalent series inductance value (ESL) of about 33 skins and 9 milliohm equivalent series impedances (ESR) repeats aforesaid operations.The dielectric constant of the smooth voltage plane substrate in this configuration is 11.Smooth voltage plane substrate dielectric constant is that change in voltage has approximately-0.1 volt peak to peak change in voltage to+0.15 volt on the voltage plane of 25 SMT electric capacity of 3.8, and smooth voltage plane substrate dielectric constant is that change in voltage has approximately-0.05 volt peak to peak change in voltage to+0.05 volt on the voltage plane of 25 embedded discrete capacitor of 11.Use embedded capacitance and the smooth voltage plane substrate of high dielectric constant, the voltage plane noise that is produced by the synchronous switching of output driver reduces clearly.

Add additional SMT electric capacity to the SMT model, definite SMT electric capacity quantity that the equivalent noise reduction of embedded capacitance configuration can be provided.Simulate 50,75 and 100 SMT electric capacity.Electric capacity is placed in the right driver tip place of each line, obtains the configuration of 50 SMT electric capacity.Add second group of electric capacity, lay respectively at every a driver tip place that line is right, obtain the configuration of 75 electric capacity, add SMT electric capacity, form 2 at first pair of driver tip place and take advantage of 50 capacitor arrays, obtain the configuration of 100 electric capacity to the 50 pair of transmission line.

The flat substrate dielectric constant is that change in voltage has approximately-0.12 volt peak to peak change in voltage to+0.12 volt on the voltage plane of 50 SMT electric capacity of 3.8.The flat substrate dielectric constant is that change in voltage has approximately-0.1 volt peak to peak change in voltage to+0.1 volt on the voltage plane of 75 SMT electric capacity of 3.8.The flat substrate dielectric constant is that change in voltage has approximately-0.075 volt peak to peak change in voltage to+0.1 volt on the voltage plane of 100 SMT electric capacity of 3.8.All 4 SMT capacitance arrangement under the synchronous switching of output driver, have all produced than having 25 electric capacity, and the voltage plane dielectric constant is 11 the higher voltage plane noise of embedded discrete capacitor configuration, or change in voltage.

Claims (28)

1. power supply heart yearn comprises:

At least one embedded surface mounting technique (SMT) discrete monolithic capacitor layer, this layer comprises at least one embedded SMT discrete monolithic capacitor; With

At least one planar capacitor lamination body;

Wherein at least one planar capacitor lamination body provides electric charge as low inductance path at least one embedded SMT discrete monolithic capacitor; With

Described embedded SMT discrete monolithic capacitor is connected to described planar capacitor lamination body in parallel.

2. power supply heart yearn as claimed in claim 1 is characterized in that, described planar capacitor lamination body comprises organic dielectric layer.

3. power supply heart yearn as claimed in claim 1 is characterized in that, described planar capacitor lamination body comprises ceramic dielectric layers.

4. power supply heart yearn as claimed in claim 1 is characterized in that, described planar capacitor lamination body comprises organic dielectric layer of filling ceramic material, and the dielectric constant of the ceramic material in the wherein said layer is greater than 500.

5. power supply heart yearn as claimed in claim 1 is characterized in that, described planar capacitor dielectric layered product comprises organic dielectric layer of filling ceramic material, and the dielectric constant of the ceramic material in the wherein said layer is less than 500.

6. power supply heart yearn as claimed in claim 1 is characterized in that, described planar capacitor lamination body is the layered product of copper-dielectric material-copper.

7. power supply heart yearn as claimed in claim 6 is characterized in that the layered product of described copper-dielectric material-copper comprises one or more dielectric layers, is selected from organic layer, the ceramic layer of organic layer, pottery filling, and their mixture.

8. method of making the power supply core structure comprises:

Planar capacitor lamination with at least one Butut side body is provided; Metal forming is provided; Described metal foil layer is depressed into the Butut side of described planar capacitor lamination body; On described metal forming, form welded disc and path pad; At least one SMT discrete monolithic capacitor is fixed on the described welded disc of described metal forming; And described at least one SMT discrete monolithic capacitor is parallel on the described planar capacitor lamination body.

9. method of making the power supply core structure comprises:

Planar capacitor lamination body with the first Butut side and second Butut side is provided; Metal forming is provided; Described metal foil layer is depressed into a described Butut side of described planar capacitor lamination body; On described metal forming, form welded disc and path pad; At least one SMT discrete monolithic capacitor is fixed on the described welded disc of described metal forming; And described at least one SMT discrete monolithic capacitor is parallel on the described planar capacitor lamination body.

10. method as claimed in claim 8 is characterized in that, adds holding wire and interconnect on identical with described SMT discrete monolithic capacitor layer layer.

11. method as claimed in claim 8 is characterized in that, adds resistor and interconnect on identical with described SMT discrete monolithic capacitor layer layer.

12. method as claimed in claim 8 is characterized in that, adds resistive element on described planar capacitor lamination body, forms the resistor-capacitor element.

13. method as claimed in claim 8 is characterized in that, method formed below described planar capacitor lamination body adopted, and comprising: first metal forming is provided; On described first metal forming, provide first dielectric layer, form the metal forming of first coating; Second metal forming is provided; On described second metal forming, provide second dielectric layer, form the metal forming of second coating; The metal foil layer of described first and second coatings is forced together.

14. method as claimed in claim 8 is characterized in that, method formed below described planar capacitor lamination body adopted, and comprising: first metal forming is provided; On described first metal forming, provide first dielectric layer, form the metal forming of coating with dielectric layer side and metal forming side; Second metal forming is provided; Metal foil layer with described second is pressed on the described dielectric layer side of metal forming of described coating.

15. method as claimed in claim 8 is characterized in that, method formed below described planar capacitor lamination body adopted, and comprising: first metal forming is provided; First dielectric layer with first side and second side is provided; Second metal forming is provided; Simultaneously described first metal foil layer is pressed onto described first side of described dielectric layer and described second metal foil layer is pressed onto described second side of described dielectric layer.

16. method as claimed in claim 8 is characterized in that, method formed below described planar capacitor lamination body adopted, and comprising: first metal forming is provided; On described first metal forming, provide first dielectric layer, thereby the described dielectric material of sintering forms the metal forming of first coating; With formation first electrode on the dielectric material of sintering.

17. method as claimed in claim 8 is characterized in that, described planar capacitor comprises the first metal layer, dielectric layer and second metal level, and wherein at least one metal level adopts and is selected from silk screen printing, sputter and electric plating method formation.

18. a device that comprises the power supply heart yearn, described power supply heart yearn comprises:

At least one embedded surface mounting technique (SMT) discrete monolithic capacitor layer, this layer comprises at least one embedded SMT discrete monolithic capacitor; With

At least one planar capacitor lamination body;

Wherein, at least one planar capacitor lamination body provides electric charge as low inductance path at least one embedded SMT discrete monolithic capacitor;

And wherein said embedded SMT discrete monolithic capacitor is connected to described planar capacitor lamination body in parallel; With

Wherein said power supply heart yearn is interconnected at least one signals layer.

19. device as claimed in claim 18 is characterized in that, described SMT discrete monolithic capacitor comprises at least the first electrode and second electrode.

20. device as claimed in claim 19 is characterized in that, described first electrode and second electrode are connected at least one power tip of semiconductor device.

21. device as claimed in claim 20 is characterized in that, described semiconductor device is an integrated circuit.

22. device as claimed in claim 18 is characterized in that, described device comprises more than one signals layer, and described signals layer connects by conductive path.

23. device as claimed in claim 18 is characterized in that, described device is selected to encapsulate in the encapsulation and system in plate, printed circuit board (PCB), multi-chip module, area array package, system.

24. a method of making device, this method comprises: the body of the planar capacitor lamination with at least one Butut side is provided; Metal forming is provided; Described metal foil layer is depressed into the Butut side of described planar capacitor lamination body; On described metal forming, form welded disc and path pad; At least one SMT discrete monolithic capacitor is fixed on the described welded disc of described metal forming; Described at least one SMT discrete monolithic capacitor is parallel on the described planar capacitor lamination body, forms the power supply heart yearn; With at least one signals layer of formation on described power supply heart yearn.

25. a method of making device, this method comprises: the planar capacitor lamination body with the first Butut side and second Butut side is provided; Metal forming is provided; Described metal foil layer is depressed into a described Butut side of described planar capacitor lamination body; On described metal forming, form welded disc and path pad; At least one SMT discrete monolithic capacitor is fixed on the described welded disc of described metal forming; Described at least one SMT discrete monolithic capacitor is parallel on the described planar capacitor lamination body, forms the power supply heart yearn; With at least one signals layer of formation on described power supply heart yearn.

26., it is characterized in that the formation method of described signals layer is: the one or both sides at described power supply heart yearn apply dielectric layer as claim 24 or 25 described methods; On described dielectric layer, form the circuit that comprises one or more holding wires; And comprise described holding wire the layer between form conductive interconnection.

27. method as claimed in claim 26 is characterized in that, the interconnection between the described layer is a conductive path.

28., it is characterized in that other passive component is connected to and is external to described power supply heart yearn as arbitrary described method in claim 24 or 25.

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