CN1794343A - Method of generating line field signal beneficial to realize digital video frequency image contraction and enlargement interpolation - Google Patents

Abstract

The invention discloses a method for generating line and field signals which is beneficial to realizing zooming and interpolation of digital video images. The method adopts an input line and field signal to modulate an output line and field signal in a bi-cubic interpolation device in a one-dimensional direction, so as to ensure the synchronization between the two , and the cumulative counting cycle length is limited within 63 lines, reducing the cumulative error and meeting the periodicity requirements of the output line and field signals. The line and field signal generation method of the present invention can meet the two requirements of ensuring the periodicity of the output line and field signals and ensuring the synchronization of the input and output line and field signals, so that the data memory of the device does not need fifo buffers before and after, saving hardware resources, and reading Writing control logic is simple.

Description

A Line and Field Signal Generation Method Facilitating Realization of Digital Video Image Scaling and Interpolation

Technical field

The invention belongs to the technical field of digital video image processing and display, and in particular relates to a method for generating line and field signals which is beneficial to realizing scaling and interpolation of digital video images.

Background technique

The digital video image scaling chip (Scaler) is an indispensable part of the flat panel display device, which realizes the function of image resolution conversion, and the image scaling interpolation algorithm is the core algorithm of the digital video image scaling chip.

Commonly used image scaling interpolation algorithms are nearest neighbor interpolation, bilinear interpolation and bicubic interpolation, among which bicubic interpolation has the best effect, but the amount of calculation and hardware implementation complexity are much larger than the former two algorithms.

Figure 1 is a device that saves hardware resources and realizes bicubic interpolation in the one-dimensional direction. One of the keys to supporting and realizing this device is the method for generating the output line and field signals.

In the above-mentioned device for realizing bicubic interpolation in the one-dimensional direction, the input line and field signals control data writing into the memory (line memory such as register bank or point memory such as fifo), and the output line and field signals control the four neighbors around the current interpolation point The data of 4 points in the domain is read from the memory and sent to the interpolation calculation module, and the output data after calculation completes the bicubic interpolation process. The advantage of the device is that no fifo cache is needed before and after the data memory, hardware resources are saved, and the read and write control logic is simple. However, this requires that the writing and reading of the data memory must maintain a certain degree of synchronization, that is, there must be no writing catch-up or delayed reading. At the same time, the device can also realize bilinear interpolation and nearest neighbor interpolation.

In order to realize the device, the requirements for the output line and field signals are:

1. Ensure the periodicity of the output line and field signals. Although flat panel display devices are not as strict as CRTs on the periodicity of video signal lines, panels produced by different manufacturers have different requirements for input line fields. Undoubtedly, outputting standard periodic line field signals will be universal.

2. Guarantee the synchronization of the input and output line and field signals, that is, to meet the synchronization of the read and write operations of the data memory, and there will be no overtaking of reading and writing, and ensure that the pixel values of the 4 fields required for the current interpolation point calculation exist in the data memory And it can be read out under the control of the output row and field signals.

Contents of the invention

Aiming at the problem of line and field signal generation in the image interpolation implementation device proposed in the background art, the purpose of the present invention is to propose a line and field signal generation method that is beneficial to realize scaling and interpolation of digital video images. The method can meet the two requirements of (1) ensuring the periodicity of the output line and field signals (2) ensuring the synchronization of the input and output line and field signals, and is conducive to the realization of the image interpolation implementation device that saves hardware resources mentioned in the background technology .

In order to achieve the above object, the technical solution of the present invention is a method for generating line and field signals that is conducive to realizing digital video image scaling and interpolation, which is characterized in that the method adopts input line and field signal modulation Output the line and field signals to ensure the synchronization of the two, and the length of a cycle of accumulated counting is limited to 63 lines, reducing the accumulation error and meeting the periodicity requirements of the output line and field signals. The method is detailed as follows:

1. Synchronization and periodicity of input and output line and field signals

The data in the image interpolation implementation device proposed in the background technology needs to pass through the memory because the clock domain changes before and after zooming, that is, the point frequency changes; but because the off-chip SDRAM is not used, the field frequency of the video signal cannot be changed, and the field frequency of the video signal cannot be changed. That is, the period of the input and output field synchronization and effective signals remains unchanged, and the data is written into the memory to wait for 3 lines before starting to read the required data for interpolation calculations, so the difference between the input and output field effective signals must be 3 Row time delay. The number of lines in each field before and after scaling, that is, the ratio of the number of input and output line synchronization heads is equal to the scaling factor, that is, if the scaling factor is m/n, then every time m lines are input, n is output line, the time of input line synchronization and valid signal m lines is equal to the time of output line synchronization and valid signal n lines.

The synchronization of the input and output line and field signals is to meet the above (1) The input and output field synchronization and the period of the effective signal are unchanged and the effective signal is different from the time delay of the input 3 lines. (2) The input line synchronization and the effective signal The time of the m line is equal to the two conditions of the synchronization of the output line and the time of the valid signal n line.

The periodicity of the input and output line and field signals means that the line and field synchronization and the number of pixels in each line of the effective signal are consistent, but the flat panel display device can tolerate a certain degree of error.

2. The principle of line synchronization and effective signal generation method

Set the scaling factor as m/n. For the convenience of hardware implementation, the scaling factor is required to be the simplest prime number ratio, and m, n<64 (it can also be 32 if the precision requirement is lowered); additionally, each line of input and output is transmitted Time, that is, the period of the line synchronization signal is hperiod_in and hperiod_out respectively, the total number of pixels in each line is htotal_in, and the input clock cycle is Tclk. According to the above synchronization condition (2), their relationship is:

$\mathrm{<span\; class="notranslate">\; hperiod</span>}<span\; class="notranslate">\; \_</span>\mathrm{<span\; class="notranslate">\; out</span>}<span\; class="notranslate">\; =</span>\mathrm{<span\; class="notranslate">\; hperiod</span>}<span\; class="notranslate">\; \_</span>\mathrm{<span\; class="notranslate">\; in</span>}<span\; class="notranslate">\; *</span>\frac{\mathrm{<span\; class="notranslate">\; m</span>}}{\mathrm{<span\; class="notranslate">\; no</span>}}<span\; class="notranslate">\; =</span>\mathrm{<span\; class="notranslate">\; Tclk</span>}<span\; class="notranslate">\; *</span>\mathrm{<span\; class="notranslate">\; htotal</span>}<span\; class="notranslate">\; \_</span>\mathrm{<span\; class="notranslate">\; in</span>}<span\; class="notranslate">\; *</span>\frac{\mathrm{<span\; class="notranslate">\; m</span>}}{\mathrm{<span\; class="notranslate">\; no</span>}}$

From the above formula, input each $(\mathrm{hnum}\_\mathrm{trans}=\mathrm{htotal}\_\mathrm{in}*\frac{m}{\mathrm{no}})$ The time of a pixel point is the transmission time of one line of output, so as long as the input pixel points are counted in the input clock domain (that is, the input clock is counted), a clear signal is generated every hnum_trans pixel points, and then the output clock is counted By clearing under the action of this signal, the output line synchronization and valid signals can be generated by setting the start and end positions of high level (or low level), and the synchronization requirements are met.

At the same time, the length of a cycle of the above operation is equal to m, that is, every input of m lines is cleared and a new round of counting cycle is restarted, so that the cumulative counting error is limited to the last line of each cycle, that is, the last line of output every n lines There are more or less errors in the number of pixels, but this error is acceptable for flat panel display devices and can be displayed normally, so it meets the periodicity requirements.

3. Principle of field synchronization and effective signal generation method

The falling edge pulse of the input field sync head is used as a clear signal to count the lines of the generated output line sync signal, by setting the high level (or low level) start and end positions, and taking into account the output field valid signal To lag the input time of the effective signal of the input field by 3 lines, the output field synchronous and effective signals can be generated, and the synchronism is satisfied.

Since the output line synchronization and effective signals have met the periodicity requirements of flat panel display devices, the field synchronization and effective signals generated on this basis are simultaneously modulated by the input field synchronization signals, which is sufficient to meet the periodicity requirements.

The line and field signal generation method of the present invention is beneficial to realize the image interpolation implementation device mentioned in the background art, so that the data memory of the device does not need fifo cache before and after, saving hardware resources, and the read and write control logic is simple. The method of the present invention uses the input line and field signal to modulate the output line and field signal, which meets the synchronization of the output line and field signal required by the device, so that the 4-field pixel values required for the current interpolation point calculation exist in the data memory and can be stored in the data memory. Read out under the control of the output line and field signals; in addition, the cumulative counting cycle length is limited within 63 lines to reduce the accumulation error, so that the periodicity of the output line and field signals meets the requirements of the device, so that the scaled video signal can be displayed on the flat panel Normal display on the display device.

Description of drawings

Fig. 1 is a device structure diagram of bicubic interpolation in one-dimensional direction;

Fig. 2 is a schematic diagram of the method for producing line and field signals of the present invention;

Fig. 3 is a schematic diagram of line synchronization and effective signal generation method;

Fig. 4 is a schematic diagram of field synchronization and effective signal generation method;

Fig. 5 is a state transition diagram of the output line counting state machine;

The present invention will be further described in detail below in conjunction with the accompanying drawings.

Detailed ways

Referring to FIG. 2 , the method for generating line and field signals of the present invention modulates input line and field signals to generate output line and field signals, and requires scaling factors and other parameters such as hnum_trans to participate in the calculation. The following describes in detail with reference to FIG. 3 and FIG. 4 .

Referring to Fig. 3, the line synchronization and effective signal generation method of the present invention comprises: trigger signal generation module 1, input row number counting module 2, input clock counting module 3, output clock counting module 4, detailed as follows:

1. Trigger signal generation module

The trigger signal trigger is effective from the falling edge of the first input field sync head after the system reset signal (low active) is reset, and all operations are performed thereafter to ensure the modulation of the input field sync signal to the output line field signal to meet the synchronization sex.

2. Input line number counting module

By counting the input line sync heads, a pulse is generated every three falling edges of the line sync heads, and a loop count clear signal loop_clr is generated, and a new round of count cycle operation is started by forced clearing every m lines input. In this way, the accumulative counting error is limited to the last line of every n lines, so that the periodicity of the output line and field signals meets the requirements of the flat panel display device.

3. Input clock counting module

By counting the pixel points in the input clock domain, a pulse is generated for each count hnum_trans, and the output line synchronous count clear signal ohs_clr is generated. It should be noted that the count is forced to be cleared when it encounters a loop_clr pulse.

4. Output clock counting module

By counting the pixel points in the output clock domain, clearing under the pulse of ohs_clr, and generating the line synchronization signal ohs and the line valid signal according to the line synchronization and valid signal low level start and end parameter values ohs_st, ohs_end, ohref_st, ohref_end values oh ref.

Referring to Fig. 3, the field synchronization of the present invention and valid signal generation method comprise: output line counting state machine module 5, output line number counting module 6, are described in detail as follows:

5. Output line counting state machine module

See Figure 4. The state transition of the state machine is a cycle per field, and the state transition process in one field is state0→state1→state2→state0, and it remains at state0 before the falling edge of the next field synchronization header. , to avoid unnecessary flipping and save power consumption.

If the current state (current state) is state2, a pulse is generated on the falling edge of the line sync head, and the output field sync count clear signal ovs_clr is generated.

It should be noted that all operations are performed when the trigger signal is valid.

6. Output row number counting module

In the output clock domain, count the output line synchronization head, clear it under the pulse of ovs_clr, and generate line synchronization signal ovs and line The effective signal ovblk, especially, the values of ovblk_st and ovblk_end should ensure that the effective ovblk signal in the output field meets the requirement of input 3-line time delay from the effective signal in the input field.

Claims (3)

1. a kind of line and field signal generation method that is beneficial to realizing digital video image scaling interpolation is characterized in that, with input line and field signal modulation output line and field signal, guarantees the synchronism of both, and a cycle length of accumulative counting is limited at 63 Within the line, the cumulative error is reduced to meet the periodicity requirements of the output line and field signals. 2. The method as claimed in claim 1, characterized in that, said line synchronization and valid signal generation method comprise a trigger signal generation module (1), an input row number counting module (2), an input clock counting module (3), an output clock counting module (4); In the trigger signal generation module, the trigger of the trigger signal is effective from the falling edge of the first input field sync head after the system reset signal is reset, and all operations are performed thereafter to ensure the modulation effect of the input field sync signal on the output line field signal, to meet the synchronicity; The input line number counting module counts the input line synchronization head, generates a pulse every three falling edges of the line synchronization head, generates a loop count clear signal loop_clr, and starts a new round of counting cycle operation by force-clearing every m lines input. In this way, the accumulative counting error is limited to the last line of every n lines of output, so that the periodicity of the output line and field signals meets the requirements of the flat panel display device; The input clock counting module counts the pixel points in the input clock domain, generates a pulse every time hnum_trans is counted, and generates the output line synchronous count clear signal ohs_clr. It should be noted that the count is forced to be cleared when encountering the loop_clr pulse; The output clock counting module counts the pixels in the output clock domain, clears under the pulse of ohs_clr, and generates the line synchronization signal ohs according to the line synchronization and valid signal low level start and end parameter values ohs_st, ohs_end, ohref_st, ohref_end value And line valid signal ohref. 3. The method according to claim 1, characterized in that, said field synchronization and valid signal generation method comprise: output line counting state machine module (5), output line number counting module (6); Each field of the output line counting state machine module is a cycle in the state transition, and its state transition process in one field is state0→state1→state2→state0, and it remains at state0 before the falling edge of the next field synchronization head. Avoid unnecessary flipping and save power consumption; If the current state (current state) is state2, a pulse is generated on the falling edge of the line sync head, and the output field sync count clear signal ovs_clr is generated; All operations are performed when the trigger signal is valid; The output line number counting module counts the output line synchronization head in the output clock domain, clears it under the pulse of ovs_clr, and generates lines according to the field synchronization and valid signal low level start and end parameter values ovs_st, ovs_end, ovblk_st, ovblk_end Synchronization signal ovs and line effective signal ovblk, in particular, the values of ovblk_st and ovblk_end should ensure that the output field effective ovblk signal meets the requirement of input 3-line time delay from the input field effective signal.