CN1790676A - Method for operating single grid non-volatile memory with multi-bit memory - Google Patents
Method for operating single grid non-volatile memory with multi-bit memory Download PDFInfo
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- CN1790676A CN1790676A CN 200410100776 CN200410100776A CN1790676A CN 1790676 A CN1790676 A CN 1790676A CN 200410100776 CN200410100776 CN 200410100776 CN 200410100776 A CN200410100776 A CN 200410100776A CN 1790676 A CN1790676 A CN 1790676A
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Abstract
The presented single-grid non-volatile memory with multi-bit storage uses single grid as storage unit. Wherein, arranging a transistor with a first conductive grid stacked on a dielectric layer surface and ion doping zones as source and drain on two sides and a capacitor structure with an ion doping zone with stacked dielectric layer and second conductive grid connected to the one of transistor to form single-floating grid for storage unit on P/N-type semiconductor substrate. This invention forces variable grid voltage to generate initial voltage and realize multi-bit storage.
Description
Technical field
The present invention is the method for operation of relevant a kind of non-volatility memorizer (Non-Volatile Memory), particularly has the method for operation of the non-volatility memorizer of many bits storages about a kind of workshop.
Background technology
Memory is broadly divided into two classes, is respectively volatility and non-volatile memory element, and after its maximum difference was power-off, the data on file of non-volatile memory element still can continue to be saved, and also can repeat to revise its content in the mode of energising simultaneously.Complementary metal oxide semiconductor (Complementary Metal Oxide Semiconductor, CMOS) process technique has become Application Specific Integrated Circuit (application specific integrated circuit, ASIC) manufacture method commonly used, in today of computing information product prosperity, but because the electronic type clear program read only memory (the Electrically ErasableProgrammable Read Only Memory in the non-volatility memorizer, EEPROM) as long as on the grid of its memory cell, impose suitable negative voltage, just can reach the effect of removing data, need not from system, remove, possess the non-volatility memorizer function of electrically writing with erase data is arranged, and turn off the back data at power supply and can not lose, therefore be widely used on the electronic product.
Figure 1 shows that the non-volatile memory cell of EEPROM of a known single grid, non-volatile memory cell 10 is provided with semiconductor substrate 102, it is provided with an one source pole 104 and a drain electrode 106 in both sides, and at the source electrode 104 and formation one path 10 8 between 106 that drains, and on surface, the semiconductor-based ends 102, fold and establish monoxide layer 110, mononitride layer 112, a monoxide layer 114 and a grid layer 116, this non-volatile memory cell 10 is carrying out that sequencing writes and when erasing, enough big voltage need be arranged to offer source electrode 104 and to drain 106, via the passage of High Pressure Difference, so that carry out above-mentioned action to form.
In non-volatility memorizer, be provided with the non-volatile memory cell of number, non-volatile memory cell is programmable, in order to store charge to change the transistorized starting voltage of memory cell, or not store charge to stay the transistorized starting voltage of former memory cell, erase operation for use then is that all electric charges that will be stored in the non-volatile memory cell remove, make all non-volatile memory cell get back to the transistorized starting voltage of former memory cell, many bits store operation method of known non-volatile memory cell, be to reach the purpose that many bits store to decide the voltage change time, but because control is difficult for, need perimeter circuit auxiliary examination starting voltage whether to reach fixed point, cause cost raising and time to expend.
Supervise in this, The present invention be directed to above-mentioned puzzlement, propose the method for operation of the non-volatility memorizer of the many bits storages of a kind of single grid tool, to improve above-mentioned shortcoming.
Summary of the invention
Main purpose of the present invention is in the method for operation that a kind of single grid tool non-volatility memorizer that many bits store is provided, and is to utilize the change grid voltage to produce different starting voltages to reach the purpose that many bits store.
According to the present invention, one single grid EEPROM memory cell comprises a metal-oxide half field effect transistor (Metal-Oxide-Semiconductor FET, MOSFET) and a capacitance structure, wherein MOSFET comprises a conductive grid and is stacked on a dielectric film surface, dielectric film is to be positioned in a P type or the N type semiconductor substrate, and has the N type of two highly conductives or P type ion doped region to be positioned at two sides to form source electrode and drain electrode; Capacitance structure also forms the top board-dielectric layer-top board structure of a picture sandwich as transistor, the top board of capacitance structure and the grid of MOSFET are isolation and are electrically connected, and the grid of the top board of capacitance structure and MOSFET is the single suspension joint grid that forms the EEPROM memory cell.
The mode of operation of this list grid EEPROM memory cell is utilized to change grid voltage to reach starting voltage reprogramming mode.Allly utilize mode of the present invention to make the EEPROM element carry out the operation of sequencing, all in scope of the present invention with different structural changes.
Description of drawings
Below by after the specific embodiment conjunction with figs. explanation, when the effect that is easier to understand purpose of the present invention, technology contents, characteristics and is reached, wherein:
Figure l is the structure cutaway view of the non-volatile memory cell of EEPROM of known single grid.
Fig. 2 is the structure cutaway view of the non-volatile memory cell of EEPROM of single grid of the present invention.
Fig. 3 is provided with the schematic diagram of four end points for the EEPROM memory cell of single grid of Fig. 2.
Fig. 4 is the equivalent circuit diagram of Fig. 3.
Fig. 5 is another structure cutaway view of the non-volatile memory cell of EEPROM of single grid of the present invention.
Fig. 6 is provided with the schematic diagram of four end points for the EEPROM memory cell of single grid of Fig. 5.
Embodiment
The present invention proposes the method for operation of the non-volatility memorizer of the many bits storages of a kind of single grid tool, is to utilize to change grid voltage to reach the purpose that changes starting voltage.
Fig. 2 is the structure cutaway view of first embodiment of single grid EEPROM memory cell of the present invention, one single grid EEPROM memory cell 20 comprises a P type semiconductor substrate 22, as silicon base, and a metal-oxide half field effect transistor (NMOSFET) 24 and N well (N-well) electric capacity 26 is set in P type semiconductor substrate 22, nmos pass transistor 24 comprises one first dielectric layer 242 and is positioned on P type semiconductor substrate 22 surfaces, and have one first conductive grid 244 to be stacked at first dielectric layer, 242 tops, and two N
+Ion doped region is positioned at P type semiconductor substrate 22, respectively as its source electrode 246 and drain 248, at source electrode 246 with drain 248 and form a passage 250; N well electric capacity 26 comprises an ion doped region in P type semiconductor substrate 22, be its N well 262, one second dielectric layer 264 is positioned on N well 262 surfaces, and one second conductive grid 266 is stacked at second dielectric layer, 264 tops, forms the capacitance structure of top board-dielectric layer-base plate; First conductive grid 244 of nmos pass transistor 24 and second conductive grid 266 of N well electric capacity 26 is electrically connected and isolate with an isolated material 28 forms the structure of a single suspension joint grid (floating gate) 30.
This single grid EEPROM memory cell 20 is provided with four end points, its schematic diagram as shown in Figure 3, these four end points are respectively source electrode, drain electrode, control grid and substrate syndeton, and apply a basic voltage V respectively on the semiconductor-based end, source electrode, drain electrode, first ion doped region
Substrate, source electrode line voltage V
Source, drain line voltage V
Drain, control gate pole tension V
Control, and Fig. 4 is its equivalent electric circuit, the method for operation condition that many bits of this single grid EEPROM memory cell 20 store is as follows:
(1) utilize the change of grid voltage to reach the sequencing that starting voltage changes:
A. this basic voltage V
SubstrateBe ground connection (=0); And
B.V
Source＞V
Substrate=0 (make source electrode-substrate connect face and produce reverse bias), and its＜V
Drain(drain current generation).
So, Vcontrol＞Vdrain＞Vsource＞Vsubstrate=O (open NMOS FET and generation grid current), wherein Vcontrol changes according to sequencing starting voltage demand difference.
Fig. 5 is the structure cutaway view of another embodiment of single grid EEPROM memory cell, and it is to comprise a N type semiconductor substrate 50, and it is to be provided with a PMOS transistor 52 and P well (P-well) electric capacity 54; The top grid 542 of the grid 522 of p channel metal oxide semiconductor transistor (PMOS) 52 and P well electric capacity 54 is electrically connected and is isolated with an isolated material 56, and forms the structure of a suspension joint grid 60.
The condition that the sequencing that starting voltage changes is reached in the grid voltage of change carry out to(for) single grid EEPROM memory cell 50 of Fig. 5 is as follows, and please consults Fig. 6 simultaneously:
(1) utilize the change of grid voltage to reach the sequencing that starting voltage changes:
A. this basic voltage Vsubstrate is ground connection (=0): and
B.Vsource＜Vsubstrate=0 (make source electrode-substrate connect face and produce reverse bias), and its＞Vdrain (drain current generation).
So, Vcontrol＜Vdrain＜Vsource＜Vsubstrate=0 (open PMOSFET and produce grid current), wherein Vcontrol changes according to sequencing starting voltage demand difference.
In the present invention, when sequencing, Vcontrol changes according to sequencing starting voltage demand difference, and applies one really useful (non-trivial) voltage in the source electrode of single gate MOS FET, and the potential drop between source electrode and drain electrode will allow the passage carrier to move to drain electrode from source electrode.
The present invention proposes the method for operation of the non-volatility memorizer of the many bits storages of a kind of single grid tool, be to utilize to change grid voltage to reach the purpose that changes starting voltage, and when sequencing, source electrode is applied a real useful voltage, volume is little to reach, the cost of the single grid EEPROM element of reduction, and has the effect of shortening time.
The above is by embodiment characteristics of the present invention to be described, its purpose makes the personage who has the knack of this technology can understand content of the present invention and is implementing according to this, and non-limiting claim of the present invention, the equivalence finished is modified so all other do not break away from disclosed spirit or revise, and must be included in the described claim.
Claims (12)
1. the method for operation of the non-volatility memorizer that stores of the many bits of a single grid tool, it is can produce different starting voltages to reach the purpose that many bits store with changing grid voltage, it is characterized in that, this non-volatility memorizer, comprise a P type semiconductor substrate, it is provided with a transistor, this transistor is respectively arranged with as several first ion doped regions of source electrode and drain electrode and one first conductive grid, in this P type semiconductor substrate and be provided with a capacitance structure, it is to comprise one second conductive grid and one second ion doped region, and this first conductive grid and this second conductive grid are connected to form a single suspension joint grid, and apply a basic voltage, one source pole line voltage, an one drain line voltage and a control gate pole tension are in this P type semiconductor substrate, this source electrode, this drain electrode, on this first ion doped region, the method of operation of the non-volatility memorizer that the many bits of this list grid tool store comprises: implement a programmed process, this source voltage is to be higher than this basic voltage, and much smaller than this control sluice voltage.
2. the method for operation of the non-volatility memorizer that the many bits of single grid tool as claimed in claim 1 store is characterized in that, wherein, this transistor is for being to be metal-oxide half field effect transistor.
3. the method for operation of the non-volatility memorizer that the many bits of single grid tool as claimed in claim 1 store is characterized in that wherein, this first ion doped region and this second ion doped region are to be the N type.
4. the method for operation of the non-volatility memorizer that stores of the many bits of a single grid tool, it is in order to change the starting voltage of a non-volatility memorizer, it is characterized in that, this non-volatility memorizer comprises a P type semiconductor substrate, it is provided with a N well, one transistor, this transistor is respectively arranged with as several first ion doped regions of source electrode and drain electrode and one first conductive grid, in this P type semiconductor substrate and be provided with a capacitance structure, it is to comprise one second conductive grid and one second ion doped region, and this first conductive grid and this second conductive grid are connected to form a single suspension joint grid, and apply a well voltage, one basic voltage, one source pole line voltage, an one drain line voltage and a control gate pole tension are in this N well, this P type semiconductor substrate, this source electrode, this drain electrode, on this first ion doped region, the method of operation of the non-volatility memorizer that the many bits of this list grid tool store comprises: implement a programmed process, this drain voltage is higher than this source voltage, this source voltage is higher than this control sluice voltage, and this control sluice voltage is to be higher than this basic voltage.
5. the non-volatility memorizer De Shu that the many bits of single grid tool as claimed in claim 4 store makes method, it is characterized in that, wherein, this transistor is for being to be metal-oxide half field effect transistor.
6. the method for operation of the non-volatility memorizer that the many bits of single grid tool as claimed in claim 4 store is characterized in that wherein, this first ion doped region and this second ion doped region are to be the N type.
7. the method for operation of the non-volatility memorizer that stores of the many bits of a single grid tool, it is in order to change the starting voltage of a non-volatility memorizer, it is characterized in that, this non-volatility memorizer comprises a N type semiconductor substrate, it is provided with a transistor, this transistor is respectively arranged with as several first ion doped regions of source electrode and drain electrode and one first conductive grid, in this N type semiconductor substrate and be provided with a capacitance structure, it is to comprise one second conductive grid and one second ion doped region, and this first conductive grid and this second conductive grid are connected to form a single suspension joint grid, and apply a basic voltage, one source pole line voltage, an one drain line voltage and a control gate pole tension are in this N type semiconductor substrate, this source electrode, this drain electrode, on this first ion doped region, the method of operation of the non-volatility memorizer that the many bits of this list grid tool store comprises: implement a programmed process, this basic voltage is that ground connection is swept F zero but near the nought state state, this source electrode and drain voltage are to be lower than this basic voltage, and far above this control sluice voltage.
8. the method for operation of the non-volatility memorizer that the many bits of single grid tool as claimed in claim 7 store is characterized in that, wherein, this transistor is for being to be metal-oxide half field effect transistor.
9. the method for operation of the non-volatility memorizer that the many bits of single grid tool as claimed in claim 7 store is characterized in that wherein, this first ion doped region and this second ion doped region are to be the P type.
10. the method for operation of the non-volatility memorizer that stores of the many bits of a single grid tool, it is in order to change the starting voltage of a non-volatility memorizer, it is characterized in that, this non-volatility memorizer comprises a N type semiconductor substrate, it is provided with a P well, one transistor, this transistor is respectively arranged with as several first ion doped regions of source electrode and drain electrode and one first conductive grid, in this N type semiconductor substrate and be provided with a capacitance structure, it is to comprise one second conductive grid and one second ion doped region, and this first conductive grid and this second conductive grid are connected to form a single suspension joint grid, and apply a well voltage, one basic voltage, one source pole line voltage, an one drain line voltage and a control gate pole tension are in this P well, this N type semiconductor substrate, this source electrode, this drain electrode, on this first ion doped region, the method of operation of the non-volatility memorizer that the many bits of this list grid tool store comprises: implement a programmed process, this basic voltage is ground connection/non-zero but near the nought state state, this source voltage is to be higher than this well voltage, this drain voltage is higher than this source voltage, and this control sluice voltage is to be higher than this source voltage and less than this basic voltage.
11. the method for operation of the non-volatility memorizer that the many bits of single grid tool as claimed in claim 10 store is characterized in that, wherein, this transistor is for being to be metal-oxide half field effect transistor.
12. the method for operation of the non-volatility memorizer that the many bits of single grid tool as claimed in claim 10 store is characterized in that wherein, this first ion doped region and this second ion doped region are to be the P type.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 200410100776 CN1790676A (en) | 2004-12-14 | 2004-12-14 | Method for operating single grid non-volatile memory with multi-bit memory |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 200410100776 CN1790676A (en) | 2004-12-14 | 2004-12-14 | Method for operating single grid non-volatile memory with multi-bit memory |
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| CN1790676A true CN1790676A (en) | 2006-06-21 |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101577286B (en) * | 2008-05-05 | 2012-01-11 | 联华电子股份有限公司 | Compound type transfer grid and production method thereof |
| CN108231776A (en) * | 2016-12-14 | 2018-06-29 | 中芯国际集成电路制造(上海)有限公司 | A kind of SRAM memory cell and its manufacturing method and electronic device |
-
2004
- 2004-12-14 CN CN 200410100776 patent/CN1790676A/en active Pending
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101577286B (en) * | 2008-05-05 | 2012-01-11 | 联华电子股份有限公司 | Compound type transfer grid and production method thereof |
| CN108231776A (en) * | 2016-12-14 | 2018-06-29 | 中芯国际集成电路制造(上海)有限公司 | A kind of SRAM memory cell and its manufacturing method and electronic device |
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