CN101577286B - Compound type transfer grid and production method thereof - Google Patents
Compound type transfer grid and production method thereof Download PDFInfo
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- CN101577286B CN101577286B CN2008100953647A CN200810095364A CN101577286B CN 101577286 B CN101577286 B CN 101577286B CN 2008100953647 A CN2008100953647 A CN 2008100953647A CN 200810095364 A CN200810095364 A CN 200810095364A CN 101577286 B CN101577286 B CN 101577286B
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Abstract
The invention relates to a compound type transfer grid which is positioned above a semiconductor base arranged between an electronic accumulation region in the semiconductor base and a floating node; and the compound type transfer grid comprises at least one transversely arranged N-shaped part and a P-shaped part.
Description
Technical field
The invention relates to semiconductor structure and manufacturing approach thereof, particularly about placing the compound type transfer grid (transfer gate) and the manufacturing approach thereof of electronics accumulation zone (electron reservoir) and floating node (floating node).
Background technology
The two the combination of transfer gate of electronics accumulation zone, floating node collocation is common in the various dissimilar signal transducers; For example be complement metal oxide semiconductor image sensor (CMOS Image Sensor); Its each pixel disposes 4 metal oxide semiconductor transistors usually, comprises transfering transistor.
In traditional complement metal oxide semiconductor image sensor, transfer gate is the same with floating node to be that full N type mixes.Yet, must below transfer gate with in the electronics accumulation zone, form extra P sprig bundle (pinning) doped region when adopting this design to reduce dark current, make full well region capacity (Full Well Capacity) reduce, thereby reduced the assorted ratio of news of transducer.Simultaneously, this kind design also is difficult to take into account simultaneously that dark current reduces effect and picture delay prevents effect.
Therefore, the transfer gate that existing some complement metal oxide semiconductor image sensor adopts full P type to mix so promptly needn't form extra pinning doped region, and full well region capacity is reduced.Yet; Can significantly raise near the start voltage below the part transfer gate of floating node when adopting this design; So can hinder the electronics transmission and cause picture delay, also can cause electric charge to inject problem (charge injection issue) and the noise of increase photodiode simultaneously.
Summary of the invention
In view of this, the present invention provides a kind of compound type transfer grid, itself or can be applicable to the transfering transistor of electronic image sensor, reduce effect and picture delay prevents the problem that effect can't be taken into account simultaneously with full well region capacity, the dark current that solves prior art.
The present invention also provides the manufacturing approach of above-mentioned compound type transfer grid.
Between the electronics accumulation zone and a floating node of compound type transfer grid of the present invention in the semiconductor substrate, comprising: transversely arranged an at least one N type part and a P type part.
In one embodiment, above-mentioned N type partly has only one, and the position is at the edge towards floating node of compound type transfer grid.In another embodiment, above-mentioned N type partly has only one, and the position is in the middle of P type part.In another embodiment, above-mentioned N type partly has at least two, comprises N type part and position at least one two N type part P type part in the middle of towards the edge of floating node of position at compound type transfer grid.In another embodiment, above-mentioned N type partly has at least two, and all the position is in the middle of P type part.
In addition, above-mentioned at least one N type part can have a horizontal N type doping content Gradient distribution, particularly when its compound type transfer grid towards the edge of floating node the time.
In certain embodiments, when the width of compound type transfer grid during greater than 0.45 μ m, the width of above-mentioned at least one N type part and P type part is than less than 1/4.When the width of compound type transfer grid during smaller or equal to 0.45 μ m, this width is than less than 1/3.
In certain embodiments, above-mentioned compound type transfer grid and electronics accumulation zone, this floating node belong to the member of an optical pickocff, and this optical pickocff for example is complement metal oxide semiconductor image sensor (CMOS Image Sensor).
One of manufacturing approach of compound type transfer grid of the present invention comprises the following steps.At first form a p type semiconductor layer in the substrate top, the patterning p type semiconductor layer is to form a gate conductor layer again.Then form a mask layer in the substrate top, it exposes the part of gate conductor layer, carries out a N type ion again and injects, so that this part of gate conductor layer becomes a N type part.
In certain embodiments, above-mentioned gate conductor layer expose the part be its one edge part towards floating node.Under this situation, the aforementioned mask layer can be designed to expose simultaneously gate conductor layer and a part of substrate above-mentioned marginal portion homonymy, and above-mentioned N type ion injects and forms floating node in this part substrate simultaneously.In addition, can carry out another time N type ion after above-mentioned N type ion injects and inject, in the middle of gate conductor layer, to form at least one extra N type part.
In addition, the dosage of above-mentioned N type ion injection for example is between 10
13/ cm
2To 10
14/ cm
2Between.When the width of compound type transfer grid during greater than 0.45 μ m, N type part can be less than 1/4 with the width ratio of this P type part.When the width of compound type transfer grid during smaller or equal to 0.45 μ m, this width ratio can be less than 1/3.
Two of the manufacturing approach of compound type transfer grid of the present invention comprises the following steps.At first; Form a doping semiconductor layer in the substrate top; It has a transversely arranged and continuous P matrix Duan Yuyi N matrix section, and this doping semiconductor layer of patterning is to form a gate conductor layer again, and it comprises a P type part of a part that is P matrix section originally; And be a N type part of the part of N matrix section originally, wherein N type part is towards the direction of floating node.
The manufacturing approach of above-mentioned compound type transfer grid can comprise also that carrying out N type ion injects, in the middle of P type part, to form at least one extra N type part.The dosage that this N type ion injects for example is between 10
13/ cm
2To 10
14/ cm
2Between.
As stated; Compound type transfer grid of the present invention comprises N type part and P type part; It is compared down with the known transfer gate that mixes for N entirely, does not need extra pinning doped region can reduce dark current, so can take into account full well region capacity and dark current reduction effect simultaneously; And compare down with the complete known transfer gate that mixes for P, its N type partly can reduce the start voltage of transfering transistor, especially when this N type partly be positioned at compound type transfer grid towards the edge of floating node the time, so can alleviate the problem of image hysteresis.
For let above-mentioned and other purposes of the present invention, feature and advantage can be more obviously understandable, hereinafter is special lifts preferred embodiment, and cooperates appended diagram, elaborates as follows.
Description of drawings
Fig. 1 is the part sectioned view of complement metal oxide semiconductor image sensor unit that comprises the compound type transfer grid of one embodiment of the invention.
Fig. 2 A～2E illustrates the present invention's structure of the compound type transfer grid of 5 embodiment in addition respectively.
Fig. 3 A～3D illustrates the process section of complement metal oxide semiconductor image sensor of the manufacturing approach of the compound type transfer grid that adopts one embodiment of the invention.
Fig. 4～6 illustrate the present invention's manufacturing approach of the compound type transfer grid of 3 embodiment in addition respectively.
[main element symbol description]
100: the semiconductor-based end
102: separator
104:P type field doped layer
106: compound type transfer grid
108a, 108b, 108a ': N type part
110:P type part
112: gate dielectric layer
114: clearance wall
116: the replacement grid
118,118a:N type doped region (floating node), its extension area
120:N type doped region (electronics accumulation zone)
300,400,500,600: doping semiconductor layer
300a, 400a, 500a, 600a:N matrix section
300b, 400b, 500b, 600b:P matrix section
302,304,308: patterning photoresist layer
306,312:N type ion injects
310: opening
Embodiment
Fig. 1 is the part sectioned view of complement metal oxide semiconductor image sensor unit that comprises the compound type transfer grid of one embodiment of the invention.This complement metal oxide semiconductor image sensor is a kind of optical pickocff.
Please with reference to Fig. 1, be formed with separator 102 at semiconductor-based the end 100, surround the P type field doped region 104 of separator 102, as the N type doped region 118 of floating node and as the N type doped region 120 of electronics accumulation zone.Compound type transfer grid 106 is disposed at substrate 100 tops between floating node 118 and the electronics accumulation zone 120; Comprise that P type part 110 and position are at the N type part 108a towards the edge of floating node 118; And and 100 of substrates are separated with gate dielectric layer 112, and a doped region 104 extends to N type part 108a below.The width of N type part 108a is preferably less than 0.15 μ m.When the width of compound type transfer grid 106 during greater than 0.45 μ m, the width of this N type part 108a and P type part 110 is than preferably less than 1/4.When the width of compound type transfer grid 106 during smaller or equal to 0.45 μ m, the width of this N type part 108a and P type part 110 is than preferably less than 1/3.
This sensor unit also comprises replacement grid 116, and it is positioned at the top of the gate dielectric layer 112 in the substrate 100, and relative with compound type transfer grid 106 across floating node 118.In addition, floating node doped region 118 can have extension area 118a, and the sidewall of compound type transfer grid 106 and replacement grid 116 disposes clearance wall 114 usually.N type doped region 120 as the electronics accumulation zone constitutes a photodiode with substrate 100.
Though the compound type transfer grid 106 of above embodiment has only a N type part 108a; And this N type part 108a position is at the edge towards floating node 118 of compound type transfer grid 106; But the number of N type part can be more than 1, and also configurable in other positions.Fig. 2 A～2E illustrates the present invention's structure of the compound type transfer grid of 5 embodiment in addition respectively.
Please with reference to Fig. 2 A, the N type part 108b of this embodiment also has only one, and its position is middle in P type part 110, and P type part 110 is separated into two 106.
Please with reference to Fig. 2 B; The N type of this embodiment partly has two; Comprise the N type part 108a that is positioned at compound type transfer grid 106 towards the edge of floating node 118, and the N type part 108b of position in the middle of P type part 110, the latter is separated into two with P type part 110.
Please with reference to Fig. 2 C, the N type part 108b of this embodiment also has two, and all the position is middle in P type part 110 for it, and P type part 110 is separated into 3.
Please with reference to Fig. 2 D, the N type part 108a ' of this embodiment has only one, its be positioned at compound type transfer grid 106 towards the edge of floating node 118, and a horizontal N type doping content Gradient distribution is arranged.
Please with reference to Fig. 2 E, the compound type transfer grid 106 of this embodiment except have aforementioned N type part 108a ', still have the N type part 108b of position in the middle of P type part 110, it is separated into two with P type part 110.Moreover the N type part 108b of this kind position in the middle of P type part 110 also can have horizontal N type doping content Gradient distribution.
Fig. 3 A～3D illustrates the process section of a complement metal oxide semiconductor image sensor of the manufacturing approach of the compound type transfer grid that adopts one embodiment of the invention.
Please with reference to Fig. 3 A, at first being provided the semiconductor-based end 100, for example is a p type single crystal silicon substrate, wherein has been formed with separator 102 and the P type field doped region 104 that surrounds separator 102.Then in substrate 100, form gate dielectric layer 112 and doping semiconductor layer 300 in regular turn, it for example is a doping compound crystal silicon layer.Doping semiconductor layer 300 comprises N matrix section 300a and P matrix section 300b, and it comprises the predetermined part and the predetermined part that forms compound type transfer grid 106 that forms replacement grid 116 respectively.Then on doping semiconductor layer 300, form patterning photoresist layer 302, it covers the part of the predetermined formation replacement grid 116 of N matrix section 300a, and the part of the predetermined formation compound type transfer grid 106 of P matrix section 300b.In addition, the formation method of above-mentioned doping semiconductor layer 300 for example is that the unadulterated semiconductor layer of formation carries out N type ion to the zone of correspondence respectively again and injects and the injection of P type ion earlier.
Please with reference to Fig. 3 B; With patterning photoresist layer 302 be the mask etching replacement grid 116 that forms the N type with the TG transfer gate conductor layer 106 ' of P type afterwards; Remove patterning photoresist layer 302, in substrate 100, form again the N type the floating node doped region extension area 118a and as the N type doped region 120 of the part of photodiode.
Please with reference to Fig. 3 C; Then form clearance wall 114 in replacement grid 116 and TG transfer gate conductor layer 106 ' sidewall; Form patterning photoresist layer 304 then in substrate 100 tops; It exposes part and the substrate 100 between replacement grid 116 and the TG transfer gate conductor layer 106 ' of the predetermined formation N type part 108a of TG transfer gate conductor layer 106 ', carries out N type ion injection 306 again, and dosage is for example between 10
13/ cm
2To 10
14/ cm
2Between, be preferably 5 * 10
13/ cm
2,, form floating node 118 in the substrate 100 between replacement grid 116 and TG transfer gate conductor layer 106 ' simultaneously to form N type part 108a.The part except that N type part 108a of TG transfer gate conductor layer 106 ' is P type part 110.
Please, after N type part 108a formation, patterning photoresist layer 304 are removed, can carry out another time N type ion and inject 312, in the middle of P type part 110, to form at least one extra N type part 108b with reference to Fig. 3 D.It is the patterning photoresist layer 308 that is formed on substrate 100 tops that this N type ion injects 312 used mask layers, wherein has at least one opening 310 to expose the part of the extra N type of the predetermined formation part 108b of P type part 110.
Fig. 4～6 illustrate the present invention's manufacturing approach of the compound type transfer grid of 3 embodiment in addition respectively.
Please with reference to Fig. 4, this embodiment is after gate dielectric layer 112 forms, and forms doping semiconductor layer 400 on it, and it comprises transversely arranged and continuous N matrix section 400a and P matrix section 400b.N matrix section 400a comprises the predetermined part that forms replacement grid 116, and its marginal portion promptly is the predetermined N type part 108a that forms compound type transfer grid 106; P matrix section 400b then comprises the predetermined part that forms the P type part 110 of compound type transfer grid 106.Then on doping semiconductor layer 400, form the patterning photoresist layer 302 of definition replacement grid 116 and compound type transfer grid 106 usefulness; It covers the part of the predetermined formation replacement grid 116 of N matrix section 400a, and the two the part of predetermined formation compound type transfer grid 106 of N matrix section 400a and P matrix section 400b.Be mask etching doping semiconductor layer 400 then, can obtain comprising the N type part 108a at edge and the compound type transfer grid 106 of P type part 110 with patterning photoresist layer 302.
Moreover, please compare Fig. 3 D, this embodiment also can carry out a N type ion and inject after the compound type transfer grid that comprises edge N type part 108a and P type part 110 106 forms, and its dosage is for example between 10
13/ cm
2To 10
14/ cm
2Between, be preferably 5 * 10
13/ cm
2, in the middle of P type part 110, to form at least one extra N type part 108b, as last embodiment.
Please with reference to Fig. 5, the formed doping semiconductor layer 500 of this embodiment comprises N matrix section 500a and P matrix section 500b.N matrix section 500a comprises the predetermined part that forms replacement grid 116, and P matrix section 500b then comprises the predetermined part that forms compound type transfer grid 106, and also has a N type part 108b to be positioned at the centre of this part of the predetermined P of formation type part 110 wherein.So; After the patterning photoresist layer 302 with definition replacement grid 116 and compound type transfer grid 106 is mask etching doping semiconductor layer 500, can obtain comprising the compound type transfer grid 106 of a P type part 110 and a middle N type part 108b thereof.
Please with reference to Fig. 6; The difference of the doping semiconductor layer 500 of formed doping semiconductor layer 600 of this embodiment and last embodiment only has two N type part 108b to be positioned at the centre of the part of the P type part 110 of being scheduled to formation compound type transfer grid 106 in the middle of its P matrix section 600b.So; After the patterning photoresist layer 302 with definition replacement grid 116 and transfer gate 106 is mask etching N matrix section 600a and P matrix section 600b, can obtain comprising the compound type transfer grid 106 of P type part 110 and middle two N type part 108b thereof.
Though the present invention discloses as above with preferred embodiment; Right its is not that any those skilled in the art is not breaking away from the spirit and scope of the present invention in order to qualification the present invention; When can doing a little change and retouching, so protection scope of the present invention is as the criterion when looking the claim person of defining.
Claims (23)
1. compound type transfer grid, the electronics accumulation zone in the semiconductor-based end and above this semiconductor-based end between the floating node comprises: transversely arranged an at least one N type part and a P type part; It is characterized in that this laterally is the direction from this floating node to this electronics accumulation zone.
2. compound type transfer grid as claimed in claim 1, wherein the N type partly has only one, and the position is at the edge towards this floating node of this compound type transfer grid.
3. compound type transfer grid as claimed in claim 1, wherein the N type partly has only one, and the position is in the middle of this P type part.
4. compound type transfer grid as claimed in claim 1, wherein the N type partly has at least two, comprises the N type part towards the edge of this floating node of position at this compound type transfer grid, and at least one two N type part of position in the middle of this P type part.
5. compound type transfer grid as claimed in claim 1, wherein the N type partly has at least two, and all the position is in the middle of this P type part.
6. compound type transfer grid as claimed in claim 1, wherein this at least one N type partly has horizontal N type doping content Gradient distribution.
7. compound type transfer grid as claimed in claim 6, wherein this at least one N type part position is at the edge towards this floating node of this compound type transfer grid.
8. compound type transfer grid as claimed in claim 1, wherein the width of this compound type transfer grid is greater than 0.45 μ m, and the width of this at least one N type part and this P type part is than less than 1/4.
9. compound type transfer grid as claimed in claim 1, wherein the width of this compound type transfer grid is smaller or equal to 0.45 μ m, and the width of this at least one N type part and this P type part is than less than 1/3.
10. compound type transfer grid as claimed in claim 1, itself and this electronics accumulation zone, this floating node belong to the member of an optical pickocff.
11. compound type transfer grid as claimed in claim 10, wherein this optical pickocff is a complement metal oxide semiconductor image sensor.
12. the manufacturing approach of a compound type transfer grid, this compound type transfer grid in the semiconductor-based end the electronics accumulation zone and above this semiconductor-based end between the floating node, this method comprises:
Form p type semiconductor layer in this substrate top;
This p type semiconductor layer of patterning is to form gate conductor layer;
Form mask layer in this substrate top, it exposes the part of this gate conductor layer; And
Carrying out N type ion injects; So that this part of this gate conductor layer becomes N type part; Other parts except that this N type part of this gate conductor layer are to be P type part, the direction arrangement along this floating node to this electronics accumulation zone of this N type part and this P type part.
13. the manufacturing approach of compound type transfer grid as claimed in claim 12, wherein this part position that exposes of this gate conductor layer is at the edge towards this floating node of this gate conductor layer.
14. the manufacturing approach of compound type transfer grid as claimed in claim 13, wherein this mask layer also exposes a part of substrate of this edge side of this gate conductor layer, and this N type ion injects simultaneously at this this floating node of part substrate formation.
15. the manufacturing approach of compound type transfer grid as claimed in claim 13 comprises that also carrying out another time N type ion injects, in the middle of this P type part, to form at least one extra N type part.
16. the manufacturing approach of compound type transfer grid as claimed in claim 12, wherein the dosage of this N type ion injection is between 10
13/ cm
2To 10
14/ cm
2Between.
17. the manufacturing approach of compound type transfer grid as claimed in claim 12, wherein the width of this compound type transfer grid is greater than 0.45 μ m, and the width of this N type part and this P type part is than less than 1/4.
18. the manufacturing approach of compound type transfer grid as claimed in claim 12, wherein the width of this compound type transfer grid is smaller or equal to 0.45 μ m, and the width of this N type part and this P type part is than less than 1/3.
19. the manufacturing approach of a compound type transfer grid, this compound type transfer grid in the semiconductor-based end the electronics accumulation zone and above this semiconductor-based end between the floating node, this method comprises:
Form doping semiconductor layer in this top, semiconductor-based end, it has transversely arranged and continuous P matrix section and N matrix section, and this laterally is the direction from this floating node to this electronics accumulation zone; And
This doping semiconductor layer of patterning is to form gate conductor layer, and it comprises the P type part of a part that is this P matrix section originally, and is the N type part of the part of this N matrix section originally, and this N type part is towards the direction of this floating node.
20. the manufacturing approach of compound type transfer grid as claimed in claim 19 comprises that also carrying out N type ion injects, in the middle of this P type part, to form at least one extra N type part.
21. the manufacturing approach of compound type transfer grid as claimed in claim 20, wherein the dosage of this N type ion injection is between 10
13/ cm
2To 10
14/ cm
2Between.
22. the manufacturing approach of compound type transfer grid as claimed in claim 19, wherein the width of this compound type transfer grid is greater than 0.45 μ m, and the width of this N type part and this P type part is than less than 1/4.
23. the manufacturing approach of compound type transfer grid as claimed in claim 19, wherein the width of this compound type transfer grid is smaller or equal to 0.45 μ m, and the width of this N type part and this P type part is than less than 1/3.
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|---|---|---|---|
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| CN2008100953647A CN101577286B (en) | 2008-05-05 | 2008-05-05 | Compound type transfer grid and production method thereof |
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| CN101577286B true CN101577286B (en) | 2012-01-11 |
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| CN114335045B (en) * | 2022-03-10 | 2022-06-03 | 合肥晶合集成电路股份有限公司 | Method for reducing dark current of CMOS image sensor |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6225165B1 (en) * | 1998-05-13 | 2001-05-01 | Micron Technology, Inc. | High density SRAM cell with latched vertical transistors |
| CN1426110A (en) * | 2001-12-11 | 2003-06-25 | 富士通株式会社 | Semiconductor device and its producing method |
| CN1790676A (en) * | 2004-12-14 | 2006-06-21 | 亿而得微电子股份有限公司 | Method for operating single grid non-volatile memory with multi-bit memory |
-
2008
- 2008-05-05 CN CN2008100953647A patent/CN101577286B/en not_active Expired - Fee Related
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6225165B1 (en) * | 1998-05-13 | 2001-05-01 | Micron Technology, Inc. | High density SRAM cell with latched vertical transistors |
| CN1426110A (en) * | 2001-12-11 | 2003-06-25 | 富士通株式会社 | Semiconductor device and its producing method |
| CN1790676A (en) * | 2004-12-14 | 2006-06-21 | 亿而得微电子股份有限公司 | Method for operating single grid non-volatile memory with multi-bit memory |
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