CN1787373A - Electric power starting resetting circuit - Google Patents
Electric power starting resetting circuit Download PDFInfo
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- CN1787373A CN1787373A CN 200410096926 CN200410096926A CN1787373A CN 1787373 A CN1787373 A CN 1787373A CN 200410096926 CN200410096926 CN 200410096926 CN 200410096926 A CN200410096926 A CN 200410096926A CN 1787373 A CN1787373 A CN 1787373A
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Abstract
This invention relates to a supply turn-on reset circuit including a regulation circuit, a charge/discharge unit and an output circuit, in which, the regulation circuit receives and regulates time pulse signals to output control signals and the lowest quasi-bit of the control signal is limited above the pre-designed one, the charge/discharge unit with the capacity device receives the control signal to decide if it charges/discharges to the capacitor according to the control signal and outputs the storage voltage of the capacitor to be received by the output circuit outputting the reset signals, in which, the regulation circuit regulates the wave and the lowest quasi-bit of the regulation control signal to decide the duty cycle ratio driving the unit to charge/discharge and the output circuit decides if to start or stop the reset signal based on that if the storage voltage reaches to the critical voltage of the output circuit.
Description
Technical field
The invention relates to that a kind of reset signal produces circuit, and particularly relevant for a kind of electric power starting resetting circuit.
Background technology
When the design electronic circuit, tend to add replacement (reset) mechanism in circuit, so that being replied when needed, designed electronic circuit is initial condition.Especially in the time of at the beginning of to electronic circuit power-on (start), each assembly in the circuit (for example buffer) is in nondeterministic statement, and promptly need this circuit of resetting this moment, being initial condition with each module sets in the circuit.
Therefore, must design a circuit, allow the setting state of all electronic circuits be initial condition well in order to produce reset signal at the beginning in start.Figure 1A is the conventional power source starting resetting circuit.Please refer to Figure 1A, as yet not during power-on, electric charge stored on the electric capacity 112 will discharge via resistance 111.Therefore, when at the beginning of the power-on, N transistor npn npn 114 is a cut-off state, so the electric power starting resetting circuit of Figure 1A can produce reset signal RST with buffer 115 via promoting resistance 113.Then, an electric current is provided and to electric capacity 112 chargings, surpasses its critical voltage up to transistorized grid voltage via resistance 110, this moment, transistor 114 transferred conducting state to.Therefore will make reset signal RST forbidden energy by transistor 114.
For guaranteeing that all component all can reset really, so the time of electric power starting resetting circuit activation reset signal must long enough.In other words, resistance 110 must reach greatly with electric capacity 112 formed time constant RC in the electric power starting resetting circuit of Figure 1A, therefore need take bigger chip area.Moreover resistance 111 forms a leakage path, produces unnecessary power consumption.
In October 11 calendar year 2001 in Christian era, among U.S. Patent Publication No. US 2001/0028263 A1 " Power on reset circuit " a kind of electric power starting resetting circuit is disclosed, shown in Figure 1B.In electric power starting resetting circuit 120, will branch to electric capacity 123 and transistor 122 through the electric current of transistor 121, therefore prolonged the charging interval of electric capacity 123.At last, make the charging potential of electric capacity 123 can allow inverter 124 transitions, to produce the effect of electric power starting resetting.Yet, the electric current of transistor 122 of flowing through must be controlled more exactly, and electric current is too little then to be not enough to keep the enough time of reset signal, and electric current then may make electric capacity can't be charged to too greatly to make the position of inverter 124 transitions accurate at all, in addition, charging and discharging process need consume more electric current.
Fig. 1 C is disclosed a kind of electric power starting resetting circuit in the U.S. Patent number 6388479 " Oscillator based power-on-resetcircuit " (May 14 2002 Christian era).Please refer to Fig. 1 C, in electric power starting resetting circuit 130, the clock signal of being exported by oscillating circuit 131 directly passes through transistor 132 and electric capacity 133 low-pass filtering, is stored in the current potential of electric capacity 133 with influence.When the current potential of electric capacity 133 arrives the transition critical point of inverter 134, can produce the effect of electric power starting resetting.Yet the RC time constant of the conducting resistance of transistor 132 and electric capacity 133 needs the pulse bandwidth greater than oscillating circuit 131 clock signal of exporting, otherwise can't reach the action of replacement.Moreover the reset signal RST that electric power starting resetting circuit 130 is exported has oscillatory occurences.
Fig. 1 D is U.S. Patent number 5386152 " Power-on reset circuit responsive to aclock signal " disclosed a kind of electric power starting resetting circuit in (January 31 nineteen ninety-five in Christian era).Please refer to Fig. 1 D, in electric power starting resetting circuit 140, to discharge and recharge signal be to utilize the positive and negative source of clock amplifier to trigger differentiator owing to obtain, so need protective circuit of diode, is unlikely to have excessive reverse signals reverse to enter circuit by earth connection.Therefore sort circuit causes unnecessary interference signal through substrate (substrate) easily, and has the signal generation that is lower than ground voltage.Moreover the reset signal RST that electric power starting resetting circuit 130 is exported also has oscillatory occurences.
Fig. 2 be the above-mentioned various known circuit and the embodiment of the invention the reset signal sequential chart that produces respectively.Please refer to Fig. 2, from top to bottom, article one line drawing is represented supply voltage, and the transient change of line drawing left side expression when electric power starting.Second line drawing (120), the 3rd line drawing (130) and the 4th group of line drawing (140) are represented electric power starting resetting circuit 120,130 and 140 reset signals of being exported respectively.By can clearly finding out among the figure under identical RC (resistance capacitance) assembly, the replacement time that electric power starting resetting circuit 120 is provided is obviously not enough.In addition, though longer by the time that can observe out the reset signal that electric power starting resetting circuit 130 exported among Fig. 2, have serious oscillatory occurences.Line drawing 140a in the 4th group of line drawing (140) represents the reset signal that electric power starting resetting circuit 140 is exported, and oscillatory occurences is as can be seen from the figure arranged.In addition, the line drawing 140b from the 4th group of line drawing (140) can find out that electric power starting resetting circuit 140 inside have the signal that is lower than earthed voltage and produce.
Summary of the invention
Purpose of the present invention is to provide a kind of electric power starting resetting circuit exactly, reaches the required resistance of RC time constant, capacity area with minimizing, reduces the current drain of operating process.And the fix time electric capacity charging direction of constant of fighting to the finish is fixed, so the processing ease of system is stable and reduce noise.
The present invention proposes a kind of electric power starting resetting circuit, is used to electric power starting and produces reset signal at the beginning.This electric power starting resetting circuit comprises adjusts circuit, charge/discharge unit and output circuit.Adjust circuit and receive and also adjust clock signal with the output control signal, wherein the low level of control signal is restricted in advance and fixes more than the position.Charge/discharge unit has a capacitive means.Charge/discharge unit is coupled to the adjustment circuit, whether capacitive means is carried out charge/discharge with reception and according to the control signal decision, and the stored voltage of output capacitance device.Output circuit is coupled to charge/discharge unit, in order to receive stored voltage and output reset signal.Wherein adjust circuit by the waveform of adjusting control signal and low level, make work period that charge/discharge unit carries out charge/discharge than (duty cycle) with decision, and whether output circuit reach the critical voltage of output circuit and determine activation/forbidden energy reset signal according to stored voltage.
According to the described electric power starting resetting circuit of the preferred embodiments of the present invention, also comprise controlled switch.This controlled switch has first link, second link and control end, in order to the clock signal that whether its first link is received according to the decision of reset signal that its control end received connect to its second link to export the adjustment circuit to.Wherein controlled switch can be the transmission lock.
According to the described electric power starting resetting circuit of the preferred embodiments of the present invention, above-mentioned adjustment circuit comprises the whole wave circuit and first clamp circuit.Whole wave circuit is put in order ripple (shaping) with the output control signal with the clock signal that is received.First clamp circuit is coupled to whole wave circuit, is positioned in advance in order to the minimum standard that limits control signal and fixes more than the position.
According to the described electric power starting resetting circuit of the preferred embodiments of the present invention, above-mentioned whole wave circuit comprises the first transistor, transistor seconds and first electric capacity.The grid of the first transistor receives clock signal, and its first source/drain electrode couples first voltage, second source/drain electrode output control signal.The grid of transistor seconds receives clock signal, and its first source/drain electrode couples second source/drain electrode of the first transistor, and second source/drain electrode of transistor seconds then couples first clamp circuit.One end of first electric capacity couples first voltage, and the other end then couples second source/drain electrode of the first transistor.Wherein this first voltage for example is system voltage.
According to the described electric power starting resetting circuit of the preferred embodiments of the present invention, the first above-mentioned clamp circuit comprises the 3rd transistor and the 4th transistor.The 3rd transistorized grid and first source/drain electrode are coupled to whole wave circuit.The 4th transistorized grid receives clock signal, and its first source/drain electrode is coupled to the 3rd transistorized second source/drain electrode, and the 4th transistorized second source/drain electrode then is coupled to second voltage.Wherein this second voltage for example is earthed voltage.
According to the described electric power starting resetting circuit of the preferred embodiments of the present invention, above-mentioned charge/discharge unit comprises the 5th transistor, the 6th transistor and the 3rd electric capacity.The 5th transistorized grid receives control signal, and its first source/drain electrode is coupled to first voltage.The 6th transistorized grid couples first voltage, and its first source/drain electrode is coupled to the 5th transistorized second source/drain electrode, and the 6th transistorized second source/drain electrode then couples second voltage.First end of the 3rd electric capacity couples the 5th transistorized second source/drain electrode and output stored voltage, and second end of the 3rd electric capacity then couples second voltage.
According to the described electric power starting resetting circuit of the preferred embodiments of the present invention, also comprise low voltage resetting circuit.Low voltage resetting circuit receives the stored voltage of reset signal and capacitive means, is scheduled to provide electrical path when accurate position is following in order to be reduced to when system voltage, so that capacitive means is put/charged to reply its initial condition.
According to the described electric power starting resetting circuit of the preferred embodiments of the present invention, above-mentioned low voltage resetting circuit comprises the 7th to the 9th transistor, buffer and second clamp circuit.The 7th transistorized grid receives reset signal, and its first source/drain electrode is coupled to first end of the 3rd electric capacity.The 8th transistorized grid receives first voltage, and its first source/drain electrode couples the 7th transistorized second source/drain electrode.The 9th transistorized first source/drain electrode is coupled to first end of the 3rd electric capacity, and the 9th transistorized second source/drain electrode is coupled to second voltage.The input of buffer couples the 8th transistorized second source/drain electrode, and the output of buffer couples the 9th transistorized grid.First end of clamp circuit couples the 8th transistorized second source/drain electrode, and second end of clamp circuit couples second voltage.
The present invention also passes through the reconstruction of signal because of utilizing clock signal, but reaches the purpose that prolongs the electric power starting resetting activationary time switching time that produces effective control switch resistance (transistor).Amplitude and time that signal adjustment in the present invention comprises clock signal limit, and the size of amplitude is relevant with the transistor turns voltage of control charge and discharge switch, and the restriction of time then will be organized into the control signal (for example less than 50% work period ratio) of opening the transistor switch path with the short period to waveform again through the clock signal (for example about 50% work period ratio) of amplitude.Therefore resistance, capacity area that can be less reach required RC time constant.Simultaneously in operating process, there is not leakage path, so can reduce unnecessary current drain.And the fix time electric capacity charging direction of constant of fighting to the finish is fixed, and does not therefore have reverse signals reverse to enter circuit by earth connection, prevents to see through substrate (substrate) and causes unnecessary interference signal.
For above and other objects of the present invention, feature and advantage can be become apparent, preferred implementation of the present invention is elaborated below in conjunction with accompanying drawing.
Description of drawings
Figure 1A is the conventional power source starting resetting circuit;
Figure 1B is a disclosed electric power starting resetting circuit in the United States Patent (USP) notification number 2001/0028263;
Fig. 1 C is disclosed a kind of electric power starting resetting circuit in the U.S. Patent number 6388479 " Oscillator based power-on-resetcircuit ";
Fig. 1 D is disclosed a kind of electric power starting resetting circuit in the U.S. Patent number 5386152 " Power-on reset circuit responsive to aclock signal ";
Fig. 2 be the various known circuits and the embodiment of the invention the reset signal sequential chart that produces respectively;
Fig. 3 A is a kind of electric power starting resetting circuit figure that illustrates according to the preferred embodiment of the present invention;
Fig. 3 B is a kind of low voltage resetting circuit that illustrates according to the preferred embodiment of the present invention;
Fig. 4 is a kind of electric power starting resetting circuit figure that illustrates according to the preferred embodiment of the present invention;
Fig. 5 is the another kind of electric power starting resetting circuit figure that illustrates according to the preferred embodiment of the present invention;
Fig. 6 is the simulate signal sequential chart of electric power starting resetting circuit among Fig. 5;
Fig. 7 is the simulate signal sequential chart of electric power starting resetting circuit under the situation of the suddenly temporary transient step-down of power supply among Fig. 5.
Main description of reference numerals:
110,111,113: resistance
112,123,133: electric capacity
114,122,132:N transistor npn npn
115,361,461,561: buffer
120,130,140: known electric power starting resetting circuit
The 121:P transistor npn npn
124,134,551～553: inverter
131: oscillating circuit
140a, 140b: the signal in the electric power starting resetting circuit 140
310,410,510: time clock source
320,420,520: controlled switch
330,430,530: adjust circuit
331,431: control signal
332,432: whole wave circuit
333,362,433,462,533,562: clamp circuit
340,440,540: charge/discharge unit
342: the stored voltage of capacitor C 3
350,450,550: output circuit
360: low voltage resetting circuit
C1～C3: electric capacity
CLK: clock signal
RST: reset signal
RSTB: anti-phase reset voltage
T1～T9: transistor
VDD: system voltage
Embodiment
Fig. 3 A is a kind of electric power starting resetting circuit figure that illustrates according to the preferred embodiment of the present invention.Please refer to Fig. 3 A, time clock source 310 is in order to produce clock signal CLK.Controlled switch 320 has first link, second link and control end, connects to its second link in order to the clock signal CLK that whether its first link is received according to reset signal RST that its control end received decision and adjusts circuit 330 to export to.Initial condition (being electric power starting state at the beginning) at this hypothesis controlled switch 320 is a conducting state.
Adjust circuit 330 and receive and adjust clock signal CLK with output control signal 331.In the present embodiment, signal the adjustment amplitude and the time that comprise clock signal CLK limit.Wherein the size of amplitude is relevant with the conducting voltage that discharges and recharges of control, for example the low level of control signal 331 is limited in advance fixes more than the position by adjusting clamp circuit 333 in the circuit 330.The restriction of time then will be organized into waveform with the short period again through the clock signal CLK of amplitude and open the control signal 331 that discharges and recharges the path, for example by the whole wave circuit of adjusting in the circuit 330 332 waveform of the clock signal CLK that received be put in order ripple (shaping) to be adjusted to the control signal 331 of less work period ratio.
Charge/discharge unit 340 has capacitive means (for example capacitor C 3).Charge/discharge unit 340 receives and whether capacitive means is carried out charge/discharge according to control signal 331 with decision, and the stored voltage 342 of output capacitance device.In the present embodiment, charge/discharge unit 340 comprises P transistor npn npn T5 and capacitor C 3.As previously mentioned, the control signal of being exported by adjustment circuit 330 331 is the pulse signal with less work period ratio, and the grid of transistor T 5 receives the charge path of control signal 331 with intermittent conduction capacitor C 3.3 chargings can obtain bigger RC time constant to capacitor C in intermittent mode.Therefore, resistance that can be less, capacity area reach enough big RC time constant.
In the present embodiment, charge/discharge unit 340 also comprises P transistor npn npn T6, the grid coupling system voltage VDD of transistor T 6, and therefore transistor T 6 is to be in cut-off state during electric power starting.Behind powered-down because capacitor C 3 contains electric charge during electric power starting, so transistor T 6 because of its source-grid voltage greater than its critical voltage conducting, 3 of capacitor C are replied via the paths discharge of transistor T 6 and are initial condition.
Output circuit 350 (for example is inverter at this) receives the stored voltage 342 of capacitor C 3.In the time of at the beginning of electric power starting, because stored voltage 342 does not reach the critical voltage of output circuit 350, the voltage of therefore exporting reset signal RST is high.When capacitor C 3 charges to its stored voltage 342 when reaching the critical voltage of output circuit 350, the voltage of then exporting reset signal RST is low.Therefore can produce enough reset signal RST for a long time at the beginning in electric power starting.
Yet because during certain former thereby temporary transient step-down, system tends to should be brownout and the state that causes expecting takes place as system voltage VDD.After system voltage VDD replied normal working voltage, system will can't operate as normal because of its internal signal entanglement.Therefore must after being returned to normal working voltage, baffled step-down send reset signal at system voltage VDD, so that system's replacement state of activation in good time.
Fig. 3 B is a kind of low voltage resetting circuit that illustrates according to the preferred embodiment of the present invention.Please be simultaneously with reference to Fig. 3 A and 3B, low voltage resetting circuit 360 comprises P transistor npn npn T7～T8, N transistor npn npn T9, buffer 361 and clamp circuit 362.Low voltage resetting circuit 360 receives the stored voltage 342 of reset signal RST and capacitor C 3.When at the beginning of the electric power starting, reset signal RST is high, so transistor T 7 is in cut-off state.
Along with the process of intermittence to capacitor C 3 chargings, reach the critical voltage of output circuit 350 when stored voltage 342 after, reset signal RST transition is that low makes transistor T 7 keep conducting state in normal work period (system voltage VDD is in the normal working voltage scope).Transistor T 8 was subjected to system voltage VDD control and was cut-off state this moment, caused the input of buffer 361 and the accurate position of output signal to be all low, so transistor T 9 is cut-off state.When being reduced to, system voltage VDD fixes the position in advance when following, transistor T 8 thereby be conducting state (this moment, transistor T 7 also was conducting state), and causing the input of buffer 361 and the transition of output signal standard is high, so transistor T 9 is conducting state.By with transistor T 9 conductings so that an electrical path to be provided, capacitive means C3 is discharged to reply its initial condition.Therefore after system voltage VDD was returned to normal working voltage from baffled step-down, electric power starting resetting circuit was able to send reset signal in good time again, so that system's replacement state of activation.
For more clearly demonstrating the present invention, below will be with more detailed circuit description embodiments of the invention.Fig. 4 is a kind of electric power starting resetting circuit figure that illustrates according to the preferred embodiment of the present invention.Please refer to Fig. 4, wherein time clock source 410, controlled switch 420 and output circuit 450 are similar to time clock source 310, controlled switch 320 and the output circuit 350 of preceding embodiment (Fig. 3 A) respectively, so do not give unnecessary details at this.
At this, it is similar to the adjustment circuit 330 of Fig. 3 A to adjust circuit 430, still is made up of with clamp circuit 433 whole wave circuit 432.Wherein clamp circuit 433 can be implemented with reference to following circuit.Clamp circuit 433 comprises N transistor npn npn T3 and T4.The grid of transistor T 3 and drain electrode are coupled to whole wave circuit 432.The drain electrode of transistor T 4 is coupled to the source electrode of transistor T 3, and the source electrode of transistor T 4 is coupled to earthed voltage, and the grid of transistor T 4 receives clock signal CLK.
At this, capacitor C 1 for example applies it with the P transistor npn npn, so that implement it in integrated circuit.In other words, promptly transistorized source electrode is coupled an end of being used as electric capacity mutually with the collection utmost point, and its grid is considered as the other end of electric capacity.One end coupling system voltage VDD of capacitor C 1, the other end then couples the drain electrode of transistor T 1.
In the present embodiment, charge/discharge unit 440 is similar to the charge/discharge unit 340 of Fig. 3 A, and wherein difference is capacitor C 3 is applied it with the N transistor npn npn.In other words, promptly the grid of N transistor npn npn is used as first end of electric capacity, and its source electrode is coupled to be considered as second end of electric capacity mutually with the collection utmost point.
At this, low voltage resetting circuit 460 is similar to the low voltage resetting circuit 360 of Fig. 3 B, so do not give unnecessary details at this.Wherein buffer 461 is for example with two inverters series connection enforcement, and clamp circuit 462 is for example with the enforcements of connecting of three diodes.
Fig. 5 is the another kind of electric power starting resetting circuit figure that illustrates according to the preferred embodiment of the present invention.The electric power starting resetting circuit of Fig. 5 is similar to Fig. 4, so partial circuit will not given unnecessary details following.Please refer to Fig. 5, the clamp circuit 533 of wherein adjusting circuit 530 is more in the coupling capacitance C2 of the grid place of transistor T 4 (implementing it with the N transistor npn npn at this).An end that also is about to capacitor C 2 is coupled to the grid of transistor T 4, and the other end ground connection of capacitor C 2.
Output circuit 550 for example comprises inverter 551～553.Receive the stored voltage (being the voltage that P2 is ordered) of capacitor C 3 to export anti-phase reset voltage RSTB by the be in series buffer formed of inverter 551～552.Inverter 553 further receives anti-phase reset voltage RSTB and exports reset voltage RST (being the voltage that P1 is ordered).
In the present embodiment, controlled switch 520 for example is the transmission lock.Two gate terminal (control end) in the transmission lock receive reset voltage RST and anti-phase reset voltage RSTB separately, so that the clock signal CLK that makes at the beginning of electric power starting is sent to adjustment circuit 530, the transfer path that just cuts off clock signal CLK after reset voltage RST (RSTB) transition.
Low voltage resetting circuit 560 is similar to the low voltage resetting circuit 460 of Fig. 4.Wherein the not gate formed with P transistor npn npn and N transistor npn npn of the inverter in the buffer 561 is implemented.Diode in the clamp circuit 562 is then implemented it with the N transistor npn npn, and the drain electrode that also is about to the N transistor npn npn couples the anode of being used as diode mutually with grid, and the source electrode of N transistor npn npn is considered as the negative electrode of diode.
Fig. 6 is the simulate signal sequential chart of electric power starting resetting circuit among Fig. 5.From top to bottom, article one line drawing is represented the sequential relationship of system voltage VDD among the figure, signal (control signal) timing variations that P3 is ordered in the second line drawing presentation graphs 5, article three, signal (stored voltage of the capacitor C 3) timing variations that P2 is ordered in the line drawing presentation graphs 5, article four, signal (clamp voltage) timing variations that P4 is ordered in the line drawing presentation graphs 5, lowermost line drawing be the timing variations of reset signal RST in the presentation graphs 5 then.
Fig. 7 is the simulate signal sequential chart of electric power starting resetting circuit under the situation of the suddenly temporary transient step-down of power supply among Fig. 5.From top to bottom, article one line drawing timing variations of P1 point (reset signal RST) in the presentation graphs 5 then among the figure, the second line drawing represents that system voltage VDD replys the sequential relationship of original accurate position after the accurate of short duration step-down in position of operate as normal, article three, signal (stored voltage of the capacitor C 3) timing variations that P2 is ordered in the line drawing presentation graphs 5, the four～six line drawing then distinguished the signal sequence that Y1 point, Y0 point and Y2 are ordered in the presentation graphs 5 and changed.
Though the present invention with preferred embodiment openly as above; right its is not in order to qualification the present invention, any those of ordinary skills, without departing from the spirit and scope of the present invention; when can doing a little change and retouching, so protection scope of the present invention is when with being as the criterion that claim was limited.
Claims (17)
1. electric power starting resetting circuit, in order to produce a reset signal at the beginning at electric power starting, this electric power starting resetting circuit comprises:
One adjusts circuit, and in order to receive and to adjust a clock pulse signal to export a control signal, wherein the low level of this control signal is limited in one and fixes more than the position in advance;
One charge/discharge unit has a capacitive means, and this charge/discharge unit is coupled to this adjustment circuit, whether this capacitive means is carried out charge/discharge in order to reception and according to this control signal with decision, and exports a stored voltage of this capacitive means; And
One output circuit is coupled to this charge/discharge unit, and in order to receive this stored voltage and to export this reset signal, wherein whether this output circuit reaches the critical voltage of this output circuit and determine this reset signal of activation/forbidden energy according to this stored voltage;
Wherein should adjust circuit by the waveform of adjusting this control signal and low level, and make work period that this charge/discharge unit carries out charge/discharge than (duty cycle) with decision.
2. electric power starting resetting circuit as claimed in claim 1 also comprises:
One controlled switch, have first link, second link and control end, in order to this clock signal that whether its first link is received according to its control end received this reset signal decision connect to its second link to export this adjustment circuit to.
3. electric power starting resetting circuit as claimed in claim 1, wherein this controlled switch is a transmission lock.
4. electric power starting resetting circuit as claimed in claim 1, wherein this adjustment circuit comprises:
One whole wave circuit is in order to be put in order ripple (shaping) to export this control signal with this clock signal that is received; And
One first clamp circuit is coupled to this whole wave circuit, is positioned at this in order to the minimum standard that limits this control signal and fixes more than the position in advance.
5. electric power starting resetting circuit as claimed in claim 4 wherein should comprise by whole wave circuit:
One the first transistor, the grid of this first transistor receives this clock signal, and first source/drain electrode of this first transistor couples one first voltage, second source of this first transistor/this control signal of drain electrode output;
One transistor seconds, the grid of this transistor seconds receives this clock signal, and first source/drain electrode of this transistor seconds couples second source/drain electrode of this first transistor, and second source/drain electrode of this transistor seconds couples this first clamp circuit; And
One first electric capacity, an end of this first electric capacity couples this first voltage, and the other end of this first electric capacity couples second source/drain electrode of this first transistor.
6. electric power starting resetting circuit as claimed in claim 5, wherein this first transistor is the P transistor npn npn, this transistor seconds is the N transistor npn npn.
7. electric power starting resetting circuit as claimed in claim 5, wherein this first voltage is system voltage.
8. electric power starting resetting circuit as claimed in claim 4, wherein this first clamp circuit comprises:
One the 3rd transistor, the 3rd transistorized grid and first source/drain electrode are coupled to this whole wave circuit; And
One the 4th transistor, the 4th transistorized grid receives this clock signal, and the 4th transistorized first source/drain electrode is coupled to the 3rd transistorized second source/drain electrode, and the 4th transistorized second source/drain electrode is coupled to one second voltage.
9. as claim 8 a described electric power starting resetting circuit, wherein this first clamp circuit also comprises:
One second electric capacity, a termination of this second electric capacity is received this clock signal, and the other end of this second electric capacity couples this second voltage.
10. electric power starting resetting circuit as claimed in claim 8, wherein this second voltage is earthed voltage.
11. electric power starting resetting circuit as claimed in claim 1, wherein this charge/discharge unit comprises:
One the 5th transistor, the 5th transistorized grid receives this control signal, and the 5th transistorized first source/drain electrode is coupled to one first voltage;
One the 6th transistor, the 6th transistorized grid couples this first voltage, and the 6th transistorized first source/drain electrode is coupled to the 5th transistorized second source/drain electrode, and the 6th transistorized second source/drain electrode couples one second voltage; And
One the 3rd electric capacity, first end of the 3rd electric capacity couple the 5th transistorized second source/drain and export this stored voltage, and second end of the 3rd electric capacity couples this second voltage.
12. electric power starting resetting circuit as claimed in claim 1, wherein this output circuit system comprises at least one inverter.
13. electric power starting resetting circuit as claimed in claim 1 also comprises:
One low voltage resetting circuit receives this reset signal and this stored voltage, fixes the position in advance and provides an electrical path when following in order to be reduced to one when a system voltage, makes this capacitive means put/charge to reply its initial condition.
14. electric power starting resetting circuit as claimed in claim 13, wherein this low voltage resetting circuit comprises:
One the 7th transistor, the 7th transistorized grid receives this reset signal, and the 7th transistorized first source/drain electrode is coupled to first end of the 3rd electric capacity;
One the 8th transistor, the 8th transistorized grid receives this first voltage, and the 8th transistorized first source/drain electrode couples the 7th transistorized second source/drain electrode;
One the 9th transistor, the 9th transistorized first source/drain electrode is coupled to first end of the 3rd electric capacity, and the 9th transistorized second source/drain electrode is coupled to one second voltage;
One buffer, the input of this buffer couple the 8th transistorized second source/drain electrode, and the output of this buffer couples the 9th transistorized grid; And
One second clamp circuit, first end of this clamp circuit couple the 8th transistorized second source/drain electrode, and second end of this clamp circuit couples this second voltage.
15. electric power starting resetting circuit as claimed in claim 14, wherein the 7th transistor AND gate the 8th transistor is the P transistor npn npn, and the 9th transistor is the N transistor npn npn.
16. electric power starting resetting circuit as claimed in claim 14, wherein this second clamp circuit is composed in series by most diodes.
17. electric power starting resetting circuit as claimed in claim 14, wherein this first voltage is system voltage, and this second voltage is earthed voltage.
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| CNB2004100969261A CN100499372C (en) | 2004-12-06 | 2004-12-06 | Electric power starting resetting circuit |
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|---|---|---|---|
| CNB2004100969261A CN100499372C (en) | 2004-12-06 | 2004-12-06 | Electric power starting resetting circuit |
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| CN100499372C CN100499372C (en) | 2009-06-10 |
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| CNB2004100969261A Expired - Fee Related CN100499372C (en) | 2004-12-06 | 2004-12-06 | Electric power starting resetting circuit |
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Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN101930374A (en) * | 2009-06-26 | 2010-12-29 | 和硕联合科技股份有限公司 | Peripheral control module, computer system and operating method of computer system |
| CN102509558A (en) * | 2011-11-25 | 2012-06-20 | 珠海天威技术开发有限公司 | Storage chip and charging method thereof |
| US8447966B2 (en) | 2009-06-26 | 2013-05-21 | Pegatron Corporation | Peripheral control module, computer system, and operation method thereof |
| CN103916569A (en) * | 2013-01-05 | 2014-07-09 | 晨星软件研发(深圳)有限公司 | Signal coupling circuit and signal coupling method |
| CN110398625A (en) * | 2018-04-24 | 2019-11-01 | 新唐科技股份有限公司 | Voltage detecting circuit |
-
2004
- 2004-12-06 CN CNB2004100969261A patent/CN100499372C/en not_active Expired - Fee Related
Cited By (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101930374A (en) * | 2009-06-26 | 2010-12-29 | 和硕联合科技股份有限公司 | Peripheral control module, computer system and operating method of computer system |
| US8447966B2 (en) | 2009-06-26 | 2013-05-21 | Pegatron Corporation | Peripheral control module, computer system, and operation method thereof |
| CN101930374B (en) * | 2009-06-26 | 2013-08-21 | 和硕联合科技股份有限公司 | Peripheral control module, computer system and operating method of computer system |
| CN102509558A (en) * | 2011-11-25 | 2012-06-20 | 珠海天威技术开发有限公司 | Storage chip and charging method thereof |
| CN102509558B (en) * | 2011-11-25 | 2015-02-25 | 珠海天威技术开发有限公司 | Storage chip and charging method thereof |
| CN103916569A (en) * | 2013-01-05 | 2014-07-09 | 晨星软件研发(深圳)有限公司 | Signal coupling circuit and signal coupling method |
| CN103916569B (en) * | 2013-01-05 | 2017-04-19 | 晨星软件研发(深圳)有限公司 | Signal coupling circuit and signal coupling method |
| CN110398625A (en) * | 2018-04-24 | 2019-11-01 | 新唐科技股份有限公司 | Voltage detecting circuit |
| CN110398625B (en) * | 2018-04-24 | 2021-06-11 | 新唐科技股份有限公司 | Voltage detection circuit |
Also Published As
| Publication number | Publication date |
|---|---|
| CN100499372C (en) | 2009-06-10 |
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