CN1787362A - Low power consumption non-ROM searching list phase amplitude converter - Google Patents

Abstract

The invention relates to a low-power-consumption ROM-free look-up table phase-to-amplitude converter and belongs to the field of integrated circuit phase-to-amplitude converters. The converter includes a conditional negation unit, a control signal generator, an input data latch, a phase-to-magnitude conversion logic unit composed of K phase-to-magnitude conversion logic modules, a multiplexer, and an N-bit adder; the control signal generation The input terminal of the device is connected to the output terminal of the conditional negation unit; the input terminal of the input data latch is connected to the output terminal of the conditional negation unit, the second bit of the input phase and the output terminal of the control signal generator; the phase amplitude conversion logic The input end of the unit is connected with the output end of the input data locker; the input end of the multiplexer is connected with the output end of the phase amplitude conversion logic unit and the output end of the control signal generator; the input end of the N-bit adder is connected with the output end of the multiplexer connected to the output of the channel selector. The present invention can also work at higher speed while greatly reducing dynamic power consumption.

Description

Low power consumption non-ROM searching list phase amplitude converter

Technical field

The invention belongs to integrated circuit phase amplitude converter design field, particularly a kind ofly be applied to just low power consumption non-ROM searching list phase amplitude converter design of generating of (surplus) string ripple signal of Direct Digital Frequency Synthesizers and other.

Background technology

Be applied to Direct Digital Frequency Synthesizers and other just just (surplus) string ripple signal phase amplitude converter of generating of (surplus) string ripple signal normally based on the ROM look-up table configuration; For reducing the scale of ROM look-up table, normally the process compression algorithm is to reduce ROM look-up table scale; One typically based on just (surplus) string phase amplitude converter structure of ROM look-up table configuration as shown in Figure 1, input phase is connected to the input of 2 twos complementer, carry out an amplitude mapping, its output is connected to the address input end of look-up table ROM as the address of look-up table ROM, the digital value that look-up table ROM is stored be not corresponding to just (surplus) string wave-shape amplitude value of phase point, the output of look-up table ROM is connected to the input of amplitude reconstruction arithmetic operation unit, just the digital amplitude and first bit of (surplus) string waveform are connected to the digital amplitude output together to obtain the half-wave of corresponding input phase point after the amplitude reconstruction arithmetic operation unit carries out amplitude reconstruction.The major defect of this ROM look-up table configuration phase amplitude converter has: just (surplus) string ripple signal of synthetic better quality, need higher digital amplitude precision, need bigger look-up table ROM capacity like this, jumbo look-up table ROM not only brings bigger area and power consumption, and can reduce the high operation speed of system, reduce just (surplus) string ripple signal bandwidth of output.

Summary of the invention

The objective of the invention is in order to overcome the shortcoming of traditional phase amplitude converter based on the ROM look-up table configuration because of the decreased performance using jumbo ROM look-up table and bring, a kind of low power consumption non-ROM searching list structure phase amplitude converter is proposed, replace look-up table ROM with pure logical operation module, effectively reduce power consumption, simultaneously, designed circuit can work in higher speed.

Low power consumption non-ROM searching list phase amplitude converter of the present invention, it is characterized in that phase amplitude conversion logical unit, MUX and a N bit adder of comprising negated condition unit, control signal maker, input data latch, forming by K phase amplitude conversion logic; Its annexation is: the back M-1 bit of the input of described negated condition unit and M bit input phase links to each other; Preceding a bit in the M-2 bit number word bit of the input of described control signal maker and the output of described negated condition unit links to each other; The input of described input data latch links to each other with back M-2-a bit, second bit of input phase and the K bit output of described control signal maker in the described negated condition unit output M-2 bit number word bit respectively; K road input in the described phase amplitude conversion logical unit links to each other with the output of the K road b+c+1 bit length of described input data lock device respectively; The K road input of described MUX links to each other with K road N, the output of L bit length and the K bit output of described control signal maker in the described phase amplitude conversion logical unit respectively; N, the L bit length output of described N bit adder input and MUX link to each other; First bit of the output of N bit adder and input phase connects the amplitude output as this transducer.

The principle of the technical solution adopted in the present invention is: the present invention realizes existing ROM look-up table function with the phase amplitude conversion logical unit; In logical operation module, use four/one-period mapping algorithm and triangle decomposition approximate data, logical operation module is compressed, reduce the scale of logical operation module; Phase amplitude logical operation in four/one-period utilizes the piecewise nonlinear interpolation characteristic of triangle decomposition approximate data, has realized the piecemeal power managed to logical operation module, reduces the dynamic power consumption of arithmetic logic unit; Second bit of input phase is used for the amplitude computing of four/one-period, has reduced the negated condition computing and has realized first quartile is shone upon the range error that brings to second quadrant, improves the undistorted dynamic range of output signal.

The invention has the beneficial effects as follows that this structure is reducing dynamic power consumption significantly, simultaneously, also can work in fair speed.

Description of drawings

Fig. 1 is traditional ROM look-up table configuration phase amplitude converter structure chart;

Fig. 2 is that low power consumption non-ROM searching list phase amplitude converter of the present invention is implemented structure chart;

Fig. 3 is that input data latch of the present invention is implemented structure chart;

Fig. 4 is that one road phase amplitude conversion logic of the present invention is implemented structure chart;

Fig. 5 is that the structure that Fig. 2 proposes is adopting 12 bit input phases, the frequency spectrum of the synthetic 136.35MHz sine wave signal of the embodiment of 10 bit output amplitudes.

Embodiment

Below in conjunction with accompanying drawing the present invention and embodiment are further specified.

A kind of embodiment of low power consumption non-ROM searching list phase amplitude converter of the present invention, its structure as shown in Figure 2, in Fig. 2, the sinusoidal wave low power consumption non-ROM searching list phase amplitude converter 10 of present embodiment is made up of negated condition unit 12, control signal maker 14, input data latch 16, phase amplitude conversion logical unit 20, MUX 30 and N bit adder 40; Among the figure, M bit input phase is removed preceding two bits (M-2 bit) phase place and is connected to the input of negated condition unit 12, is connected to second bit (2MSB) that also has input phase of negated condition unit 12 inputs simultaneously; The preceding a bit of the output of negated condition unit 12 is connected to the input of control signal maker 14, and second bit phase of all the other M-a-2 digital bit positions (b+c) and input phase is connected to the input of data latches 16 together; Control signal maker 14 generates the signal input end that K bit control signal is connected respectively to input data latch and MUX; Phase amplitude conversion logical unit 20 is by K road phase amplitude conversion logic 22,24,26 ... form, the output of the K road b+c+1 bit length of input data latch 16 is connected respectively to K submodule 22 of phase amplitude conversion logical unit 20,24,26 ... input, K road phase amplitude conversion logic 22 in the phase amplitude conversion logical unit 20,24,26 ... N, the output of L bit length be connected to the K road input of MUX 30, the N of MUX 30, L bit length output are connected to the input of N bit adder 40; First bit phase of the output of N bit adder 40 and input phase connects the amplitude output as present embodiment.

The operation principle of present embodiment is: the back M-2 bit phase in the M bit input phase is input to negated condition unit 12, under the control of second bit, carry out the negated condition computing, when second bit is high level, negated condition unit 12 output signals are the M-2 bit phase signal of negating, otherwise, the output signal of negated condition unit 12 equals M-2 bit input phase, by the negated condition computing, realizes the amplitude mapping of first quartile to second quadrant; The preceding a bit of negated condition unit 12 outputs is input to control signal maker 14, and remaining the M-2-a bit and second bit are input to input data latch 16 together; The output signal K bit signal of control signal maker 14 is selected signal as the output of input data latch 16 and MUX 30, in the K road input signal that guarantees in each clock cycle to provide for phase amplitude conversion logical unit 20 by output data latch 16, the changing of having only that riches all the way, multi-channel data selector 30 is selected the output of the output of the phase amplitude conversion logic that the input data change in the phase amplitude conversion logical unit 20 as MUX under the control of K bit signal simultaneously.Finally be implemented in each clock cycle, K phase amplitude conversion logic in the phase amplitude conversion logical unit 20 has only the input and output of a module to change, and produces dynamic power consumption, and other each module input and output remain unchanged, and do not produce dynamic power consumption; 20 pairs of input phases of phase amplitude conversion logical unit carry out the sine amplitude computing, obtain a N bit amplitudes initial value and a L bit interpolation range value corresponding to the sinusoidal wave amplitude of input phase, the N bit initial value digital amplitude and the L bit interpolation digital amplitude of 30 outputs of 40 pairs of MUX of N bit adder are carried out addition, N-1 bit of reconstruct is corresponding to just (surplus) string half-wave voltage signal digital amplitude of input phase, and and input phase constitute the output of the phase amplitude converter 10 of present embodiment together.

A kind of embodiment of input data latch of the present invention, its structure as shown in Figure 3, the input data latch 16 of present embodiment is by K latch module 124,125,126 ... form, wherein, each latch module constitutes by a b bit latch and a c+1 bit latch; Among the figure, phase place input 121, second bit phase 122 is connected to the input (promptly linking to each other with the b bit latch of each latch module and the input of c+1 bit latch respectively) of input data latch 16, as latch module 124,125,126 ... Deng the input signal that is total to K road latch; K bit control signal 123 is connected to the signal input end (promptly all linking to each other with the b bit latch of each latch module and the input of c+1 bit latch) of input data latch, as the control signal of input data latch 16; In the latch module of K road, the signal input end of each road latch module links to each other with a bit in the K bit control signal respectively, in each clock cycle, have only one to be the higher bit position in the K bit control signal, make and have only one road output end signal to obtain upgrading in the K road latch module output end signal in the input data latch 16, other each road remains unchanged.

A kind of embodiment of a phase amplitude conversion logic of the present invention, its structure as shown in Figure 4, the phase amplitude conversion logic 200 of present embodiment comprises amplitude interpolation formation logic module 220, amplitude initial value formation logic module 222, as shown in frame of broken lines among the figure, wherein, the input of amplitude interpolation formation logic module 220 links to each other with second bit (2MSB) with the phase place C bit of data latches module output, its output output amplitude interpolated signal L, amplitude initial value formation logic module 222 links to each other with the phase place B of data latches module output, its output output amplitude initial value signal N.Among the figure, phase place A is connected to the input (referring to Fig. 2) of control signal maker 14, and the one digit number of the output of control signal maker 14 is according to selecting signal to be connected to the signal input end of input data latch 210.

The operation principle of present embodiment is: phase place B, phase place C and second bit (2MSB) phase place are connected to the data input pin of input data latch 210, phase place B in input data latch 210 outputs is connected to the input of amplitude initial value formation logic 222, and phase place C in input data latch 210 output signals and 2MSB are connected to the input of amplitude interpolation formation logic 220; The output of amplitude initial value formation logic 220 is connected to the initial value amplitude output of phase amplitude computing module 200, and the output of amplitude interpolation formation logic 222 is connected to the interpolation amplitude output of phase amplitude computing module 200.

If input phase is θ=alpha+beta+γ, wherein α is the phase value of input phase A correspondence, and β is the value of input phase B correspondence, and γ is the angle value of input phase C correspondence, and pairing approximation is as follows:

sinθ＝sin(α+β+γ)

＝sin(α+β)cos(γ)+cos(α+β)sin(γ) (1)

≈sin(α+β)+cos(α)sin(γ)

The α pointwise is launched and can get:

$\mathrm{sin\theta }\≈\left\{\begin{array}{c}\sin ({\mathrm{\α}}_0+\mathrm{\β})+\cos \left({\mathrm{\α}}_0\right)\sin \left(\mathrm{\γ}\right)\\ \sin ({\mathrm{\α}}_1+\mathrm{\β})+\cos \left({\mathrm{\α}}_1\right)\sin \left(\mathrm{\γ}\right)\\ \·\\ \·\\ \·\\ \sin ({\mathrm{\α}}_K+\mathrm{\β})+\cos \left({\mathrm{\α}}_K\right)\sin \left(\mathrm{\γ}\right)\end{array}\right.---\left(2\right)$

K=2 wherein ^a, a is the length of input phase A.

Amplitude initial value formation logic 220 is realized sin (α _i+ β) (i=1,2 ... K) computing, amplitude interpolation formation logic 222 is realized cos (α _K) sin (γ) (i=1,2 ... K) computing, phase place A is input to control signal maker 14 and produces K Bit data selection signal, the K Bit data selects has only one to be high level in the signal, everybody is low level for other, and the K Bit data is selected the input end signal of signal deciding latch module: whether phase place B, phase place C and 2MSB output to the output of latch module; By under the control of data select signal, guarantee that in each clock cycle the input that has only a phase amplitude conversion logic 200 is new data more, the fan-in of other each phase transition logic module is according to remaining unchanged.

In Fig. 5, provided the synthesis sine signal spectral analysis figure that uses an embodiment of the low power consumption non-ROM searching list phase amplitude converter structure that is proposed; This embodiment adopts 12 bit input phase resolution, 10 bit output amplitude resolution; The frequency of the sine wave signal that is synthesized among the figure is 136.35MHz, and the clock of employing is 500MHz, and this spectrogram is obtained by Matlab emulation.

The specific embodiment of each components and parts among the present invention is respectively described below:

1, input data latch can be the traditional structure latch, no specific (special) requirements;

2, N bit adder unit can adopt structure adder or other traditional structure adders such as condition carry;

3, K phase amplitude modular converter in the phase amplitude conversion logical unit can be made up of the gate of ordinary construction;

4, the negated condition unit is made up of the XOR gate of M-2 ordinary construction;

5, the control signal maker is by an a-2 ^aDecoder is realized;

6, MUX is the traditional structure MUX.

Claims (3)

1. low power consumption non-ROM searching list phase amplitude converter, it is characterized in that phase amplitude conversion logical unit, MUX and a N bit adder of comprising negated condition unit, control signal maker, input data latch, forming by K phase amplitude conversion logic; Its annexation is: the back M-1 bit of the input of described negated condition unit and M bit input phase links to each other; Preceding a bit in the M-2 bit number word bit of the input of described control signal maker and the output of described negated condition unit links to each other; The input of described input data latch links to each other with back M-2-a bit, second bit of input phase and the K bit output of described control signal maker in the described negated condition unit output M-2 bit number word bit respectively; K road input in the described phase amplitude conversion logical unit links to each other with the output of the K road b+c+1 bit length of described input data lock device respectively; The K road input of described MUX links to each other with K road N, the output of L bit length and the K bit output of described control signal maker in the described phase amplitude conversion logical unit respectively; N, the L bit length output of described N bit adder input and MUX link to each other; First bit of the output of N bit adder and input phase connects the amplitude output as this transducer.

2. low power consumption non-ROM searching list phase amplitude converter according to claim 1, it is characterized in that, described input data latch is made up of K latch module, and wherein, each latch module constitutes by a b bit latch and a c+1 bit latch; Its annexation is: phase place input, second bit phase link to each other with the b bit latch of each latch module and the input of c+1 bit latch respectively, and K bit control signal links to each other with the b bit latch of each latch module and the input of c+1 bit latch respectively.

3. low power consumption non-ROM searching list phase amplitude converter according to claim 2, it is characterized in that, described phase amplitude conversion logic comprises amplitude interpolation formation logic module and amplitude initial value formation logic module, wherein, the input of amplitude interpolation formation logic module links to each other with second bit with the phase place C bit of data latches module output, its output output amplitude interpolated signal L, amplitude initial value formation logic module links to each other with the phase place B of data latches module output, its output output amplitude initial value signal.

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