CN1783772A

CN1783772A - Method for receiving asynchronous receiver

Info

Publication number: CN1783772A
Application number: CN 200410096090
Authority: CN
Inventors: 石璧渊
Original assignee: 404 SCI-TECH Co Ltd
Current assignee: 404 SCI-TECH Co Ltd
Priority date: 2004-11-29
Filing date: 2004-11-29
Publication date: 2006-06-07

Abstract

This invention relates to a receiving method by synchronous receivers, in which, the asynchronous receiving transmitter includes a shift register and a computer, the receiving shift register is connected with the receiving register connecting to a preset microprocessor via the bus, when the register receives the serial data sent by the shift register, the computer computes the correct data volume labeled in the error bit, so that the microprocessor takes the number computed by the computer as the times of reading data address by the microprocessor to read all labeled correct data to increase the read efficiency.

Description

The method of reseptance of asynchronous receiver

Technical field

The present invention relates to a kind of method of reseptance of asynchronous receiver, relate in particular to a kind of interior set counter of asynchronous receiver that utilizes and calculate the correct data amount, to improve the method for reseptance of reading efficiency.

Background technology

The original meaning of communication is meant the communication of suggestion or the exchange of information, but modern communication has also comprised in wireless or wired mode, with sound, multimedia messages such as image and literal is transferred to the long-range meaning, define from technological layer, then be meant with various signals encoded with modulation process after, still can be efficient, safety and successfully be sent to a distant place, utilize the transfer function of " ", just can see TV fast again easily, make a phone call, the broadcast listening program, transmit file, also can utilize modulator-demodulator through telephone wire or cable of cable TV line, send or receive Email by network, the webpage and the use networking telephone etc. surf the web.

Become today of second largest medium at network, network is the indispensable information sources of most of people, and the important channel of communicating with each other between men, if Network Transmission is used as a highway, then each user must be provided with an overpass and just receives transmitter and transmit or receive the information that is circulated on this highway, and along with transmission rate is constantly accelerated, make that receiving transmitter also must have operating rate faster, and that the most normal use at present promptly is asynchronous reception transmitter (UniversalAsynchronous Receiver Transmitter, be called for short UART), and asynchronous reception transmitter is also referred to as serial communication interface (Serial Communication Interface is called for short SCI) sometimes, the just general instrument of the asynchronous reception transmitter of this kind, computer, set serial line interface RS-232 in this electronic product such as PDA also is the main flow of present serial transmission mode.

Please consult Fig. 1-7 simultaneously, be illustrated as the schematic flow sheet () of existing asynchronous reception transmitter when reading of data, figure (two), figure (three), figure (four), figure (five), figure (six) and figure (seven), from figure, can know and learn, when asynchronous reception transmitter A receives serial data, this serial data can leave in and receive shift register (Receive Shift Register, abbreviation RSR) among the A1, and this reception shift register A1 can comprise every group of serial data start bit, stop bit and data bit are stored in and receive in the shift register A1, yet, because receive the reflection that shift register A1 does not have memory address, so can't be to receiving the serial data direct access among the shift register A1, so after reception shift register A1 receives stop bit, receiving data bit among the shift register A1 partly will be moved among the data address A21 among receiving register (Receive Register) A2, and in the receiving course of serial data, after receiving, data bit should receive a stop bit, if what received this moment is not a stop bit, the situation of " frame error " (Frame Error) will take place in that, in addition, if the sync check of activation mechanism is arranged, and the sync check position of receiving is wrong, can produce parity error (Parity Error), and in receiving register A2, be set at mistake among the error bit A22 with respect to this group data address A21, and if receive a stop bit after data bit is received, then in receiving register A2, be set at correct among the error bit A22 with respect to this group data address A21, and when microprocessor B reads serial data stored in the receiving register A2 by bus C, will read every group of data secondary successively, it wherein once is the correct or mistake that is indicated among the A22 of read error position, and another time is stored data among the A21 of reading of data address, to take out stored serial data in the receiving register A2, and utilize error bit A22 to judge the correctness of these group data, and when being set at mistake among its error bit of the data that read A22, microprocessor B must handle these group data especially; And, reading six groups of stored serial datas in the receiving register A2 according to this mode with this example, microprocessor B then need read ten secondary receiving register A2.

Above-mentioned existing asynchronous reception transmitter is when receiving, just can obtain because of reading secondary by group, make the workload of microprocessor B increase and reduced efficient, and emphasize under the situation of a tractor serves several purposes at electronic product now, microprocessor B can't have unnecessary efficient to handle other work or reduce processing speed, and allows the user feel inconvenience.

Therefore, how to solve above-mentioned existing problem and defective, be the relevant manufacturer that is engaged in the industry and desire most ardently the direction place that research improves.

Summary of the invention

The technical problem that the present invention mainly solves is, the method for reseptance of the high asynchronous receiver of a kind of efficient is provided.It mainly is the counter that utilizes asynchronous receiver set, when receiving register receives by the reception serial data that shift register transmitted, indicated correct data volume with accumulate mode mistake in computation position, make microprocessor only need to be used as the number of times of microprocessor reading of data address according to the quantity that counter calculated, can be denoted as correct error bit in the relative data address stored data all read and finish, the efficient that reads with raising.

The concrete technical scheme that realizes this invention is as follows:

A kind of method of reseptance of asynchronous receiver, this asynchronous reception transmitter is to have the reception shift register that can receive serial data, be connected with the receiving register that can store and receive shift register by receiving the serial data that shift register transmitted, and receiving register is for being connected to default microprocessor by bus, and in receiving register, be provided with data address and corresponding error bit, and data address can store the data bit part in the serial data, and error bit is the correctness that can set stored data in its corresponding data address, being provided with in this asynchronous reception transmitter can be when receiving register receives the serial data that shift register transmits, calculate the counter that the frame error position is indicated correct data volume with accumulate mode, make microprocessor only need to be used as the number of times of microprocessor reading of data address according to the quantity that counter calculated, can be denoted as correct error bit in the relative data address stored data all read and finish, the efficient that reads with raising.

This counter stops to calculate when error bit occurs being denoted as wrong data.

The efficient of reading of data effectively improves like this.

Description of drawings

Fig. 1 is the schematic flow sheet () of existing asynchronous reception transmitter when reading of data;

Fig. 2 is the schematic flow sheet (two) of existing asynchronous reception transmitter when reading of data;

Fig. 3 is the schematic flow sheet (three) of existing asynchronous reception transmitter when reading of data;

Fig. 4 is the schematic flow sheet (four) of existing asynchronous reception transmitter when reading of data;

Fig. 5 is the schematic flow sheet (five) of existing asynchronous reception transmitter when reading of data;

Fig. 6 is the schematic flow sheet (six) of existing asynchronous reception transmitter when reading of data;

Fig. 7 is the schematic flow sheet (seven) of existing asynchronous reception transmitter when reading of data;

Fig. 8 is the schematic flow sheet () of asynchronous receiver reading of data method of the present invention preferred embodiment;

Fig. 9 is the schematic flow sheet (two) of asynchronous receiver reading of data method of the present invention preferred embodiment;

Figure 10 is the schematic flow sheet (three) of asynchronous receiver reading of data method of the present invention preferred embodiment.

Wherein symbolic representation is as follows:

1, asynchronous reception transmitter

11, receive shift register 122, error bit

12, receiving register 13, counter

121, data address

2, microprocessor

3, bus

A, asynchronous reception transmitter

A1, reception shift register A21, data address

A2, receiving register A22, error bit

B, microprocessor

C, bus

Embodiment

For achieving the above object and effect, the technical solution adopted in the present invention and structure thereof as mentioned above, existing with reference to the accompanying drawings just feature and the function of preferred embodiment of the present invention be described as follows in detail, in order to understanding fully.

See also shown in Figure 8, it is for the schematic flow sheet () of asynchronous receiver reading of data method of the present invention, find out that by knowing among the figure this asynchronous reception transmitter (Universal AsynchronousReceiver Transmitter) 1 has reception shift register (Receive Shift Register) 11, receiving register (Receive Register) 12 and counter 13; Wherein:

This reception shift register 11 is for can receive serial data, and its serial data comprises start bit, stop bit and data bit, and can be with Serial Data Transfer Mode to receiving register 12.

This receiving register 12 is for storing by receiving the serial data that shift register 11 is transmitted, and receiving register 12 is connected to microprocessor 2 by bus 3, and this receiving register 12 is provided with data address 121 and corresponding error bit 122, and data address 121 can store the data bit part in the serial data, and frame error position 122 is the correctness that can set stored data in its corresponding data address 121.

This counter 13 is can be when the serial data that receiving register 12 reception shift registers 11 are transmitted, with the accumulate mode mistake in computation position 122 correct data volumes that indicated.

And when asynchronous reception transmitter 1 receives serial data by receiving shift register 11, can be with the start bit of every group of serial data, stop bit and data bit are stored in and receive in the shift register 11, and after reception shift register 11 receives stop bit, data bit in the reception shift register 11 partly can be sent in the data address 121 in the receiving register 12, and in the receiving course of serial data, after receiving, data bit should receive a stop bit, if what received this moment is not a stop bit, the situation of " frame error " (Frame Error) will take place in that, or the sync check of activation mechanism is being arranged, and when the sync check position of receiving is mistake, can produce parity error (Parity Error), and in receiving register 12, can be set at mistake in the error bit 122 with respect to this group data address 121, if and data bit receives a stop bit after receiving, then in receiving register 12, can be set at correct in the error bit 122 with respect to this group data address 121.

Please consult Fig. 8-10 simultaneously, be depicted as the schematic flow sheet () of asynchronous receiver reading of data method of the present invention preferred embodiment, figure (two) and figure (three), learn by knowing among the figure, when receiving register 12 when receiving the data that shift register 11 transmitted, frame error position 122 is denoted as correct data volume in the calculating receiving register 12 that this counter 13 can continue, and when occurring being denoted as wrong data, error bit 122 stops to calculate, when counter 13 stops to calculate, this microprocessor 2 can be obtained the quantity that counter 13 is calculated by bus 3, and utilize this quantity to decide the number of times of reading of data address 121, and because of counter 13 correct data set number occurs being denoted as to calculate error bit 122, make microprocessor 2 not need read error position 122 once more, and only need be used as the number of times of microprocessor 2 reading of data addresses 121 according to the quantity that counter 13 is calculated, can be denoted as correct error bit 122 in the relative data address 121 stored data all read and finish, and when microprocessor 2 will be denoted as correct error bit 122 in the relative data address 121 stored data all read finish after, reading of data address 121 secondaries again, can be denoted as wrong error bit 122 in the relative data address 121 stored data reads come out.

Yet, according to this embodiment performed read six groups of stored serial datas in the receiving

register

12,2 need of its microprocessor read asynchronous reception transmitter 1 eight times, under identical group number and data status situation, existing mode need read ten secondaries, and hence one can see that, and the present invention can reduce the number of processes of microprocessor 2, and can improve reading efficiency, also can allow the improved efficiency of microprocessor 2.

Therefore; the method of reseptance of asynchronous receiver of the present invention is to be its key protection point at set counter 13 in the asynchronous receiver 1 with correct data volume that accumulate mode mistake in computation position 122 is indicated; so that the quantity that 2 need of microprocessor are calculated according to counter 13 is used as the number of times of microprocessor 2 reading of data addresses 121; can be denoted as correct error bit 122 in the relative data address 121 stored data all read; the efficient that reads with raising; and in the present embodiment; the auditor is convenient to be understood in order to make; this data address 121 is for utilizing arrangement mode in regular turn; and when actual operation, also can have discontinuous state, but therefore do not influence enforcement of the present invention.

Above-mentioned detailed description is at a kind of preferable possible embodiments explanation of the present invention, this embodiment is not in order to limit claim of the present invention, all other do not break away from the equivalence finished under the disclosed solution to be changed and modifies change, all should be included in the claim that the present invention contains.

Claims

1. the method for reseptance of an asynchronous receiver, this asynchronous reception transmitter has the reception shift register that can receive serial data, and described reception shift register connects the receiving register that can store by receiving the serial data that shift register transmitted, and receiving register is connected to default microprocessor by bus, and in receiving register, be provided with data address and corresponding error bit, and data address can store the data bit part in the serial data, and error bit set its correctness of stored data in the corresponding data address, it is characterized in that: being provided with in this asynchronous reception transmitter can be when receiving register receives the serial data that shift register transmits, calculate the counter that the frame error position is indicated correct data volume with accumulate mode, make microprocessor only need be used as the number of times of microprocessor reading of data address according to the quantity that counter calculated, can be denoted as correct error bit in the relative data address stored data all read and finish.

2. the method for reseptance of asynchronous receiver as claimed in claim 1 is characterized in that: this counter stops to calculate when error bit occurs being denoted as wrong data.