CN1783701A - High order sigma delta noise shaping direct digital frequency synthesizer - Google Patents

Abstract

A high stage Sigma Delta noise shaping direct digital frequency synthesizer includes a phase accumulator, a high stage Sigma Delta noise shaping interpolator, a sine or a cosine inquiry list, a D/A converter and a low-pass filter, among which, the interpolator includes a shaping accumulator and a delay circuit, outside N bit frequency digits are input into a phase accumulator and the output of which is connected with the shaping accumulator, the output of which is divided into a high p bit as the sine or cosine phase value and an intercepted low N-p bit and its output is connected with the delay circuit, the operation output of which is returned to the shaping accumulator, the output of the shaped phased value is output to the enquiry list, the output of which is connected with the input of the D/A converter, finally the output of which is connected to the input of the filter.

Description

A kind of high-order ∑ Δ noise shaping Direct Digital Frequency Synthesizers

Technical field

The present invention relates to a kind of high-order ∑ Δ noise shaping Direct Digital Frequency Synthesizers that is used to improve the output signal dynamic characteristic.

Background technology

Direct Digital Frequency Synthesizers (DDFS) is a kind of important low-cost high resolution frequency synthetic method.Different with the synthesizer based on phase-locked loop, DDFS and digital CMOS process are compatible fully, often are embedded into base band ASIC transceiver.Though DDFS has come out much years, because the restriction of Digital Logical Circuits and digital to analog converter performance can only be employed with narrow band frequency synthetic.Along with the improvement of Digital Logical Circuits and digital to analog converter technology, DDFS has become the synthetic main flow of wideband frequency recently.As shown in Figure 1, traditional DDFS comprises a phase accumulator 20 that generates phase value based on incoming frequency word 10.DDFS uses the mode that searches sine or cosine question blank 30 phase value is converted to sinusoidal magnitude value, and its restricted width is in the resolution of digital to analog converter 40.The anti-spike filter 50 that is added in digital to analog converter 40 back will filter out the glitch noise in data conversion process.

But the structures shape of DDFS itself have a large amount of clutters in its output signal, the source of these clutters comprises: as phase-accumulated 20 truncation noise of sine table address, be stored in the sample magnitude truncation noise in the question blank 30, the noise of digital to analog converter 50 and the phase noise of clock.Wherein the influence that brings with phase truncation again is the most serious.Because the periodicity of DDFS itself, the process that has caused phase truncation also are periodic, the phase truncation noise of Yin Ruing is very obvious on some Frequency point thus.

The method of multiple inhibition phase truncation noise has been proposed so far.The most direct scheme is exactly the length that increases the phase place word, but can cause the rapid increase of synthesizer hardware.And along with the increase of phase place word, the figure place of phase accumulator 20 also increases thereupon, will influence the speed that phase accumulator 20 adds up like this.

Summary of the invention

The objective of the invention is to, a kind of high-order ∑ Δ noise shaping Direct Digital Frequency Synthesizers (DDFS) that is used to improve the output signal dynamic characteristic is provided, eliminated because the quantizing noise that phase truncation caused.This method is by the MATLAB simulating, verifying, and realizes on chip.The test result of experiment chip shows: compare with the DDFS that does not add high-order ∑ Δ noise shaping interpolater, the dynamic range of no parasitic signal (SFDR) has improved 10dB, and chip area does not have to increase substantially.This invention also can reduce the ROM area of DDFS under the situation that does not reduce SFDR, and ROM accounts for the very most of of whole DDFS area.

The present invention is a kind of high-order ∑ Δ noise shaping Direct Digital Frequency Synthesizers, comprising: a phase accumulator, high-order ∑ Δ noise shaping interpolater, sine or cosine question blank, digital to analog converter and low pass filter, it is characterized in that,

Wherein high-order ∑ Δ noise shaping interpolater comprises shaping accumulator and delay circuit; Outside N bit frequency word is input to phase accumulator, and the output of phase accumulator is connected to the shaping accumulator; The output of shaping accumulator is divided into as the high p position of sine or cosine phase value with as intercepted low N-p position;

The output of wherein low N-p position is connected to delay circuit, and delay circuit computing output is returned again and is connected to the shaping accumulator; The phase value output of shaping is connected to sine or cosine question blank, the input that digital to analog converter is linked in the output of sine or cosine question blank again, the input that low pass filter is linked in the output of last digital to analog converter.

Wherein phase accumulator is 16 bit accumulators.

Wherein, this high-order ∑ Δ interpolater is 4 rank or more than 4 rank.

Shaping accumulator wherein is 16 bit accumulators, and wherein most-significant byte output is as the phase value of sine or cosine, and least-significant byte turns back to the shaping accumulator again through delay circuit and adds up.

Shaping accumulator wherein is 16 bit accumulators.Wherein most-significant byte output is as the phase value of sine or cosine, and this phase value is connected to sine or cosine table.

Wherein sine or cosine table are input 8 bit address, the sine or the cosine table of 12 amplitudes of output.

Wherein digital to analog converter is 12 figure place weighted-voltage D/A converters.

Wherein low pass filter is anti-spike low pass filter.

Description of drawings

For further specifying technology contents of the present invention, be described in detail as follows below in conjunction with example and accompanying drawing, wherein:

Fig. 1 is the structured flowchart of conventional digital direct synthesizer;

Fig. 2 is the structured flowchart that the present invention has increased the digital direct frequency synthesizer of high-order ∑ Δ shaping interpolater;

Fig. 3 is the example of one 4 rank ∑ Δ shaping interpolater of design.

Fig. 4 is the example of one 5 rank ∑ Δ shaping interpolater of design.

Fig. 5 is the chip photo in conjunction with a Direct Digital Frequency Synthesizers of the structural design of Fig. 2 and Fig. 3.

Fig. 6 a, b are integrated and the contrast figure of the spectral characteristic of the frequency synthesis of not integrated ∑ Δ shaping.

Embodiment

According to Fig. 1, the output of a desirable Direct Digital Frequency Synthesizers can be expressed as:

$A_{\mathrm{out}}=A\sin \left(\frac{2\mathrm{\πWt}}{2^n{T}_{\mathrm{clk}}}\right)=A\sin \left(\frac{2\mathrm{\πWi}}{2^n}\right)$

Wherein A is the full amplitude output valve of digital to analog converter, time variable t=T _ClkI.The output here is desirable sine wave, yet owing to certainly existing noise jamming in the following reason output wave signal.

1, the synthesizer step-length is f _Clk/ 2 ⁿIn order to obtain higher frequency resolution, use the accumulator of longer figure place usually, for example 16.Yet big accumulator needs big with 2 ⁿQuestion blank for the address.The ROM question blank has just occupied the major part of whole DDFS area like this.In order to reduce the area of ROM question blank, phase value was blocked a part usually before being used to the question blank address.This blocks the introducing quantizing noise, and the noise that this quantizing noise can be described as a linearity is added on the sinusoidal wave phase place.Signal to noise ratio snr by the phase truncation introducing _p=6.02p-3.992dB, wherein p is the width of phase place word.

2, the output valve width of ROM question blank is subjected to the restriction of the figure place of digital to analog converter.Only with the byte of finite width represent sine wave must introduce quantizing noise be added to output signal on.Similar to the phase truncation noise, because the signal to noise ratio snr that limited output amplitude width is introduced _A=6.02D+1.76dB, wherein D is the resolution of digital to analog converter.

Consider because phase truncation e _pThe quantizing noise and the amplitude that produce are blocked (limited ROM value width) e _A, suppose the phase quantization noise much smaller than phase place, this complete DDFS output can be expressed as:

$A_{\mathrm{out}}=A\sin (\frac{2\mathrm{\πWi}}{2^n}+e_p\left(i\right))+{\mathrm{Ae}}_A\left(i\right)\≈A\sin \left(\frac{2\mathrm{\πWi}}{2^n}\right)+{\mathrm{Ae}}_p\left(i\right)\cos \left(\frac{2\mathrm{\πWi}}{2^n}\right)+{\mathrm{Ae}}_A\left(i\right)$

Therefore as can be seen, phase noise is output the integration of signal and has modulated on amplitude.Above-mentioned equation provides simple DDFS output and quantization noise model.

Overlapping for avoiding in data conversion process occurring, the frequency that is synthesized is less than the clock frequency of DDFS.Therefore have over-sampling in DDFS, this just provides possibility for noise shaping.Noise shaping can be transferred to high-frequency region to phase noise, makes things convenient for low pass filter filters out.

See also Fig. 2, a kind of high-order ∑ of the present invention Δ noise shaping Direct Digital Frequency Synthesizers comprises: a phase accumulator 20, high-order ∑ Δ noise shaping interpolater 21, sine or cosine question blank 30, digital to analog converter 40 and low pass filter 50.

Wherein high-order ∑ Δ noise shaping interpolater 21 comprises shaping accumulator 22 and delay circuit 23; Outside N bit frequency word is input to phase accumulator 20, and the output of phase accumulator 20 is connected to shaping accumulator 22; The output of shaping accumulator 22 is divided into as the high p position of sine or cosine phase value with as intercepted low N-p position; Wherein phase accumulator 20 is 16 bit accumulators; This high-order ∑ Δ interpolater 21 is 4 rank or more than 4 rank; Shaping accumulator 22 wherein is 16 bit accumulators, and wherein most-significant byte output is as the phase value of sine or cosine, and least-significant byte turns back to the shaping accumulator again through delay circuit and adds up;

The output of wherein low N-p position is connected to delay circuit 23, and delay circuit 23 computings output is returned again and is connected to shaping accumulator 22; The phase value output of shaping is connected to sine or cosine question blank 30, the input that digital to analog converter 40 is linked in the output of sine or cosine question blank 30 again, the input that low pass filter 50 is linked in the output of last digital to analog converter; Shaping accumulator 22 wherein is 16 bit accumulators; Wherein most-significant byte output is as the phase value of sine or cosine, and this phase value is connected to sine or cosine table, and wherein sine or cosine table are input 8 bit address, the sine or the cosine table of 12 amplitudes of output.

Wherein digital to analog converter 40 is 12 figure place weighted-voltage D/A converters.

Wherein low pass filter 50 is anti-spike low pass filter.

See also shown in Figure 2 again, the numerical frequency word that accumulator produces corresponding frequency synthesis to being used to of receiving is summed into the digital value of a N position, high p position in the digital value of this N position is as the phase value of sine or cosine, and low N-p position turns back to accumulator again through delay circuit and adds up.The transfer function of delay circuit is 1-(1-Z ^-1) ⁿ, wherein n is the exponent number of ∑ Δ noise shaping interpolater.Process is hanged down the delay computing of N-p position and is returned again and add up, and revises the high p position as the phase value of sine or cosine.At this moment DDFS output can be expressed as:

$A_{\mathrm{out}}=A\sin (\frac{2\mathrm{\πWi}}{2^n}+e_p\left(i\right){(1-z^{-1})}^k)+{\mathrm{Ae}}_A\left(i\right)$

$\≈A\sin \left(\frac{2\mathrm{\πWi}}{2^n}\right)+{\mathrm{Ae}}_p\left(i\right){(1-z^{-1})}^k\cos \left(\frac{2\mathrm{\πWi}}{2^n}\right)+{\mathrm{Ae}}_A\left(i\right)$

Phase noise has been added a high pass filter as can be seen from the above equation.This algorithm greatly reduces near the phase truncation noise the output frequency.Phase noise after the high pass shaping can be by the low pass filter filters out behind the digital to analog converter.Therefore the noise of being introduced by phase truncation is greatly diminished.

Shaping is exported high p position and is connected to sine or cosine table through high-order ∑ Δ shaping interpolater, converts digital sine or cosine amplitude to by sine or cosine table.This digital sine or cosine amplitude convert analog sine or cosine signal to through digital to analog converter and low pass filter again.

By above analysis, two kinds of high-order ∑s of following specific design Δ shaping interpolater.In order to realize high-speed applications, adopted single cycle ∑ Δ shaping interpolater.Fig. 3 and Fig. 4 are requirement, 4 rank of design and the 5 rank ∑ Δ shaping interpolaters according to different shaping degree.This structure has realized blocking (N-p) LSB (low-value) with equation 1-(1-z ^-1) ^kHigh pass noise shift " A " 24 expression (N-p) LSB among Fig. 3 and Fig. 4.P MSB (high-value) is used as the address of sine look up table 30.Because multiplier becomes the bottleneck of area and speed probably, shifting function is used to replace multiplier in conjunction with add operation.In Fig. 3 and Fig. 4 "＜＜" 25 representatives are to shifting left, then "＜＜2 " 25 representatives promptly are equivalent to take advantage of 4 to moving to left two.The ∑ Δ noise shaping interpolater of Fig. 3 and Fig. 4 adopts 16 inputs to add up, and 8 are blocked.

Now be that example specifies and how to realize blocking (N-p) LSB (low-value) with equation 1-(1-z with Fig. 3 ^-1) ^kHigh pass noise shift.Noise accumulator 22 adds up the output of the output valve of phase accumulator 20 and delay circuit 23 in Fig. 3, and output is divided into two parts, as the high p position of the phase value of sine or cosine with as intercepted low N-p position.Wherein low N-p position is through Z ^-1Postpone to obtain exporting AZ ^-1, AZ ^-1Be divided into three the tunnel.Wherein one road bit manipulation that moves to left promptly takes advantage of 2 operations to obtain 2AZ ^-1Output is connected to adder 26; Another road promptly takes advantage of 4 operations to obtain 4AZ through moving to left two bit manipulations ^-1Output, this output divide two-way wherein one the tunnel also to be connected to adder 26, export through the addition of adder and obtain 6AZ ^-1Output; Third Road postpones Z ^-2The AZ that attains the Way ^-3Output, this output also divides two-way wherein one the road to be connected to adder 28.The output 6AZ of adder 26 ^-1Also be divided into two-way, wherein one the tunnel also be connected to adder 28, adder 28 is 6AZ like this ^-1And AZ ^-3Addition obtains A (6Z ^-1+ Z ^-3) output, Z is passed through in this output again ^-1Postpone to obtain exporting A (6Z ^-2+ Z ^-4).AZ ^-3Another road of output promptly takes advantage of 4 operations to obtain 4AZ through moving to left two bit manipulations ^-3Output also is connected to adder 27, and 4AZ ^-1Another road of output also is connected to adder 27, so adder 27 is 4AZ ^-1And AZ ^-3Addition obtains 4A (Z ^-1+ Z ^-3) output.A (6Z ^-2+ Z ^-4) output gets complement code and be connected to adder 29 later on, 4A (Z ^-1+ Z ^-3) output also be connected to adder 29, obtain exporting A (4Z at last ^-1-6Z ^-2+ 4Z ^-3-Z ^-4), i.e. A (1-(1-Z ^-1) ^-4), then the shaping accumulator is returned in output again, has realized at last blocking (N-p) LSB (low-value) with equation 1-(1-z ^-1) ^kHigh pass noise shift.

Fig. 5 is the chip photo in conjunction with a Direct Digital Frequency Synthesizers of the structural design of Fig. 2 and Fig. 3.As can be seen from the figure, the chip of this Direct Digital Frequency Synthesizers mainly comprises three parts: accumulator and 4 rank ∑ Δ shaping interpolaters 70, sine look up table 60 and digital to analog converter 80.In accumulator and 4 rank ∑ Δ shaping interpolaters, 70 modules a control end is arranged, integrated or not integrated ∑ Δ shaping when being used for controlling frequency synthesis is used for the spectral characteristic of the integrated frequency synthesis with the shaping of not integrated ∑ Δ of convenient contrast.Fig. 6 a, b are integrated and the contrast of the spectral characteristic of the frequency synthesis of not integrated ∑ Δ shaping, and obviously the shaping of integrated as can be seen ∑ Δ is better than not integrated spectral characteristic, promptly do not have the dynamic range (SFDR) of parasitic signal and want big.

Claims (8)

1, a kind of high-order ∑ Δ noise shaping Direct Digital Frequency Synthesizers comprises: a phase accumulator, high-order ∑ Δ noise shaping interpolater, sine or cosine question blank, digital to analog converter and low pass filter, it is characterized in that,

Wherein high-order ∑ Δ noise shaping interpolater comprises shaping accumulator and delay circuit; Outside N bit frequency word is input to phase accumulator, and the output of phase accumulator is connected to the shaping accumulator; The output of shaping accumulator is divided into as the high p position of sine or cosine phase value with as intercepted low N-p position;

The output of wherein low N-p position is connected to delay circuit, and delay circuit computing output is returned again and is connected to the shaping accumulator; The phase value output of shaping is connected to sine or cosine question blank, the input that digital to analog converter is linked in the output of sine or cosine question blank again, the input that low pass filter is linked in the output of last digital to analog converter.

2, high-order ∑ Δ noise shaping Direct Digital Frequency Synthesizers according to claim 1 is characterized in that wherein phase accumulator is 16 bit accumulators.

3, high-order ∑ Δ noise shaping Direct Digital Frequency Synthesizers according to claim 1 is characterized in that, wherein, this high-order ∑ Δ interpolater is 4 rank or more than 4 rank.

4, high-order ∑ Δ noise shaping Direct Digital Frequency Synthesizers according to claim 1, it is characterized in that, shaping accumulator wherein is 16 bit accumulators, wherein most-significant byte output is as the phase value of sine or cosine, and least-significant byte turns back to the shaping accumulator again through delay circuit and adds up.

5, high-order ∑ Δ noise shaping Direct Digital Frequency Synthesizers according to claim 1 is characterized in that shaping accumulator wherein is 16 bit accumulators.Wherein most-significant byte output is as the phase value of sine or cosine, and this phase value is connected to sine or cosine table.

6, high-order ∑ Δ noise shaping Direct Digital Frequency Synthesizers according to claim 5 is characterized in that, wherein sine or cosine table are input 8 bit address, the sine or the cosine table of 12 amplitudes of output.

7, high-order ∑ Δ noise shaping Direct Digital Frequency Synthesizers according to claim 1 is characterized in that wherein digital to analog converter is 12 figure place weighted-voltage D/A converters.

8, high-order ∑ Δ noise shaping Direct Digital Frequency Synthesizers according to claim 1 is characterized in that wherein low pass filter is anti-spike low pass filter.

Images