CN1779643A - Basic inputting and outputting system and method for upgrading FLASH device - Google Patents
Basic inputting and outputting system and method for upgrading FLASH device Download PDFInfo
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- CN1779643A CN1779643A CNA2004100972870A CN200410097287A CN1779643A CN 1779643 A CN1779643 A CN 1779643A CN A2004100972870 A CNA2004100972870 A CN A2004100972870A CN 200410097287 A CN200410097287 A CN 200410097287A CN 1779643 A CN1779643 A CN 1779643A
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- flash device
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
- G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
- G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
- G11C29/18—Address generation devices; Devices for accessing memories, e.g. details of addressing circuits
- G11C29/30—Accessing single arrays
- G11C29/32—Serial access; Scan testing
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Abstract
A method for loading basic I / O system upgrade program on FLASH component includes embedding TBC on main control board of product and connecting it to central processing unit, connecting boundary scan component on service board to be boundary scan chain connected with FLASH component, connecting said scan chain to boundary scan system bus through ASP, utilizing central processing unit to call basic I / O system upgrade program to drive TBC for generating boundary scan signal stream, connecting FLASH component to boundary scan chain through boundary scan system bus and ASP to load basic I / O system upgrade program onto FLASH component.
Description
Technical field
The present invention relates to method for upgrading software, refer to the method for the Basic Input or Output System (BIOS) (BIOS) of FLASH device in a kind of upgrading products especially.
Background technology
The programming mode of FLASH device is divided into two big classes: (OBP On-BoardProgramming) and from plate (Off-Board) programmes in the plate programming.Be meant after programming device is soldered on the printed circuit board (PCB) in plate programming it is programmed.Be meant before programming device is installed to printed circuit board (PCB) from plate programming it is programmed.
Utilize ICT (ICT:In-Circuit Test in plate programming method commonly used, on-line testing) online programming (ICP that carries out, In-Circuit Programming), systems programming (the ISP that utilizes CPU to carry out, In-System Programming) and utilize JTAG (Joint Test Action Group, JTAG often refers to boundary scan technique) carry out in plate programming etc.
The online programming that utilizes ICT to carry out is meant by ICT equipment and is connected on the printed circuit board (PCB), provides necessary isolation and programming signal to drive and realizes programming.But the ICT apparatus expensive also can't safeguarded on-the-spot the use.
Systems programming is meant the programming that realizes programming device with programmed algorithm of wiping of carrying out programming device by the CPU in the system.As shown in Figure 1, by address wire and the control line that CPU controls the FLASH device, realize the bios program upgrading.
The shortcoming of this kind method is as follows:
1, require that cpu chip is arranged on the circuit board, and can operate as normal;
2, to cause the loss that to retrieve in order preventing to upgrade to fail, to need, when the upgrading failure, more original program is write back again program backup portion to be upgraded; Need the program of the read-write FLASH chip of write specialized, the FLASH model is different, and program also needs to change;
If fail in 3 escalation processs, will cause system normally to start.
Along with the development of JTAG technology, support that the device of JTAG standard is more and more, though FLASH device itself is not supported the JTAG standard, all support the JTAG standard the chip (as CPU, bridge sheet, logic chip etc.) that interconnects with FLASH.So utilize the JTAG technology to realize that the programming at plate of bios program in the FLASH device become a kind of important means.As shown in Figure 2, for utilizing computing machine and loaded cable to realize the synoptic diagram of bios program upgrading in the FLASH.Upgrading software system and the needed data file of upgrading have been installed on the computing machine, can pass through multiple hardwares interface shapes such as parallel port, PCI (PeripheralComponent Interconnection local bus) interface, network interface and be connected with circuit board, loading control of intermediate demand is transferred to boundary scan interface (jtag interface) on the circuit board with these interfaces.Control address wire, data line and the control line of FLASH device by the JTAG chain of CPU and realize the bios program upgrading.
Said method shortcoming as follows:
1, needs terminal computer, special loading control and loaded cable;
2, can't realize the remote upgrade of BIOS.
Summary of the invention
The invention provides a kind of BIOS upgrade method of FLASH device, can be effectively the bios program of FLASH device in the product be carried out online or remote upgrade.
The inventive method comprises: embed a test bus controller (TBC) on the master control borad of product, be connected with CPU (central processing unit); Boundary scanning device on the business board is connected into boundary scan chain, the FLASH device on the business board is connected with boundary scan chain; Described boundary scan chain is connected on the border scanning system bus by the addressable scanning port (ASP) that is arranged on the business board;
Call the Basic Input or Output System (BIOS) ROMPaq by CPU (central processing unit), driving test bus controller produces the boundary scan signal flow, passes through border scanning system bus and addressable scanning port, the boundary scan chain that control is connected with the FLASH device is loaded into the Basic Input or Output System (BIOS) ROMPaq in the FLSAH device.
Boundary scan chain on the described business board can be one or more; Each FLASH device can be connected with identical or different boundary scan chain.
Described Basic Input or Output System (BIOS) ROMPaq comprises programming information file and upgrade data file; Described programming information file comprises the link information of boundary scan chain information, FLASH device information, FLASH device and boundary scan chain and the time sequence information of operation FLASH; After CPU (central processing unit) receives the upgrading order that the user sends, according to designated parameters in the order, programming information file and upgrade data file are construed to boundary scan data, send into the border scanning system bus by driving described test bus controller generation boundary scan signal flow.
Described upgrading order can be by sending or send by the Internet Long-distance Control with the direct-connected control desk of master control borad.
Described programming information file and upgrade data file can download to the storer of product from other storage medium in the process of upgrading.
Described programming information file and upgrade data file can be stored in Compact Flash (CF) card, flash memory or other storage medium of product in advance.
Described border scanning system bus is made up of five boundary scan signal wires, is respectively: test pattern is selected incoming line, test clock incoming line, test data incoming line, test data output line and test logic reset line.
Described test bus controller can all turn-off the signal that transmits in the scan signal line of border.
According to said method of the present invention, if master control borad is provided with the backup plate, and master control borad is provided with the FLASH device that need carry out the Basic Input or Output System (BIOS) upgrading, then the FLASH device on the master control borad is connected with boundary scan chain on this plate, be connected on the border scanning system bus by the addressable scanning port, and make slave board have identical setting; By turn-offing the border scanning system bus on master control borad and one of them plate of slave board, realize the Basic Input or Output System (BIOS) program upgrade of the FLASH device on another plate.
The inventive method has following advantage:
1, BIOS upgrading order can issue at the scene, also can long-rangely issue, and can realize online upgrading or the remote upgrade of BIOS in the product so easily.Upgrading and maintenance cost have been reduced.
2, the present invention can realize the bios program upgrading of all FLASH devices in the product, and the BIOS upgrading of master control borad can adopt the mode of masterslave switchover to realize.
3, the present invention only needs the master control borad operate as normal to get final product, and each business board only need power on and can upgrade, and restrictive condition is considerably less.
4, the present invention is not influenced upgrading again by unexpected termination in escalation process, and reliability is than higher.
Description of drawings
Fig. 1 is the synoptic diagram that the signal wire that utilizes CPU on the circuit board directly to control FLASH is realized the BIOS upgrading;
Fig. 2 realizes bios program upgrading synoptic diagram for utilizing computing machine and loaded cable;
Fig. 3 realizes the frame diagram of BIOS upgrading for the present invention;
Fig. 4 is the annexation synoptic diagram of the boundary scan chain in FLASH device and the chip in the embodiment of the invention;
Fig. 5 is a software control flow chart in the inventive method.
Embodiment
General electronic product all has master control borad and business board, as shown in Figure 3, a TBC (Test BusController, test controller) is embedded on the master control borad, described TBC for example: the LVT8980 of the SCANSTA101 of NS company, TI company etc.; ASP (Addressable scan port, addressable scanning port) chip is placed on each business board, described ASP for example: the LVT8996 of the SCANSTA111 of NS company, TI company etc.; JTAG device on each business board all connects into one or more of JTAG chains, and is connected with ASP on every block of plate.The pin of the FLASH device on the business board is connected with boundary scan cell in JTAG chain wherein; TBC communicates by letter with each ASP by the JTAG system bus on the backboard.Concrete grammar is: during the TBC transmitting order to lower levels, carry the address of the ASP that needs gating, the ASP on the matching addresses is by gating, and beams back a respond packet, and the address of oneself is returned.The ASP that matching addresses does not go up does not send out respond packet.An ASP can be connected with one or more JTAG chain, and ASP is by selecting different JTAG chains, and the corresponding FLASH device of control realizes that bios program loads.
The JTAG system bus is made up of five JTAG signal wires, comprise TMS (Test Mode Selectinput, test pattern selection incoming line), TCK (Test ClocK input, the test clock incoming line), TDI (Test Data Input, the test data incoming line), TDO (Test Data Output, the test data output line) and TRST (Test Logic Reset, test logic reset line).
Referring to Fig. 4, be the annexation synoptic diagram of the boundary scan chain of a FLASH device and a JTAG chip.Support among the figure that each boundary scan cell connects into a JTAG chain in the chip of JTAG standard, and the JTAG chain is connected with the pin of FLASH, five JTAG signal wires are controlled this JTAG chain by test access port (TAP), thereby by the pin of JTAG chain control FLASH, realize read-write operation indirectly to the FLASH device.A FLASH device is connected with a JTAG chain, if on a business board a plurality of FLASH devices are arranged, then this a plurality of FLASH devices can be connected with a JTAG chain simultaneously, also can be respectively and different JTAG chain connections.
If master control borad is provided with the backup plate, the CPU in then also embedding a TBC and back up plate on the backup plate is connected.If master control borad is provided with the FLASH device that needs upgrading, then respectively the FLASH device on the active/standby plate is connected with boundary scan chain on this plate, be connected on the JTAG system bus by ASP; By turn-offing the JTAG system bus on the active/standby plate respectively, realize the bios program upgrading of the FLASH device on the active/standby plate.Concrete grammar is: make the TBC on the backup plate be broken into high resistant to whole the closing of the signal of core bus side, by the JTAG chain that is connected with the FLASH device on the TBC gating backup plate on the control of the CPU on the master control borad master control borad, realize the bios program upgrading of FLASH device on the backup plate; Otherwise, make the TBC on the master control borad be broken into high resistant to whole the closing of the signal of core bus side, by the JTAG chain that is connected with the FLASH device on the TBC gating master control borad on the CPU control backup plate on the backup plate, realize the bios program upgrading of FLASH device on the master control borad.
The BIOS ROMPaq, can be in the process of upgrading by any way, as FTP (FileTransfer Protocol, file transfer protocol (FTP)) etc. download to the storer of product from other storage medium, be kept at CF (Compact Flash Card, the Compact Flash (CF) card) card of product in advance or FLASH goes up or other storage medium in.
The BIOS ROMPaq comprises programming information file and the needed data file of upgrading, and wherein the programming information literature kit contains the link information of JTAG chain information, FLASH device information, JTAG chain and FLASH, the time sequence information of operation FLASH etc.After the BIOS upgrading order that CPU reception user in the master control borad sends, start an administration module, as shown in Figure 5, administration module receives and resolve command, if upgrading order, then at first compile the programming information file, extract scan chain information, the link information of FLASH and JTAG link and FLASH time sequential routine, put out the JTAG data in order according to correlation parameter and upgrade data running paper in the upgrading order then, drive TBC chip output JTAG signal at last and flow on the JTAG system bus, realize being attached thereto the bios program upgrading of the FLASH device that connects by the corresponding JTAG chain of gating.
The upgrading order can adopt the mode of order line to issue by the control desk scene that is connected with master control borad, also can start the BIOS upgrading by long-range CPU that is handed down on the master control borad such as Internets.
The above; only for the preferable embodiment of the present invention, but protection scope of the present invention is not limited thereto, and anyly is familiar with those skilled in the art in the technical scope that the present invention discloses; the variation that can expect easily or replacement all should be encompassed within protection scope of the present invention.Therefore, protection scope of the present invention should be as the criterion with the protection domain of claims.
Claims (9)
1, the method for a kind of Basic Input or Output System (BIOS) of upgrading FLASH device (BIOS) is characterized in that comprising:
On the master control borad of product, embed a test bus controller (TBC), be connected with CPU (central processing unit); Boundary scanning device on the business board is connected into boundary scan chain, the FLASH device on the business board is connected with boundary scan chain; Described boundary scan chain is connected on the border scanning system bus by the addressable scanning port (ASP) that is arranged on the business board;
Call the Basic Input or Output System (BIOS) ROMPaq by CPU (central processing unit), driving test bus controller produces the boundary scan signal flow, passes through border scanning system bus and addressable scanning port, the boundary scan chain that control is connected with the FLASH device is loaded into the Basic Input or Output System (BIOS) ROMPaq in the FLSAH device.
2, the method for the Basic Input or Output System (BIOS) of upgrading FLASH device as claimed in claim 1 is characterized in that: the boundary scan chain on the described business board can be one or more; Each FLASH device can be connected with identical or different boundary scan chain.
3, the method for the Basic Input or Output System (BIOS) of upgrading FLASH device as claimed in claim 2 is characterized in that: described Basic Input or Output System (BIOS) ROMPaq comprises programming information file and upgrade data file; Described programming information file comprises the link information of boundary scan chain information, FLASH device information, FLASH device and boundary scan chain and the time sequence information of operation FLASH; After CPU (central processing unit) receives the upgrading order that the user sends, according to designated parameters in the order, programming information file and upgrade data file are construed to boundary scan data, send into the border scanning system bus by driving described test bus controller generation boundary scan signal flow.
4, the method for the Basic Input or Output System (BIOS) of upgrading FLASH device as claimed in claim 3 is characterized in that: described upgrading order, and can be by sending or send by the Internet Long-distance Control with the direct-connected control desk of master control borad.
5, the method for the Basic Input or Output System (BIOS) of upgrading FLASH device as claimed in claim 3 is characterized in that: described programming information file and upgrade data file can download to the storer of product from other storage medium in the process of upgrading.
6, the method for the Basic Input or Output System (BIOS) of upgrading FLASH device as claimed in claim 3 is characterized in that: described programming information file and upgrade data file can be stored in Compact Flash (CF) card, flash memory or other storage medium of product in advance.
7, the method for the Basic Input or Output System (BIOS) of upgrading FLASH device as claimed in claim 2, it is characterized in that: described border scanning system bus is made up of five boundary scan signal wires, is respectively: test pattern is selected incoming line, test clock incoming line, test data incoming line, test data output line and test logic reset line.
8, the method for the Basic Input or Output System (BIOS) of upgrading FLASH device as claimed in claim 7 is characterized in that: described test bus controller can all turn-off the signal that transmits in the scan signal line of border.
9, the method for the Basic Input or Output System (BIOS) of upgrading FLASH device as claimed in claim 8 is characterized in that:
If master control borad is provided with the backup plate, and master control borad is provided with the FLASH device that need carry out the Basic Input or Output System (BIOS) upgrading, then the FLASH device on the master control borad is connected with boundary scan chain on this plate, be connected on the border scanning system bus by the addressable scanning port, and make slave board have identical setting; By turn-offing the border scanning system bus on master control borad and one of them plate of slave board, realize the Basic Input or Output System (BIOS) program upgrade of the FLASH device on another plate.
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| Application Number | Priority Date | Filing Date | Title |
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| CNB2004100972870A CN100337199C (en) | 2004-11-25 | 2004-11-25 | Basic inputting and outputting system and method for upgrading FLASH device |
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| CNB2004100972870A CN100337199C (en) | 2004-11-25 | 2004-11-25 | Basic inputting and outputting system and method for upgrading FLASH device |
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| CN1779643A true CN1779643A (en) | 2006-05-31 |
| CN100337199C CN100337199C (en) | 2007-09-12 |
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102388366A (en) * | 2011-09-22 | 2012-03-21 | 华为技术有限公司 | Method and device for realizing compatibility of different processors |
| WO2020240227A1 (en) * | 2019-05-31 | 2020-12-03 | Micron Technology, Inc. | A memory device architecture coupled to a system-on-chip |
| CN112463243A (en) * | 2019-09-09 | 2021-03-09 | 英业达科技有限公司 | Online cascade loading firmware system based on boundary scanning and method thereof |
Family Cites Families (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP3762643B2 (en) * | 2001-01-10 | 2006-04-05 | 株式会社ケンウッド | Mobile terminal device, stored data update method, and firmware update method |
| KR100443918B1 (en) * | 2002-01-25 | 2004-08-09 | 삼성전자주식회사 | Method for Remote Upgrade of FPGA Program |
| CN1270324C (en) * | 2002-06-14 | 2006-08-16 | 华为技术有限公司 | FLASH device onboard programming method based on boundary scanning technique |
| CN100495954C (en) * | 2003-01-27 | 2009-06-03 | 华为技术有限公司 | Method and system for loading or updating logic device |
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2004
- 2004-11-25 CN CNB2004100972870A patent/CN100337199C/en active Active
Cited By (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102388366A (en) * | 2011-09-22 | 2012-03-21 | 华为技术有限公司 | Method and device for realizing compatibility of different processors |
| CN102388366B (en) * | 2011-09-22 | 2013-03-20 | 华为技术有限公司 | Method and device for realizing compatibility of different processors |
| US9298470B2 (en) | 2011-09-22 | 2016-03-29 | Huawei Technologies Co., Ltd. | Method and apparatus for selecting bios program for a processor |
| WO2020240227A1 (en) * | 2019-05-31 | 2020-12-03 | Micron Technology, Inc. | A memory device architecture coupled to a system-on-chip |
| US11443821B2 (en) | 2019-05-31 | 2022-09-13 | Micron Technology, Inc. | Memory device architecture coupled to a System-on-Chip |
| US11749369B2 (en) | 2019-05-31 | 2023-09-05 | Micron Technology, Inc. | Memory device architecture coupled to a system-on-chip |
| CN112463243A (en) * | 2019-09-09 | 2021-03-09 | 英业达科技有限公司 | Online cascade loading firmware system based on boundary scanning and method thereof |
| CN112463243B (en) * | 2019-09-09 | 2022-11-18 | 英业达科技有限公司 | Online cascade loading firmware system based on boundary scanning and method thereof |
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| CN100337199C (en) | 2007-09-12 |
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Effective date of registration: 20201130 Address after: 225700 No.1 science and Technology Park, Zhangguo Town, Xinghua City, Taizhou City, Jiangsu Province Patentee after: Jiangsu Shuangjin New Material Co.,Ltd. Address before: 510640 Unit 2414-2416, Main Building, No. 371 Wushan Road, Tianhe District, Guangzhou City, Guangdong Province Patentee before: GUANGDONG GAOHANG INTELLECTUAL PROPERTY OPERATION Co.,Ltd. Effective date of registration: 20201130 Address after: 510640 Unit 2414-2416, Main Building, No. 371 Wushan Road, Tianhe District, Guangzhou City, Guangdong Province Patentee after: GUANGDONG GAOHANG INTELLECTUAL PROPERTY OPERATION Co.,Ltd. Address before: 518129 Bantian HUAWEI headquarters office building, Longgang District, Guangdong, Shenzhen Patentee before: HUAWEI TECHNOLOGIES Co.,Ltd. |
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