CN1771601A - Electronic packaging structure with integrated distributed decoupling capacitors - Google Patents

Abstract

An electronic packaging structure, comprising a substrate; a first electrode layer on a first side of said substrate; dielectric material arranged in a preselected pattern on said first electrode layer); and a second electrode layer forming a plurality of second electrodes which are arranged on said preselected pattern of dielectric material to form a distributed capacitive structure together with said first electrode layer, is characterized in that a second decoupling capacitor stage is arranged on a second side of said substrate opposite said first side and is electrically connected to said distributed capacitive structure, said second decoupling stage having a capacity higher than that of said distributed capacitive structure.

Description

Electron package structure with integrated distributed decoupling capacitors

The present invention relates to a kind of electron package structure, comprise first electrode layer on substrate, described substrate first side, with the graphical layout of preliminary election on described first electrode layer dielectric material and form the second electrode lay of a plurality of the second electrode lays, described a plurality of the second electrode lay is arranged on the described preliminary election figure of dielectric material, forms distributed capacitive structure as the first decoupling level with described first electrode layer.The invention still further relates to a kind of integrated circuit that comprises electron package structure of the present invention.

Power supply to the system on chip that comprises the high-speed figure core by high electric current and low voltage operating need have high-speed power module and minimum parasitic passive component in supply network, to avoid noise most possibly.

The known technology that is used to reduce noise level is to arrange discrete capacitor between relevant voltage pin.Usually the discrete capacitor of installing apart from the semiconductive core certain distance is electrically coupled to semiconductive core by a plurality of power wirings or big power bus.These power wirings are the high inductance path of representative usually, should that these paths are reduced to is minimum by discrete capacitor being moved closer to as far as possible semiconductor chip.For the high frequency decoupling capacitance that is mounted closest core, its characteristic aspect spurious impedance has determined maximum current transient and has determined system speed thus.The performance of this electric capacity is unreasonable to be thought, current transient just can be moved to higher value in the given tolerance for the admissible voltage fluctuation and the higher-order of oscillation more.

US4,945,399 disclose a kind of electron package structure, and it comprises a plurality of integrated, distributed decoupling capacitors.The metal back layer that is formed on the substrate comprises at least a portion of first pole plate that forms decoupling capacitor, and comprises at least one electrical connection that is used to attach semiconductor chip.The thin layer of dielectric material covers this bottom.Be formed on this dielectric material and as the top layer of second pole plate of capacitor and place, to form decoupling capacitor with respect to first pole plate.This structure can be arranged under the tube core of chip.The length of connector is kept minimum, so that make any inductance that causes thus minimize and make decoupling capacitor as far as possible near tube core.

One object of the present invention is to provide a kind of further improved electron package structure.

By on second side of the described substrate relative, arranging to have the second decoupling capacitor level of high capacitance and it is electrically connected to described distributed capacitive structure, in above-mentioned electron package structure, realize this purpose with described first side.The electric capacity height of the second decoupling capacitor level must be enough to provide low-impedance connection to power sink, and can be 5 to 100 times of the electric capacity of the first decoupling level, preferred about 10 times.

The figure that should be noted that second electrode and dielectric material depends on the spacing of connector to the chip that will be powered.

Have the described distributed capacitive structure of low-down series inductance and have 1000 or the dielectric material of bigger very high dielectric constant, can be directly installed under tube core or its substrate and be supported on element that next filter stage the is provided side relative with it.Therefore, not only distributed electroplax structure is coupled to power sink in optimum low inductance mode, and the quite big improved second decoupling capacitor level of generation decoupling also can be coupled to power sink in optimum low inductance mode in high-frequency range.

In a preferred embodiment, described distributed capacitive structure is included in polarity that replaces on the first direction on the described substrate and the polarity that replaces on the second direction that is basically perpendicular to described first direction on the described substrate.Therefore, provide the meticulous grid capacitor regions that constitutes by the public electrode that is installed between substrate and the dielectric material.This distributed capacitive structure comprises in a large number the individual unit that (for example 100) are in parallel.

In order to realize this effect effectively, can in the hole of the described preliminary election figure of described dielectric material, be formed into the contact area of described first electrode layer, so that one of described polarity of described distributed capacitive structure to be provided.Because the polarity that replaces is close to another layout, so high frequency peaks is filtered off, because this layout shows minimum inductance.

Preferably, the through hole that provides in order to connect described distributed capacitive structure and the described second decoupling capacitor level is provided described substrate.One of skill in the art will appreciate that if necessary described through hole extends through described first electrode layer and as the part of the preliminary election figure of described dielectric material with being equal to.

The described second decoupling capacitor level can comprise a plurality of capacitors.

Described substrate can be made by electric conducting material, is for example made by the silicon (Si) of conduction.

Can set up a kind of integrated circuit, it comprises processor and electron package structure of the present invention, and wherein the described the second electrode lay of preferred this electron package structure is in the face of described processor.

Electron package structure of the present invention provides a kind of module that the spurious impedance of reduction is arranged at inductance and resistive square mask.Reduced the fluctuation of the supply voltage that the voltage drop by resistance and inductance causes, this allows to use higher current transient.Therefore, the amplitude with higher frequency and reduction that only excites of power line vibration takes place.The problems of Signal Integrity that causes by EMI will significantly be alleviated.

It is as the connection between power subsystem (for example voltage regulator module (VRM)) and the load in supply network that typical case of the present invention uses.Usually, this supply network comprises a plurality of power-supply filter levels of being used for socket and as the decoupling capacitance of the part of chip self.When the route from the voltage regulator module to the chip is advanced, observing two kinds of trend.The capacitance of electric capacity, connection inductance and the impedance of resistance and the parasitic series inductance and the resistance decreasing of capacitor.This means can be stored in load the capacitor that reduces of distance in energy diminish, yet because the very little impedance in the neighborhood that is right after, this energy can obtain rapidly.Filter high frequency load amplitude of fluctuation (load step) by the parts in the zone in its vicinity, represent the low frequency load change amplitude of the longer lasting variation of electric current demand mainly to cover by the big electric capacity in the farther environment, however voltage regulator module self must follow in the load slowly many variations.Therefore, supply network comprises the device that is made of filter stage, and described filter stage is adjusted between another subtly and also arrived load, and its characteristic is optimized for spurious impedance forever.In the present invention, first filter stage provide a plurality of electric capacity or or even distributed capacitor, this distributed capacitor is connected to chip and comprises quite low capacitance in the quite low mode of inductance, but this means and can obtain quite low stored energy rapidly.And this module has comprised second filter stage (that is, the second decoupling capacitor level) that is adjacent, and this second filter stage has about 5 to 100 times energy storage, and form is discrete capacitor, for example multi-layer ceramic capacitance.Compare with hitherto known structure, these capacitors of described second filter stage are connected to first filter stage with quite low impedance, yet because straight-through contact, it is the quite high impedance connection to first filter stage.

Will by with reference to the accompanying drawings and explanation thereafter the present invention is described in more detail.

Fig. 1 shows structure according to electron package structure of the present invention with vertical cross-section; And

Fig. 2 show Fig. 1 structure a part the item view.

In Fig. 1, between first electrode 2 and a plurality of second electrode 3, dielectric material 1 is set.Dielectric material for example is to have 1000 or the thin pottery of bigger relative dielectric constant.The representative value of the thickness of dielectric material is 50nm to 500nm.Structure dielectric material 1 is to be provided to the path of first electrode layer 2, so that can form contact area 6.Thus, realize the connector zone of alternating polarity 5a and 5b.For example, flip-chip solder bump provides contacting of each second electrode 3 and public first electrode layer 2 by contact area 6.This device is supported on the substrate 4, for the resistance that reduces by first electrode 2 with inductance and save the straight-through of electrode 10 and be connected, substrate 4 can conduct electricity.A plurality of discrete capacitors 9 are arranged under the substrate 4, so that the second decoupling capacitor level to be provided.Conduction by electrode 10 on described substrate 4 downsides and through hole 11 inwall places runs through coating 8 provides alter polarity, and described through hole 11 is provided in substrate 4, first electrode layer 2 and the dielectric material 1.Insulating cell 7 is introduced in each through hole to avoid contacting of coating and first electrode layer 2 and conductive substrates 4.

Fig. 2 shows the top view of the structure of Fig. 1.On orthogonal both direction, extend to form the mesh-like area of alter polarity 5a, 5b.The size of single capacitor unit is limited by spacing 12, itself so that depend on spacing (distance between the connector of the chip that will be powered).

Yet the electrode of the described discrete capacitor 9 (the second decoupling filter level) by being used to contact place, described substrate 4 bottom sides is connected to form the similar grid figure that demonstrates obviously bigger spacing.

Claims (9)

1, a kind of electron package structure comprises: substrate (4); First electrode layer (2) on first side of described substrate (4); With the dielectric material (1) of preliminary election graphical layout on described first electrode layer (2); With the second electrode lay that forms a plurality of second electrodes (3), these a plurality of second electrodes (3) are arranged on the described preliminary election figure of dielectric material (1), so that form distributed capacitive structure as the first decoupling level with described first electrode layer (2), it is characterized in that: the second decoupling capacitor level (9) is arranged on second side of the described substrate (4) relative with described first side and is electrically connected to described distributed capacitive structure, and the electric capacity of the described second decoupling capacitor level (9) is higher than the electric capacity of described distributed capacitive structure.

2, electron package structure as claimed in claim 1, it is characterized in that described distributed capacitive structure is included in alter polarity (5a, 5b) and the alter polarity on the second direction on the described substrate (4) (5a, 5b) on the first direction on the described substrate (4), described second direction is basically perpendicular to described first direction.

3, electron package structure as claimed in claim 2 is characterized in that being formed into the contact area (6) of described first electrode layer (2), so that one of described polarity of described distributed capacitive structure to be provided in the hole of the described preliminary election figure of described dielectric material (1).

4, electron package structure as claimed in claim 1 is characterized in that the through hole (11) that connects described distributed capacitive structure and the described second decoupling level (9) and provide is provided described substrate (4).

5, electron package structure as claimed in claim 1 is characterized in that described high capacitance decoupling level (9) comprises a plurality of capacitors.

6, electron package structure as claimed in claim 1, the electric capacity that it is characterized in that the described second decoupling level (9) are 5 to 100 times of electric capacity of described distributed capacitive structure, preferred about 10 times.

7, electron package structure as claimed in claim 1 is characterized in that described substrate (4) made by electric conducting material.

8, a kind of integrated circuit comprises processor and according to each electron package structure of aforementioned claim.

9, integrated circuit as claimed in claim 7, wherein the described the second electrode lay (3) of this electron package structure is in the face of described processor.