CN1767611A - Method for controlling panel display interface video processing circuit - Google Patents

Abstract

This invention discloses a system and method for controlling the interface video process circuit of an AC plasma plane display or a liquid crystal plane display, in which, the system is composed of a microprocessor MCU and a programmable gate array (FPGA), various video signals are output automatically by this control system via different terminal input interface circuits. The usage of the system is: when the display is turned on, it outputs the signal source used last time in turning off the switch automatically, if said signal source does not receive signals, it selects signals with high priority in the source with signals according to priority of the source and outputs them to reduce the operation times of the keyboard.

Description

A kind of control method of panel display interface video processing circuit

Technical field

The invention belongs to the flat display technology field, relate to the control method of a kind of AC plasma flat-panel monitor (PDP), liquid crystal flat panel display (LCD) interface video processing circuit.

Background technology

Not remake simple monitor under AC plasma flat-panel monitor (PDP), a lot of situations of liquid crystal flat panel display (LCD) uses, they are a large amount of is applied to family and public place, PDP particularly, because large scale, can be used as household electrical appliance uses, so all have profuse video signal input terminal mouth, can import the signal source of various different-formats, comprise CVBS, S-VIDEO, YPrPb, YCrCb, DVI or the like, much can also be by built-in tuner and intermediate-frequency circuit input broadcast TV program.

So many signal source, the user must select before each the use, and this selection operation bothers concerning the user very much.

Summary of the invention

The objective of the invention is to, a kind of control method of panel display interface video processing circuit is provided, this method is utilized existing FPGA (or CPLD) on the interface card, uses MCU suitably to cooperate simultaneously, realizes function by programming.

In order to achieve the above object, the present invention takes following technical solution:

A kind of control method of panel display interface video processing circuit, it is characterized in that, this method adopts existing programmable gate array FPGA or CPLD on the AC plasma panel display interface circuit board, use the MCU microprocessor to cooperate jointly simultaneously, by the program of setting, finish the signal source of a plurality of display startings and search and select switching automatically, realize the automatic output of all kinds of video signal images of different terminal inputs, the signal source of finishing start is searched automatically and is selected and switches, and specifically comprises the following steps:

1) set up the selection priority sequence of an input signal source, the first order is the signal source that last user is selected, i.e. the last signal source of selecting of user, all the other fixed order at different levels;

2) use the capable counting of FPGA, judge whether certain signal source has signal, again the result is informed the MCU microprocessor;

3) MCU is a kind of at the highest that of the signal source selecting priority that signal is arranged, if this signal source does not connect signal, MCU in defining the signal source of signal, selects the high signal output of priority then according to the signal source priority of setting.

The present invention is not additionally increasing under the situation of hardware, utilize existing FPGA and MCU on the interface circuit, by the reference signal condition that the user selects of shutting down last time, the available signal source searches automatically and switches when realizing the flat-panel monitor start, directly export display image, need not user's manual switchover, for user's use is provided convenience.

Description of drawings

Fig. 1 realizes video processing circuit system architecture diagram of the present invention;

Fig. 2 fpga logic sequential flow chart;

Fig. 3 MCU software flow pattern;

Table 1 array D[0] [1..0] and the graph of a relation of importing the FPGA signal.

The present invention is described in further detail below in conjunction with drawings and Examples.

Embodiment

Specific implementation method of the present invention is: utilize FPGA, MCU to form the control system that the interface circuit signal source is selected automatically.

Referring to Fig. 1, video processing circuit system configuration of the present invention mainly is made up of ADC (analog to digital converter), TUNER (high-frequency signal demodulator), DECODER (decoder), PROCESSER (signal processor), Fig. 1 has represented the relation between them, and has provided the position of signal source selection circuit in the panel display interface video processing circuit system.The TV signal, CVBS, the S-terminal, DVI, multiple analog signals such as YPrPb, YCrCb are all passed through corresponding pin input DECODER, finish decoding at DECODER, and the analog rgb signal of computer input is then imported ADC and is finished analog-to-digital conversion.MCU is by writing the function that register is realized its output of control to DECODER and ADC.

Finish the control system that signal source is selected automatically, the part that rises in frame of broken lines realizes, comprises FPGA in this frame, MCU.

The present invention has come down to set up the selection priority sequence of an input signal source, and the first order is the signal source that last user is selected, all the other fixed order at different levels.Judged whether signal by the way of using the capable counting of FPGA, again the result is informed MCU, MCU is a kind of at the highest that of the signal source selecting priority that signal is arranged, and handles output, and what at this moment show on the screen is exactly the program of this port that chooses.By this method, finish display one start, to the automatic selection of signal source.

Need to change program source if the user thinks, can carry out program by OSD and remote keypad again and switch.

Because realize that the logic of this function is also uncomplicated, so FPGA is not had specific (special) requirements, the low side FPGA/CPLD of ALTERA company or XILINX company all can satisfy.

FPGA selects the ACEX series EPCIK100QC208 of ALTERA company for use, and MCU selects the 80C51 microprocessor for use, has Computer signal (RGB), TV signal, CVBS, S-terminal, DVI, six kinds of input signal ports of YcrCb.

Their priority orders of being ranked is followed successively by from high to low: the signal source of using when shut down last time, Computer signal (RGB), TV signal, CVBS, S-terminal, DVI, YcrCb.

DECODER, ADC control by MCU, and MCU carries out write operation by the I2C universal serial bus to them.

The digital rgb signal that to import FPGA among the figure is named and is INPUT1.The signal that the DECODER decoding obtains is named and is INPUT2.

The INPUT1 and the INPUT2 that are sent here by AD converter and DECODER decoding chip import FPGA.FPGA carries out communication with serial code mode and MCU, and MCU can read and write FPGA.

The automatic selection function of signal source when Fig. 2 has represented to finish start, the logical sequence of FPGA inside.At first signal INPUT1, the INPUT2 of corresponding input set up two corresponding counters in FPGA, after system initialization finishes, each counter is initial with the field sync signal of each paths input, its row is counted synchronously, if can count predefined numerical value, judge that then this has been input as signal condition.With a predefine is set, waits for that MCU reads.

The automatic selection function of signal source when Fig. 3 has represented to finish start, the control flow of MCU.In the EEPROM of MCU data storage areas, set a unit, because selecting the operation of signal source to write register by MCU finishes, so can be after whenever finishing a signal source selection, MCU writes this memory cell with selective value, and the sheet that this numerical value comprises DECODER that system's the last time carries out and ADC selects the numerical value of information and write signal source mask register.After start, system finish initialization, at first will read the numerical value in this memory cell.

After the start, the memory cell numerical value read is write register when initialization DECODER and the ADC, in other words, selected picture signal identical when shutting down with last time.Afterwards, DECODER and ADC start working, output signal.The process of time-delay 50MS is the process that FPGA counts, wait for that the FPAG counting finishes after, carry out a logic determines, put an array D[0] value of [1..0].MCU is by reading the D[0 of FPGA] [1..0] data bit, just can learn whether signal output is arranged now.

Table 1 is array D[0] [1..0] and the relation of importing the FPGA signal.

Table 1: array D[0] [1..0] and the relation of importing the FPGA signal

D[0][1]	D[0][0]	DECODER output	ADC output
					1	0	Have	Do not have
0	1	Do not have	Have
				1	1	Have	Have
0	0	Do not have	Do not have

By this table, can see, the signal that display showed when if FPGA had found to shut down last time, found that perhaps the five-star computer input of signal source selection priority has signal, then with D[0] [1..0] be changed to 01 or 10 or 11, at this time MCU end signal source search is simultaneously with this numerical value write memory.Signal will be finished in FPGA (programmable gate array) and PROCESSER (signal processor) and deliver to the display screen demonstration after other is handled.

If D[0] [1..0] be 00, illustrate that the signal source of selecting does not have signal, (the computer input no signal of limit priority also has been described simultaneously) at this moment will select TV signal source value corresponding to write the register of DECODER, in other words, selected the picture signal of TV signal source, the 50MS that delays time once more waits for that the FPAG counting finishes, read D[0] [1..0], if not 00, output image, memory write A simultaneously.

If 00, shown the second priority TV signal source no signal, at this moment select the CVBS value corresponding to write the register of DECODER, the 50MS that delays time once more waits for that the FPAG counting finishes, and reads D[0] [1..0], if not 00, output image, memory write A simultaneously.

If 00, shown the 3rd priority CVBS no signal, at this moment select S-terminal value corresponding to write the register of DECODER, the 50MS that delays time once more waits for that the FPAG counting finishes, and reads D[0] [1..0], if not 00, output image, memory write A simultaneously.

If 00, shown the 4th priority S-terminal no signal, at this moment select the DVI value corresponding to write the register of DECODER, the 50MS that delays time once more waits for that the FPAG counting finishes, and reads D[0] [1..0], and if not 00, output image, memory write A simultaneously.

If 00, shown the 5th priority DVI no signal, at this moment select the YCrCb value corresponding to write the register of DECODER, the 50MS that delays time once more waits for that the FPAG counting finishes, and reads D[0] [1..0], and if not 00, output image, memory write A simultaneously.

If 00, show that without any input at this moment will have the character in the FPAG: NO SIGNAL exports demonstration.

In the present embodiment, the not extra hardware that adds is only by increasing subprogram and logical circuit, and make it to cooperatively interact, just reached the purpose that increases function, can improve the signal processing effect, effectively improve the plasma display performance, can be widely used in the various multifunction displays.

Claims (1)

1. the control method of a panel display interface video processing circuit, it is characterized in that, this method adopts existing programmable gate array FPGA or CPLD on the AC plasma panel display interface circuit board, use the MCU microprocessor to cooperate jointly simultaneously, by the program of setting, finish the signal source of a plurality of display startings and search and select switching automatically, realize the automatic output of all kinds of video signal images of different terminal inputs, the signal source of finishing start is searched automatically and is selected and switches, and specifically comprises the following steps:

1) set up the selection priority sequence of an input signal source, the first order is the signal source that last user is selected, i.e. the last signal source of selecting of user, all the other fixed order at different levels;

2) use the capable counting of FPGA, judge whether certain signal source has signal, again the result is informed the MCU microprocessor;

3) MCU is a kind of at the highest that of the signal source selecting priority that signal is arranged, if this signal source does not connect signal, MCU in defining the signal source of signal, selects the high signal output of priority then according to the signal source priority of setting.

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