CN103399720A - Data processing method and electronic equipment - Google Patents
Data processing method and electronic equipment Download PDFInfo
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- CN103399720A CN103399720A CN2013102980851A CN201310298085A CN103399720A CN 103399720 A CN103399720 A CN 103399720A CN 2013102980851 A CN2013102980851 A CN 2013102980851A CN 201310298085 A CN201310298085 A CN 201310298085A CN 103399720 A CN103399720 A CN 103399720A
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Abstract
The invention discloses a data processing method and electronic equipment. The method includes: when OSD (on-screen display) data needs to be displayed on a display module, acquiring an inverted-screen reading mode configured by a register through a DMA (direct memory access) controller; based on the inverted-screen reading mode, determining an initial read address of the OSD data in DDR through the DMA controller; sending a corresponding read command to the DDR through the DMA controller, reading the OSD data from the DDR according to the initial read address, sequentially storing the OSD data into N caches; based on the inverted-screen reading mode, extracting the OSD data from the N caches in a reverse direction through the DMA controller, and transmitting the OSD data to the display module for displaying. The letter N is a positive integer. The reverse direction is opposite to the sequence of the OSD data stored in the N caches by the DMA controller.
Description
Technical field
The present invention relates to electronic technology field, particularly a kind of data processing method and a kind of electronic equipment.
Background technology
At present, in LCDs, the high definition of screen and large scale, less thickness has become the development trend of LCDs.In order to pursue thinner screen, a lot of manufacturers can place circuit main board and power panel etc. as in base, and also be positioned at the top of screen due to the TCON of screen, too far away apart from circuit board, be unfavorable for the transmission of signal, thereby a lot of manufacturer starts to take with the screen inversion, TCON(Timer Control Register, time schedule controller) be placed in the base of screen below, to save the space of LCDs.And for TCON, TCON is for the display timing generator of controlling screen, due to the first row (mode of screen scanning generally in accordance with the order from top to bottom scan) of the display circuit board in display screen near screen scanning, and more accurate for the control that makes TCON, in general TCON is together with the first row of screen scanning.Therefore, after TCON is placed on base, can change the sequential control mode of TCON, and then change OSD(on-screen display, the screen menu type regulative mode) demonstration of data.The osd data of this moment is the picture for standing upside down likely, for example demonstration of the osd data in Fig. 1.
Demonstration image for the osd data that obtains forward, before user interface display image, all need this osd data is rotated operation, but the applicant finds in realizing the application's process, prior art is generally to utilize the method for software, to have osd data now and utilize algorithm to be rotated, form postrotational image and storage, and then utilize DMA to move rear direct demonstration.And osd data is all to be stored in DDR, as CPU, from DDR, osd data is read out while calculating, and DDR can open up special memory block and store postrotational osd data, causes the memory usage of DDR larger, and further reduces the efficiency of system.
Therefore, the technical matters of prior art existence is: need DDR to open up special memory block and store postrotational osd data, cause the memory usage of DDR larger, and further reduce the efficiency of system.
Summary of the invention
The invention provides a kind of data processing method and a kind of electronic equipment, in order to solve exist in prior art need DDR to open up special memory block to store postrotational osd data, cause the memory usage of DDR larger, and further reduce the technical matters of the efficiency of system.
On the one hand, the present invention, by the application's a embodiment, provides following technical scheme:
A kind of data processing method, described method comprises: when needs, screen menu type is regulated (OSD) data while being presented on display module, obtained the reading manner that shields of register configuration by dma controller; , based on the described reading manner that shields, by described dma controller, determine the initial reading address of described osd data in described DDR; Send corresponding reading order by described dma controller to described DDR, read described osd data according to described initial reading address from described DDR, and described OSD data are deposited in N buffer area successively, wherein, N is positive integer; Based on the described reading manner that shields, extract described osd data from a described N buffer area with reverse sequence by described dma controller, and described osd data is sent to described display module demonstration, reversed in order when wherein, described reverse sequence and described dma controller deposit described osd data in to a described N buffer area.
On the other hand, the present invention provides by another embodiment of the application:
A kind of electronic equipment, described electronic equipment comprises: Installed System Memory (DDR), display module, and be connected to dma module between described DDR and described display module; Described DDR, be used for the storage screen menu type and regulate (OSD) data; Described dma module, comprise dma controller, a register and N buffer area, and wherein, N is positive integer; Wherein said dma controller be connected DDR and connect, described register is connected with described dma controller, a described N buffer area and described DDR, described display module, and described dma controller three connection; Dispose the reading manner that shields of described osd data in described register; Described dma controller is used for when needs are presented at described osd data on described display module, obtains the described reading manner that shields from described register; Then determine the initial reading address of described osd data in described DDR based on the described reading manner that shields, and to described DDR, send corresponding reading order, read described osd data according to described initial reading address from described DDR; Then described osd data is deposited in N buffer area, and extract described osd data with reverse sequence and be sent to the display module demonstration from a described N buffer area, reversed in order when wherein, described reverse sequence and described dma controller deposit described osd data in to a described N buffer area; Described display module, be used for receiving and showing described osd data from described N buffer area.
One or more technical schemes in technique scheme have following technique effect or advantage:
Data processing method of the present invention is when needs, screen menu type to be regulated (OSD) data while being presented on display module, obtains the reading manner that shields of register configuration by dma controller; Then, based on shielding reading manner, by dma controller, determine the initial reading address of osd data in DDR; Send corresponding reading order by dma controller to DDR again, read osd data according to initial reading address from DDR, and osd data is deposited in N buffer area successively, wherein, N is positive integer; Finally,, based on shielding reading manner, extract osd data with reverse sequence by dma controller from N buffer area, and osd data is sent to the display module demonstration, reversed in order when wherein, reverse sequence and dma controller deposit osd data in to N buffer area.The present invention is by reading the reading manner that shields that configures in register, deposit in N buffer area with reading out data from DDR, and show with reverse sequence extraction data from N buffer area, realize that osd data is rotated, only need hardware to carry out in whole process, use N buffer area to replace opening up special memory block in DDR, and configuration is shielded reading manner and is used for dma controller in register, need not to use software algorithm to be rotated osd data, the internal memory of DDR can be too much do not taken, and then the service efficiency of system can be improved.The present invention can be applied to TCON is positioned over the flatscreen electronic equipment of base, and is applicable to common giant-screen electronic equipment.
Description of drawings
Fig. 1 is that in the embodiment of the present invention, osd data is the schematic diagram of the picture of handstand;
Fig. 2 is the structural representation of electronic equipment in the embodiment of the present invention;
Fig. 3 A is that the display direction of osd data in the embodiment of the present invention is the schematic diagram of forward;
Fig. 3 B-Fig. 3 C is that the display direction of osd data in the embodiment of the present invention is also the schematic diagram of swinging to demonstration;
Fig. 4 A is the schematic diagram of the mode that reads according to forward in the embodiment of the present invention;
Fig. 4 B is according to the schematic diagram of the mode of reverse read in the embodiment of the present invention;
Fig. 5 is the connection diagram of buffer area in the embodiment of the present invention;
Fig. 6 extracts the schematic diagram of osd data in the embodiment of the present invention;
Fig. 7 A is after in the embodiment of the present invention, dma controller 21 extracts data according to reverse sequence with osd data from N buffer area 23, deposits the schematic diagram of display module 3 in;
Fig. 7 B is the sequential control reason that there is no TCON in the embodiment of the present invention, the design sketch of display screen when showing osd data;
Fig. 7 C is after the sequential control of comprehensive TCON in the embodiment of the present invention, the design sketch of display screen when showing osd data;
Fig. 8 A-Fig. 8 B be in the embodiment of the present invention due to the sequential control reason of TCON, the shield schematic diagram of other of display when showing osd data;
Fig. 9 A-Fig. 9 B is the schematic diagram that in the embodiment of the present invention, osd data deposits display module 3 in;
Figure 10 is another schematic diagram that in the embodiment of the present invention, osd data deposits display module 3 in;
Figure 11 is the implementation process figure of data processing method in the embodiment of the present invention.
Embodiment
For solve exist in prior art need DDR to open up special memory block to store postrotational osd data, cause the memory usage of DDR larger, and further reduce the technical matters of the efficiency of system, the embodiment of the present invention has proposed a kind of data processing method and a kind of electronic equipment, and its solution general thought is as follows:
At first, the present invention improves at hardware aspect, and is concrete, and electronic equipment of the present invention comprises Installed System Memory 1(DDR), display module 3, and be connected to dma module 2 between DDR and display module 3; DDR, be used for the storage screen menu type and regulate (OSD) data; Dma module 2, comprise the dma controller 21 that is connected with DDR, and the register 22 that is connected with dma controller 21; Also have N buffer area 23.And dispose the reading manner that shields of osd data in register 22; When dma controller 21 is used at needs, osd data being presented on display module 3, obtain to shield reading manner from register 22, then determine the initial reading address of osd data in DDR based on shielding reading manner, and to DDR, send corresponding reading order, read osd data according to initial reading address from DDR; Then osd data is deposited in N buffer area 23, and extract osd data with reverse sequence and be sent to display module 3 demonstrations from N buffer area 23, wherein, the reversed in order when reverse sequence and dma controller 21 deposit osd data in to N buffer area 23; Display module 3, be used for receiving and showing osd data from dma module 2.
In addition, data processing method of the present invention is when needs, screen menu type to be regulated (OSD) data while being presented on display module, obtains the reading manner that shields of register configuration by dma controller; Then, based on shielding reading manner, by dma controller, determine the initial reading address of osd data in DDR; Send corresponding reading order by dma controller to DDR again, read osd data according to initial reading address from DDR, and osd data is deposited in N buffer area successively, wherein, N is positive integer; Finally,, based on shielding reading manner, extract osd data with reverse sequence by dma controller from N buffer area, and osd data is sent to the display module demonstration, reversed in order when wherein, reverse sequence and dma controller deposit osd data in to N buffer area.
The present invention is by reading the reading manner that shields that configures in register, deposit in N buffer area with reading out data from DDR, and show with reverse sequence extraction data from N buffer area, realize that osd data is rotated, only need hardware to carry out in whole process, use N buffer area to replace opening up special memory block in DDR, and configuration is shielded reading manner and is used for dma controller in register, need not to use software algorithm to be rotated osd data, the internal memory of DDR can be too much do not taken, and then the service efficiency of system can be improved.
Below by accompanying drawing and specific embodiment, technical solution of the present invention is described in detail, be to be understood that specific features in the embodiment of the present invention and embodiment is the detailed explanation to technical solution of the present invention, rather than to the restriction of technical solution of the present invention, in the situation that do not conflict, the technical characterictic in the embodiment of the present invention and embodiment can make up mutually.
Embodiment one:
In embodiments of the present invention, provide a kind of data processing method.
Concrete, the method produces take electronic equipment as hardware supported, therefore, and a kind of electronic equipment of paper in the embodiment of the present invention.
In addition, in embodiments of the present invention, this electronic equipment can be televisor, perhaps computer etc.
Concrete, as shown in Figure 2, this electronic equipment comprises: Installed System Memory 1(DDR), and display module 3, and be connected to dma module 2 between DDR and display module 3.
DDR, be used for the storage screen menu type and regulate (OSD) data.
Below introduce the various functions of each device in dma module 2.
At first, dispose the reading manner that shields of osd data in register 22; When dma controller 21 is used at needs, osd data being presented on display module 3, obtain to shield reading manner from register 22, then determine the initial reading address of osd data in DDR based on shielding reading manner, and to DDR, send corresponding reading order, read osd data according to initial reading address from DDR; Then osd data is deposited in N buffer area 23, and extract osd data with reverse sequence and be sent to display module 3 demonstrations from N buffer area 23, wherein, the reversed in order when reverse sequence and dma controller 21 deposit osd data in to N buffer area 23.
Lower mask body is introduced the function of each device.
For DDR, it is mainly used in storing osd data.When needs show osd data, can call from DDR.
And osd data generally refers to the user press the Menu key after, the rectangle menu of the every reconciling items information of display that screen ejects, can comprise that to display work in every index color, pattern, geometric configuration etc. adjust by this menu, thereby reach best use state.The data that for example oppositely show in Fig. 1 are namely osd datas.
, for dma module 2, in fact comprised three parts: dma controller 21, the register 22 that is connected with dma controller 21, and are connected N the buffer area 23 that connects with dma controller.
Just shielding and falling the implication of screen and be based on that user's vision differentiates.The implication of just shielding is that the display direction of the cable video data that show in display direction and the display of the osd data that shows in display screen is consistent, and perhaps with user's vision, the display direction of the osd data that shows in display screen is normal or forward.As Fig. 3 A, the user watch TV the time, the personage of the XX satellite TV that plays in TV is normal for the user, and the osd data that occurs in picture is also normal, and is the same with the personage of XX satellite TV, is all forward.The implication of screen of falling is that the display direction of the cable video data that show in the display direction of the osd data that shows in display screen and display is different, perhaps with user's vision, the display direction of the osd data that shows in display screen is abnormality or reverse.As Fig. 1, the user watch TV the time, personage's forward of the XX satellite TV that plays in TV shows, normal for the user, and the osd data that occurs in picture is to stand upside down to show, with the personage's of XX satellite TV opposite direction, the demonstration of osd data is equivalent to display screen has been stood upside down 180 ° and shown, therefore is called as down screen.In addition, the osd data in Fig. 3 B and Fig. 3 C is also referred to as down screen.
Just shielding the mode that reading manner reads according to forward, dma controller 21 starts to read from the initial OPADD of DDR backward, and namely reading address is the reading manner of initial OPADD.Initial OPADD is specially the user and compiles the OPADD that obtains when needs reads osd data.Shield reading manner and be the mode according to reverse read, dma controller 21 is determined initial reading address in DDP, then start to read from initial reading address in DDR backward, and namely reading address is the reading manner of initial reading address.For example, the data volume of storing in DDR is 1000, and initial storage address is 0, since 0 to 999, stored this 1000 data.And the initial OPADD of just shielding reading manner is 1, if, according to just shielding reading manner, please refer to Fig. 4 A, the mode that can read according to forward, start to read from initial OPADD 1 in DDR, reads successively 2,3,4...... to 999.If, according to shielding reading manner, please refer to Fig. 4 B, can at first calculate initial reading address (as initial reading address, being 900) according to the mode of reverse read, then from initial reading address 900, read successively 901,902,903...... to 999.
For N buffer area 23, overall, this N buffer area 23 all is connected connection with dma controller.And be used for the osd data that storage dma controller 21 reads from DDR according to initial reading address.Wherein, N is positive integer.In addition, this N buffer area 23 also has annexation with DDR and display module 3 respectively, and, when dma controller 21 needs the transmission of data to show to display module 3, also can extract data from 23 kinds of this N buffer areas.
For N buffer area 23 inside, each buffer area is relatively independent, and each buffer area is connected connection with dma controller.In addition, each buffer area also is connected display module 3 and is connected with DDR.As shown in Figure 5, suppose to have 4 buffer areas, be respectively buffer area 1, buffer area 2, buffer area 3, buffer area 4.These 4 buffer areas have all connected dma controller 21, DDR, display module 3.
In addition, for N buffer area 23, osd data can be deposited in a buffer area, also can deposit in a plurality of buffer areas.
For display module 3, be the display chip in display in fact, major function is to accept from dma module 2 and show osd data.
From top structure, DDR and dma module 2 are direct-connected.DDR and dma module 2 also can indirect joints.For example in Fig. 2, this electronic equipment has also comprised bus 4.
In the embodiment of the present application, bus 4 is AXI(Advanced eXtensible Interface specifically, a kind of bus 4 agreements) bus.And bus 4 specifically is connected between DDR and dma controller 21, is used for the reading order of transmission dma controller 21 to DDR, so that read osd data from DDR.
And more specifically, DMA is in DDR during reading out data, and is different according to the storage mode that register 22 arranges, and has different reading manners.
The storage mode that arranges when register 22 is when shielding reading manner, and the concrete effect of dma controller 21 is as follows:
The first, when dma controller 21 is presented at osd data at needs on display module 3, obtain to shield reading manner from register 22.
The second, the data volume that the initial OPADD of dma controller 21 meeting acquisition DDR and the screen resolution of display module 3 take.
Concrete, can full screen display in display screen due to osd data, for example common are the osd data of line TV, when adjusting, be to be in full screen in display screen.If, so will calculate the initial reading address that reads the OSD data, must calculate and obtain the data volume that screen resolution takies.
The 3rd, dma controller 21 can, based on shielding reading manner,, according to initial OPADD and data volume, be determined the initial reading address of osd data in DDR.
For example,, since 0 until 1000,1000 data have been stored altogether in DDR.If initial OPADD is 999.When calculating screen resolution, the data volume of acquisition is 100, so can be take initial OPADD as benchmark, export 100 data volumes forward since 999, and obtaining initial reading address is 900.If with initial OPADD called after addr1, this moment addr1=999.Data volume size=100, initial reading address addr2 has following relational expression:
addr2=addr1-size+ 1=999-100+1=900。
The 4th, dma controller 21, based on shielding reading manner, after determining the initial reading address of osd data in DDR, sends corresponding reading order to DDR, reads osd data according to initial reading address from DDR.
Concrete, after having obtained initial reading address, can send corresponding reading order, read 100 osd datas according to initial reading address from DDR.Can read successively since 900 while reading in DDR, read 1000 always and finish.Fig. 4 B for example is dma controller 21 since 900 schematic diagram that read osd data.
The 5th, the osd data that dma controller 21 will read deposits in N buffer area 23.
Concrete, in the time of in depositing N buffer area 23 in, be also according to 900,901,902...... until 1000 such orders deposit in.
The 6th, dma controller 21, based on shielding reading manner, extracts osd data according to reverse sequence, and osd data is transferred to display module 3 from N buffer area 23.
Order called after forward sequence when wherein, the embodiment of the present application deposits dma controller 21 from osd data to N buffer area 23; And reverse sequence and dma controller 21 reversed in order while to N buffer area 23, depositing osd data in.
Concrete,, according to reverse sequence, extract when shielding reading manner extract the OSD data in N buffer area 23 at dma controller 21.For example in Fig. 6, when extracting osd data, can be take 1000 as initial extraction address, according to 1000,999, the such order extraction osd data of 998......900.
In addition, when being transferred to display module 3, be also according to 1000,999,998......900 such sequential delivery., because when osd data originally shows in display,, due to the sequential control reason of TCON, fallen screen display the user and shown.Therefore, in this control by dma controller 21, the osd data that the script forward is transferred to the display screen demonstration is transferred to display according to reverse sequence and shows,, so by the sequential control of TCON, can make the user see the osd data that positive screen display is shown.
Concrete, when display shows osd data in positive screen display, general data show be according to from left to right, from top to bottom mode shows.And when screen display is shown, be according to from right to left, show from top to bottom.For example Fig. 7 A, be dma controller 21 extracts data according to reverse sequence with osd data from N buffer area 23 after, deposits the schematic diagram of display module 3 in.Specifically according to from right to left, order from top to bottom deposits in.If there is no the sequential control reason of TCON, display screen when showing the OSD data, shows result as shown in Figure 7 B., if combine the sequential control reason of TCON, show that result is as shown in Fig. 7 C.
In addition, due to the sequential control reason of TCON, display when showing osd data, likely also there will be the situation in Fig. 8 A and Fig. 8 B.
Wherein, Fig. 8 A is osd data while originally with positive screen display, showing,, due to the sequential control reason of TCON, makes osd data that originally positive screen display shows appear to through the display effect after the exchange of left and right the user.Fig. 8 B is osd data while originally with positive screen display, showing,, due to the sequential control reason of TCON, makes osd data that originally positive screen display shows appear to through the display effect after exchange up and down the user.
For the situation in the situation in Fig. 8 A and Fig. 8 B, dma controller 21 is reading osd data according to initial reading address from DDR, and to deposit osd data in N the process in buffer area 23 be all the same.Mode when unique difference is from N buffer area 23 that extracting osd data sends into display module 3 is different.
If there is the situation in Fig. 8 A, if this moment dma controller 21 control osd datas with 900,901,902...... has been until 1000 such orders have deposited N buffer area 23 in.When extracting, will be according to 1000,999, the such order of 998......900, with osd data from right to left, deposit in from top to bottom.As shown in Figure 9 A.After depositing osd data in by this way, last display effect can be as shown in Fig. 7 C.
If if there is situation in Fig. 8 B, if this moment dma controller 21 control osd datas with 900,901,902...... has been until 1000 such orders have deposited N buffer area 23 in.When extracting, will be according to 1000,999, the such order of 998......900, with osd data from left to right, deposit in from top to bottom.As shown in Fig. 9 B.After depositing osd data in by this way, last display effect can be as shown in Fig. 7 C.
Above implementation process, all can calculate and obtain initial reading address according to the reading manner that shields of the setting of register 22, then send corresponding reading order to DDR, and read out corresponding osd data from DDR.Then be to control osd data to be presented on display module 3 with second portion.
In addition, the storage mode that arranges when register 22 is when just shielding reading manner, and the concrete effect of dma controller 21 is as follows:
The first, when dma controller 21 is presented at osd data at needs on display module 3, obtain just shielding reading manner from register 22.
The second, dma controller 21 can obtain initial OPADD and data volume.
Concrete, the reason of the data volume that calculating acquisition screen resolution takies has had description in the above, does not repeat them here.
The 3rd, dma controller 21 can, based on just shielding reading manner,, according to initial OPADD and data volume,, take initial OPADD as initial reading address, read osd data from DDR.
For example,, since 0 until 1000,1001 data have been stored altogether in DDR.If initial OPADD is 900.When calculating screen resolution, the data volume of acquisition is 100.So can be take initial OPADD address as initial reading address, in DDR since 900, with 900,901,902...... is until 1000 such osd datas that call over.
The 4th, osd data is transferred to display module 3 shows.
When with 900,901,902...... until 1000 such call over osd data after, can osd data be outputed in display module 3 and show with this order.
Concrete, because the display screen of this moment is that positive screen display is shown, data show be according to from left to right, from top to bottom mode shows.Therefore, when DMA controls osd data is put into display module 3, can put into osd data according to the mode in Figure 10 (from left to right, from top to bottom mode).
This positive screen display shows that mode is applicable to common electronic equipment, and namely TCON is not positioned over the electronic equipment of base.This moment also can be by the just screen reading manner of register 22 settings, and then by the control of dma controller 21, the mode that osd data is shown according to positive screen display is presented in display module 3.Its design sketch can be as shown in Fig. 7 C.
In the above embodiments, introduction be hardware configuration aspect reading out data and the mode that shows data, below with concrete example, describe.
In prior art, in order to reduce screen thickness, so in when design, circuit main board and power panel etc. being placed on base.And also be positioned at the top of screen due to the TCON of screen, and too far away apart from circuit board, be unfavorable for the transmission of signal.Thereby after circuit main board and power panel etc. is placed on base, also screen can be inverted, TCON is placed near base.Can be inverted like this 180 degree rotations of osd data.
In order to solve top shortcoming, the present invention realizes 180 degree despinings of OSD data in the situation that need not change electronic apparatus application, so that osd data can normally be presented on display screen.Implementation procedure also can be supported the simple reason of the sequential control due to TCON, the situation that causes the osd data that occurs to become the left and right exchange and exchange up and down.
What generally, the viewing area of screen was corresponding is the internal memory of an integral body of system.Suppose that the osd data corresponding to viewing area of screen all store in DDR, calculate with full HD 1920 * 1080 resolution, if each pixel is divided into the R(redness), G(is green), B(is blue), the A(transparency) four kinds, the data volume that can calculate screen resolution is 1920 * 1080 * 4 to be about 8M bytes.Data in this 8M internal memory can be used as pixel data and show.
If on display screen the demonstration numeral 12 of forward, as shown in Fig. 7 C.
The reading manner of register 22 settings this moment is for just shielding reading manner, if take 16 systems as example, the value that register 22 arranges is 0x00.
Obtained the just screen reading manner of register 22 when dma controller 21, can generate corresponding reading order, read the data volume of 8M bytes from DDR.
In screen situation just, what upper left first point of screen showed is first address of internal memory, then cumulative successively according to order vertical after first level.If according to ARGB(transparency, redness, green, blueness) form is stored, if a pixel data storage format supposes that as table 1(initial OPADD is 0x00000000), wherein, table 1 is internal color position, address table.
Table 1
Be present in the most-significant byte of this address due to transparency A, there are minimum 8 in blue B,, so at first dma controller 21 carries minimum 8 B when moving from DDR, presses afterwards G, R, and the order of A is carried out.This address read complete after, continue the B of next address (0x00000004), G, R, the A order reads successively.Skip to following delegation after the one's own profession osd data is completed, continue to read the address of back.In addition, read successively number from DDR at the osd data with each address after, can deposit in successively in display module 3 and show (storage area that perhaps deposits other in).
Take full HD 1920 * 1080 resolution as example, the size that takes up room is 1920 * 1080 * 4=0x7E9000byte(16 system), dma controller 21 can start to read successively osd data from 0x00000000, until that the osd data in this 0x7E9000byte space all reads is complete.
If oppositely show numeral 12 on the screen of this moment, as shown in Figure 7 B.If will make 12 forwards be presented at display screen (as shown in Fig. 7 C) this moment.
And numeral 12 handstand of this moment are presented in display screen, are equivalent to left and right and catch up with lower exchange simultaneously.
The reading manner of register 22 settings this moment is for shielding reading manner, if with 16 systems for example, the value that the register 22 of this moment arranges is 0x11.
Obtained the reading manner that shields of register 22 when dma controller 21, can generate corresponding reading order, read the data volume of 8M bytes from DDR.
Because in the situation that fall screen, what bottom-right first point of screen showed is first address of internal memory, then according to from right to left, order from top to bottom is cumulative successively.This moment, need to be with 0x7E9000-1=0x7E8FFF when calculating initial OPADD, namely the highest 1 byte of last pixel of last column.
For dma controller 21, dma controller 21 is understood the data volume of OPADD initial according to this and screen resolution at this moment, calculates the initial reading address of the osd data that reads in DDR.That is: addr2=addr1-size+ 1=0x7E8FFF-0x7E9000+ 1=0x00000000.
At this moment, dma controller 21 can generate corresponding reading order after obtaining initial reading address, from 0x00000000, reads 0x7E9000 data in DDR, then it is deposited in N buffer area 23.Further, can carry out carrying out data in N buffer area 23 by reverse manner and extract (from big to small, read by byte the address of reading out data), then it be deposited in display module 3 and show (storage area that perhaps deposits other in).At first can extract the address of last pixel, as table 2.Fig. 2 is last pixel color position table.
Table 2
If oppositely extract data this moment, the data of extracting are respectively A, R, G, B, the data reversed in order that order is extracted when just shielding.Therefore should reset color format, with the setting of corresponding register 22.Color format is set to preset form opposite.Become B, G, R, A from high byte to low byte A, R, G, B.Then successively decrease successively in address, until the 0x7E9000 byte of memory reads complete (address is decremented to 0x00000000).
If on the screen of this moment, the left and right exchange shows numeral 12, as shown in Figure 8 A.If will make 12 forwards be presented at display screen (as shown in Fig. 7 C) this moment.
The reading manner of register 22 settings this moment is for shielding reading manner, if with 16 systems for example, the value that the register 22 of this moment arranges is 0x01.
, because do not need up and down conversion, need this moment every delegation to carry out from right to left reverse read, and row still sequentially read from top to bottom.Therefore, the start address that reads for the first time is set to last byte width * 4-1 of the first row.Take full HD 1920 * 1080 resolution as example, the start address that internal memory reads is set to 1920 * 4-1=0x1DFF(16 system).Successively decrease successively in address afterwards, and reducing to first pixel of one's own profession needs again to jump to afterwards last pixel of the second row, and address is 0x1DFF+ (1920 * 1 * 4), and reading order is also to successively decrease successively.By that analogy, the start address that n is capable is 0x1DFF+ (1920 * (n-1) * 4).Until 1080 row circulations are complete.Also need to reset pixel format in this process with opposite before.Be ARGB if form is set before, should be re-set as BGRA now.
If exchanging up and down, the screen of this moment shows numeral 12, as shown in Figure 8 B.If will make 12 forwards be presented at display screen (as shown in Fig. 7 C) this moment.
The reading manner of register 22 settings this moment is for shielding reading manner, if with 16 systems for example, the value that the register 22 of this moment arranges is 0x10.
At this moment, the data of every delegation are that positive sequence reads, but need to up read from last column.Therefore, take full HD 1920 * 1080 resolution as example, start address is first pixel of last column for the first time, and address is 1920 * (1080-1) * 4=0x7E7200.Address starts cumulative reading out data afterwards,, when reading last pixel of one's own profession, starts to read top data line, and resetting start address is 1920 * (1080-2) * 4=0x7E5400.The like, n start of line address is 1920 * (1080-n) * 4, until 1080 row circulations are complete.Because this process is to read in order with delegation's pixel, so pixel format needn't reset.
In addition,, in order to improve the refresh rate of screen, used N buffer zone in dma module 2.N the buffer area 23 of this moment is at least two buffer areas.
Concrete, below use two buffer areas to give an example,, for the ease of distinguishing the effect of DMA in these two buffer areas, will revise the name of osd data, with osd data called after OSD picture data, both fleshes and bloods are the same.
When N buffer area 23 comprises the first buffer area and the second buffer area at least, the first buffer area and the second buffer area are arranged side by side, and reading manner is when shielding reading manner, and dma controller 21 specifically is used for:
The first,, based on shielding reading manner, determine the first start address of an OSD picture data, and read an OSD picture data according to the first start address from DDR and write in the first buffer area.
Concrete, the mode that dma controller 21 reads an OSD picture data with above to read the method for osd data consistent, do not repeat them here.
Concrete, each frame OSD picture data all is comprised of a plurality of OSD picture datas, for example an OSD picture data, the 2nd OSD picture data ... etc. a plurality of OSD picture datas can jointly form the first frame OSD picture data.
Second, based on shielding reading manner, extract an OSD picture data from the first buffer area from the first buffer area shows for display module 3 according to reverse sequence, simultaneously, based on shielding reading manner, determine the second start address of the 2nd OSD picture data, and read the 2nd OSD picture data according to the second start address from DDR and write in the second buffer area.
Concrete, when dma controller 21 extracts an OSD picture data demonstration, can read the 2nd OSD picture data from DDR, to improve the efficiency that refreshes of display.
The 3rd, after extracting a complete OSD picture data,, based on shielding reading manner, extract the 2nd OSD picture data according to reverse sequence and show for display module 3 from the second buffer area from the second buffer area.
With two buffer areas for example, extract previous OSD picture data (i.e. an OSD picture data) at DMA while showing from previous buffer area, dma controller 21 can set about reading the OSD picture data (i.e. the 2nd OSD picture data) of rear.And start prepare to extract a rear OSD picture data and show.So just be equivalent to use the memory headroom of twice before being equivalent to.After previous OSD picture data demonstration was complete, the direction of extraction arranged the address of pointing to next OSD picture data.
Take 1920 * 1080 resolution as example, the handoff procedure of the OSD picture data between each frame is described first.
The data volume of each frame OSD picture data is 1920 * 1080 * 4=0x7E9000 byte.Therefore, if the initial extraction address of former frame OSD picture data is 0x00000000, last address is 0x7E8FFF.So, the initial extraction address of a frame OSD picture data is 0x7E9000.Like this,, from the angle of overall OSD Picture switch, can realize the quick switching of two OSD pictures by the variation of two start addresses, and not be used in same address, again read and write data.Therefore, in the processing procedure of next frame OSD picture data, also to realize accordingly the processing procedure of similar previous frame OSD picture data.For the operation of OSD picture rotation exchange, the exchange of two width OSD picture start addresses does not have too large difference concerning dma module 2 operations, only need to add accordingly when calculating initial extraction address each time 0x7E9000.
And, for each frame OSD picture data, suppose that each frame OSD picture data all consists of an OSD picture data and the 2nd OSD picture data.So, dma controller can be carried out the process of above-named extraction the one OSD picture data and extraction the 2nd OSD picture data.Namely at first can determine the first start address of an OSD picture data, then read an OSD picture data and deposit the first buffer area in from DDR.When showing, OSD picture data inverted order from the first buffer area is read.Simultaneously, read the 2nd OSD picture data based on the second start address from DDR, and deposit in the second buffer area.An OSD picture data in the first buffer area be extracted show complete after, then the 2nd OSD picture data that extracts in the second buffer area according to reverse sequence from the second buffer area shows.
Switching from the OSD picture data between frame and frame, if register 22 is set to just shield reading manner, initial extraction address in first buffer area in N buffer area 23 is set to 0x00000000, the initial extraction address in next buffer area is arranged to start to read from 0x7E9000, and other class of operation seemingly read the operation of OSD picture data.
From the switching of the OSD picture data between frame and frame, if register 22 is set to shield reading manner, register 22 is set to 0x11.Dma controller 21 will carry out by reverse manner data extractions (from big to small, read by byte the address of reading out data) in N buffer area 23 this moment.When extracting data, the initial extraction address of the first frame OSD picture data is 0x7E8FFF.I.e. the highest 1 byte of last pixel of last column of the osd data of the first picture.And the account form of the initial extraction address of next frame OSD picture data is specially: 0x7E9000+0x7E9000-1=0xFD1FFF.It is the highest 1 byte of last pixel of last column of next picture.When dma controller 21 is extracting the first frame OSD picture data and deposits display module 3 in and show, at first can start extraction according to the initial extraction of 0x7E8FFF address in N buffer area.After the first frame OSD picture data extraction is complete, then according to the initial extraction of 0xFD1FFF address, start to extract next frame OSD picture data.And extract the OSD picture data this moment, and the osd data that extracts is respectively A, R, G, B, the data reversed in order that order is extracted when just shielding.Therefore should reset color format, color format is set to preset form opposite.Become B, G, R, A from high byte to low byte A, R, G, B.Then successively decrease successively in address, until the 0x7E9000 byte of memory reads complete (address is decremented to 0).
If register 22 is set to shield reading manner, and is concrete, be that the OSD picture data of each frame will carry out the left and right exchange, this moment, the value of register 22 was set to 0x01., because do not need up and down conversion, need this moment every delegation to carry out from right to left reverse read, and row still sequentially read from top to bottom.Therefore, the start address that reads for the first time is set to last byte width * 4-1 of the first row.Take full HD 1920 * 1080 resolution as example, the start address that internal memory reads is set to 0x7E9000+1920 * 4-1=0x7EADFF(16 system).Successively decrease successively in address afterwards, and reducing to first pixel of one's own profession needs again to jump to afterwards last pixel of the second row, and address is 0x7E9000+0x1DFF+ (1920 * 1 * 4), and reading order is also to successively decrease successively.By that analogy, the start address that n is capable is 0x7E9000+0x1DFF+ (1920 * (n-1) * 4).Until 1080 row circulations are complete.Also need to reset pixel format in this process with opposite before.Be ARGB if form is set before, should be re-set as BGRA now.Further, after having read previous frame OSD picture data, start to read next frame OSD picture data, reading manner and top similar.
If register 22 is set to shield reading manner, and is concrete, be that the osd data in picture will carry out the left and right exchange, this moment, the value of register 22 was set to 0x10.At this moment, the data of every delegation are that positive sequence reads, but need to up read from last column.Therefore, take full HD 1920 * 1080 resolution as example, start address is first pixel of last column for the first time, and address is 0x7E9000+1920 * (1080-1) * 4=0xFD0200.Address starts cumulative reading out data afterwards,, when reading last pixel of one's own profession, starts to read top data line, and resetting start address is 0x7E9000+1920 * (1080-2) * 4=0xFCE400.The like, n start of line address is 0x7E9000+1920 * (1080-n) * 4, until 1080 row circulations are complete.Because this process is to read in order with delegation's pixel, so pixel format needn't reset.Further, after having read the OSD picture data of previous frame, start to read the OSD picture data of next frame, reading manner and top similar.
Further, for the driving of N buffer area 23, special switching function is arranged, to the switching of in fact extracting address of this N buffer area 23.
Code in the situation for various screens is changed, and corresponding register 22 is changed and the operation of dma module 2 can be loaded in system drive or even application, can transplant for various screens easily.At first carry out initialize routine after system powers on, then the value of the spin register 22 of judgement input, carry out respectively the realization of each rotary manipulation.Simultaneously can arrange whether need to use double buffering.
Concrete, the code in the situation for various screens is changed, and can, based on the configuration of register and the screen resolution parameter of display module, obtain run time version; Then, with run time version writing system script, with the corresponding execution parameter that changes in run time version of parameter variation of the screen resolution for display module, and drive execution.
Further, corresponding register 22 changes and dma operation are loaded in system drive or even application.Such as,, if be added in display driver, can be added in the system booting script ordering accordingly.The linux system example is as follows:
insmod?display.ko?w=1920h=1080reverse=0x11
Wherein, w represents the width that shields, and h represents the height that shields, and the 0x11 of reverse back is exactly the value of controlling register 22 settings of Image Reversal.
In addition, can set the screen that falls of 1920x1080 resolution when the system startup is initialized.Need not like this each screen and all re-start the modification of code and the compiling of driver, the very big workload that must reduce software, different screens are directly transplanted also convenient.
In superincumbent description, specifically described the hardware configuration of electronic equipment and concrete principle of work, the data processing method in the embodiment of the present application has been described below.
Wherein, the method is applied in above-described electronic equipment.
Below please refer to Figure 11, describe the specific implementation process of the method.
S111, while at needs, osd data being presented on display module 3, obtain to shield reading manner from register 22 by dma controller 21.
S112, determine the initial reading address of osd data in DDR by dma controller 21 based on shielding reading manner.
Concrete, reading manner can be divided into and just shielding reading manner and shielding reading manner, and about the implication of these two kinds of reading manners, top embodiment tool is described later in detail, and does not repeat them here.
In addition, according to the difference of reading manner, also different by the initial reading address that dma controller 21 obtains.
When shielding reading manner, by dma controller 21, based on reading manner, determine the initial reading address of osd data in DDR when reading manner, specifically comprise:
Obtain by dma controller 21 data volume that the screen resolution of the initial OPADD of DDR and display module 3 takies.
Then, based on shielding reading manner,, according to initial OPADD and data volume, determine the initial reading address of osd data in DDR.
, if reading manner, for being just to shield reading manner, is determined the initial reading address of osd data in DDR by dma controller 21 based on reading manner, specifically comprise:
At first, obtain initial OPADD and data volume.
Then,, based on just shielding reading manner,, according to initial OPADD and data volume,, take initial OPADD as initial reading address, read osd data from DDR.
, when based on shielding reading manner, after having obtained initial reading address, can carry out following step.
S113, send corresponding reading order by dma controller 21 to DDR, reads osd data according to initial reading address from DDR, and osd data is deposited in N buffer area successively.
Wherein, N is positive integer.
Concrete, if reading manner is when shielding reading manner, dma module 2 also comprises: N buffer area 23, wherein, N is positive integer.
Sending corresponding reading order by dma controller 21 to DDR, read osd data according to initial reading address from DDR after, method also comprises:
By dma controller 21, osd data is deposited in N buffer area 23.
S114,, based on shielding reading manner, extract osd data with reverse sequence by dma controller 21 from N buffer area 23, and osd data is sent to display module 3 demonstrations.
Reversed in order when wherein, reverse sequence and dma controller 21 deposit osd data in to N buffer area 23.
And when reading manner when just shielding reading manner, dma controller 21 after reading osd data, can directly be transferred to osd data display module 3 and show.
In addition, the method also comprises:
Based on shielding reading manner, the parameter that each pixel of display module is set puts in order, and parameter is put in order while with osd data, with forward sequence, being sent to display module, and putting in order of the parameter of each pixel of display module is identical.
Wherein, forward sequence is the order of dma controller while to N buffer area, depositing osd data in.Concrete, it is red that the parameter of each pixel has comprised R(), G(is green), B(is blue), the A(transparency) four kinds,, when if osd data deposits display module according to forward sequence, be according to ARGB(transparency, redness, green, blueness) form is stored, and when reverse sequence deposits in, ARGB can be adjusted into BGRA so.
In addition, when N buffer area comprises the first buffer area and the second buffer area at least, the first buffer area and the second buffer area are arranged side by side, and based on shielding reading manner, the data processing method in the present embodiment also has following implementation process.
The first,, based on shielding reading manner, by dma controller 21, determine first start address of an OSD picture data in DDR.
The second, read an OSD picture data by dma controller 21 according to the first start address from DDR and write successively in the first buffer area.
The 3rd, based on shielding reading manner, extract an OSD picture data from the first buffer area shows for display module 3 with reverse sequence by dma controller 21, simultaneously, based on shielding reading manner, determine the second start address of the 2nd OSD picture data, and read the 2nd OSD picture data according to the second start address from DDR and write successively in the second buffer area.
Concrete, when dma controller 21 extracts an OSD picture data demonstration, can read the 2nd OSD picture data from DDR, to improve the efficiency that refreshes of display.
The 4th, after extracting a complete OSD picture data,, based on shielding reading manner, extract the 2nd OSD picture data by dma controller 21 with reverse sequence and show for display module 3 from the second buffer area.
, by one or more embodiment of the present invention, can be achieved as follows technique effect:
Data processing method of the present invention is when needs, screen menu type to be regulated (OSD) data while being presented on display module, obtains the reading manner that shields of register configuration by dma controller; Then, based on shielding reading manner, by dma controller, determine the initial reading address of osd data in DDR; Send corresponding reading order by dma controller to DDR again, read osd data according to initial reading address from DDR, and osd data is deposited in N buffer area successively, wherein, N is positive integer; Finally,, based on shielding reading manner, extract osd data with reverse sequence by dma controller from N buffer area, and osd data is sent to the display module demonstration, reversed in order when wherein, reverse sequence and dma controller deposit osd data in to N buffer area.The present invention is by reading the reading manner that shields that configures in register, deposit in N buffer area with reading out data from DDR, and show with reverse sequence extraction data from N buffer area, realize that osd data is rotated, only need hardware to carry out in whole process, use N buffer area to replace opening up special memory block in DDR, and configuration is shielded reading manner and is used for dma controller in register, need not to use software algorithm to be rotated osd data, the internal memory of DDR can be too much do not taken, and then the service efficiency of system can be improved.The present invention can be applied to TCON is positioned over the flatscreen electronic equipment of base, and is applicable to common giant-screen electronic equipment.
Those skilled in the art should understand, embodiments of the invention can be provided as method, system or computer program.Therefore, the present invention can adopt complete hardware implementation example, implement software example or in conjunction with the form of the embodiment of software and hardware aspect fully.And the present invention can adopt the form that wherein includes the upper computer program of implementing of computer-usable storage medium (including but not limited to magnetic disk memory, CD-ROM, optical memory etc.) of computer usable program code one or more.
The present invention describes with reference to process flow diagram and/or the block scheme of method, equipment (system) and computer program according to the embodiment of the present invention.Should understand can be by the flow process in each flow process in computer program instructions realization flow figure and/or block scheme and/or square frame and process flow diagram and/or block scheme and/or the combination of square frame.Can provide these computer program instructions to the processor of multi-purpose computer, special purpose computer, Embedded Processor or other programmable data processing device to produce a machine, make the instruction of carrying out by the processor of computing machine or other programmable data processing device produce to be used for the device of realizing in the function of flow process of process flow diagram or a plurality of flow process and/or square frame of block scheme or a plurality of square frame appointments.
These computer program instructions also can be stored in energy vectoring computer or the computer-readable memory of other programmable data processing device with ad hoc fashion work, make the instruction that is stored in this computer-readable memory produce the manufacture that comprises command device, this command device is realized the function of appointment in flow process of process flow diagram or a plurality of flow process and/or square frame of block scheme or a plurality of square frame.
These computer program instructions also can be loaded on computing machine or other programmable data processing device, make on computing machine or other programmable devices and to carry out the sequence of operations step to produce computer implemented processing, thereby be provided for realizing the step of the function of appointment in flow process of process flow diagram or a plurality of flow process and/or square frame of block scheme or a plurality of square frame in the instruction of carrying out on computing machine or other programmable devices.
Obviously, those skilled in the art can carry out various changes and modification and not break away from the spirit and scope of the present invention the present invention.Like this, if within of the present invention these are revised and modification belongs to the scope of the claims in the present invention and equivalent technologies thereof, the present invention also is intended to comprise these changes and modification interior.
Claims (10)
1. a data processing method, is characterized in that, described method comprises:
When needs, screen menu type is regulated (OSD) data while being presented on display module, obtained the reading manner that shields of register configuration by dma controller;
, based on the described reading manner that shields, by described dma controller, determine the initial reading address of described osd data in described DDR;
Send corresponding reading order by described dma controller to described DDR, read described osd data according to described initial reading address from described DDR, and described osd data is deposited in N buffer area successively, wherein, N is positive integer;
Based on the described reading manner that shields, extract described osd data from a described N buffer area with reverse sequence by described dma controller, and described osd data is sent to described display module demonstration, reversed in order when wherein, described reverse sequence and described dma controller deposit described osd data in to a described N buffer area.
2. the method for claim 1, is characterized in that, described method also comprises:
Based on the described reading manner that shields, the parameter that each pixel of described display module is set puts in order, described parameter is put in order while with described osd data, with forward sequence, being sent to described display module, putting in order of the parameter of each pixel of described display module is identical, wherein, described forward sequence is the order of described dma controller while to a described N buffer area, depositing described osd data in.
3. the method for claim 1, is characterized in that, described method also comprises:
Described based on the described reading manner that shields, determine the initial reading address of described osd data in described DDR by described dma controller, specifically comprise:
Obtain by described dma controller the data volume that the screen resolution of the initial OPADD of described DDR and described display module takies;
, based on the described reading manner that shields,, according to described initial OPADD and described data volume, determine the initial reading address of described osd data in described DDR.
4. the method for claim 1, it is characterized in that, when a described N buffer area comprises the first buffer area and the second buffer area at least, described the first buffer area and described the second buffer area are arranged side by side, described based on the described reading manner that shields, determine the initial reading address of described osd data in described DDR by described dma controller, specifically comprise:
, based on the described reading manner that shields, by described dma controller, determine first start address of an OSD picture data in described DDR.
5. method as claimed in claim 4, is characterized in that, described determine first start address of an OSD picture data in described DDR by described dma controller after, described method also comprises:
Reading a described OSD picture data by described dma controller according to described the first start address from described DDR writes in described the first buffer area successively;
Based on the described reading manner that shields, extract a described OSD picture data from described the first buffer area shows for described display module with described reverse sequence by described dma controller, simultaneously, based on the described reading manner that shields, determine the second start address of the 2nd OSD picture data, and read described the 2nd OSD picture data according to described the second start address from described DDR and write successively in described the second buffer area;
After extracting a complete described OSD picture data,, based on the described reading manner that shields, extract described the 2nd OSD picture data by described dma controller with described reverse sequence and show for described display module from described the second buffer area.
6. method as claimed in claim 4, is characterized in that, described method also comprises:
, based on the configuration of described register and the screen resolution parameter of described display module, obtain run time version;
, with described run time version writing system script, with the corresponding execution parameter that changes in described run time version of parameter variation of the screen resolution for described display module, and drive execution.
7. an electronic equipment, is characterized in that, described electronic equipment comprises: Installed System Memory (DDR), and display module, and be connected to dma module between described DDR and described display module;
Described DDR, be used for the storage screen menu type and regulate (OSD) data;
Described dma module, comprise dma controller, a register and N buffer area, and wherein, N is positive integer; Wherein said dma controller be connected DDR and connect, described register is connected with described dma controller, a described N buffer area and described DDR, described display module, and described dma controller three connection; Dispose the reading manner that shields of described osd data in described register; Described dma controller is used for when needs are presented at described osd data on described display module, obtains the described reading manner that shields from described register; Then determine the initial reading address of described osd data in described DDR based on the described reading manner that shields, and to described DDR, send corresponding reading order, read described osd data according to described initial reading address from described DDR; Then described osd data is deposited in N buffer area, and extract described osd data with reverse sequence and be sent to the display module demonstration from a described N buffer area, reversed in order when wherein, described reverse sequence and described dma controller deposit described osd data in to a described N buffer area;
Described display module, be used for receiving and showing described osd data from described N buffer area.
8. electronic equipment as claimed in claim 7, is characterized in that, described electronic equipment also comprises:
Bus, be connected between described DDR and described dma controller, is used for transmitting the reading order of described dma controller to described dma controller.
9. electronic equipment as claimed in claim 7, is characterized in that, described dma controller specifically is used for:
Obtain the data volume that the screen resolution of the initial OPADD of described DDR and described display module takies;
, based on the described reading manner that shields,, according to described initial OPADD and described data volume, determine the initial reading address of described osd data in described DDR.
10. electronic equipment as claimed in claim 7, it is characterized in that, when a described N buffer area comprises the first buffer area and the second buffer area at least, described the first buffer area and described the second buffer area are arranged side by side, and described reading manner is when shielding reading manner, and described dma controller specifically is used for:
, based on the described reading manner that shields, determine the first start address of an OSD picture data, and read a described OSD picture data according to described the first start address from described DDR and write in described the first buffer area;
Based on the described reading manner that shields, extract a described OSD picture data from described the first buffer area shows for described display module with described reverse sequence, simultaneously, based on the described reading manner that shields, determine the second start address of the 2nd OSD picture data, and read described the 2nd OSD picture data according to described the second start address from described DDR and write in described the second buffer area;
After extracting a complete described OSD picture data,, based on the described reading manner that shields, to extract described the 2nd OSD picture data from described the second buffer area according to described reverse sequence, for described display module, show.
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Effective date of registration: 20160801 Address after: 266100 Zhuzhou Road, Laoshan District, Shandong, No. 151, No. Patentee after: Qingdao Hisense Electric Co., Ltd. Address before: 266100 Shandong city of Qingdao province Jiangxi City Road No. 11 Patentee before: Qingdao Hisense Xinxin Technology Co., Ltd. |
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Address after: 266100 Zhuzhou Road, Laoshan District, Shandong, No. 151, No. Patentee after: Hisense Video Technology Co., Ltd Address before: 266100 Zhuzhou Road, Laoshan District, Shandong, No. 151, No. Patentee before: HISENSE ELECTRIC Co.,Ltd. |
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