CN1767334A - Switching power supply control device and switching power supply - Google Patents

Abstract

A switching power supply comprises a switching device, a smoothing circuit, and a control circuit including a current detector for detecting a current flowing through an inductor in the smoothing circuit. The detected current is multiplied by a current control gain to generate a signal PIS. The rectangular wave signal is add to and the signal PIS is subtracted from a voltage detection signal corresponding to the output voltage of the switching power supply. The current control gain is adjusted so that DeltaPIS/DeltaD becomes closer to a predetermined constant, where DeltaPIS represents an amount of change in the signal PIS, and DeltaD an amount of change in the duty ratio of a driving signal for the switching device.

Description

Switching power supply control device and Switching Power Supply

Technical field

The present invention relates to carry out the switching power supply control device and the Switching Power Supply of phase lead compensation by means of Controlled in Current Mode and Based.

Background technology

Switching Power Supply has the characteristic of small-sized light weight and high efficiency etc., has been assembled into the interior power supply as microcomputer or personal computer etc. of various device and has been widely used.In these personal computers etc., constantly advancing lower voltage and high speed processingization, current sinking is in continuous increase on the other hand.For this reason, in Switching Power Supply, load current will correspondingly with the processing load in the personal computer etc. increase sharp or reduce.In addition, Switching Power Supply also has the characteristic of the input voltage range that is easy to tackle wide region, can also be used as the power supply that can tackle in several countries of the world or the specification of input voltage and set wide power supply.In Switching Power Supply, must ensure stable output voltage for the variation of this load current or input voltage.In addition, even if corresponding to the rapid variation of load current or input voltage, output voltage demonstrates transient state when replying, and also requires promptly to return to stable status.

Particularly to drive the Switching Power Supply of LSI (large scale integrated circuit large scale integration) of the high and low voltage of clock frequency of the microprocessor of VRM (voltage regulator module voltage regulator module) or POL (POL point of load) etc. or DSP (digital signal processor digital signal processor) etc., in order to tackle the rapid variation of load current, generally require high-speed responsive.But, possessing as output circuit in the Switching Power Supply of LC filter circuit, because phase lag can take place in the influence of LC filter circuit.

Switching Power Supply also can possess the control device of controller IC (Intergrated circuit) etc., makes the output voltage of the switch element of FET (Field effect transistor) etc. carry out ON/OFF by means of this control device.This control device feeds back the formation Voltage loop to the output voltage of Switching Power Supply, according to this output voltage, produces and is used for making switch element to carry out pulse-width modulation (PWM) signal of ON/OFF.In " An Accurate and Practical Small-Signal Modelfor Current-Mode Control ", Ridley Engineering inc., 1999, the electric current that discloses flowing in the inductor of LC filter circuit feeds back the formation electric current loop, carries out the control device of phase lead compensation by means of the Controlled in Current Mode and Based of using the electric current that flows in inductor.In electric current loop, generally to feed back the value that detected electric current is multiplied by constant Current Control gain.In this Current Control gain, exist an optimum value.In addition, at Data Sheetof HIP6301 PWM controller, intersil corporation in 2002, has put down in writing the situation of the electric current that the voltage detecting at the two ends of the ON resistance when becoming ON according to switch element flows in inductor.

But when using the ON resistance detection electric current of switch element, the resistance value of this ON resistance will influence the gain of electric current loop.Thus, when existing fluctuation or variations in temperature etc. in the resistance value of ON resistance, then the gain of electric current loop just will change from optimum value, control system is become be instability.Its result can make the change of output voltage become big, exists the vibrative possibility of output voltage.If it is big that the gain of electric current loop becomes, then gain margin will be not enough in high-frequency region, and it is unstable that the control of output voltage becomes.On the other hand, if the gain of electric current loop reduces, then phase margin is insufficient in high-frequency region, and the leading effect of phase place reduces makes the control of output voltage become unstable.

Summary of the invention

Therefore, the object of the present invention is to provide the Switching Power Supply control device and the Switching Power Supply of the gain optimization that makes electric current loop.

One aspect of the present invention relates to the switching power supply control device of control switching.Switching Power Supply comprises switch element that the switch periods and the switching frequency of regulation with regulation carry out switch and the smoothing circuit that makes the output smoothingization of switch element.Smoothing circuit possesses the inductor that connects Switching Power Supply.This switching power supply control device possesses: the output voltage of sense switch power supply produces the voltage detection mechanism of the voltage detection signal corresponding with this output voltage; In each switch periods, detect the electric current that in inductor, flows, produce the current detecting mechanism of the current detection signal corresponding with this electric current; The square-wave signal of square-wave signal that generation has 1/2 frequency of switching frequency produces mechanism; Be multiplied by the Current Control gain to current detection signal, produce gain and take advantage of taking advantage of of calculation current detection signal to calculate mechanism; When voltage detection signal is added square-wave signal, deduct gain and take advantage of the calculation current detection signal, to produce the arithmetical organ of control signal; Generation has the drive pulse signal with the big or small time corresponding ratio of control signal, supplies with this drive pulse signal to switch element and produces mechanism with the drive signal of driving switch element; Adjust the gain adjusting mechanism that Current Control gains according to gain multiplied signal and time ratio.Drive signal produces mechanism and produces above-mentioned drive pulse signal, makes Δ D/ Δ CS (, Δ D is the variable quantity of each switch periods of time ratio, and Δ CS is the variable quantity of each switch periods of control signal) become constant a herein.The gain adjusting mechanism is adjusted the Current Control gain, makes to satisfy Δ PIS/ Δ D=-1/2a (Δ PIS is the variable quantity that each switch periods of calculating current detection signal is taken advantage of in gain) herein.

Another aspect of the present invention relates to the switching power supply control device that is connected to smoothing circuit formation Switching Power Supply.Smoothing circuit comprises inductor.This switching power supply control device possesses: carry out switch with the switch periods of regulation and the switching frequency of regulation, should be connected to the switch element on the inductor; The output voltage of sense switch power supply produces the voltage detection mechanism of the voltage detection signal corresponding with this output voltage; In each switch periods, detect the electric current that in inductor, flows, produce the current detecting mechanism of the current detection signal corresponding with this electric current; The square-wave signal of square-wave signal that generation has 1/2 frequency of switching frequency produces mechanism; Be multiplied by the Current Control gain to current detection signal, produce gain and take advantage of taking advantage of of calculation current detection signal to calculate mechanism; On voltage detection signal, add square-wave signal, deduct gain simultaneously and take advantage of the calculation current detection signal, produce the arithmetical organ of control signal; Generation has the drive pulse signal with the big or small time corresponding ratio of control signal, supplies with this drive pulse signal to switch element and produces mechanism with the drive signal of driving switch element; Take advantage of the gain adjusting mechanism of calculating detection signal and the gain of time ratio adjustment Current Control according to gain.Drive signal produces mechanism and produces drive pulse signal, makes Δ D/ Δ CS (, Δ D is the variable quantity of each switch periods of time ratio, and Δ CS is the variable quantity of each switch periods of control signal) become constant a herein.The gain adjusting mechanism is adjusted the Current Control gain, makes to satisfy Δ PIS/ Δ D=-1/2a (Δ PIS is the variable quantity that each switch periods of calculating current detection signal is taken advantage of in gain) herein.

Above-mentioned switching power supply control device possesses and is used for producing the Voltage loop of drive pulse signal and being used for carrying out according to the electric current that flows in the inductor in Switching Power Supply the electric current loop of phase lead compensation according to the output voltage of Switching Power Supply.Produce drive pulse signal owing to be added to the control signal that is produced on the voltage detection signal corresponding with output voltage based on square-wave signal with 1/2 switching frequency, so during square-wave signal is high and square-wave signal be between lowstand in the pulsewidth of drive pulse signal can change, meanwhile, the time ratio also will change.Because the square wave letter is for equaling 1 switch periods respectively during high and during low, so the time ratio of this drive pulse signal all will change in each switch periods.Corresponding with this drive pulse signal, the electric current that flows in the inductor of smoothing circuit also can change, and is corresponding with this electric current change, and gain takes advantage of the calculation current detection signal all to change in each switch periods.Because the gain adjusting mechanism is adjusted the Current Control gain, make and satisfy Δ PIS/ Δ D=-1/2a, so can make the gain of electric current loop converge to best value, promptly converge to the value that can obtain the leading effect of sufficient phase place and can make the control system stabilisation.Even if because switch element has ON resistance, this resistance value changes because of the fluctuation of element or variations in temperature etc., also can adjust the Current Control gain automatically, offsets the variation of ON resistance value, makes the gain of electric current loop become value for the best.Since can make the current loop gain optimization, just can obtain the leading effect of sufficient phase place by the current loop control in the control device, can be corresponding to the control of high switching frequency.Therefore, in Switching Power Supply, the control system stabilisation, output voltage does not have big change, can carry out high-speed responsive yet.In addition, irrelevant with the resistance value of the ON resistance of switch element in the overcurrent of Switching Power Supply detects, can carry out overcurrent and detect.In addition, even if the action etc. of load of Switching Power Supply of resulting from makes load current alternatively increase repeatedly in each switch periods and when reducing, owing in each same switch periods, detect Δ PIS/ Δ D adjusting the Current Control gain, thus can be stable carry out current loop control.

In addition, drive pulse signal is to be used for making the switch element of Switching Power Supply to carry out the signal of ON/OFF, for example, is pwm signal.The voltage detection signal corresponding with the output voltage of Switching Power Supply is to be used for carrying out according to output voltage the signal of FEEDBACK CONTROL, for example, is the signal after detected output voltage and target voltage difference are amplified.The time ratio of drive pulse signal, be in 1 cycle of drive pulse signal, occupied switch element is become be the ratio during the ON (that is the ratio during the ON that in 1 cycle of switch motion, is occupied).The time ratio of drive pulse signal both can have directly been used in the adjustment of Current Control gain, also can use other parameter of reflection time ratio, for example, used the pulsewidth of drive pulse signal.

Switch element also can have ON resistance.Current detecting mechanism, the voltage at two ends that also can be by detecting ON resistance detects the electric current that flows in inductor.

The calculation current detection signal is taken advantage of in gain, also can alternatively rise repeatedly and descend in each switch periods.The time ratio also can be taken advantage of the rising of calculating current detection signal and synchronously reduces along with gain, along with gain is taken advantage of the decline of calculating current detection signal and synchronously increased.

Drive signal produces mechanism, can comprise that the ramp signal of the ramp signal (ramp) that generation is vibrated with specified amplitude and switching frequency produces mechanism.Constant a can be the inverse of the amplitude of ramp signal.

The gain adjusting mechanism, can comprise: calculate (1/2a) D_A+PIS_A (herein, D_A is the time ratio of square-wave signal during height, PIS_A is that the size of calculating current detection signal is taken advantage of in the gain of square-wave signal during height), and first arithmetical organ of first consequential signal of this result of calculation of generation expression; Calculate (1/2a) D_B+PIS_B (herein, D_B is the time ratio of square-wave signal between lowstand, PIS_B is that the size of calculating current detection signal is taken advantage of in the gain of square-wave signal between lowstand), and second arithmetical organ of second consequential signal of this result of calculation of generation expression; Compare first consequential signal and second consequential signal, first of first comparison signal of this comparative result of generation expression compares mechanism; From drive pulse signal, detect the time ratio testing agency of D_A and D_B, more detected D_A and detected D_B, second of second comparison signal of this comparative result of generation expression compares mechanism; Increase or reduce the gain determination means of Current Control gain accordingly with the gain of decision Current Control with first and second comparison signals.

Gain is taken advantage of and calculated current detection signal also can be analog signal.The gain adjusting mechanism also can comprise: gain is taken advantage of calculated the calculation signal is taken advantage of in the current detection signal digitlization with the generation digital gain analogue-to-digital converters; Take advantage of the first Digital Detecting circuit of calculating detection Δ PIS the signal from digital gain; From drive pulse signal, detect the second Digital Detecting circuit of Δ D; Use detected Δ PIS and Δ D to calculate the digital divider of Δ PIS/ Δ D; Relatively the Δ PIS/ Δ D of Ji Suaning and-1/2a, produce the digital comparator of the output signal of this comparative result of expression; Based on the output signal of digital comparator, increase or reduce the Current Control gain, make Δ PIS/ Δ D approaching-1/2a, to produce the digital gain decision-making circuit of the digital gain signal that this Current Control that has increased or has reduced of expression gains; Make digital gain signal imitationization, produce the digital-analog convertor of analog gain signal.Take advantage of and calculate mechanism, also can accept analog gain signal and current detection signal, produce the long-pending output signal that is equivalent to both and take advantage of the calculation current detection signal as gain.

Further aspect of the present invention relates to Switching Power Supply.This Switching Power Supply possesses: the switch element that carries out switch with the switching frequency of prescribed switch cycle and regulation; Make the output smoothingization of switch element, produce the smoothing circuit of the output voltage of this Switching Power Supply; The controlling organization of the switch of control switch element.Smoothing circuit comprises the inductor that is connected on the switch element.Control device possesses: above-mentioned voltage detection mechanism, current detecting mechanism, square-wave signal produce mechanism, take advantage of and calculate mechanism, arithmetical organ, drive signal generation mechanism and gain adjusting mechanism.

In this Switching Power Supply, can adjust the Current Control gain automatically by control device, thus, can make the gain optimization of electric current loop.Therefore, this Switching Power Supply can make switch element carry out ON/OFF with the drive pulse signal that has fully carried out phase lead compensation.Consequently in this Switching Power Supply, can carry out high-speed responsive, and make the control system stabilisation by phase lead compensation.

According to the present invention, when carrying out phase lead compensation by Controlled in Current Mode and Based, by the gain of automatic adjustment Current Control, can be so that the gain optimization of electric current loop, obtain the leading effect of sufficient phase place, can also make hierarchy of control stabilisation simultaneously.Therefore, when using the ON resistance effect of switch element to detect electric current, can compensate the change of ON resistance value, make output voltage stabilizationization.

Description of drawings

Fig. 1 is the pie graph of the DC/DC transducer of first execution mode.

Fig. 2 is the time diagram of the controller IC of Fig. 1, (a) be voltage signal from differential amplifier circuit, (b) be to take advantage of the calculation current detection signal from the gain of multiplier, (c) be pwm signal from comparator, (d) come square-wave signal to produce the square-wave signal of circuit, (e) be from the gain of the Current Control of Current Control gain adjustment circuit, (f) be the gain of current loop circuit.

Fig. 3 is illustrated in to make the block diagram of electric current loop of gain optimization in the DC/DC transducer of Fig. 1.

The characteristic of the transfer function when Fig. 4 is illustrated in gain akik=1 in the electric current loop of Fig. 3, (a) expression gain characteristic, (b) expression phase characteristic.

The characteristic of the transfer function when Fig. 5 is illustrated in gain akik=0.5 in the electric current loop of Fig. 3, (a) expression gain characteristic, (b) expression phase characteristic.

The characteristic of the transfer function when Fig. 6 is illustrated in gain akik=1.5 in the electric current loop of Fig. 3, (a) expression gain characteristic, (b) expression phase characteristic.

Fig. 7 is the gain akik of electric current loop of presentation graphs 3 and the curve chart of the relation between the transfer function G.

Fig. 8 is used for illustrating that gain takes advantage of the time diagram of the variation delta PIS that calculates current detection signal and the variation delta D of pwm signal, is to gain to take advantage of the calculation current detection signal (a), (b) is square-wave signal, (c) is pwm signal.

Fig. 9 is the detail circuits figure of Current Control gain adjustment circuit.

Figure 10 is the time diagram of the Current Control gain adjustment circuit of Fig. 1, (a) be square-wave signal, (b) be pwm signal, (c) being maximum pwm signal, (d) is that the calculation signal is taken advantage of in gain, (e) is the add operation signal, (f) be the time rate signal, (g) being first clock signal, (h) is the second clock signal, (i) is the 3rd clock signal.

Figure 11 is the left side and the magnitude relationship on the right and the table that increases/subtract of Current Control gain of representation formula (17).

Figure 12 is the pie graph of the Current Control gain adjustment circuit that uses in second execution mode.

Figure 13 is the pie graph of the DC/DC transducer of the 3rd execution mode.

Symbol description

The 1DC/DC transducer; 2 high-end FET; 3 low side FET; 4 inductors; 5 capacitors; 6 controller ICs; 6a Voltage loop circuit; The 6b current loop circuit; 6c gain optimization circuit; 10 differential amplifier circuits; The 10a differential amplifier; The 10b direct voltage source; 10c～10e resistance; The 10f capacitor; 11 addometers; 12 ramp signals produce circuit; 13 comparators; 14 current detection circuits; 15 multipliers; 16 square-wave signals produce circuit; 17 Current Control gain adjustment circuits; The 17a direct voltage source; 17b, 17c switch; The 17d addometer; 17e, 17f Voltage-controlled Current Source; 17g, 17h capacitor; 17i, 17j reset switch; 17k, 17l, 17m, 17n sampling hold circuit; 17o, 17p comparator; 17q increment depreciation counter; The 17r D/A converter

Embodiment

Below, the execution mode that present invention will be described in detail with reference to the accompanying.In addition, in the explanation of drawing, also the repetitive description thereof will be omitted to give identical label for identical key element.

First execution mode

In the present embodiment, Switching Power Supply of the present invention is applied to the DC/DC transducer of voltage-dropping type, switching power supply control device of the present invention is applied to produce the controller IC of the pwm signal of the switch element that is used for controlling the DC/DC transducer.The controller IC of present embodiment carries out phase lead compensation by Controlled in Current Mode and Based.

The formation of DC/DC transducer 1 is described with reference to Fig. 1.Fig. 1 is the figure of the formation of expression DC/DC transducer device.

DC/DC transducer 1 is output voltage V o (＜Vi) the power circuit that the input voltage Vi of direct current is transformed into direct current.DC/DC transducer 1 can use in various purposes, for example, can be used as VRM or POL and uses.In addition, DC/DC transducer 1 still makes switch element carry out the switching regulaor of ON/OFF by PWM control.Input voltage Vi is variable, has set input voltage range (for example, 5～12V).Output voltage V o, the target voltage that can set regulation according to load L (for example, 1V).Load L is CPU, MPU, the DSP that for example is equivalent in the communication equipments such as computer or router etc., and with high clock frequency (for example, number GHz) action, load current is corresponding to handling the big load of load change.

DC/DC transducer 1, the formation as main possesses: the high-end FET2 of switch element and low side FET3 and inductor 4, capacitor 5 and controller IC 6.High-end FET2 becomes when pulse-width modulation (PWM) the signal PS from controller IC 6 is high signal and is ON.On the other hand, pwm signal PS counter-rotating input low side FET3.Thus, when pwm signal PS was low signal, input low side FET3 was high signal, and low side FET3 just becomes and is ON.Inductor 4 and capacitor 5 constitute the LC filter circuit, and these work as smoothing circuit 25.By FET2,3 switch motion, have the pulse-like voltage of the amplitude that equates with input voltage Vi to smoothing circuit 25 outputs, smoothing circuit 25 makes this pulse-like voltage equalization.Controller IC 6, the electric current I that flows according to output voltage V o with in inductor 4 produces pwm signal by Controlled in Current Mode and Based, and control FET2,3 state (in other words, ON state or OFF state) make output voltage V o become target voltage.

Below, with reference to Fig. 1 and Fig. 2, explain controller IC 6.Fig. 2 is the time diagram that is used for illustrating the action of controller IC 6, (a) be voltage signal from differential amplifier circuit, (b) be to take advantage of the calculation current detection signal from the gain of multiplier, (c) be pwm signal from comparator, (d) be the square-wave signal that produces circuit from square-wave signal, (e) be by the Current Control gain of Current Control gain adjustment circuit decision, (f) be the gain of current loop circuit.

Controller IC 6 mainly possesses: differential amplifier circuit 10, addometer 11, ramp signal produce circuit 12, comparator 13, current detection circuit 14, multiplier 15, square-wave signal generation circuit 16, Current Control gain adjustment circuit 17.These inscapes constitute Voltage loop circuit 6a, current loop circuit 6b and gain optimization circuit 6c.To Voltage loop circuit 6a feedback output voltage V o.Voltage loop circuit 6a produces pwm signal PS according to its output voltage V o.Feed back the electric current I that in inductor 4, flows to current loop circuit 6b.Current loop circuit 6b carries out phase lead compensation with this electric current I.Gain optimization circuit 6c adjusts Current Control gain automatically for the gain that makes electric current loop becomes to optimum value (being 1 in the present embodiment).

Differential amplifier circuit 10 is circuit that the output voltage V o to Switching Power Supply 1 detects, and possesses differential amplifier 10a, direct voltage source 10b, resistance 10c～10e and capacitor 10f.On the non-counter-rotating input terminal of differential amplifier 10a, be connected with DC current source 10b, to this terminal input target voltage Vref.Resistance 10c, to an end input and output voltage Vo, the other end is connected with resistance 10d.The other end ground connection of resistance 10d.The counter-rotating input terminal of differential amplifier 10a is connected on the node between resistance 10c and the resistance 10d, the voltage after the input of counter-rotating input terminal is with resistance 10c and resistance 10d pressure-dividing output voltage Vo.The lead-out terminal of differential amplifier 10a then is connected with the counter-rotating input terminal with capacitor 10f by the resistance 10e that is connected in series on this lead-out terminal.Differential amplifier circuit 10 is with the multiplication factor amplification output voltage V o of regulation and the differential voltage between the target voltage Vref, output voltage signal VS (with reference to Fig. 2 (a)).This voltage signal VS reflection output voltage V o.Below, VS is called voltage detection signal.The multiplication factor of differential amplifier circuit 10, being the ratio multiplication factor of available (resistance value of the resistance value of resistance 10e/resistance 10c) expression in high-frequency region, then is the integration multiplication factor of available (resistance value of the electric capacity of 1/[j ω * capacitor 10f * resistance 10c]) expression in low frequency region.

Produce the square-wave signal RS of circuit 16 and take advantage of from the voltage detection signal VS of differential amplifier circuit 10, from square-wave signal to addometer 11 input and calculate signal PIS from the gain of multiplier 15.Addometer 11 takes advantage of square-wave signal RS and gain the reverse signal of calculating signal PIS to be added on the voltage detection signal VS, produces control signal CS.

Ramp signal produces circuit 12, produces ramp signal RPS.The voltage level of ramp signal RPS is made replying to the rising edge of the ON signal of pwm signal PS and is reset to 0V, increases from 0V with constant increment rate.The amplitude of this ramp signal RPS for example is 1V.

Comparator 13 is to produce the drive signal be used for driving FET2,3 pwm signal to produce mechanism.To the non-counter-rotating input terminal input of comparator 13 control signal CS, produce the ramp signal RPS of circuit 12 from ramp signal to the input of counter-rotating input terminal from addometer 11.13 couples of ramp signal RPS of comparator and control signal CS compare, and just export high signal at ramp signal RPS during less than control signal CS, just export low signal when ramp signal RPS has surpassed control signal CS.The signal that is made of this high signal and low signal is exactly to be used for FET2,3 is carried out the pwm signal PS (with reference to Fig. 2 (c)) that switch is controlled.The upward period of high signal is periodic, but the downward period of high signal then changes with control signal CS is corresponding.The frequency of this pwm signal PS is exactly that switching frequency (for example, is number 100k～1MHz).

Voltage loop circuit 6a produces circuit 12 and comparator 13 constitutes by this differential amplifier circuit 10, addometer 11, ramp signal, produces pwm signal PS according to output voltage V o, makes the dividing potential drop of output voltage V o become and is target voltage Vref.As mentioned above,, deduct from the gain of current loop circuit 6b and take advantage of calculation current detection signal PIS, simultaneously, add square-wave signal RS (as described later) from gain optimization circuit 6c for the voltage detection signal VS corresponding with output voltage V o.

Current detection circuit 14 all will detect the electric current I that flows in (each switch periods in other words) in inductor 4 before low side FET3 becomes to the end during each of ON.Current detection circuit 14 comprises capacitor, through making during constant and the proportional electric current of both end voltage (drain voltage) of the ON resistance (resistance between drain electrode and source electrode) of low side FET3 is given this capacitor charging (integration).Then, current detection circuit 14, before the end during the ON of low side FET3, the value after the electric current equalization of charging making (magnitude of voltage of capacitor) is exported as current detection signal IS.The value of this current detection signal IS, remain to before the end during the Next ON of low side FET3 always, be utilized to determine the downward period (as a result of, also determining pulsewidth and the time ratio of pwm signal PS) of the Next high signal of pwm signal PS.Incidentally, why will detect before finishing during the ON of low side FET3, be because be variable during the ON of high-end FET2, so even if when elongated, also can positively carry out current detecting during the ON of high-end FET2.

To multiplier 15 input from the current detection signal IS of current detection circuit 14 with from the voltage signal of Current Control gain adjustment circuit 17, i.e. Current Control gain signal.The level of this Current Control gain signal and the employed gain of the control of electric current loop, i.e. Current Control gain Kamp equates that the output voltage PIS of multiplier 15 equates with the product of current detection signal IS and Current Control gain signal.That is, multiplier 15 multiply by Current Control gain Kamp on current detection signal IS, produce output signal PIS.Below, this PIS is called gain takes advantage of the calculation current detection signal.

In addition, the broken line of Fig. 2 (b), expression be to be multiplied by the voltage that obtains behind the Current Control gain Kamp with the proportional voltage of electric current I that in inductor 4, flows.The size of calculating current detection signal PIS is taken advantage of in gain, is the value that goes out from the voltage detecting of this polyline shaped in each switch periods.In Fig. 2 (b), with the various values of circle and box indicating PIS signal.The rising of circle and square-wave signal RS is synchronous, and the decline of square frame and square-wave signal is synchronous.

Current loop circuit 6b produces circuit 12 by this current detection circuit 14, multiplier 15, addometer 11, ramp signal and comparator 13 constitutes, with the corresponding phase lead compensation that carries out of electric current I that flows in inductor 4.The LC filtering that phase lead compensation inductor 4 and the capacitor 5 of phase lead compensation by control model CS forms is encased inside the phase delay of generation.The employed Current Control gain of this current loop circuit 6b Kamp is adjusted in gain optimization circuit 6c automatically, makes the gain of current loop circuit 6b become 1.The gain of current loop circuit 6b is 1 to be meant that bit phase delay is by the compensation of fullest.To describe in detail in the back about this point.

Below, with reference to Fig. 3～Fig. 9, gain and the Current Control gain Kamp of current loop circuit 6b is described.Current loop circuit 6b can be with block representation shown in Figure 3.In Fig. 3, Δ VS is the variable quantity of the output (voltage detection signal VS) of differential amplifier circuit 10, Δ RS is the variable quantity that square-wave signal produces the output (square-wave signal RS) of circuit 16, Δ CS is the variable quantity of the output (control signal CS) of addometer 11, Δ D is the variable quantity of time ratio D of the output (pwm signal PS) of comparator 13, Δ I is the variable quantity of the electric current I that flows in inductor 4, and Δ PIS is the variable quantity of the output (gain is taken advantage of and calculated current detection signal PIS) of multiplier 15.The time ratio D of pwm signal is the ratio during the ON of the high-end FET2 that occupied in 1 cycle of pwm signal PS, reflection be pulsewidth in 1 cycle of pwm signal PS.Time ratio D is called as duty (duty) ratio.Because current detection circuit 14 all will detect electric current I in each switch periods, so can reflect the electric current I that before 1 switch periods of present calculation, inductor 4, flows, time ratio D (pulsewidth that therefore, also reflects pwm signal PS) in present switch periods.That is what, current loop circuit 6b can be approximated to be feedback is the accumulation of 1 switch periods hysteresis of time ratio D.The transfer function Pc1 of current loop circuit 6b can use following formula (1) expression, obtains formula (2) after formula (1) is launched.

$\mathrm{Pcl}=\frac{\mathrm{\&Delta;D}}{\mathrm{\&Delta;VS}}=\frac{\mathrm{<figure-callout\; id="1"\; label="a"\; filenames="A20051011696700351.png,A20051011696700451.png"\; state="\{\{state\}\}">a</figure-callout>}}{1+a\&CenterDot;\mathrm{ki}\&CenterDot;k\&CenterDot;\frac{z^{-1}}{1-z^{-1}}}---\left(1\right)$

$=\frac{a\&CenterDot;(1-z^{-1})}{1-(1-a\&CenterDot;\mathrm{ki}\&CenterDot;k)\&CenterDot;z^{-1}}---\left(2\right)$

Wherein, $a=\frac{1}{A},$ ki＝Kamp·Ron， $k=\frac{\mathrm{Vi}}{L\&CenterDot;\mathrm{Fsw}}$

A is the amplitude of ramp signal RPS, and Kamp is the Current Control gain, and Ron is the resistance value of the ON resistance of low side FET3, and Vi is the input voltage of DC/DC transducer 1, and L is the inductance of inductor 4, and Fsw is the switching frequency of DC/DC transducer 1.Multiplication coefficient a is the inverse of A, equals the time ratio D of pwm signal PS and the ratio of the size of control signal CS, promptly equates with D/CS.Akik is the gain of current loop circuit 6b.Formula (2) is an expression formula of representing 1 time IIR (infinite impulse response infinite impulse response) high pass filter, and the expression position is mutually leading.The oscillating condition of this IIR high pass filter, available formula shown below (3) expression.

|1-a·ki·k|＞1 (3)

By formula (3) as can be known akik become and greatly then can vibrate than 2.In addition, akik becomes 0, by formula (2) as can be known Pc1 just will become for a (steady state value), just can not get the leading effect of phase place that realizes by this IIR high pass filter.Gain characteristic and the phase characteristic of the transfer function Pc1 of 1,0.5,1.5 o'clock current loop circuit 6b in Fig. 4～6, have been represented the value of akik is decided to be here.The characteristic of the transfer function the when curve representation of Fig. 4 gains akik=1 in the electric current loop of Fig. 3, (a) expression gain characteristic, (b) expression phase characteristic.The characteristic of transfer function when the curve representation of Fig. 5 gains akik=0.5 in the electric current loop of Fig. 3, (a) expression gain characteristic, (b) expression phase characteristic.The characteristic of the transfer function when gaining akik=1.5 in the electric current loop of curve representation Fig. 3 of Fig. 6, (a) expression gain characteristic, (b) expression phase characteristic.In addition, in the figure of expression gain characteristic, the longitudinal axis is gain [dB], and transverse axis is frequency [Hz].In addition, the expression phase characteristic figure in, the longitudinal axis be phase place [°], transverse axis is frequency [Hz].

As shown in Figure 4, when akik=1, in high-frequency region, gain characteristic and phase characteristic all have surplus, can obtain the leading effect of sufficient phase place, and make the control system stabilisation.But, as shown in Figure 5, when akik=0.5, at high-frequency region, phase margin deficiency (with reference to the phase characteristic in the circle of the chain line of Fig. 5 (b)), the leading effect of phase place reduces.In addition, as shown in Figure 6, when akik=1.5, at high-frequency region, gain margin deficiency (with reference to the gain characteristic in the circle of the chain line of Fig. 6 (a)), the change of output voltage increases, and it is unstable that control system becomes.So, bring into play the leading effect of sufficient phase place in order to make current loop circuit 6b, and to make control system stabilisation (and then, prevent produce vibration), the MIN condition of gain akik of current loop circuit 6b be to satisfy following formula (4).

0.5＜a·ki·k＜1.5 (4)

Satisfying formula (4) is MIN condition, and the gain akik of the best that can obtain the stabilisation of leading effect of sufficient phase place and control is 1.So gain optimization circuit 6c will make gain akik the best of current loop circuit 6b turn to 1 control.For this reason, in gain optimization circuit 6c, will inject the square wave of 1/2 frequency with switching frequency Fsw (below, be called " 1/2 switching frequency ") to Δ VS.After injecting square wave to Δ VS, (therefore the pulsewidth of pwm signal PS will change, time, ratio D also will change), (therefore, take advantage of in gain calculate among the current detection signal PIS too) will produce pulsation with 1/2 switching frequency in the electric current I that flows in inductor 4.In gain optimization circuit 6c, utilize this pulsation, make the gain aik optimization of electric current loop electric current 6b.

Transfer function G between Δ CS and the Δ PIS, available formula shown below (5) expression.In Δ CS, injected the square wave of 1/2 frequency with switching frequency Fsw.When being directed to this frequency, the z in the formula (5) then ^-1, as shown in Equation (6), will become-1.Therefore, when having injected the square wave of 1/2 switching frequency in Δ CS, transfer function G becomes formula (7).This formulate is according to the square wave that injects 1/2 frequency with switching frequency in Δ CS, and how Δ PIS can change actually.

$G=\frac{\mathrm{\&Delta;PIS}}{\mathrm{\&Delta;CS}}=a\&CenterDot;\mathrm{ki}\&CenterDot;k\&CenterDot;\frac{z^{-1}}{1-z^{-1}}=a\&CenterDot;\mathrm{Kamp}\&CenterDot;\mathrm{Ron}\&CenterDot;k\&CenterDot;\frac{z^{-1}}{1-z^{-1}}---\left(5\right)$

z ^-1＝-1 (6)

$G=-\frac{1}{2}\&CenterDot;a\&CenterDot;\mathrm{ki}\&CenterDot;k=-\frac{1}{2}\&CenterDot;a\&CenterDot;\mathrm{Kamp}\&CenterDot;\mathrm{Ron}\&CenterDot;k---\left(7\right)$

The curve representation of Fig. 7 the gain akik of the current loop circuit 6b in the formula (7) and the relation between the transfer function G.As shown in Figure 7, want to make gain akik to become 1, shown in the just necessary formula described as follows (8), transfer function G is become be-1/2.With formula (8) distortion, just obtain the formula shown in the formula (9).On the other hand, to calculate coefficient a be time ratio D and the ratio of control signal CS owing to take advantage of, so Δ D as shown in Equation (10), is called Δ CS be multiply by value behind the calculation coefficient a.Therefore, set up to the relation of formula (11) from formula (9) and (10).Make this formula (11) distortion, obtain formula (12).Promptly, 1/2 frequency with switching frequency Fsw is pulsed (promptly, in each switch periods, all to change) Δ PIS/ Δ D become the negative value of the inverse of taking advantage of 2 times value calculating coefficient a, then transfer function G becomes-1/2, the gain akik of current loop circuit 6b becomes 1 of optimum value.

$G=\frac{\mathrm{\&Delta;PIS}}{\mathrm{\&Delta;CS}}=-\frac{1}{2}---\left(8\right)$

$\mathrm{\&Delta;PIS}=-\frac{1}{2}\&CenterDot;\mathrm{\&Delta;CS}---\left(9\right)$

ΔD＝a·ΔCS (10)

$\mathrm{\&Delta;PIS}=-\frac{1}{2a}\&CenterDot;\mathrm{\&Delta;D}---\left(11\right)$

$\frac{\mathrm{\&Delta;PIS}}{\mathrm{\&Delta;D}}=-\frac{1}{2a}---\left(12\right)$

Satisfy formula (12) for Kamp that Current Control is gained adjusts to, gain optimization circuit 6c just become possess multiplier 15, square-wave signal produces circuit 16 and the structure of Current Control gain adjustment circuit 17.

Fig. 8 is used for illustrating that gain takes advantage of the time diagram of variation delta D of the time ratio of the variation delta PIS that calculates current detection signal and pwm signal, (a) be the signal that to multiply each other and to obtain with the proportional voltage of inductor current I and Current Control gain Kamp, (b) be square-wave signal RS, (c) be pwm signal PS, (d) be that calculation current detection signal PIS is taken advantage of in gain, (e) be the time ratio D of pwm signal.In Fig. 8 (a), also show that with circle and square frame being illustrated in the gain of upgrading in each switch periods takes advantage of the value of calculating current detection signal.

Square-wave signal produces circuit 16, produces the square-wave signal RS (with reference to Fig. 8 (b)) of 1/2 frequency with switching frequency Fsw.This square-wave signal RS has 50% time ratio (duty ratio) and minimum amplitude voltage (for example, the amplitude of 10mV).Owing to will inject this square-wave signal RS to the voltage detection signal VS of the output of differential amplifier circuit 10, impact for the downward period during the ON of pwm signal PS by addometer 11.During the height of square-wave signal RS, the ON period P W_A of pwm signal PS is elongated, between the lowstand of square-wave signal RS in the ON period P W_B of pwm signal PS shorten (with reference to Fig. 8 (b), (c)).Δ PW in Fig. 8 (c), expression results from the variable quantity of pulsewidth of pwm signal of square-wave signal RS.The change of the pulsewidth of the pwm signal PS that produces by square-wave signal RS, the electric current I that flows in inductor 4 change, gain are taken advantage of and are calculated current detection signal PIS just will pulse with 1/2 frequency of switching frequency (with reference to Fig. 8 (d)).This signal PIS is to make the mutual square wave repeatedly that rises and descend in each switch periods.Therefore, it is that gain between lowstand the time is taken advantage of in the voltage of calculating current detection signal PIS and will be produced poor (with reference to Fig. 8 (a) and (b), (d)) that the voltage of calculating current detection signal PIS and square-wave signal RS are taken advantage of in the gain in the time of during square-wave signal RS is height.This difference is Δ PIS, is the variable quantity that each switch periods of calculating current detection signal PIS is taken advantage of in gain.

In addition, square-wave signal RS is that the ON period P W_A of the pwm signal PS during the height time and square-wave signal RS are that difference between the ON period P W_B of the pwm signal PS between lowstand the time is exactly Δ PW, the variable quantity of each switch periods of the pulsewidth of its expression pwm signal PS.Be accompanied by the variation of pulsewidth, the time ratio D of pwm signal also will be with 1/2 frequency of switching frequency pulse (with reference to Fig. 8 (b), (c), (e)).Herein, Δ D express time ratio D is at the variable quantity of each switch periods.In addition, in Fig. 8 (e), though Δ D is constant, because when the target voltage change of output voltage V o etc., time ratio D can be because of slowly change of PWM control, so Δ D is not invariable forever.

Below, with reference to Fig. 9 and Figure 10, the formation and the action of Current Control gain adjustment circuit 17 are described.Fig. 9 is the detailed circuit diagram of Current Control gain adjustment circuit 17.Figure 10 is the time diagram that is used for illustrating the action of Current Control gain adjustment circuit 17, (a) be square-wave signal, (b) be pwm signal, (c) being maximum pwm signal, (d) is that the calculation current detection signal is taken advantage of in gain, (e) is the signal that adds, (f) be the time rate signal, (g) being first clock signal, (h) is the second clock signal, (i) is the 3rd clock signal.

Current Control gain adjustment circuit 17 is adjusted into the Current Control Kamp that gains to make it satisfy formula (12).Δ PIS in the formula (12), as shown in the formula (13) expression, it is poor (with reference to Figure 10 (a), (d)) that the mean value of the magnitude of voltage (PIS_B) of calculating signal PIS is taken advantage of in gain between lowstand the time that the mean value of the magnitude of voltage (PIS_A) of calculating signal PIS and square-wave signal RS are taken advantage of in the gain when being equivalent to square-wave signal RS and being during the height.

ΔPIS＝ PIS_A- PIS_B (13)

In addition, the Δ D of formula (12), shown in (14), the mean value of the time ratio D_A of the pwm signal PS when being equivalent to square-wave signal RS and being during the height and square-wave signal RS are poor (with reference to Figure 10 (a) and (b)) of mean value of the time ratio D_B of the pwm signal RS between lowstand the time.Wherein, time ratio D_A reflection be that square-wave signal RS is (PW_A) during the ON of the pwm signal RS during the height time, time ratio D_B reflection be that square-wave signal RS is (PW_B) during the ON of the pwm signal RS between lowstand the time.

ΔD＝ D_A- D_B (14)

Formula (13) and (14) substitution formula (11), then obtain the relation of formula (15), deformation formula (15) obtains formula (16).Obtain formula (17) as remove the mark (going up ledger line) of averaging from formula (16).

$\stackrel{\&OverBar;}{\mathrm{PIS}\_A}-\stackrel{\&OverBar;}{\mathrm{PIS}\_B}=-\frac{1}{2a}(\stackrel{\&OverBar;}{D\_A}-\stackrel{\&OverBar;}{D\_B})---\left(15\right)$

$\frac{1}{2a}\&CenterDot;\stackrel{\&OverBar;}{D\_A}+\stackrel{\&OverBar;}{\mathrm{PIS}\_A}=\frac{1}{2a}\&CenterDot;\stackrel{\&OverBar;}{D\_B}+\stackrel{\&OverBar;}{\mathrm{PIS}\_B}---\left(16\right)$

$\frac{1}{2a}\&CenterDot;D\_A+\mathrm{PIS}\_A=\frac{1}{2a}\&CenterDot;D\_B+\mathrm{PIS}\_B---\left(17\right)$

Current Control gain adjustment circuit 17 is adjusted Current Control gain Kamp, makes and satisfies formula (17).Specifically, in each control ring, adjust Current Control gain Kamp, make the left side of formula (17) and the difference on the right diminish, the frequency of overlapping this control ring is with regard to satisfiable formula (16).

The left side of the table representation formula (17) of Figure 11 and the magnitude relationship between the right and Current Control gain Kamp increase/subtract.At first, just as shown in the row 101 of Figure 11, (1/2a) D_A on the left side of formula (17) is greater than (1/2a) D_B on the right, and the PIS_A on the left side is less than (1/2a) D_B on the right, the example that consequently exists the left side to equate with the right.At this moment, because current loop control is stable, the gain of electric current loop is optimization, so do not need to adjust Current Control gain Kamp.But shown in row 102, (1/2a) D_A of on the left side is big and PIS_A is little, and (1/2a) D_B on the right is little and PIS_B hour, and the left side of formula (17) just becomes bigger than the right.This means that then the left side of formula (17) will become bigger than the right when the PIS_B on the right PIS_B when stablizing reduces.Want to make the left side to equate with the right, Current Control gain Kamp is increased, the ratio PIS_A that PIS_B is become is big fully.On the other hand, shown in row 103, (1/2a) D_A of on the left side is big and PIS_A is little, and when the little and PIS_B of (1/2a) D_B on the right is big especially, the right of formula (17) will become bigger than the left side.This means that the right of formula (17) will become bigger than the left side when the PIS_B on the right PIS_B when stablizing further increases.Want to make the left side to equate, just must reduce Current Control gain Kamp, make PIS_B near PIS_A with the right.

Secondly, shown in row 104, (1/2a) D_A on the left side that considers formula (17) is littler and the PIS_A left side is bigger than the PIS_B on the right than (1/2a) D_B on the right, the example that consequently exists the left side of formula (17) to equate with the right.At this moment, because current loop control is also stable, the gain of electric current loop is optimization also, so do not need to adjust the Current Control Kamp that gains.But shown in row 105, (1/2a) D_A of on the left side is little and PIS_A is little, and (1/2a) D_B on the right is big and PIS_B hour, and the right side, limit of formula (17) will become big.This means that then the right of formula (17) will become bigger than the left side when the PIS_A on the left side PIS_A when stablizing reduces.Want to make the left side to equate with the right, Current Control gain Kamp is increased, the ratio PIS_B that PIS_A is become is big fully.On the other hand, shown in row 106, (1/2a) D_A of on the left side is little and PIS_A is big especially, and (1/2a) D_B on the right is big and PIS_B hour, and it is big that the left side of formula (17) just becomes.When this meaning further increased as the PIS_A on the left side PIS_A when stablizing, the left side of formula (17) just became bigger than the right.Want to make the left side to equate, just must reduce Current Control gain Kamp, make PIS_A near PIS_B with the right.

So Current Control gain adjustment circuit 17 will detect the left side that is equivalent to formula (17) and the value on the right respectively, and these values are compared.In addition, Current Control gain adjustment circuit 17 also will be distinguished (1/2a) D_A on the left side of detection formula (17) and (1/2a) D_B on the right, and both are compared.Then, according to these 2 comparative results, Current Control gain adjustment circuit 17 according to relation shown in Figure 11, makes Current Control gain Kamp increase/subtract.In order to realize such action, as shown in Figure 9, Current Control gain adjustment circuit 17 possesses: direct voltage source 17a, switch 17b and 17c, addometer 17d, Voltage-controlled Current Source 17e and 17f, capacitor 17g and 17h, reset switch 17i and 17j, sampling hold circuit 17k, 17l, 17m and 17n, comparator 17o and 17p, increment depreciation counter 17q and D/A converter 17r.Since make the left side and the right of formula (17) become equally each each ± 1 ground increases/subtracts the Current Control Kamp that gains, so can satisfy the formula (16) that makes formula (17) equalization.

Multiplier 15 is connected on the switch 17b, and takes advantage of calculation current detection signal PIS to its input gain, and switch 17b carries out ON/OFF (with reference to (c) of Figure 10) according to maximum pwm signal PS0.Maximum pwm signal PS0 has the frequency identical with pwm signal PS, all is high signal during corresponding with the maximum Dmax of the regulation of time ratio, then is low signal in during in addition.Switch 17b during maximum pwm signal PS0 is height the time output gain take advantage of the voltage of calculating current detection signal PIS, be output 0V between lowstand the time at maximum pwm signal PS0.

DC current source 17a is connected on the switch 17c.DC current source 17a produces the voltage except that the value of the maximum Dmax of time ratio with 2a.Switch 17c carries out ON/OFF (with reference to (b) of Figure 10) according to pwm signal PS.Switch 17c, in the time of during pwm signal PS is height, the voltage that output produces with DC current source 17a is between lowstand the time at pwm signal PS, output 0V.To be called time rate signal SD (with reference to Figure 10 (f)) from the signal of this switch 17c output.Area during square-wave signal RS is height within each area of the oblique line part of the square shape of the time of Figure 10 (f) rate signal SD is equivalent to (1/2a) D_A on the left side of formula (17), and the area between the lowstand of square-wave signal RS then is equivalent to (1/2a) D_B on the right.

On addometer 17d, be connected with switch 17b and switch 17c, therefore, can import from the signal of switch 17b output and the signal of exporting from switch 17c (time rate signal SD).Addometer 17d implements 2 signals being exported and adds, and exports the signal SI (with reference to Figure 10 (e)) that adds.Within each area of the part of the step shape that draws oblique line of the signal SI that adds, square-wave signal RS is the area during the height, PIS_A+ (1/2a) D_A that is equivalent to formula (17) left side, square-wave signal RS are PIS_B+ (1/2a) D_B that the area between lowstand then is equivalent to the right.

Voltage-controlled Current Source 17e, 17f are output and the current source of the proportional electric current of voltage imported.Voltage-controlled Current Source 17e accepts the signal SI that adds from addometer 17d, the proportional electric current of signal SI of exporting and add.Voltage-controlled Current Source 17f accepts the time rate signal SD from switch 17c, output and the proportional voltage of time rate signal SD.

Connect Voltage-controlled Current Source 17e, other end ground connection on the end of capacitor 17g.In addition, on capacitor 17g, also be parallel with reset switch 17i.Reset switch 17i carries out ON/OFF according to first clock signal clk 1.First clock signal clk 1 is believed before high signal rises (that is, in each switch periods) from low at each pwm signal PS, all the high signal of moment property ground output.Therefore, reset switch 17i became before high signal rises from low signal at each pwm signal PS in a flash and is ON, then was OFF during in addition always.Capacitor 17g, when reset switch 17i was OFF, charging was from the electric current of Voltage-controlled Current Source 17e output, the current discharge that this is charged during for ON at reset switch 17i.Therefore, the voltage of the end of capacitor 17g, become for the proportional value of area of the oblique line part of the signal SI that adds of Figure 10 (e) after, each pwm signal PS from low signal before high signal rises, all to become and be 0V.

Be connected with Voltage-controlled Current Source 17f on the end of capacitor 17h, other end ground connection.In addition, on capacitor 17h, also be connected in parallel to reset switch 17j.Reset switch 17j also carries out ON/OFF according to first clock signal clk 1.Therefore, in reset switch 17j, all became before high signal rises from low signal at each pwm signal PS in a flash and to be ON, then be OFF during in addition always.Capacitor 17g, when reset switch 17j was OFF, charging was from the electric current of Voltage-controlled Current Source 17f output, the current discharge that this is charged during for ON at reset switch 17j.Therefore, the voltage of the end of capacitor 17h, after the proportional value of area that becomes with the oblique line part of the signal SD that adds of Figure 10 (f), each pwm signal PS from low signal before high signal rises, all to become and be 0V.

On sampling hold circuit 17k, be connected with the end of capacitor 17g, and import the voltage of this end.In addition, also to sampling hold circuit 17k, input second clock signal CLK2 (with reference to Figure 10 (h)).Second clock signal CLK2 constitute each square-wave signal RS from high signal before low signal descends and also first clock signal clk 1 be the high signal of (that is in 2 times cycle) moment property generation before the high signal in each switch periods.Receive the high signal of second clock signal CLK2 as sampling hold circuit 17k after, just the voltage of the end of capacitor 17g is sampled, until keep this magnitude of voltage till receiving the Next high signal of second clock signal CLK2.Therefore, just can keep on sampling hold circuit 17k with square-wave signal RS is the proportional voltage of area (with reference to Figure 10 (a), (e)) of the oblique line part of the signal SI that adds during the height time.The value that this kept is equivalent to the value on the left side of formula (17).

On sampling hold circuit 17l, be connected with the end of capacitor 17g, and import the voltage of this end.In addition, also to sampling hold circuit 17l, import the 3rd clock signal clk 3 (with reference to Figure 10 (i)).The 3rd clock signal clk 3 constitute each square-wave signal RS from high signal before low signal descends and first clock signal clk 1 be (that is in 2 times cycle) high signal of moment property generation before the high signal in each switch periods.When sampling hold circuit 17l receives the high signal of the 3rd clock signal clk 3, just the voltage of the end of capacitor 17g is sampled, until keep this voltage till receiving the Next high signal of the 3rd clock signal clk 3.Therefore, on sampling hold circuit 17l, just can keep and square-wave signal RS is the proportional voltage of area (with reference to Figure 10 (a), (e)) of the oblique line part of the signal SI that adds between lowstand the time.The value that this kept is equivalent to the value on the right of formula (17).

On sampling hold circuit 17m, be connected with the end of capacitor 17h, and import the voltage of this end.In addition, also to sampling hold circuit 17m, input second clock signal CLK2 (with reference to Figure 10 (h)).When sampling hold circuit 17m receives the high signal of second clock signal CLK2, just the voltage of the end of capacitor 17h is sampled, until keep this voltage till receiving the Next high signal of second clock signal CLK2.Therefore, just can keep on sampling hold circuit 17m with square-wave signal RS is the proportional voltage of area (with reference to Figure 10 (a), (f)) of the oblique line part of the time rate signal SD during the height time.The value that this kept is equivalent to (1/2a) D_A on the left side of formula (17).

On sampling hold circuit 17n, be connected with the end of capacitor 17h, and import the voltage of this end.In addition, also to sampling hold circuit 17n, import the 3rd clock signal clk 3 (with reference to Figure 10 (i)).When sampling hold circuit 17n receives the high signal of the 3rd clock signal clk 3, just the voltage of the end of capacitor 17h is sampled, until keep this voltage till receiving the next high signal of the 3rd clock signal clk 3.Therefore, on sampling hold circuit 17n, just can keep and square-wave signal RS is the proportional voltage of area (with reference to Figure 10 (a), (f)) of the oblique line part of the time rate signal SD between lowstand the time.The value that this kept is equivalent to (1/2a) D_B on the right of formula (17).

To the retention value of the non-counter-rotating input terminal input sample holding circuit 17k of comparator 17o, to the retention value of counter-rotating input terminal input sample holding circuit 17l.Comparator 17o, the retention value of sampling hold circuit 17k and the retention value of sampling hold circuit 17l are compared, when the retention value of sampling hold circuit 17k is bigger than the retention value of sampling hold circuit 17l, just export high signal, when the retention value of sampling hold circuit 17l is bigger than the retention value of sampling hold circuit 17k, just export low signal.By the signal that this high signal and low signal constitute, be exactly the first comparison signal CP1, the left side of representation formula (17) and the size between the right result relatively.That is, the first comparison signal CP1 is high signal on the left side of formula (17) when bigger than the right, is low signal when bigger than the left side on the right.

To the retention value of the non-counter-rotating input terminal input sample holding circuit 17m of comparator 17p, to the retention value of counter-rotating input terminal input sample holding circuit 17n.Comparator 17p, the retention value of sampling hold circuit 17m and the retention value of sampling hold circuit 17n are compared, when the retention value of sampling hold circuit 17m is bigger than the retention value of sampling hold circuit 17n, just export high signal, when the retention value of sampling hold circuit 17n is bigger than the retention value of sampling hold circuit 17m, just export low signal.By the signal that this high signal and low signal constitute, be exactly the second comparison signal CP2, the result relatively of the size between (1/2a) D_B on (1/2a) D_A on the left side of representation formula (17) and the right.That is, the second comparison signal CP2 is high signal at (1/2a) D_A when D_B is big than (1/2a), is low signal at (1/2a) D_B when D_A is big than (1/2a).

To increment depreciation counter 17q input from the first comparison signal CP1 of comparator 17o with from the second comparison signal CP2 of the second comparator 17p.In addition, also import first clock signal clk 1 to increment depreciation counter 17q.Then, increment depreciation counter 17q, when having received the high signal of first clock signal clk 1,, increase or reduce Current Control gain Kamp according to relation shown in Figure 11 just according to high signal/low signal of the first comparison signal CP1 and high signal/low signal of the second comparison signal CP2.Specifically, in increment depreciation counter 17q, at the first comparison signal CP1 is that the high signal and the second comparison signal CP2 are high signal, perhaps the first comparison signal CP1 is that the low signal and the second comparison signal CP2 are when being low signal, Current Control gain Kamp is increased, at the first comparison signal CP1 is that the high signal and the second comparison signal CP2 are that the low signal or the first comparison signal CP1 are the low signal and the second comparison signal CP2 when being high signal, and Current Control gain Kamp is reduced.Initial value as Current Control gain Kamp is set to smaller value.Therefore, Current Control gain Kamp usually, the limit to increase or minimizing, the limit along with the gain akik of electric current loop electric current 6b to 1 close, constantly become big value (with reference to Fig. 2 (e), (f)).From the Current Control gain Kamp of increment depreciation counter 17q output is digital value, once just increases 1 or subtract 1 just whenever first clock signal clk 1 rises.

In addition, the Kamp upper and lower bound ground that can not surpass the output valve of increment depreciation counter 17q increases and decreases.For example, when increment depreciation counter 17q was output as 9bit, if increment depreciation counter 17q is output as 0, even then when Kamp reduces according to Figure 11, it is constant that output also can remain 0 original state.Otherwise if increment depreciation counter 17q is output as 511, even when then Kamp increases according to Figure 11, it is 511 constant that output also can keep.

D/A converter 17r accepts the Current Control gain Kamp (for example, 0～511) of digital value from increment depreciation counter 17q, and converts the analogue value (for example, 89mV～600mV) to.Then, D/A converter 17r is to the Current Control gain Kamp of multiplier 15 these analogues value of output.In this case, 89mV just becomes the lower limit for output, and 600mV just becomes the upper limit for output.Thus, can become the Current Control gain signal to the output voltage of D/A converter 17r and supply to simulation multiplier 15.The output voltage of multiplier 15 promptly, just can be taken advantage of gain and calculate electric current inspection signal PIS for toward Current Control gain adjustment circuit 17, uses in the control of Current Control gain Kamp.

As mentioned above, gain optimization circuit 6c has formed loop by multiplier 15 and Current Control gain adjustment circuit 17, and adjusts Current Control gain Kamp automatically, makes the relation of formula (12) set up, and makes gain akik the best of electric current loop electric current 6b turn to 1.If the relation of formula (12) is set up, then transfer function G just will become and be-1/2.The gain akik of electric current loop electric current 6b will converge to 1.Therefore, even if the resistance value of FET2,3 ON resistance, owing to the fluctuation of element or variations in temperature etc. change, the gain of electric current loop is optimization automatically also.Consequently when can obtaining the leading effect of phase place that produces by electric current loop fully, can also make the control system stabilisation.

In addition, gain optimization circuit 6c becomes by the frequency that makes square-wave signal RS and to be 1/2 of switching frequency, and becomes to very simply constituting.Have again,,, in addition, also do not need the outer parts that install on the controller IC 6 so do not need jumbo capacitor because Current Control gain adjustment circuit 17 usefulness digital values are adjusted Current Control gain Kamp.Therefore, controller IC 6 can miniaturization.

Below, with reference to Fig. 1 and Fig. 9, the action of DC/DC transducer 1 and controller IC 6 is described.In addition, in the action specification of controller IC 6, be with reference to the time diagram of Fig. 2 and Figure 10.

After having imported input voltage Vi to DC/DC transducer 1, DC/DC transducer 1 just makes FET2,3 alternatively carry out ON/OFF with pwm signal PS from controller IC 6 accordingly.In addition, in DC/DC transducer 1, become input voltage Vi equalization in making during the ON of high-end FET2 by means of the smoothing circuit that constitutes by inductor 4 and capacitor 5, produce output voltage V o for pulse output.DC/DC transducer 1 is to controller IC 6 this output voltage V of feedback o.In addition, the electric current I that also in inductor 4, flows to controller IC 6 feedbacks.

Behind feedback output voltage V o, this output voltage V o and target voltage Vref are just by differential amplification.In addition, before each low side FET3 switches to OFF from ON, all to the electric current I that flow in inductor 4 be detected, and be multiplied by Current Control gain Kamp for detected current detection signal IS according to the both end voltage of the ON resistance of low side FET3.Then, controller IC 6 when the voltage signal VS after the differential amplification is added square-wave signal RS, deducts gain and takes advantage of calculation current detection signal PIS (with reference to Fig. 2 (a) and (b), (d)), produces control signal CS.Then, in controller IC 6, control signal CS and ramp signal RPS are compared, produce control signal CS become during less than ramp signal RPS and be high signal, control signal CS surpass ramp signal RPS during become pwm signal PS (with reference to Fig. 2 (c)) for low signal.As mentioned above, calculate current detection signal PIS generation pwm signal PS by adding that by means of current loop control gain is taken advantage of, thus the leading effect of phase place can be obtained, can high-speed responsive.

Current Control gain adjustment circuit 17, gain acceptance in take advantage of calculate current detecting PIS and pwm signal PS in, also produce the voltage that obtains except that the voltage of the maximum Dmax that is equivalent to the time ratio with 2a with direct voltage source 17a.Therefore, can produce by the composition of PIS_A+ (1/2a) D_A on the left side that is equivalent to formula (17) and be equivalent to the signal SI that adds (with reference to Figure 10 (e)) that the composition of PIS_B+ (1/2a) D_B on the right constitutes.Current Control gain adjustment circuit 17, from this adds signal SI, the composition that separates PIS_B+ (1/2a) D_B on the composition of PIS_A+ (1/2a) D_A on the left side and the right, and the magnitude of voltage that each composition is used as numeral kept with sampling hold circuit 17k, 17l respectively.In addition, Current Control gain adjustment circuit 17 also produces by the composition of (1/2a) D_A on the left side that is equivalent to formula (17) and is equivalent to the time rate signal SD (with reference to Figure 10 (f)) that the composition of (1/2a) D_B on the right constitutes.The composition of (1/2a) D_B on the composition of (1/2a) D_A on the separation left side and the right from this time rate signal SD, the magnitude of voltage of each composition being used as numeral keeps with sampling hold circuit 17m, 17n respectively.

Current Control gain adjustment circuit 17 compares the composition (magnitude of voltage) of PIS_A+ (1/2a) D_A and the composition (magnitude of voltage) of PIS_B+ (1/2a) D_B with comparator 17o, produces the first comparison signal CP1 that is made of high signal or low signal.This relatively, as object, the area when area when being equivalent to that square-wave signal RS is high signal and square-wave signal RS are low signal compares with each area of the step-like oblique line part among Figure 10 (e).In addition, Current Control gain adjustment circuit 17 is also used comparator 17p, to the composition (magnitude of voltage) of (1/2a) D_A and (1/2a) composition of D_B (magnitude of voltage) compare, produce the second comparison signal CP2 that constitutes by high signal or low signal.This relatively, as object, the area when area when being equivalent to that square-wave signal RS is high signal and square-wave signal RS are low signal compares with each area of the oblique line part of the square configuration among Figure 10 (f).

Have, Current Control gain adjustment circuit 17 also increases and decreases Current Control gain Kamp with increment depreciation counter 17q according to the first comparison signal CP1 of comparator 17o and the second comparison signal CP2 of comparator 17p again.Then, Current Control gain adjustment circuit 17, the Current Control gain Kamp the Current Control of digital value gain Kamp is varied to the analogue value exports to multiplier 15 as the Current Control gain signal.

Promptly, Current Control gain adjustment circuit 17, detect for gain take advantage of each switch periods of calculating current detection signal PIS variable quantity Δ PIS and be the Δ D of the variable quantity of each switch periods of the time ratio D of pwm signal, and adjustment Current Control gain Kamp, make Δ PIS/ Δ D become and be-1/2a (that is, satisfying formula (12)).Owing to the square-wave signal RS of 1/2 frequency with switching frequency has been added on the voltage signal VS, so the pulsewidth of pwm signal PS (and then, the time ratio) will vibrate with 1/2 switching frequency, with it accordingly, the electric current I that flows in inductor 4 (and then gain is taken advantage of and calculated current detection signal PIS) also will change.At this moment, during RS is height and between between lowstand, although variation has taken place time ratio D, when gain took advantage of calculation current detection signal PIS almost not change, the result can make that Current Control gain Kamp is littler than ideal value.Therefore, Current Control gain adjustment circuit 17 will make Current Control gain Kamp increase.On the other hand.During the height of square-wave signal RS and between between lowstand, when taking advantage of calculation current detection signal PIS to change greatly with the variation of time ratio D than gain, the result can make that Current Control gain Kamp is bigger than ideal value.Therefore, Current Control gain adjustment circuit 17 will reduce Current Control gain Kamp.

Adopt such way, just can adjust Current Control gain Kamp (with reference to Fig. 2 (e)) lentamente, make and take advantage of the transfer function G approaching-1/2 that calculates current detection signal PIS to gain from the control signal CS that contains square-wave signal RS.Along with transfer function G to-1/2 approaching, by the curve chart of Fig. 7 as can be known, the gain akik of electric current loop electric current 6b to 1 near (with reference to Fig. 2 (f)).

Current Control gain Kamp becomes soon and is desirable value (with reference to Fig. 2 (e)), and the gain akik of electric current loop electric current 6b converges on (with reference to Fig. 2 (f)) 1.At this moment, transfer function G will converge on 1/2, take advantage of the transfer function of calculating current detection signal PIS then to converge on-1/2a from pwm signal PS to gain, take advantage of calculation current detection signal PIS transfer function then to converge on-1/2 from control signal CS to gain.Consequently the leading effect of the phase place that obtains by current loop circuit 6b can be brought into play fully, simultaneously, also the control system stabilisation will be made.In addition, even if exist in resistance value the Ron last fluctuation or the variations in temperature of the ON resistance of low side FET3 as element, can adjust the variation of Current Control gain Kamp last trading day value Ron, the gain akik of electric current loop electric current 6b can not change yet yet, and control system can not become yet and is instability.

According to controller IC 6, owing to inject the square-wave signal RS of 1/2 switching frequency to voltage signal VS, and adjust Current Control gain Kamp, make Δ PIS/ Δ D become 1/2a, so can make gain akik the best of electric current loop electric current 6b turn to 1.For this reason, even if when the ON of low side FET3 resistance value Ron change, control system also can be stablized, and can obtain the leading effect of sufficient phase place, can tackle high-speed responsive.Because control system is stabilized, so can also suppress the change of output voltage V o, certainly, the vibrative situation of output voltage V o can not take place.

Have again, according to controller IC, owing to use the Δ PIS and the Δ D that all alternatively rise repeatedly and descend in each switch periods, so that becoming to the mode of-1/2a, Δ PIS/ Δ D controls, even if, also can carry out stable Control current ring so load current results from action on the load L etc. under the situation that each switch periods alternatively increases repeatedly or reduces.Incidentally, when the utilization Switching Power Supply, usually to prevent that temperature from rising to purpose the action cycle property ground of load L is stopped, the frequency that usually makes it to stop is 1/2 of a switching frequency, and the time that makes it to stop to equate with switch periods.In this case, load current just will vibrate with 1/2 switching frequency.

In addition, controller IC 6 is calculated current detection signal PIS and is detected electric current accurately owing to can take advantage of with gain, thus can detection of excessive current, and have nothing to do with the value of FET2,3 ON resistance.Consequently can protect DC-DC transducer 1 to exempt from over-current damage satisfactorily.

Second execution mode

The Switching Power Supply of present embodiment has the formation of adjusting circuit 17 in the DC/DC of first execution mode transducer 1 with Current Control gain adjustment circuit 18 displacement current ride gains.In addition formation, with DC/DC transducer 1 be same.

Figure 12 is the pie graph of Current Control gain adjustment circuit 18.Current Control gain adjustment circuit 18 takes advantage of calculation current detection signal PIS and pwm signal PS to adjust Current Control gain Kamp according to gain.Current Control gain adjustment circuit 18 has A/D converter 18a, digital operational circuit 18b and D/A converter 18c.Present embodiment adopts and uses digital operational circuit 18b, directly calculates the left side of above-mentioned formula (12), and it and the right are compared to adjust Current Control gain Kamp.

Digital operational circuit 18 comprises Δ PIS testing circuit 18d, Δ D testing circuit 18e, removes and calculate circuit 18f, comparison circuit 18g and increment depreciation counter 18h.These circuit 18d～18h is a digital circuit.Δ PIS testing circuit 18d takes advantage of from multiplier 15 gain acceptance ins and calculates current detection signal PIS, asks above-mentioned Δ PIS.Δ D testing circuit 18e accepts pwm signal PS from comparator 13, asks above-mentioned Δ D.Remove and calculate circuit 18f, accept Δ PIS and Δ D, calculate Δ PIS/ Δ D from circuit 18d and 18e.Comparison circuit 18g, Δ PIS/ Δ D that makes this calculating and-1/2a compare, and just export high signal during less than-1/2a at Δ PIS/ Δ D, just export low signal during greater than-1/2a at Δ PIS/ Δ D.Increment depreciation counter 18h increases or reduces Current Control gain Kamp according to the output signal of comparison circuit 18g, make Δ PIS/ Δ D approaching-1/2a.The Kamp of the digital value that D/A converter 18c will determine thus converts the analogue value to, supplies to multiplier 15 as the Current Control gain signal.

As mentioned above, Current Control gain adjustment circuit 18 is owing to slowly adjust Current Control gain Kamp so that satisfy the mode of above-mentioned formula (12), so be that the gain akik of current loop circuit 6b is just near optimum value 1.Therefore, in the present embodiment, can obtain the effect same with first execution mode.

The 3rd execution mode

Figure 13 is the pie graph of the DC/DC transducer of present embodiment.Present embodiment comprises switch element FET2,3 in controller IC 30, do not comprise that with controller IC 6 FET2,3 first execution mode are different on this point.The inscape of the DC/DC transducer of present embodiment, with first execution mode be same.Therefore, present embodiment can obtain the effect same with first execution mode.

Owing in controller IC 30, be equipped with FET2,3,, just can obtain DC/DC transducer 1 as Switching Power Supply so only smoothing circuit 25 is connected on the controller IC 30.Promptly use controller IC 30, just can easily make DC/DC transducer 1.

Though more than embodiments of the present invention are illustrated,, the present invention is not limited to above-mentioned execution mode, can carry out various distortion.

For example, when constituting control device of the present invention, also can realize various mechanisms in the controlling organization by being assembled into program (software) in the microcomputer etc. by digital circuit (hardware).Realize the program of these various mechanisms, the information delivery that medium that sometimes will be by CD-ROM etc. or the Internet etc. carry out circulates, and also circulates with computer with the state that is assembled in the computer sometimes.

In the above-described embodiment, though be that the present invention is applied to the DC/DC transducer,, the present invention also can use in AC/DC transducer or DC/AC transducer.In addition, though in the above-described embodiment the present invention is applied to not have the nonisulated type of transformer and the transducer of voltage-dropping type,, the present invention also can use in the transducer of the insulating properties with transformer, in addition, in the transducer of booster type or buck-boost type, also can use.

In the above-described embodiment, owing to fix between the rising stage of the ON signal used of high-end FET, so will before the end during the ON of each time low side FET, detect inductor current.But the upward period of the ON signal of using at low side FET fixedly the time, just must change the detection time of inductor current, and electric current is detected in the beginning back during the ON of each low side FET.

In the above-described embodiment, directly use the time ratio of drive pulse signal to adjust the Current Control gain, to satisfy above-mentioned formula (12).But, also can directly not use the time ratio of drive pulse signal, and replace other parameter of using reflection time ratio, for example, use the pulsewidth body of drive pulse signal to adjust the Current Control gain, to satisfy formula (12).

Claims (8)

1. the switching power supply control device of a control switching is characterized in that:

Described Switching Power Supply comprises with the switch periods of regulation and the switching frequency of regulation and carries out the switch element of switch and make the smoothing circuit of the output smoothingization of described switch element that this smoothing circuit possesses the inductor that is connected on the described switch element,

Described switching power supply control device possesses:

The output voltage of sense switch power supply produces the voltage detection mechanism of the voltage detection signal corresponding with this output voltage;

In each described switch periods, detect the electric current that in described inductor, flows, produce the current detecting mechanism of the current detection signal corresponding with described electric current;

The square-wave signal of square-wave signal that generation has 1/2 frequency of described switching frequency produces mechanism;

Make described current detection signal multiply by the Current Control gain, produce gain and take advantage of taking advantage of of calculation current detection signal to calculate mechanism;

Make described voltage detection signal add the above square-wave signal, deduct described gain simultaneously and take advantage of the calculation current detection signal, produce the arithmetical organ of control signal;

Generation has the drive pulse signal with the big or small time corresponding ratio of described control signal, supplies with this drive pulse signal to described switch element and produces mechanism with the drive signal that drives described switch element; With

Take advantage of the gain adjusting mechanism of calculating current detection signal and the gain of described time ratio adjustment Current Control according to described gain,

Described drive signal produces mechanism and produces described drive pulse signal, makes Δ D/ Δ CS become constant a,

Described gain adjusting mechanism is adjusted the gain of described Current Control, satisfying Δ PIS/ Δ D=-1/2a,

Wherein, Δ D is the variable quantity of each described switch periods of described time ratio, and Δ CS is the variable quantity of each described switch periods of described control signal, and Δ PIS is the variable quantity that each described switch periods of calculating current detection signal is taken advantage of in described gain.

2. switching power supply control device is by being connected to the switching power supply control device that smoothing circuit constitutes Switching Power Supply, it is characterized in that:

Described smoothing circuit comprises inductor,

Described switching power supply control device possesses:

Carry out switch with the switch periods of regulation and the switching frequency of regulation, must be connected to the switch element on the described inductor;

Detect the output voltage of described Switching Power Supply, produce the voltage detection mechanism of the voltage detection signal corresponding with this output voltage;

In each described switch periods, detect the electric current that in described inductor, flows, produce the current detecting mechanism of the current detection signal corresponding with described electric current;

The square-wave signal of square-wave signal that generation has 1/2 frequency of described switching frequency produces mechanism;

Make described current detection signal multiply by the Current Control gain, produce gain and take advantage of taking advantage of of calculation current detection signal to calculate mechanism;

Make described voltage detection signal add the above square-wave signal, deduct described gain simultaneously and take advantage of the calculation current detection signal, produce the arithmetical organ of control signal;

Generation has the drive pulse signal with the big or small time corresponding ratio of described control signal, supplies with this drive pulse signal to described switch element and produces mechanism with the drive signal that drives described switch element; With

Take advantage of calculation current detection signal and described time ratio to adjust the gain adjusting mechanism of described Current Control gain according to described gain,

Described drive signal produces mechanism and produces described drive pulse signal, makes Δ D/ Δ CS become constant a,

Described gain adjusting mechanism is adjusted the gain of described Current Control, satisfying Δ PIS/ Δ D=-1/2a,

Wherein, Δ D is the variable quantity of each described switch periods of described time ratio, and Δ CS is the variable quantity of each described switch periods of described control signal, and Δ PIS is the variable quantity that each described switch periods of calculating current detection signal is taken advantage of in described gain.

3. switching power supply control device as claimed in claim 1 or 2 is characterized in that:

Described switch element has ON resistance,

Described current sensing means, the voltage at the two ends by detecting described ON resistance detects the electric current that flows in described inductor.

4. switching power supply control device as claimed in claim 1 or 2 is characterized in that:

The calculation current detection signal is taken advantage of in described gain, and in described each switch periods, rise repeatedly alternately and descend,

Described time ratio takes advantage of the rising of calculating current detection signal to reduce synchronously with described gain, takes advantage of the decline of calculating current detection signal to increase synchronously with described gain.

5. switching power supply control device as claimed in claim 1 or 2 is characterized in that:

Described drive signal produces mechanism, comprises the ramp signal generation device of the ramp signal that generation is vibrated with specified amplitude with described switching frequency,

Described constant a is the inverse of the amplitude of described ramp signal.

6. switching power supply control device as claimed in claim 1 or 2 is characterized in that:

Described gain adjusting mechanism comprises:

Calculate (1/2a) D_A+PIS_A, and produce first arithmetical organ of first consequential signal of this result of calculation of expression;

Calculate (1/2a) D_B+PIS_B, and produce second arithmetical organ of second consequential signal of this result of calculation of expression;

Described first consequential signal and described second consequential signal are compared, and first of first comparison signal of this comparative result of generation expression compares mechanism;

From described drive pulse signal, detect the time ratio testing agency of described D_A and described D_B;

Detected described D_A and detected described D_B are compared, and second of second comparison signal of this testing result of generation expression compares mechanism; With

Increase or reduce described Current Control gain accordingly with described first and second comparison signals, with the gain determination means that determines that described Current Control gains,

Wherein, D_A is that described square-wave signal is the described time ratio during the height, and PIS_A is that described square-wave signal is that the size of calculating current detection signal is taken advantage of in described gain during the height,

D_B is that described square-wave signal is the described time ratio between lowstand, and PIS_B is that described square-wave signal is that the size of calculating current detection signal is taken advantage of in described gain between lowstand.

7. switching power supply control device as claimed in claim 1 or 2 is characterized in that:

The calculation current detection signal is taken advantage of in described gain, is analog signal,

Described gain adjusting mechanism comprises:

Described gain is taken advantage of calculated the current detection signal digitlization, take advantage of the digital-analog convertor of calculating signal to produce digital gain;

Take advantage of the first Digital Detecting circuit of calculating the described Δ PIS of detection the signal from described digital gain;

From described drive pulse signal, detect the second Digital Detecting circuit of described Δ D;

Calculate the numeral of Δ PIS/ Δ D with detected described Δ PIS and Δ D and remove the calculation device;

To the Δ PIS/ Δ D that calculates and-1/2a compares, and produces the digital comparator of the output signal of this comparative result of expression;

According to the output signal of described digital comparator, increase or reduce the gain of described Current Control, make Δ PIS/ Δ D approaching-1/2a, with produce this increase of expression or reduce after the digital gain decision-making circuit of digital gain signal of Current Control gain; With

Make described digital gain signal imitationization, produce the digital-analog convertor of analog gain signal,

Described taking advantage of calculated mechanism, accepts described analog gain signal and described current detection signal, produces the long-pending output signal that is equivalent to both and takes advantage of the calculation current detection signal as described gain.

8. Switching Power Supply possesses:

The switch element that carries out switch with the switch periods and the switching frequency of regulation of regulation;

Make the output smoothingization of described switch element, produce the smoothing circuit of the output voltage of this Switching Power Supply; With

Control the control device of the switch of described switch element, wherein,

Described smoothing circuit comprises the inductor that is connected on the described switch element,

Described control device possesses:

Detect the output voltage of described Switching Power Supply, produce the voltage detection mechanism of the voltage detection signal corresponding with this output voltage;

In each described switch periods, detect the electric current that in described inductor, flows, produce the current detecting mechanism of the current detection signal corresponding with this electric current;

The square-wave signal of square-wave signal that generation has 1/2 frequency of described switching frequency produces mechanism;

Make described current detection signal multiply by the Current Control gain, produce gain and take advantage of taking advantage of of calculation current detection signal to calculate mechanism;

Make described voltage detection signal add the above square-wave signal, deduct described gain simultaneously and take advantage of the calculation current detection signal, produce the arithmetical organ of control signal;

Generation has the drive pulse signal with the big or small time corresponding ratio of described control signal, supplies with this drive pulse signal to described switch element and produces mechanism with the drive signal that drives described switch element; With

Adjust the gain adjusting mechanism that described Current Control gains according to described gain multiplied signal and described time ratio,

Described drive signal produces mechanism and produces described drive pulse signal, makes Δ D/ Δ CS become constant a,

Described gain adjusting mechanism is adjusted the gain of described Current Control, satisfying Δ PIS/ Δ D=-1/2a,

Wherein, Δ D is the variable quantity of each described switch periods of described time ratio, and Δ CS is the variable quantity of each described switch periods of described control signal, and Δ PIS is the variable quantity that each described switch periods of calculating current detection signal is taken advantage of in described gain.

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