CN1766834A - 8-bit RISC microcontroller with double arithmetic logic units - Google Patents
8-bit RISC microcontroller with double arithmetic logic units Download PDFInfo
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- CN1766834A CN1766834A CN 200510041649 CN200510041649A CN1766834A CN 1766834 A CN1766834 A CN 1766834A CN 200510041649 CN200510041649 CN 200510041649 CN 200510041649 A CN200510041649 A CN 200510041649A CN 1766834 A CN1766834 A CN 1766834A
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Abstract
The invention discloses a double arithmetic logic unit tamping instruction set 8 bit microcontroller. It adopts the current register pile and arithmetic logic unit ALU-1 of the 8 bit RISC structure and parallel connects with the multi-function register pile and arithmetic logic unit ALU-2, it arranges the bit holder and bit operating quoting device inside the order decoder of the initial RISC structure and the bite operator structure on the current arithmetic logic unit ALU-1, then it adds the operating function and the data processing function to the multi-byte data of the 8 bit microcontroller and provides the register address mode of the data space and amplifies the data address space by coupling the multi-function register pile and the arithmetic logic unit ALU-2.
Description
Technical field
The present invention relates to general microcontroller (MCU) technical field of structures, particularly relate to 8 8-digit microcontrollers of double arithmetic logic units (ALU) reduced instruction set computer (RISC).Be applicable to personal digital terminal PDA, e-book, electronic dictionary, handwriting pad, MP3, fields such as Industry Control.
Background technology:
Along with development of semiconductor, the scale of integrated circuit is increasing, and integrated level is more and more higher, microcontroller and its relational storage such as flash memory (Flash Memory), electricity erasable memorizer (E
2PROM), static RAM (SRAM) etc. and peripheral hardware logic controller can be integrated on the same chips in a large number.And the project organization of RISC and powerful electric design automation (EDA) method make that designer's work is more effective, and programming more becomes easily, thereby have further promoted the decline of microcontroller cost and the raising of integrated level.
Owing to adopted the RISC architecture, program's memory space separates with data space, the programming of microcontroller is more convenient than in the past, arithmetic speed is accelerated, efficient increases, and in the technology high development, integrated level is unchallenged today, the application of microcontroller is also just more extensive, and the microcontroller of existing RISC framework has had the gesture that replaces original sophisticated vocabulary controller (CISC) greatly.Why popular the RISC system is in recent years, can be owing to following several characteristics: 1) most of instructions can be finished in the same clock period; 2) Zhi Ling decoding is normally fixed, and compares microcoding, and execution speed greatly improves; 3) order format is fixed, and is convenient to decoding; 4) data routing streamlined, instruction can parallel processings, and the data that height is provided are processing power simultaneously; 5) adopt Harvard's bus structure, the program space, data space separate, and clear in structure is easily learnt usefulness well.The most noticeable application of risc architecture is PowerPC, and it is by Apple, IBM, several companies of Motorola joint research and development.Typical case's representative of 8 MCU then is the PIC16C5X Series of MCU of Microchip technology.What this microcontroller used is Harvard's dual-bus structure, and in this structure, data and programmed instruction have its independently storer and bus.What PIC16C5X used is a level production line; When an instruction was being carried out, next instruction can read out from program storage in advance.But because RAM double as register, so just there is not internal register truly.Because all storeies can be static memories (SRAM), so operation registers has just been simplified very much.
The development of technology makes people pursue higher to the comfort level of life.Performance at above-mentioned these the traditional microcontrollers in a lot of application scenarios can not satisfy the application need of people to its control performance far away, and its principal contradiction concentrates on two aspects: the one, and the operational performance of microcontroller is poor, can not satisfy the requirement of data processing; The 2nd, the space, memory block is little, can not satisfy the needs of programming.Therefore in some cases, force people to have to select for use expensive 16,32 bit processors, and the costs such as expensive and high power consumption of these processors usually can make practical matter purpose plan miscarriage.Therefore, 8 8-digit microcontrollers must be broken through data space deficiency, the more weak shortcoming of data-handling capacity, the sufficient program space are provided for software design teacher, and data space and enough powerful data-handling capacity are to satisfy the needs that great majority are used.On the other hand, undoubtedly, when the design microcontroller, the software role is held the balance, the Application Design of microcontroller is that the interface between direct and software programmer and the Hardware Engineer is closely-related, the instruction set that is microcontroller is as the bridge between the software and hardware slip-stick artist, and the success or not of its design concerns the success or failure of microcontroller.The design of instruction set must be complete, efficient, makes most computings to carry out, and often the function of using should be finished with several less instructions that compare.These application demands make people wish to design a kind of microcontroller, provide complete and instruction set efficiently to give the application software developer, and higher data processing speed and storage space are arranged.
The content of invention
The objective of the invention is to overcome existing 8 deficiencies that the 8-digit microcontroller storage space is little, data processing speed is low, a kind of 8 8-digit microcontrollers of double arithmetic logic units risc architecture are provided, data space with comprehensive expansion 8 8-digit microcontrollers, and be that 8 8-digit microcontrollers increase by 16 arithmetic instruction processing poweies of part and monocycle bit operating ability, improve the operational performance of 8 8-digit microcontrollers, formation is applicable to PDA, e-book, big data quantity such as electronic dictionary, MP3, the high-performance embedded microprocessor of the application demand of high arithmetic speed.
The gordian technique that realizes the object of the invention is in the general-purpose register and universal arithmetic logic unit ALU-1 of original 8 risc architectures, connect multi-functional register file and multi-functional arithmetic logic unit alu-2 side by side, and in the command decoder of original 8 risc architectures, be provided with bit steady arm and bit operating determining device respectively, in universal arithmetic logic unit ALU-1, be provided with the bit arithmetical unit.
Entire controller comprises:
Program storage is used for stored programme, visits by program pointer, and the instruction of the program memory address of program pointer appointment is read, and delivers to order register, and this program storage can be Flash, E
2PROM, ROM etc.;
Programmable counter, it is program pointer, be used for pointing out the physical address that the instruction that will carry out is deposited at program storage, it translates signal controlling by command decoder and is offset computing when the rising edge clock, finish order and add 1 or jump to the operation of appointed positions, it is output as the current instruction address that will read, and this address is as the address pointer of program storage, and the data of control program storer are exported;
Order register is used for the temporary instruction that obtains from program storage, and its output is delivered to command decoder and deciphered;
Command decoder, decoding explanation is carried out in the instruction that is used for being deposited with order register, generate control signal corresponding, the redirect of the choosing of the action of control register heap, arithmetic logic unit alu and the data flow of data bus, address bus, programmable counter, the moving etc. of stack pointer;
The bit steady arm is used for the bit operational order is done to determine the bit position than certain bits computing;
The bit operating determining device is used for judging whether the instruction of present instruction code translator is the bit operating instruction, determines whether that a bit operating enable signal puts 1;
Stack pointer, when being used for program jump, preservation/recovery routine pointer, promptly when call subroutine, preserve the entry address of subroutine, the address that the designated program pointer is preserved in the data storage area, behind the save routine pointer, stack pointer will point to next stack position; When subroutine is returned, recover the value of original program pointer, the entry address of backspace subroutine from assigned address.Program need be set up storehouse at first, promptly specifies certain address realm at data space, this stack pointer points to the storehouse bottom position after storehouse is set up, work as each push operation in the time of in working order, then stack pointer adds 1, and when go out stack operation at every turn, then stack pointer subtracts 1;
Static RAM SRAM, the data that are used for storing calculating process, the address bus visit by appointment in the multi-functional register file has 8 bit data bus as data input/output interface;
General-purpose register is as totalizer, for universal arithmetic logic unit ALU-1 provides operand and preserves operation result;
Universal arithmetic logic unit ALU-1 finishes 8 arithmetic logical operations and bit operating computing; Be provided with the bit arithmetical unit among the universal arithmetic logic unit ALU-1, be used to finish bit operating, promptly carry out bit and read instructions such as BTRAN, bit set BSET, bit zero clearing BCLR and bit rewriting BCHN;
The bit arithmetical unit is used to finish bit operating, carries out bit and reads instructions such as BTRAN, bit set BSET, bit zero clearing BCLR and bit rewriting BCHN;
Multi-functional register file is used to finish 8 bit data and adds up, the spread bandwidth data accumulation, and functions such as data address pointer are for multi-functional arithmetic logic unit alu-2 provides operand and preserves operation result;
Multi-functional arithmetic logic unit alu-2 is used to carry out the arithmetic logical operation and the address computation of spread bandwidth;
Status register is used for the operation result of ALU is made mark; This mark is by interrupt enable bit I, sign bit S, and negative sign N, zero flag Z, overflow indicator V and carry flag C form; The content of status register is determined by ALU result of calculation, also can carry out register access by address bus, is write or is read by 8 bit data bus;
Clock unit generates the needed clock of microcontroller, and being mainly streamline provides IDLE, SLEEP clock and the test scan clock of the house dog of flowing water phase clock, exceptional reset (WDR) clock, energy saver mode;
Other peripheral interfaces, as required, the peripheral interface of configuration can comprise timer/counter, modulus/digital-to-analog conversion, interrupt location, universal asynchronous receiver/transmitter (UART) (UART), comparer, universal serial bus (I
2C), Serial Peripheral Interface (SPI) (SPI) and universal input/output interface (GPIO) etc.
Above-mentioned multi-functional register file constitute dual port RAM, have two output ports and two input ports; Described two output port addresses are respectively the address of source operand and the address of destination operand, by command decoder control, select from command decoder, address register; The output data of two output ports is delivered to the input port of multi-functional arithmetic logic unit alu-2, and as the input option of multi-functional arithmetic logic unit alu-2, data bandwidth equals spread bandwidth.Described two input ports, one is the wide input ports of 8 bit strips, and one is the spread bandwidth input port, and the address of 8 input ports is determined that by command decoder the address of spread bandwidth port is also determined by command decoder; The input data of two ports, the wide input port of 8 bit strips is connected to 8 bit data bus, and this multi-functional register file is finished external reference by this 8 bit data port by 8 bit data bus; The spread bandwidth input connects the output port of multi-functional arithmetic logic unit alu-2.The mode of operation of multi-functional register file has three kinds, and the one, the byte mode of operation is a unit access with the byte, finishes the exterior read-write of general-purpose register function and multi-functional register file; The 2nd, the multibyte mode of operation is a unit access with the multibyte, is used to cooperate multi-functional arithmetic logic unit alu-2 to finish the arithmetic logical operation of multibyte spread bandwidth; The 3rd, the counter works pattern as address register, is finished the address pointer computing.When multi-functional register file is used as the address register function, can when instruction is carried out, not only can finishes the computing of address automatically according to the setting of address bandwidth, and can cooperate infinite expanding data addressing space with the branch page register that adds;
Above-mentioned multi-functional arithmetic logic unit alu-2, when carrying out the spread bandwidth arithmetic logical operation, two operands are arranged, one is the destination operand as multi-functional register file output, another is from multi-functional register file, constant (0x0 by command decoder, 0x1 0xFF), the source operand chosen in 8 bit data bus, outputs to multi-functional register file by the result of these two operand computings.This ALU can be finished the arithmetic logical operation of expansion back bandwidth such as 16,24,32 in a clock period, improve data communication bandwidth and multibyte data processing power; Carry out address arithmetic, be when the instruction of command decoder decoding is the access instruction of static RAM SRAM, by the control signal of command decoder decoding at first with arithmetic logic unit alu-2, be configured to the address arithmetic device, multi-functional register file is configured to address register, then when arithmetic logic unit alu-2 is carried out this access instruction, automatically finish adding 1, passing 1 or the numerical operation of plus-minus command decoder appointment of address register content, and operation result is write back described address register.
Above-mentioned bit steady arm is done than certain bits computing the bit operational order, at first the bit position information that comprises in the bit operating instruction is deciphered, demarcate the bit position that to carry out bit operating with unique 0 or 1, by the control of bit operating enable signal this bit position information is loaded into data bus then.
It is to generate control signal by command decoder that above-mentioned bit arithmetical unit is finished bit operating, determine the register that to operate and the bit position that is loaded into data bus, as two operands of universal arithmetic logic unit ALU-1, and control arithmetic logic unit alu-1 pair these two operands carry out logical operation and finish bit operating.
Above-mentioned multi-functional register file and multi-functional arithmetic logic unit alu-2 are connected with universal arithmetic logic unit ALU-1 with general-purpose register by data bus.
The course of work of the present invention is as follows:
After system reset, programmable counter makes zero, and program pointer points to the zero-address of program storage, begins reading command from zero-address; The address that program storage is pointed out according to programmable counter reads out and gives order register the programmed instruction that will carry out, and simultaneously, programmable counter is counted, and points to next bar instruction; Order register from the program bus reading command, is given command decoder at the rising edge of each clock period; Command decoder is deciphered instruction, and the definite operation that will carry out generates control signal, the action of control register heap and ALU; Register file comprises general-purpose register and multi-functional register file, serves as totalizer, and being used for provides operand and preserve its operation result to ALU; ALU, comprise universal arithmetic logic unit ALU-1 and multi-functional arithmetic logic unit alu-2, control signal according to the command decoder generation, the selection operation number, carry out corresponding computing, and influence the mode bit of status register, ALU can be finished common arithmetical operation and logical operation, also can finish the bit operating of register, and data are saved in data-carrier store and are used for calling of subroutine from the reading and write and as the passage of programmable counter, the content of programmable counter is sent to 8 bit data bus by the ALU gradation of storer, perhaps be delivered to outside port, be used for the monitoring and the debugging of program; Decipher at command decoder, when ALU carried out computing, the instruction of the programmable counter appointment after the renewal was read into order register, prepared instruction execution cycle next time, had so formed program implementation.
The present invention is owing to adopt the double arithmetic logic units risc architecture, can in traditional central processor CPU framework, embed 16, even some arithmetical logic operations of 24,32, special application demands such as audio frequency have been satisfied, the arithmetic capability and the instruction execution speed of system have been improved, make the execution speed of 16 bit arithmetics instruction reach 1.0 IPC, expanded data space greatly simultaneously, as shown in table 1.
Table 1 the present invention is compared as follows with existing common 8 8-digit microcontroller performances:
Description of drawings
Fig. 1 is an one-piece construction block diagram of the present invention
Fig. 2 is that multi-functional register file of the present invention and multi-functional arithmetic logic unit alu-2 expand to 8 at data bandwidth respectively, 16, and the structural drawing in the time of 32
Fig. 3 (a) is that the present invention is used as the multi-functional register file of 8 bit address registers and generates address bus in 8 pages or leaves as the coupling of the multi-functional arithmetic logic unit alu-2 of 8 bit address computings, and symphysis becomes the structural drawing of address bus with the paging registers group
Fig. 3 (b) is that the present invention is used as the multi-functional register file of 16 bit address registers and generates address bus in 16 pages or leaves as the coupling of the multi-functional arithmetic logic unit alu-2 of 16 bit address computings, and symphysis becomes the structural drawing of address bus with the paging registers group
Fig. 3 (c) is that the present invention is used as the multi-functional register file of 32 bit address registers and generates address bus in 32 pages or leaves as the coupling of the multi-functional arithmetic logic unit alu-2 of 8 bit address computings, and symphysis becomes the structural drawing of address bus with the paging registers group
Fig. 4 is a command decoder structural drawing of the present invention
Fig. 5 is the structural drawing of programmable counter of the present invention
Fig. 6 is the structured flowchart of application example XD0308-E of the present invention
Fig. 7 is the structured flowchart of existing risc architecture microcontroller
Embodiment
Followingly the present invention is described in further detail with reference to accompanying drawing:
As shown in Figure 1, the present invention is the double arithmetic logic units microcontroller of 8 risc architectures, has 8 bit data bus, and 16 program buss can be unrestricted on the data access Space Theory, and the routine access space can reach more than the 16MB.This controller comprises: program bus, program storage, program pointer, stack pointer, static RAM SRAM, general-purpose register, universal arithmetic logic unit ALU-1, multi-functional register file, multi-functional arithmetic logic unit alu-2, status register, command decoder, data bus, address bus and timer, comparer, UART Universal Asynchronous Receiver Transmitter (UART), other interface such as universal input/output interface, wherein 8 bit data bus connect general-purpose register respectively, multi-functional register file, universal arithmetic logic unit ALU-1, multi-functional arithmetic logic unit alu-2, status register, parts such as SRAM, the data routing core that this 8 bit data bus is a microcontroller.The present invention is that passage launches with 8 bit data bus, the invention main points comprise the universal arithmetic logic unit that can carry out bit operating, multi-functional ALU, general-purpose register, multi-functional register file, the command decoder with bit positioning function, the nested technology of storehouse, programmable counter arrives the passage of FPDP etc.Wherein:
Program counter unit is responsible for the addressing of instruction in the program storage, and it is output as program pointer, and when system power-up started, program pointer pointed to the program storage zero-address, in program process, whenever reads an instruction, and program pointer adds 1.When subroutine call, the content of programmable counter is stored in stack pointer data designated storage space by data bus.
Program storage is used for save routine instruction, program write finish after, program storage is in a read states, is input as program pointer, is connected to the address bus of program storage, is responsible for the addressing of the program space; Be output as the present instruction that needs execution, be connected to 16 program buss.
Order register, address according to the program pointer appointment, after instruction is exported from program storage, it is temporary to be input to order register, program pointer discharges, programmable counter is finished and is added 1 counting, points to the instruction of next bar, and temporary present instruction outputs to command decoder and deciphers in the order register.
Command decoder, comprise universal command code translator, bit steady arm and bit operating determining device, be responsible for reading and explaining instruction temporary in the present instruction register, generate control signal corresponding, the redirect of the choosing of the action of control register heap, arithmetic logic unit alu and the data flow of data bus, address bus, programmable counter, the moving etc. of stack pointer.When the instruction of reading from order register is the instruction of non-bit operating, the general controls signal that universal command decoder for decoding bit operating is irrelevant, the bit control signal is invalid, and the bit operating enable signal puts 0, by the action of general controls signal as the control signal control microprocessor; When the instruction of reading from order register is the bit operating instruction, the general controls signal that the universal command decoder for decoding is relevant, the bit steady arm is done than certain bits computing the bit operational order, at first the bit position information that comprises in the bit operating instruction is deciphered, need carry out the bit position of bit operating with 0 or 1 unique demarcation, by the control of bit operating enable signal this bit position information is loaded into data bus then, and generates the bit control signal; The bit operating determining device judges whether the instruction in the present instruction code translator is the bit operating instruction, determine whether that a bit operating enable signal puts 1, be combined into control signal by general controls signal, bit control signal, bit operating enable signal, determine the register that to operate and the bit position that is loaded into data bus, as two operands of universal arithmetic logic unit ALU-1, and control arithmetic logic unit alu-1 pair these two operands carry out logical operation and finish bit operating.
Register file, the control signal that command decoder generates according to instruction determines the duty of register file.Register file is made up of general-purpose register and multi-functional register file, and under the control of control signal, register file is responsible for data being provided and preserving the operation result of ALU to arithmetic logic unit alu.
The dual port RAM that constitutes the 8 bit data bandwidth that are made of eight bit register of general-purpose register has two output ports and an input port, and the action of execution is determined by command decoder; Two output port addresses are respectively the address of source operand and the address of destination operand, and the output data of two output ports is delivered to two input ports of universal arithmetic logic unit ALU-1, as the input option of universal arithmetic logic unit ALU-1; Its input port is connected to 8 bit data bus, and Input Address is determined by command decoder; In working order, the I/O Address of general-purpose register and input data are determined through decoding generation control signal by the instruction of depositing in the order register.
Multi-functional register file constitute dual port RAM, have two output ports and two input ports; Two output port addresses are respectively the address of source operand and the address of destination operand, are selected from command decoder, address register by control signal; The output data of two output ports is delivered to the input port of multi-functional arithmetic logic unit alu-2, and as the input option of multi-functional arithmetic logic unit alu-2, data bandwidth equals spread bandwidth.Two input ports, one is the wide data-in ports of 8 bit strips, is connected to 8 bit data bus, its Input Address determines that by command decoder this multi-functional register file is finished external reference by this 8 bit data port by 8 bit data bus; One is the spread bandwidth data-in port, connects the output of multi-functional arithmetic logic unit alu-2, and its Input Address is determined by command decoder.In working order, multi-functional register file has three kinds of mode of operations, the one, the byte mode of operation, with the byte is unit access, carry out general 8 arithmetical logics instruction, this moment, multi-functional register file was equal to the general-purpose register function, perhaps carried out multi-functional register file access visit, finish the read-write to outside 8 bit data bus of multi-functional register file with the byte form, this mode of operation is default mode of operation; The 2nd, the multibyte mode of operation, with the multibyte is unit access, cooperate multi-functional arithmetic logic unit alu-2 to carry out multibyte spread bandwidth arithmetic logical operation instruction, one-period is finished the operation of multibyte arithmetical logic, and being written back to register, this moment, multi-functional register file and multi-functional ALU inner couplings data bus equaled growth data multibyte width.When the instruction of buffer memory in the order register is instructed for the spread bandwidth arithmetic logical operation, command decoder is controlled multi-functional register file and is entered the multibyte mode of operation, register in the multi-functional register file is an organization unit with the continuous register of some, with the multibyte is unit access, its address is a jumping address, the span of jumping determined by instruction decode, as expands to 16 bit strips when wide, and its address is provided by command decoder, be 0x00,0x02 ..., expand to 32 bit strips when wide, its address is 0x00,0x04 ..., the data bandwidth respective extension of multi-functional register file and multi-functional ALU inner couplings is the bandwidth of this multibyte correspondence; The 3rd, the counter works pattern as address register, is finished the address pointer computing, address register can be arranged to 8 as required, and 16,32,, be used to finish the addressing mode of data space greatly such as register addressing, relative addressing, absolute addressing.When the instruction of buffer memory in the order register is the access instruction of static RAM SRAM, command decoder is controlled multi-functional register file and is entered the counter works pattern, multi-functional register file is as the address register function, when instruction is carried out, multi-functional register file is selected the output of control address register according to the control signal of instruction decode, be sent to multi-functional arithmetic logic unit alu-2, and when this instruction execution cycle finishes, preserve the result that automatic computing is carried out in multi-functional arithmetic logic unit alu-2 pair address.When multi-functional register file is used as the address register function, the register of corresponding appointment becomes address register, can be set to three groups, selecting wherein by the instruction decode control signal, a group address register outputs to multi-functional ALU, after finishing automatic computing, by multi-functional ALU output, be called a page interior address bus.Address bus can cooperate with the branch page register that adds in the page or leaf, divide page register that the high-order portion of address bus is provided, finish page addressing, address bus constitutes the low portion of address bus in the page or leaf, finish a page interior addressing, divide page register and address register two parts to merge bus infinite expanding data addressing space, calculated address.
ALU, command decoder also determines the duty of ALU and the selection of operand according to the control signal that instruction generates.ALU is divided into 8 universal arithmetic logic unit ALU-1 and multi-functional arithmetic logic unit alu-2, their distinguish corresponding and general-purpose register, the coupling of multi-functional register file are used, finish arithmetic, logical operation and the bit computing of data, the difference of microcontroller instruction set is mainly embodied by this part, command decoder translates different control signals according to instruction code, the control ALU carries out different operations, thereby finished different instructions, formed corresponding instruction set.Universal arithmetic logic unit ALU-1 finishes 8 arithmetical logic operation and bit operating, its source operand source can be general-purpose register, multi-functional register file, number, constant, command decoder, SRAM etc. immediately, its destination operand source is general-purpose register, and operation result is by 8 bit data bus write-back general-purpose register or SRAM.Multi-functional arithmetic logic unit alu-2 is finished arithmetic logical operation, address arithmetic and 8 arithmetic logical operations of spread bandwidth.When carrying out the spread bandwidth arithmetic logical operation, two operands are arranged, one is the destination operand as multi-functional register file output, another is from multi-functional register file by command decoder, constant 0x0,0x1,0xFF, the source operand of choosing in 8 bit data bus outputs to multi-functional register file by the result of these two operand computings.This ALU can be finished the arithmetic logical operation of expansion back bandwidth such as 16,24,32 in a clock period, improve data communication bandwidth and multibyte data processing power; Carry out address arithmetic, be when the instruction of command decoder decoding is the access instruction of static RAM SRAM, by the control signal of command decoder decoding at first with arithmetic logic unit alu-2, be configured to the address arithmetic device, multi-functional register file is configured to address register, then when arithmetic logic unit alu-2 is carried out this access instruction, automatically finish adding 1, passing 1 or the numerical operation of plus-minus command decoder appointment of address register content, and operation result is write back described address register.
Status register is after ALU executes instruction manipulation, makes corresponding changes according to operation result, makes the content of status register reflect the state of current microcontroller.Status register carries out register access by address bus, is write or is read by 8 bit data bus.
SRAM, be in program process, a lot of process datas need to preserve, and these data are kept among the SRAM by the SRAM access instruction, by the address bus visit of appointment in the multi-functional register file, have 8 bit data bus among the SRAM as data input/output interface.
Stack pointer is when having subroutine call in the program, and the stack pointer that need use.When this stack pointer was used for program jump, preservation/recovery routine pointer was promptly when call subroutine, preserve the entry address of subroutine, the address that the designated program pointer is preserved in the data storage area, behind the save routine pointer, stack pointer will point to next stack position; When subroutine is returned, recover the value of original program pointer, the entry address of backspace subroutine from assigned address.Program is at first, need set up storehouse, promptly in data space SRAM, specify certain zone as storehouse, this stack pointer is after storehouse is set up, point to the storehouse bottom position, when each push operation, then stack pointer adds 1 in the time of in working order, when go out stack operation at every turn, then stack pointer subtracts 1;
Clock unit provides microcontroller used clock, is mainly streamline the house dog WDR clock of flowing water phase clock, exceptional reset, IDLE, SLEEP clock and the test scan clock of energy saver mode are provided.It is once or the repeatedly frequency-dividing clock of system clock that the present invention adopts flowing water design, flowing water phase clock; The house dog clock comprises an oscillator, and independent operating generates the house dog clock; Energy saver mode then can be closed corresponding clock.
Other peripheral interfaces comprise as required the peripheral interface of configuration, i.e. timer/counter, modulus/digital-to-analog conversion, interrupt location, watchdog unit, universal asynchronous receiver/transmitter (UART), comparer, universal serial bus, Serial Peripheral Interface (SPI) and universal input/output interface etc.Peripheral interface is assigned address separately, by data bus, address bus by the port access instruction access.
Described universal arithmetic logic unit ALU-1 and general-purpose register coupling are used, and finish the instruction of immediate addressing arithmetical logic, several operational orders, state dependent instruction, register increase and decrease instruction, the not execution of write-back arithmetic operation instruction, data reversal instruction, logical shift instruction, memory reference instruction, bit operating instruction immediately respectively.This immediate addressing arithmetical logic instruction comprises: ADDB, and ADCB, SUBB, SUCB, ANDB, ORB, EORB, MOVB, SNIF, these instructions have two operands, and all from general-purpose register, the result is written back to general-purpose register; This execution of counting operational order immediately comprises: ADIB, and SUIB, ANIB, ORIB, SETI, this instruction has two operands, and wherein destination operand is from general-purpose register, and source operand is provided by command decoder for counting immediately, and the result writes back general-purpose register; The execution of this state dependent instruction comprises: COMB, and NEGB, CLRB, this batch instruction is single-operand instruction, and operand is from general-purpose register, and the result is write-back not, only influences the mode bit of status register; The execution of this register increase and decrease instruction comprises: INC, and DEC, this batch instruction is single-operand instruction, and its destination operand is from general-purpose register, and source operand is a constant 1, and the result writes back general-purpose register; This is the execution of write-back arithmetic operation instruction not, comprising: SSUB, and SSUC, SADD, SADC, this batch instruction has two operands, and all from general-purpose register, the result is write-back not, only influences status register; The instruction of this data reversal comprises and is single-operand instruction by HDSD, and operand is from general-purpose register, and the result is written back to register file; The execution of this logical shift instruction comprises: LSL, LSH, LS1, LS1, RSL, RSH, RS0, RS1, this batch instruction has two operands, its destination operand is from general-purpose register, and source operand is determined the quantity of displacement, as a result the write-back general-purpose register for counting immediately; The execution of this memory reference instruction needs and multi-functional arithmetic logic unit alu-2 cooperation is finished, finish the preparation of data by universal arithmetic logic unit ALU-1, multi-functional arithmetic logic unit alu-2 is finished the computing of address, and this instruction comprises: LD/ST, LDX/STX, LDY/STY, LDZ/STZ, LDX+/STX+, LDY+/STY+, LDZ+/STZ+ ,-LDX/-STX ,-LDY/-STY,-LDZ/-STZ, LDXP/STXP, LDYP/STYP, LDZP/STZP, this batch instruction provides data address by multi-functional register file, and according to instruction control signal change address, when carrying out storage instruction, universal arithmetic logic unit is not moved, just the data that register is read directly are put into 8 bit data bus, when carrying out reading command, universal arithmetic logic unit ALU-1 is written back to register file from 8 bit data bus reading of data; The execution of this bit operating instruction comprises: BTRAN, BSET, BCLR and BCHN, and finish the zero clearing of specifying register bit, put 1, read, operation such as modification, its result writes general-purpose register and is sent to 8 bit data bus, for the external component visit.
Described multi-functional arithmetic logic unit alu-2 is as Fig. 2.
With reference to Fig. 2, multi-functional arithmetic logic unit alu-2 uses with multi-functional register file coupling, multiple array configuration can be arranged, when multi-functional register file constitutes with 8 bit register forms, the coupling bandwidth is 8 bits, multi-functional arithmetic logic unit alu-2 corresponds to 8 bit A LU, visit multi-functional register file with the byte form, multi-functional arithmetic logic unit alu-2 is finished 8 bit arithmetic logical operations, carry out general arithmetical logic instruction, also finish the read-write of multi-functional register file, the execute store access instruction; When multi-functional register file constitutes than top grade multibyte register form with 16 bits, 32, coupling bandwidth position is 16 bits, 32 multibyte width than the top grade expansion, multi-functional arithmetic logic unit alu-2 corresponds to 16 bits, 32 bit multibyte operations, multi-functional register is with 2,4 multibyte parallel output data such as byte, multi-functional arithmetic logic unit alu-2 is finished the multibyte arithmetic logical operation, carry out the instruction of multibyte arithmetical logic, perhaps multi-functional arithmetic logic unit alu-2 is finished address arithmetic, the execute store access instruction.Multi-functional ALU can carry out 16 than the multibyte arithmetic logical operation of top grade, this microcontroller is had in 8 bit operating environment, in the monocycle, finish the ability of multibyte operation, thereby increase the s operation control ability of this microcontroller, expand its application scenario.
Multi-functional arithmetic logic unit alu-2 uses with multi-functional register file coupling, finishes the execution of 8 bit arithmetic logical operations, address arithmetic instruction, multibyte arithmetic operation instruction.This 8 bit arithmetic logical operation instruction is used for 8 bit arithmetic logical operations, and be equal to universal arithmetic logic unit ALU-1 this moment, can carry out all general arithmetical logic instructions; This spread bandwidth multibyte arithmetic logical operation, comprise: ADDW, ADCW, SUBW, SUCW, ANDW, ORW, the execution of EORW word arithmetical logic instruction, these instructions have two operands, all from multi-functional register file, finish word arithmetic in the clock period, the result writes back multi-functional register file; Finish the execution of counting the instruction of multibyte arithmetical logic immediately, comprise: ADIW, SUIW, ANIW, ORIW, SETW, these instructions have two operands, and wherein destination operand is from multi-functional register file, and source operand is for counting immediately, can finish word arithmetic within a clock period, the result writes back multi-functional register file; This multibyte state dependent instruction comprises: COMW, and NEGW, CLRW, these instructions are single-operand instruction, and operand is from multi-functional register file, and the result is write-back not, only influences the mode bit of status register.The special arithmetic capability of multi-functional ALU can support the design of instructions such as the broadband computing demand of special occasions and matrix manipulation to realize easily.
Multi-functional register file can be organized into the form that becomes bus with a plurality of combination of bytes, be coupled into the row address computing with multi-functional arithmetic logic unit alu-2, for memory access provides effective addressing means, increase the addressing space of program and data, improved the data access capabilities of microcontroller greatly.The execution of memory reference instruction and port read write instruction needs and universal arithmetic logic unit ALU-1 cooperation is finished, and finishes the preparation of data by universal arithmetic logic unit ALU-1, and multi-functional arithmetic logic unit alu-2 is finished the computing of address.This memory reference instruction comprises: LD/ST, and LDX/STX, LDY/STY, LDZ/STZ, LDX+/STX+, LDY+/STY+, LDZ+/STZ+ ,-LDX/-STX ,-LDY/-STY ,-LDZ/-STZ, LDXP/STXP, LDYP/STYP, LDZP/STZP.The port read write instruction comprises: PTRD, PTWR.
Described multi-functional register file as shown in Figure 3.
With reference to Fig. 3, when multi-functional register file is finished the address register function, can unite with the branch page register of appointment among the SRAM, form the address pointer of expansion.
Shown in Fig. 3 (a), multi-functional register file is an organization unit with 8 bit byte forms, be configured to three address register x, y, z, the number immediately of address register and participation address arithmetic is input to multi-functional arithmetic logic unit alu-2 as operand and carries out address arithmetic, and operation result outputs to a page interior address bus, and is written back to address register.The present invention is respectively by address register x, y, and address bus x in the address bus called after page or leaf in the page or leaf that comes of z computing, y, z as the low portion of address bus, is used for addressing space in the page or leaf of 2^8 byte; In SRAM, corresponding three address register x, y, z have specified three page register PageX that width is the n bit, PageY, PageZ, respectively as the high-order portion of address bus, the width of corresponding address register, an addressing space is the 2^8 byte in the page or leaf; When instruction is carried out, the command decoder translation instruction generates control signal, and control is from three address register x, y, z selects one to carry out address arithmetic as address bus in the page or leaf, selects the corresponding page register from three page registers, carry out page addressing, the coupling of address bus and corresponding page register forms the addressing capability of (2^8) * (2^n) byte as 8+n bit address bus in the page or leaf, finishes the addressing of data space.
Shown in Fig. 3 (b), multi-functional register file is an organization unit with 16 bit words forms, be configured to three address register r, s, t, the number immediately of address register and participation address arithmetic is input to multi-functional arithmetic logic unit alu-2 as operand and carries out address arithmetic, and operation result outputs to a page interior address bus, and is written back to address register.The present invention is respectively by address register r, s, and address bus r in the address bus called after page or leaf in the page or leaf that comes of t computing, s, t, as the low portion of address bus, the width of corresponding address register, an addressing space is the 2^16 byte in the page or leaf; In SRAM, corresponding three address register r, s, t have specified three page register PageR that width is the n bit, PageS, PageT respectively as the high-order portion of address bus, is used for the page addressing of 2^n; When instruction is carried out, the command decoder translation instruction generates control signal, and control is from three address register r, s, t selects one to carry out address arithmetic as address bus in the page or leaf, selects the corresponding page register from three page registers, carry out page addressing, the coupling of address bus and corresponding page register forms the addressing capability of (2^16) * (2^n) byte as 16+n bit address bus in the page or leaf, finishes the addressing of data space.
Shown in Fig. 3 (c), multi-functional register file is an organization unit with 32 bit double word forms, be configured to three address register u, v, w, the number immediately of address register and participation address arithmetic is input to multi-functional arithmetic logic unit alu-2 as operand and carries out address arithmetic, and operation result outputs to a page interior address bus, and is written back to address register.The present invention is respectively by address register u, v, and address bus u in the address bus called after page or leaf in the page or leaf that comes of w computing, v, w, as the low portion of address bus, the width of corresponding address register, an addressing space is the 2^32 byte in the page or leaf; In SRAM, corresponding three address register u, v, w have specified three page register PageU that width is the n bit, PageV, PageW respectively as the high-order portion of address bus, is used for the page addressing of 2^n; When instruction is carried out, the command decoder translation instruction generates control signal, and control is from three address register u, v, w selects one to carry out address arithmetic as address bus in the page or leaf, selects the corresponding page register from three page registers, carry out page addressing, the coupling of address bus and corresponding page register forms the addressing capability of (2^32) * (2^n) byte as 32+n bit address bus in the page or leaf, finishes the addressing of data space.The optimum implementation of the multi-functional register file of the present invention is to be that organization unit constitutes three groups of independently 16 bit address registers with 16 bit words forms, form three independently 16 interior address pointers of page or leaf, the low 64K byte in visit data space, this 64K byte is called the page, and outside paging register width can dispose as required, several pages of addressing, each page are the 64K byte, divide page register that the page by 16 bit register addressing is together in series and form bigger data space.These characteristics make 8 MCU that unprecedented addressing space arranged, and in theory, as long as divide the width of page register enough big, data space can be unlimited.Such as, when minute page register was 4, storer can be divided into 16 pages of 64K, the i.e. RAM of 64K*16=1M byte; And when dividing page register to be 8, storer can be divided into 256 pages of 64K, i.e. the RAM of 64K*256=16M byte.Certainly, divide page register whether carry is arranged, determine whether to carry out page turn over operation by the operation result of judging 16 bit address pointer registers.Needs according to commercial Application, best applications of the present invention is three branch page registers of design, and three 16 bit address registers with multi-functional register file are coupled respectively, form three address pointers, write down three data locus, be used for matrix operation and the control of other audio, video datas easily.
Described command decoder unit as shown in Figure 4.
With reference to Fig. 4, command decoder comprises universal command code translator, bit operating determining device, bit steady arm three parts.The decoding that the universal command code translator is responsible for instructing generates control signal; The bit operating determining device judges whether to be the bit dependent instruction, determines whether that a bit enable signal puts 1; The bit steady arm is determined the bit position.Such decoding architecture, allowing increases various bit operating instructions in instruction set, put 1 as bit, the bit zero clearing, bit is read, bit writes, and bit is replaced, bit decision transfer etc., these instructions can be finished the bit operation of register a clock period, need not complicated the register conversion and the packing of orders, greatly facilitate writing of program, saved operation time.This batch instruction has BTRAN, BSET, BCLR and BCHN, and after bit operating enabled, the bit steady arm was logical to some bit information decodings in the instruction, carry out the bit decoding location, the bit information that comprises in the instruction is deciphered, is determined the bit position, finish following several bit operating:
(1) generates the bit location code of demarcating with " 1 ", as 0000_1000, with universal arithmetic logic unit ALU-1 combination, be sent to universal arithmetic logic unit as an operand, another operand is for carrying out the register of bit operating, universal arithmetic logic unit ALU-1 carries out inclusive-OR operation, and that finishes the register bit position puts 1;
(2) generate the bit location code of demarcating with " 0 ", as 1111_0111, with the combination of ALU unit, be sent to ALU as an operand, another operand is for carrying out the register of bit operating, universal arithmetic logic unit ALU-1 does AND operation, finishes the zero clearing of register bit position;
(3) generate the bit location code of putting " M " demarcation with the bit that needs transmission, as 0000_M0000, with the combination of ALU unit, be sent to universal arithmetic logic unit ALU-1 as an operand, another operand is for carrying out the register of bit operating, ALU is done inclusive-OR operation, and the numerical value of finishing register M position transmits, and numerical value " M " writes the position that M demarcates;
(4) generate the bit location code of demarcating with " 1 ", as 0000_1000, with the universal arithmetic logic unit combination, be sent to ALU as an operand, another operand is for carrying out the register of bit operating, ALU carries out AND operation, reads in the register and is demarcated bit value.
Above-mentioned four kinds of bit operatings and the bit of deriving instruct and bring great convenience to programmed control, use these instructions, the programmer can control to each bit of register very easily, has both reduced the difficulty of programming, improve the operational efficiency of program again greatly, saved the program space.
In addition, the bit operating determining device is also finished the program redirect by bit control, finishes the execution of jump instruction, comprising: JbEQ, JbNQ, JbGE, JbSE.Command decoder is deciphered instruction, signal is judged in the control signal and the redirect that generate redirect, the bit steady arm compares certain bits, selected bit put 1 or put 0 and determine whether redirect as the redirect enable signal, when selected bit is identical with agreement, redirect enables, redirect control signal control program counter is done the biasing computing, reposition after the sensing redirect, current instruction of reading in order register abandons and will not carry out, carry out from the decoding of reposition reading command again, at this moment, this jump instruction occupies two clock period; When selected bit and agreement not simultaneously, redirect does not enable, the programmable counter sequential counting, instruction decode in the order register is carried out, this jump instruction occupies a clock period.Jump instruction does not influence the value of status register.
Described programmable counter as shown in Figure 5.
With reference to Fig. 5, programmable counter is made up of counter and arithmetical unit.The preferred plan of counter is by 23 bit register configuration program pointers, forms the addressing capability of 16M byte; Arithmetical unit is realized add-one operation and redirect skew computing, and counter is corresponding to be finished sequential counting and shift counting.When instructions such as execution arithmetical logic, bit computing and memory access, arithmetical unit adds 1, counter is made sequential counting, when carrying out some branch transition instructions, programmable counter needs redirect, arithmetical unit carries out redirect skew computing, calculates the destination address of wanting redirect, and counter is finished and shifted counting.The programmable counter module can be finished unconditional jump instruction, subroutine call link order, register holds/recovery instruction.This unconditional jump instruction comprises: RGO, IGO and GO.Command decoder judges that the instruction of reading in is the unconditional jump instruction, generate control signal, the computing of setovering of control program counter, program pointer points to the reposition after the redirect, current instruction of reading in order register abandons and will not carry out, carry out from reposition reading command again, this batch jump instruction occupies two clock period.This subroutine call/link order comprises: RCALL/PCALL/CALL, RET/RETI.Command decoder judges that the instruction read in is subroutine call instruction, generates control signal, and the content of programmable counter is saved in stack pointer data designated space according to from low to high order, and this space is called storehouse.Stack pointer changes accordingly, points to next stack position, and programmable counter carries out the redirect computing then, jumps to new position---the entry position of subroutine, and reading command is carried out, and the content of reading in order register originally abandons, and will not carry out.The performance period of this instruction when programmable counter is three bytes, needs three clock period by the length decision of programmable counter, when length is four bytes, needs four clock period.The RET/RETI subroutine return instruction is the link order of subroutine call instruction, and after subroutine was carried out end, subroutine was returned original father's program, needs to recover the entry position of subroutine in father's program this moment.Command decoder decoding link order, generate control signal,, one by one the program pointer value that was kept at originally in the storehouse is read from the stack position of stack pointer appointment, from high to low, write back programmable counter, the position before the program return jump, reading command again, decipher, carry out, and subroutine is read in the instruction of order register before returning and is abandoned and will not carry out, the corresponding travelling backwards of stack pointer.The performance period of this instruction is determined by the length of programmable counter equally.This register holds/recovery instruction comprises: PUSH/POP, wherein: PUSH instruction is used for being kept at needs the content of registers of preserving in the program process, when carrying out this instruction, command decoder generates control signal, the content of register is preserved by the stack position that 8 bit data bus are sent to the stack pointer appointment, and stack pointer points to next stack position; POP instruction is used for the content of the register that recovers to preserve in program process, when carrying out this instruction, command decoder generates control signal, the content of the original register of preserving is read from the stack position of stack pointer appointment, write back to the register of appointment by 8 bit data bus, register data recovers, stack pointer corresponding modify, stack position of travelling backwards.
Concrete application example of the present invention is the application in the microcontroller XD0308-E of e-book, as shown in Figure 6.
With reference to Fig. 6, in the microcontroller XD0308-E of e-book, general-purpose register is designed to 16 8 bit register, and the corresponding address space is 0x0000～0x000F; Universal arithmetic logic unit ALU-1 finishes 8 bit arithmetic logical operations and bit computing; Multi-functional register file design is 16 8 bit register, and the corresponding address space is 0x0010～0x001F, with the visit of 8 bit byte bandwidth-version, perhaps visits with 16 bit words bandwidth-version.When visiting with 16 bit words forms, then begin with even address, and can be organized into three 16 bit addresses register form, form the interior addressing space of page or leaf of 64K byte, specifying in SRAM has 10 branch page registers, and address register and branch page register constitute the data space addressing capability of 2^10*2^16=64M byte.Multi-functional arithmetic logic unit alu-2 is designed to 16 ALUs, plus-minus method, the data that can finish 16 in a clock period shift, exchanges data, " with ", " or " etc. arithmetical logic operation, also can be in the automatic computing of the location simultaneously of addressing, need not specialized instructions modified address pointer, save instruction execution cycle, improve operation efficiency.Command decoder is responsible for instruction decode, generate control signal, generation is to general-purpose register, multi-functional register file, universal arithmetic logic unit ALU-1, the operation control of unit such as multi-functional arithmetic logic unit alu-2, wherein whether the instruction of bit operating determining device arbitration in order register contains bit operating, the bit steady arm compares certain bits, the definite bit position that will operate, the bit arithmetical unit that universal arithmetic logic unit ALU-1 is provided with carries out the bit computing, in the read-write of finishing the optional position bit of register in a clock period.Should be with in the example, the operating process of this controller is: controller resets-the programmable counter zero clearing-from program area reading command-instruction temporary/programmable counter adds 1-the write-back of instruction decode-generation control signal-mask register heap-selection ALU unit-execution computing-as a result-read next bar to instruct.When adopting the 0.18um processes, the XD0308-E arithmetic speed of this works can reach 200MIPS, and promptly per second can be carried out the instruction of 200M bar; 16 bit arithmetics, the execution speed of complicated orders such as any D-bit modification of register reaches 1.0IPC, be per clock period to carry out 1 instruction, arithmetic capability is greatly improved, processing power is traditional more than 100 times of CISC structure 8 8-digit microcontrollers 8051, can fully satisfy application such as Ebook, MP3, handwriting pad.
Example of the present invention carries out programming and testing to print and can draw following data by actual flow:
(1) should compare with the performance of instance X D0308-E and other products of market as table 2:
Table 2 XD0308-E compares with the performance of existing other products
| Title | Architecture | Instruction cycles | Program's memory space | Data space | Highest running speed | |
| 80/89C51 series | CISC | 3-23 | 1K～64K | 128B~4K | 24MHz | |
| Eight series of | RISC | 1 | 4K~96K | 128B~8K | 24MHz | |
| | RISC | 1 | 4K~128K | 512B~64K | 12MHz | |
| XD0308- | RISC | 1 | 32MB | 64MB | 200MHz |
By table 2 as seen, the XD0308-E arithmetic speed is the fastest, and its maximum operation frequency is more than 15 times of AVR series, is eight series of PIC, 80/89C51 series 8 times; The XD0308-E program space is more than 200 times of other microprocessor, and data space is 1000 times of other microprocessor, can satisfy electronic dictionary, e-book, MP3 etc. very easily and use high handling property, the requirement of data space greatly.
(2) should compare as table 3 with the demand and the handling property of the instance X D0308-E and the program space of existing 8-bit microprocessor when voice applications.
The performance of table 3 XD0308-E and existing 8-bit microprocessor relatively
| Title | Program size (KB) | Frequency of operation (MHz) | Working time (μ S) | Power consumption (mW) |
| 80/89C51 | 112 | 24 | 391 | 16 |
| PIC16C74 | 87 | 20 | 125 | 13.5 |
| AT90S8515 | 46 | 8 | 42 | 11.5 |
| XD0308-E | 29 | 8 | 20 | 9.5 |
As can be drawn from Table 3 to draw a conclusion:
(1) processing speed of the XD0308-E microprocessor of 8MHz is equivalent to the processing speed of the 89C51 microprocessor of 235MHz;
(2) the XD0308-E processing speed of 8MHz exceeds 6.25 times than the PIC1616C74 speed of 20MHz;
(3) under identical frequency of operation condition, the power consumption of XD0308-E is lower by 1/5th than AVR, and program space demand is little by 1/3rd.
Above comparing data shows, adopt XD0308-E of the present invention designing program, when particularly the audio frequency relative program designed, code efficiency was very high, faster than PIC, AVR series microprocessor on speed, then lower on the power consumption than PIC, AVR series microprocessor, can be widely used in personal digital terminal PDA, e-book, electronic dictionary, handwriting pad, MP3, fields such as Industry Control.
For those skilled in the art; after having understood content of the present invention and principle; can be under the situation that does not deviate from the principle and scope of the present invention; the method according to this invention is carried out various corrections and the change on form and the details, but these are based on correction of the present invention with change still within claim protection domain of the present invention.
Claims (9)
1. double arithmetic logic units reduced instruction set computer 8 8-digit microcontrollers, comprise: program bus, program storage, program pointer, stack pointer, static RAM SRAM, general-purpose register, universal arithmetic logic unit ALU-1, multi-functional register file, multi-functional arithmetic logic unit alu-2, status register, command decoder, data bus, address bus is characterized in that:
(1) general-purpose register and universal arithmetic logic unit ALU-1 are connected with multi-functional register file and multi-functional arithmetic logic unit alu-2 side by side, this multi-functional register file is used to finish 8 bit data and adds up, the spread bandwidth data accumulation, functions such as data space address pointer, and, preserve its operation result for multi-functional arithmetic logic unit alu-2 provides operand; This multi-functional arithmetic logic unit alu-2 is used to finish arithmetic logical operation, address arithmetic and 8 arithmetic logical operations of spread bandwidth;
(2) be provided with bit steady arm and bit operating determining device in the command decoder, this bit steady arm is used for the bit operational order is done to determine the bit position than certain bits computing; This bit operating determining device is used for judging whether the instruction of present instruction code translator is the bit operating instruction, determines whether that a bit operating enable signal puts 1;
(3) be provided with the bit arithmetical unit among the universal arithmetic logic unit ALU-1, be used to finish bit operating, promptly carry out bit and read instructions such as BTRAN, bit set BSET, bit zero clearing BCLR and bit rewriting BCHN.
2. microcontroller according to claim 1, the structure that it is characterized in that multi-functional register file is a dual port RAM, promptly has two output ports and two input ports; The output data of described two output ports is delivered to the input port of multi-functional arithmetic logic unit alu-2, and as the input option of multi-functional arithmetic logic unit alu-2, data bandwidth equals spread bandwidth; Described two input ports, one is the wide input ports of 8 bit strips, is connected to 8 bit data bus, one is the spread bandwidth input port, connects the output port of multi-functional arithmetic logic unit alu-2.
3. microcontroller according to claim 1 and 2, the output port address that it is characterized in that multi-functional register file is controlled by command decoder, from command decoder, address register, select, the address of 8 input ports determines that by command decoder the address of spread bandwidth port is an address register.
4. microcontroller according to claim 1 and 2, the mode of operation that it is characterized in that multi-functional register file has three kinds, the one, the byte mode of operation is a unit access with the byte, finishes the exterior read-write of general-purpose register function and multi-functional register file; The 2nd, the multibyte mode of operation is a unit access with the multibyte, is used to cooperate multi-functional arithmetic logic unit alu-2 to finish the arithmetic logical operation of multibyte spread bandwidth; The 3rd, the counter works pattern as address register, is finished the address pointer computing.
5. microcontroller according to claim 1, it is characterized in that multi-functional arithmetic logic unit alu-2, when carrying out the spread bandwidth arithmetic logical operation, two operands are arranged, one is the destination operand as multi-functional register file output, another is the source operand of being chosen from multi-functional register file, constant, 8 bit data bus by command decoder, and the result of described two operand computings is outputed to multi-functional register file.
6. microcontroller according to claim 1, it is characterized in that multi-functional arithmetic logic unit alu-2 carries out address arithmetic, be when the instruction of command decoder decoding is the access instruction of static RAM SRAM, by the control signal of command decoder decoding at first with arithmetic logic unit alu-2, be configured to the address arithmetic device, multi-functional register file is configured to address register, then when arithmetic logic unit alu-2 is carried out this access instruction, that finishes the address register content automatically adds 1, pass 1 or the numerical operation of plus-minus command decoder appointment, and operation result is write back described address register.
7. microcontroller according to claim 1, it is characterized in that the bit steady arm does than certain bits computing the bit operational order, at first the bit position information that comprises in the bit operating instruction is deciphered, demarcate the bit position that to carry out bit operating with unique 0 or 1, by the control of bit operating enable signal this bit position information is loaded into data bus then.
8. microcontroller according to claim 1, it is characterized in that it is to generate control signal by command decoder that the bit arithmetical unit is finished bit operating, determine the register that to operate and the bit position that is loaded into data bus, as two operands of universal arithmetic logic unit ALU-1, and control universal arithmetic logic unit ALU-1 carries out logical operation to these two operands and finishes bit operating.
9. microcontroller according to claim 1 is characterized in that multi-functional register file and multi-functional arithmetic logic unit alu-2, is connected with universal arithmetic logic unit ALU-1 with general-purpose register by data bus.
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| CN103186977B (en) * | 2011-12-30 | 2016-02-03 | 无锡华润矽科微电子有限公司 | The circuit structure that remote signal firing order controls is realized in microprocessor |
Family Cites Families (2)
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|---|---|---|---|---|
| US5931941A (en) * | 1995-04-28 | 1999-08-03 | Lsi Logic Corporation | Interface for a modularized computational unit to a CPU |
| EP0942359B1 (en) * | 1998-02-19 | 2012-07-04 | Lantiq Deutschland GmbH | An apparatus for executing instructions of a program |
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