CN1203402C - System architecture of 16 bits microprocessor - Google Patents

Abstract

The present invention discloses a 16-bit microprocessor, particularly a 16-bit RISC microprocessor based on an accumulator. Universal embedded type peripheral controllers, such as a timer, an interrupt controller, a universal asynchronous serial port, a universal synchronous serial port, a double-port RAM controller, etc. are integrated on a chip. A four-stage pseudo pipeline structure is adopted, and all instructions are single-word single-cycle instructions. Working frequency is 16MHZ, and 16-stage interrupt is supported. Both of the internal data and an address bus of an LS-IPU16 microprocessor are 16 bits, and the LS-IPU16 microprocessor comprises a program code bus, a data bus and a register bus. The buses are mutually independent, and the mutual transmission of data can be realized in a single cycle. A register of the LS-IPU16 microprocessor comprises 64 internal registers and 64 external registers. The 64 external registers can be used for I/O channel expansion, and I/O controllers, such as the internally integrated timer, the interrupt controller, etc. are all accessed from an expansion register. When the LS-IPU16 is used as an auxiliary processor of a main processor, a double-port RAM is adopted between the LS-IPU16 and a main CPU in a system so as to realize the exchange of data and commands.

Description

A kind of system architecture of the microprocessor of 16 bit

One, technical field

The invention belongs to field of computer technology, relate to a kind of design and manufacturing of microprocessor, particularly a kind of system architecture of the microprocessor of 16 bit.

Two, background technology

Microprocessor is the important core part that realizes control in present electronics, the electric equipment.Because its volume is little, easily expand, characteristics such as cost is low are widely used in all kinds of control system.Present microprocessor generally has 8,16 and 32 s'.

Common 8-bit microprocessor is the center with controller and arithmetical unit, has following shortcoming:

(1) the whole system operation efficiency ratio is lower.

(2) instruction sequences is carried out, and the instruction strip number of finishing in the unit interval is few, can not satisfy the Industry Control of fair speed or the demand of other control system.

(3) command function is simple, has limited it in much application of fields and environment.

(4) precision of deal with data is not enough.Data width has only 8, and with comparing of 16 or 32, the precision of deal with data differs greatly, and is difficult to realize accurately handling fast data.

The present microprocessor of 16 bit generally adopts the CISC structure, also has more shortcoming:

(1) order set is huge, the function complexity, and addressing mode, order format disunity make that the controller hardware of decoding, analysis and the execution finish instruction is very huge.Be unfavorable for the employing of design automation technology, prolonged the design cycle, increased design cost, increase the chance that mistake occurs, reduced the reliability of system.

(2) instruction manipulation is numerous and diverse, and execution speed is low.

(3) code density height, program compiler are difficult to optimize compiling and generate the real efficient machine language program.

(4) general-purpose register is not general veritably, the instruction that has can only be used several registers of appointment, the register that has must spare them could move into the data that will use, and this has just increased unnecessary data and has transmitted number of times, makes the optimum management of general-purpose register complicated.

(5) the hardware complexity of realization CISC.

Facts have proved, when the architecture of computing machine when the CISC direction develops, the order set of bulky complex not only implements more and more difficultly day by day, in fact also might reduce the performance of total system, has also reduced the ratio of performance to price of system.

For overcoming the shortcoming of CISC, the function that reduces total number of instructions and reduction instruction reduces the complexity of hardware design, improves the execution speed of instruction, and people have been developed the RISC computing machine.What adopt risc architecture at present generally is 32-bit microprocessor, adopts the very dark flowing water degree of depth, mainly contains following shortcoming:

(1) target of risc architecture is: be used in the VLSI slice, thin piece realize that the shared ratio of this part area of controller significantly reduces.Like this, can abdicate more area in the VLSI slice, thin piece of risc architecture, reduce design cost, be beneficial to realize one-chip CPU as setting up or enlarging main memory, input/output end port usefulness.The degree of depth of streamline is more than three grades, and what have has reached seven grades.Because the output result of each pipelining-stage will be temporary in the corresponding streamline buffer register, need a large amount of hardware resources to support.Progression is too much, and it is meticulous to operate, and has all increased the hardware spending of system, has improved design cost, and this runs counter to the target that adopts risc architecture.

(2) the streamline conflict comprises the relevant conflict of control, data dependent hazard and shifts relevant conflict.Execution efficient to RISC has very large influence.For this reason, very complicated algorithm and a large amount of hardware solve various collision problems, make the design of processor complicated.Can not adapt to the requirement of low-end applications.

Three, summary of the invention

Defective or deficiency at above-mentioned prior art exists the objective of the invention is to, and a kind of arbitration body that reduces instruction bus and data bus is provided, raising speed, the system architecture of a kind of microprocessor of 16 bit of reduction design complexities.

The microprocessor of 16 bit of realizing the foregoing invention purpose is 16 risc microcontrollers based on totalizer; It comprises:

One Bus Interface Unit, this Bus Interface Unit contains a host interface controller, an IPU16 interface controller and a two-port RAM controller, host interface controller is used to handle from the visit of primary processor to memory bus, the IPU16 interface controller is used to handle from the visit of IPU16 processor for memory bus, the two-port RAM controller is arbitrated the memory bus visit of primary processor and the memory bus visit of IPU16 processor, and the IPU16 processor has right of priority to the visit of memory bus; In the two-port RAM controller, also comprised storer EDAC module, this EDAC module has memory data EDC error detection and correction ability, when this microprocessor of 16 bit during, adopt dual port RAM to realize the exchange of data and order between the primary processor in it and the system as the auxiliary processor of primary processor; Whole storage space of this IPU16 processor all can be by main processor accesses;

One control module comprises programmable counter PC, gets and refer to that unit, order register IR, command decoder, control signal form parts in the control module; Said procedure counter PC, get and refer to that unit, order register IR, command decoder, control signal form parts and connect successively;

One processing unit, processing unit comprise 64 internal registers, and wherein 56 is that inner general-purpose register, 8 are special registers; 8 special registers are respectively accumulator registers ACC, program status word register PSW, temporary register T, SP SP, version register VR and 3 reservation registers; Processing unit has also comprised register controller, arithmetic logical unit ALU, shift unit and data path controller; Wherein inner general-purpose register is communicated with register controller, and arithmetic logical unit ALU is communicated with accumulator registers ACC, and is communicated with data path controller by shift unit, and shift unit is communicated with program status word register PSW;

Be connected with interruptable controller PIC, synchronous serial ports controller SYNC, general parallel port controller GPIO, general asynchronous serial port controller UART, timer/counter Timer on the register bus; They can be used as the external register access that the expansion of I/O passage is used by 64, and they are communicated with the register controller of processing unit by register bus respectively;

The two-port RAM controller of Bus Interface Unit is communicated with by external bus and external memory storage, its IPU16 interface controller is communicated with by the data path controller of inner data bus and processing unit, and refers to that by getting of program code bus and control module the unit is communicated with;

The register controller of processing unit, arithmetic logical unit ALU, accumulator registers ACC, program status word register PSW, temporary register T, SP SP are communicated with data path controller by internal bus, and and the programmable counter PC of control module and order register IR be communicated with;

Wherein, this microprocessor adopts the pseudo-flowing structure of level Four, and all instruction is the individual character one-cycle instruction, and frequency of operation is 16MHZ, supports 16 grades of interruptions;

Microprocessor internal data and address bus are 16, comprise separate program code bus, data bus, register bus, can realize the mutual transmission of data in the monocycle;

Storer and general-purpose register interface adopt the EDAC scheme.

Microprocessor of 16 bit structure of the present invention has following advantage:

(1) microprocessor adopts the Harvard structure, and instruction bus and data bus are separated, and has reduced the arbitration body of instruction bus and data bus, has improved speed, has reduced design complexities.Simplify internal logic, reduced area of chip.

(2) embedded I/O controller has been included counter, interruptable controller, parallel port, asynchronous serial port, synchronous serial interface, has satisfied the conventional demand in the control.

(3) microprocessor and outside input and output are with 8 or 16 communications, and microprocessor internal is handled with 16, thereby can realize 16 processing to 8 peripheral hardwares.

(4) integrated dual port RAM controller is supported master-salve distributed application, has reduced the outer hardware resource requirement of sheet, has reduced the application and development cost, has shortened the construction cycle.

(5) have storer EDAC function, can detect the data mistake more than 2, correct 1 data mistake, be supported in the highly reliable application of space environment.

(6) complete 16 high speed MEM-CPU bus.

(7) microprocessor can offer nearly 56 general-purpose registers of user, has reduced the number of times of reference-to storage, has improved data-handling efficiency.

(8) totalizer in the arithmetical unit adopts " parallel carry look ahead produces circuit ", has improved the speed of arithmetical unit.

(9) system has dormant state, when dormant state, stops every operation, and system clock also can be static, reduced the power consumption of CPU widely.

(10) microprocessor adopts the SOC technology, is a kind of form that realizes embedded system, makes the conditional electronic system enter contemporary electronic systems comprehensively.Embedded computer has characteristics such as volume is little, compact conformation, reliability height, often can be operated under the harsh conditions.

(11) microprocessor adopts the RISC architecture, and order format is regular, and all instruction is the monocycle.Simplified the design of controller greatly, improved the reliability of system, be fit to VLSI (very large scale integrated circuit) and realize.

(12) order set comprises 37 instructions of 5 classes, it is simple relatively to seek how, make the decoding of controller relative simple with execution hardware, use the hard wire steering logic, be used to realize that the shared ratio of this part area of controller obviously reduces, abdicate more area, also can enlarge the throughput that the register number improves CPU as setting up main memory, input/output end port usefulness, strengthen the regularity of slice, thin piece, reduce design cost.

(13) adopt pseudo-level Four flowing structure.Use two physics pipelining-stages, realized the level Four flowing water of instruction, developed the advantage of risc architecture; In order to strengthen command function, utilize the order number space as much as possible, some instruction can realize two or more functions, has absorbed the elite of CISC structure.

(14) microprocessor can soft kernel form provide, and compare the wiring area with conventional 16 microprocessors little, and the SOC design that control is used to low side provides good support.

Four, description of drawings

Fig. 1 is a microprocessor of 16 bit architectural schematic of the present invention;

Fig. 2 is that the instruction of the microprocessor of 16 bit is got finger, decoding and carried out sequential chart.

Five, embodiment

For a more clear understanding of the present invention, below in conjunction with the specific embodiment that accompanying drawing and inventor provide, LS-IPU16 microprocessor system structure, the present invention is described in further detail.

The LS-IPU16 microprocessor is mainly used in the intelligent management to input/output interface as 16 I/O processors of an intelligence.Also can use as a microprocessor separately, or use as the auxiliary processor of primary processor.

The LS-IPU16 microprocessor is 16 risc microcontrollers based on totalizer, integrated general-purpose built-in type peripheral control units such as timer Timer, interruptable controller PIC, general asynchronous serial port controller UART, synchronous serial ports controller SYNC, general parallel port controller GPIO, dual port RAM controller on the sheet.Adopt pseudo-level Four flowing structure, all instruction is the individual character one-cycle instruction, and frequency of operation is 16MHz, supports 16 grades of interruptions.

LS-IPU16 microprocessor internal data and address bus are 16, three buses have been comprised, be respectively program code bus Code Bus, data bus Data Bus, register bus Register Bus, these three buses are separate, can realize the mutual transmission of data in the monocycle.The register of LS-IPU16 microprocessor comprises 64 internal registers, 64 external registers; Internal register is divided into: 8 special registers, 56 general-purpose registers; 64 external registers can be used as the expansion of I/O passage and use, and I/O controllers such as inner integrated timer, interruptable controller all insert from this extended register.

When LS-IPU16 microprocessor during, adopt dual port RAM to realize the exchange of data and order between the host CPU in it and the system as the auxiliary processor of primary processor.LS-IPU16 inside has comprised a double port memory controller, and all storage space all can be visited by host CPU.

The system architecture of LS-IPU16 microprocessor is referring to Fig. 1;

Controller core LS-IPU16 Core is that the core of LS-IPU16 microprocessor is formed, and is one 16 8-digit microcontroller.It is made up of control module LS-IPU16Controller, processing unit LS-IPU16Processor, register file and Bus Interface Unit BIU (Bus Interface Unit) four parts, as shown in Figure 1.It supports 37 instructions of following 5 classes, and instruction all is the individual character one-cycle instruction.

A, count loads immediately

1. number → internal register immediately

B, data transmit the class instruction

1. internal register register

2. internal register storer

3. stack manipulation: comprise pop down and pull instruction

C, the instruction of arithmetic logical operation class

In order to improve the speed of multiplication iteration, shifting function is additional to after the arithmetic logical operation.

1. add " 1 " instruction

2. subtract " 1 " instruction

3. addition or bring into the position addition

4. subtraction or bring into the position subtraction

5. logical and

6. logical OR

7. logic XOR

8. Boolean complementation

9. displacement

10. byte exchange

D, the instruction of transfer class

1. unconditional transfer/call

2. register shifts/calls

3. conditional transfer

E, miscellany instruction

1. ON/OFF interrupt instruction

2. remove the instruction of break in service sign

3. remove the instruction of storehouse overflow indicator

4. stop instruction

5. soft interrupt instruction

6. NOP instruction

7. link order

The control module of LS-IPU16 microprocessor is finished functions such as getting finger, decoding, register and memory access request and reference address generation, is the important component part in the microprocessor.System clock, systematic reset signal generator are arranged in the control module of LS-IPU16 microprocessor.Under the normal condition, system clock is produced by the source clock signal that impulse source produces; When system was in dormant state, system clock was static, but can be waken up by interruption, for system provides synchronous clock.Systematic reset signal is asynchronous clear ' 0 ' by the source reset signal, and is effective synchronously by system clock.The LS-IPU16 microprocessor adopts flowing water mechanism, and next the bar instruction that carry out always is prefetched among the order register IR in advance.Get the finger unit and also will keep an instruction address register PC, getting of holding instruction refers to the address, and it always points to the address of instruction in storer that next bar will be carried out, and is 0 after this register resets, and promptly program is carried out since 0.After taking out an instruction, in decoding, also to finish PC is added 1.Then do not get new instruction of finger unit latches if there is when transfer, and PC is added 1 automatically.When take place shifting, the controller notice is got and is referred to the cancel instruction of current taking-up of unit, PC is not added 1.At this moment controller also can be controlled to get and refer to the next machine cycle of unit with the output of ALU (ALU) PC that packs into, thereby realizes shifting.

Because the LS-IPU16 microprocessor has adopted pseudo-level Four flowing structure, getting of instruction refers to that decoding and execution walk abreast, and promptly will carry out an instruction in a machine cycle, also will finish getting of next bar instruction simultaneously and refer to and decoding.As shown in Figure 2.

Bus Interface Unit BIU is the interface of LS-IPU16 microprocessor and main frame and external memory storage.The signal sequence that the memory bus controller provides the outside can satisfy general EPROM, PROM and SRAM to be used, and output data has retention time more than the 5ns to write signal.BIU is used for realizing primary processor and the LS-IPU16 microprocessor data access for external storage.An IPU interface controller, host interface controller and two-port RAM controller have been comprised among the BIU.Host interface controller is used to handle from the visit of primary processor to memory bus, the IPU interface controller is used to handle from the visit of LS-IPU16 processor for memory bus, the two-port RAM controller is arbitrated the memory bus visit of primary processor and the memory bus visit of LS-IPU16 processor, and the LS-IPU16 processor has right of priority to the visit of memory bus.Generally speaking, i.e. the discontinuous execution twice storage of LS-IPU16 device operational order, main frame is waited for an instruction cycle at most.Also comprised storer EDAC module in the two-port RAM controller, this EDAC module has memory data EDC error detection and correction ability.By parameter is set, whether the use of configurable EDAC function, when using this function, can detect 1～2 dislocation to 16 bit memories, corrects 1 dislocation.This function also makes the LS-IPU16 microprocessor be different from the microprocessor of general simple functions.

The LS-IPU16 microprocessor is supported 128 registers, is made up of register file and extended register two parts.Wherein register file is made up of 64 16 bit registers, and extended register is made up of 64 16 bit registers.64 register files are divided into 8 special registers and 56 general-purpose registers, and the address is respectively 0～7, and 8～63.64 extended registers can be used as input/output port and use.8 special register: accumulator registers ACC, SP SP, temporary register T, program status word register PSW, version register VR and three reservation registers.The address is respectively that the address of 0,1,2,3,7, three reservation register is respectively 4,5,6.

Accumulator registers ACC is except that using as general register, also as a default data source and target register of operational order.Program status word register PSW is used for writing down some signs of computing as zero flag, carry flag, overflow indicator, shift-out bit sign etc.Data splicing when realizing with 8 outside input-output device communications, temporary register T only allows to write least-significant byte usually, is realizing exchange instruction (SWAP) or playing stack instruction (POP) Shi Caike to write most-significant byte.Version information register VR, the version number of depositing this microprocessor is fixed value 5 at present.Everybody of flag register PSW is defined as follows:

The definition of PSW register: D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0

?SO

IS

IE

?BF

OF

?CF

?ZF

ZF: the last result calculated is zero;

CF: the last result calculated has carry;

OF: the last result calculated is overflowed;

BF: the last result calculated displacement output;

IE: interrupt enabling, ' 1 ' for allowing interruption, and ' 0 ' for not allowing;

IS: the break in service sign, ' 1 ' for just in break in service, hardware set, software is removed;

SO: the storehouse overflow indicator, ' 1 ' expression is overflowed, hardware set, software is removed.

SP SP is used for depositing stack pointer, pop down with play stack instruction with its addressing of address as storer.The least-significant byte of this register adds 1 automatically when carrying out the pop down instruction, carries out when playing stack instruction to subtract 1 automatically.When carrying out routine call or response interruption, the return address will be stored the indicated memory cell of SP into and SP will be added 1 automatically.When carrying out that routine call finishes or interrupt routine is finished and returning makes SP subtract 1 automatically.The output of stack register SP can be the value of SP register or the value of SP-1.When carrying out pop down, select SP output, select SP-1 when popping by control module.Also to control the SP new value of packing into simultaneously, in order to improve execution speed,, not use the totalizer in the arithmetical unit the adding one, subtract an operation of SP at the stack operation post-processing unit, and use oneself independently totalizer realize.

The processing unit of LS-IPU16 microprocessor is used to carry out the control command that control module sends and carries out arithmetic logical operation, and the data path in the microprocessor is effectively managed.Because this microprocessor will flow out an instruction two clock period, and integrated a plurality of general purpose I/O controller, therefore require this performance element execution speed fast, the area resource is used too much unsuitable.Processing unit is made up of register bus controller module, arithmetic logical unit ALU and data path controller module.

Supporting three kinds of registers owing to the LS-IPU16 microprocessor is actual: special register, general-purpose register and extended register, corresponding address is respectively: 0～7,8～63,64～127.For they are carried out unified management, be provided with register controller.For special register, the control module of LS-IPU16 microprocessor directly produces control signal to its step-by-step control or local control, and to the read-write of its whole word with the same to the control of general-purpose register, extended register, all conduct interviews by register controller.When the high-order Raddr (7) of 7 bit register address bus Raddr of processor core is ' 0 ', make the read/write signal of internal register effective, the read/write signal of external register is invalid; Otherwise, when the high-order Raddr (7) of Raddr is ' 1 ', make the read/write signal of external register effective, the read/write signal of internal register is invalid.And the register data bus of the data bus of internal register and extended register and processor core is connected, and low 6 of the register address bus of 6 bit address buses and processor core is connected.

Arithmetic logical unit ALU is the important component part in the processing unit, and it also has shift function except finishing arithmetic, logical operation function, and can be used as the part of data path.To ALU, all use combinational logic to realize.Arithmetic logical unit ALU is made up of two parts: arithmetic section and displacing part.Arithmetic section is wherein realized three kinds of functions: logical operation, arithmetical operation and transmitting function.The arithmetic logic unit completion logic with or, function such as non-, XOR; Arithmetic operation unit finish add, subtract, add with carry, carry subtract, add one, subtract first-class function; ALU also can be used as data channel, realizes the transmission of data.For arithmetical operation function and transmitting function, by transforming, simplifying, be merged into a kind of computing-addition, realize with a totalizer.In order to accelerate arithmetic speed, the totalizer among the ALU adopts the totalizer of " carry look ahead generation circuit " to realize.16 bit data are divided into 4 groups, and 4 every group, parallel in the group when carrying out additive operation, serial between group has been considered speed so on the one hand, has taken into account the resource area on the other hand.Also comprised a shift unit in the rear end of ALU, the shift mode signal of sending according to controller comes corresponding displacement is done in the output of arithmetic element, comprised move to left, move to right, ring shift left, ring shift right, the ring shift left of band displacement sign and the ring shift right of band displacement sign.

The data path controller module is used for the processor internal data is carried out gating, transmission and formed the internal system bus.The Data Source of LS-IPU16 microprocessor data path has: order register, ALU unit, programmable counter, SP, internal data input bus, register output data bus etc.The bus that forms has: internal address bus, internal data output bus, register data input bus.The control command that data path controller is sent according to controller, to importing data distribute data path effectively, the data-signal that needs keep is deposited with one 16 bit register MA, formed three big buses of internal system: address bus, data bus, register data bus.

Integrated two Timer in the LS-IPU16 microprocessor, 16 grades of interruptable controller PIC, one 16 general parallel port controller GPIO, synchronous serial ports controller SYNC and one road general asynchronous serial port controller UART, they reside in the register space of LS-IPU16, take register address 64～127.

General parallel port controller GPIO

General parallel port controller GPIO is 16 general bit parallel bi-directional digital amount IO mouths, and corresponding port PORTA15～PORTA0 can write down the past and present logic state of each port of PORTA respectively; Produce interrupt request in the time of can changing by the input state of programmed control in some input port; Also can will be from the logic state of each port output by programmed control.

Interruptable controller PIC

Interruptable controller PIC is used for discerning the interrupt request from outside and other embedded device, and priority queueing is carried out in these interruptions, sends look-at-me PICIntr to processor core CORE, and the vector of identification interrupt source is provided to CORE by INTV.When the processor core response is interrupted, obtain interrupt vector from INTV, send acknowledge interrupt to PIC simultaneously, PIC cancels PICIntr when acknowledge interrupt is effective, simultaneously corresponding interrupt request sign among the interrupt request register INTR is removed.This interruptable controller is supported 16 grades of interruptions, shielding able to programme, and priority orders is 0～15.

Synchronous serial ports controller SYNC

Synchronous serial ports controller SYNC defers to the SPI standard for the LS-IPU processor core provides a serial data interface logic, produces after receiving eight bit data and interrupts.It comprises the frequency dividing circuit of serial input and serial output and serial input shift clock.

General asynchronous serial port controller UART

General asynchronous serial port controller UART provides the asynchronous serial communication ability for LS-IPU16.Data are had transmission-receiving function, support the transmission of 7,8 bit data, the parity check system of control able to programme carries Baud rate generator.The parity check that can set when receiving data, frame integrity checking and data cover bug check, can produce interrupt request when mistake occurring.The function that is realized is compatible fully with 8250 counterparts except that not having the MODEM function.

Timer Timer

Timer TIMER comprises two 16 bit timings/counters (T0, T1) and a programmable pre-divider (T2).T0 and T1 adopt the working method with 82C54 pattern 1,2,3 compatibilities.T2 is one 4 a programmable counter, can realize 2～32 frequency divisions of IPU major clock are exported by different count values is set, and its output Pre_CLK can be as the work clock of T0, T1 and synchronous serial interface.

The LS-IPU16 microprocessor is as an IP (Intellectual Property) product, it is the processor that we develop voluntarily, can be applied in the robotization control in fields such as commercial production, business activity, scientific experiment and family life with embedding, it is integrated in processor core and I/O controller in the chip, realizes with SOC (SOC (system on a chip)) technology.

Of particular note:

(1) in order to realize, can increase memory register to storage protection.The memory bus controller according to the memory configuration register content to the memory fragmentation write-protect.When writing the protected field, will end write operation, and produce the write-protect interruption.If write is then to produce the write-protect interrupt request to Core from Core, if write request from primary processor, then produces the primary processor interrupt request, sign is that the memory write protection is interrupted in interrupt source register.

(2) the extensive work register to being provided with among the CPU adopts the overlapping register window technology.In order to reduce the memory access number of times, allow operating between the register of instruction carry out as far as possible, return on-the-spot required non-productive operation, the directly parameter transmission between implementation procedure and the process in order to reduce the invocation of procedure simultaneously.Allow each process use the register window of a limited quantity, and allow the register window of each process overlap.

(3) the interrupt priority level number of modification interrupt source increases confidentiality.

(4) the embedded type peripherals controller also can be done suitable abreviation, even fully phases out.

Claims (1)

1. a microprocessor of 16 bit is characterized in that, this microprocessor of 16 bit is 16 risc microcontrollers based on totalizer, and it comprises:

One Bus Interface Unit, this Bus Interface Unit contains a host interface controller, an IPU16 interface controller and a two-port RAM controller, host interface controller is used to handle from the visit of primary processor to memory bus, the IPU16 interface controller is used to handle from the visit of IPU16 processor for memory bus, the two-port RAM controller is arbitrated the memory bus visit of primary processor and the memory bus visit of IPU16 processor, and the IPU16 processor has right of priority to the visit of memory bus; In the two-port RAM controller, also comprised storer EDAC module, this EDAC module has memory data EDC error detection and correction ability, when this microprocessor of 16 bit during, adopt dual port RAM to realize the exchange of data and order between the primary processor in it and the system as the auxiliary processor of primary processor; Whole storage space of this IPU16 processor all can be by main processor accesses;

One control module comprises programmable counter PC, gets and refer to that unit, order register IR, command decoder, control signal form parts in the control module; Said procedure counter PC, get and refer to that unit, order register IR, command decoder, control signal form parts and connect successively;

One processing unit, processing unit comprise 64 internal registers, and wherein 56 is that inner general-purpose register, 8 are special registers; 8 special registers are respectively accumulator registers ACC, program status word register PSW, temporary register T, SP SP, version register VR and 3 reservation registers; Processing unit has also comprised register controller, arithmetic logical unit ALU, shift unit and data path controller; Wherein inner general-purpose register is communicated with register controller, and arithmetic logical unit ALU is communicated with accumulator registers ACC, and is communicated with data path controller by shift unit, and shift unit is communicated with program status word register PSW;

Be connected with interruptable controller PIC, synchronous serial ports controller SYNC, general parallel port controller GPIO, general asynchronous serial port controller UART, timer/counter Timer on the register bus; They can be used as the external register access that the expansion of I/O passage is used by 64, and they are communicated with the register controller of processing unit by register bus respectively;

The two-port RAM controller of Bus Interface Unit is communicated with by external bus and external memory storage, its IPU16 interface controller is communicated with by the data path controller of inner data bus and processing unit, and refers to that by getting of program code bus and control module the unit is communicated with;

The register controller of processing unit, arithmetic logical unit ALU, accumulator registers ACC, program status word register PSW, temporary register T, SP SP are communicated with data path controller by internal bus, and and the programmable counter PC of control module and order register IR be communicated with;

Wherein, this microprocessor adopts the pseudo-flowing structure of level Four, and all instruction is the individual character one-cycle instruction, and frequency of operation is 16MHZ, supports 16 grades of interruptions;

Microprocessor internal data and address bus are 16, comprise separate program code bus, data bus, register bus, can realize the mutual transmission of data in the monocycle;

Storer and general-purpose register interface adopt the EDAC scheme.