CN111198838B - Double-track signal asynchronous transmission link system - Google Patents
Double-track signal asynchronous transmission link system Download PDFInfo
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- CN111198838B CN111198838B CN201911392277.2A CN201911392277A CN111198838B CN 111198838 B CN111198838 B CN 111198838B CN 201911392277 A CN201911392277 A CN 201911392277A CN 111198838 B CN111198838 B CN 111198838B
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Abstract
The invention relates to a double-track signal asynchronous transmission link system, which comprises: a plurality of cascaded transmission modules; the transmission module includes: the asynchronous water station generates a transmission signal based on the received transmission signal and the feedback signal; the check unit generates a check signal based on a transmission signal sent by the asynchronous pipelining station; the error correction unit is used for correcting the error of the transmission signal generated by the asynchronous pipeline station based on the check signal sent by the check unit and sending the transmission signal after error correction to the asynchronous pipeline station or external receiving equipment of the next-stage transmission module; the detection unit sends out detection signals based on the check signals sent out by the check unit and the transmission signals sent out by the asynchronous flow station; the backward response unit sends a feedback signal based on the detection signal sent by the detection unit; the invention can tolerate 1 bit transient error on the double-track signal asynchronous transmission link, keeps the time sequence robustness, and has the characteristics of flexible configuration, high link utilization rate and small area overhead.
Description
Technical Field
The invention relates to the technical field of integrated circuits, in particular to a double-track signal asynchronous transmission link system.
Background
The continued development of semiconductor processes allows more and more transistors and metal lines to be integrated on a single chip, increasing processor performance. However, the performance of the processor cannot meet the rapidly increasing computing demand by simply depending on the process progress, and the problems of drastic increase of power consumption, diminishing returns and the like in designing complex single-core processors lead the industry to adopt multi-core design, and the multi-core technology becomes the main means for improving the performance of the current processor chip. The multi-core chip puts higher requirements on-chip interconnection, and needs to have the characteristics of high performance, low power consumption, high extensibility, high reliability and the like. Typical on-chip interconnects include conventional bus, point-to-point interconnects, network-on-chip, and the like. In a particular implementation, on-chip interconnect circuits are typically designed as pipelined structures to improve their performance. As the size of multi-core chips continues to increase, the challenges of designing on-chip interconnects in a synchronous pipeline manner will become more prominent, and asynchronous pipelines become an important choice for designing on-chip interconnects.
The core of the asynchronous pipeline is an asynchronous circuit. Different from a synchronous circuit, the asynchronous circuit has no global clock, adopts an asynchronous handshake protocol instead of communication between clock signal control modules, and has event-driven or data-driven characteristics, so that the problem of clock domain crossing caused by global clock distribution is avoided, the asynchronous circuit has the advantages of low dynamic power consumption, robust time sequence, good electromagnetic compatibility, good expansibility, modular design support and the like, and a series of problems and challenges faced by the traditional synchronous pipeline are effectively overcome.
In the aspect of fault-tolerant capability of a circuit, along with the great reduction of the size of a semiconductor process, the power supply voltage of a chip is continuously reduced, the clock frequency is continuously improved, the density of the chip is continuously increased, electronic devices are more sensitive to environmental changes, signal delay and instantaneous turnover are more easily caused by various noise sources, high-energy particle radiation and the like, time sequence errors caused by signal delay changes and instantaneous logic errors caused by signal error turnover are more greatly increased. These all have great negative effects on the reliability of the chip, and although fault tolerance has become an indispensable evaluation index for a chip or an integrated circuit with high importance, the number of fault tolerance technologies for asynchronous circuits is small, and fault tolerance technologies and methods for asynchronous circuits are still in a development stage. The asynchronous circuit and the asynchronous assembly line are easy to generate errors, the normal functions of the circuit and a chip are threatened, and the fault-tolerant capability is improved by using a fault-tolerant design, so that the fault-tolerant capability is important for the practical application of the asynchronous assembly line.
A quasi-delay insensitive asynchronous pipeline realized by using a 4-section handshake protocol and a double-track coding mode can effectively overcome time sequence errors, is very attractive to large-scale long-distance on-chip communication, but often shows a more complex fault scene in the presence of instantaneous errors, and a 1-bit instantaneous error can not only pollute data, but also overturn handshake signals, disturb or even destroy a handshake process, cause asynchronous pipeline deadlock, and seriously threaten the reliability of a system. The existing technical method for aiming at the instant fault tolerance of the asynchronous production line usually uses the fault tolerance technology of a synchronous circuit, so that the fault tolerance capability is obtained, the original timing robustness of the asynchronous production line is damaged, the fault tolerance capability and the timing robustness are difficult to obtain simultaneously, and the application range of the asynchronous production line is limited.
Disclosure of Invention
Aiming at the defects of the prior art, the invention aims to provide a double-track signal transmission link system which is low in complexity, expandable and capable of tolerating transient errors, simultaneously ensures the time sequence robustness and fault-tolerant capability of an asynchronous pipeline, and solves the problems of a quasi-delay insensitive asynchronous pipeline in the prior art.
The purpose of the invention is realized by adopting the following technical scheme:
the invention provides a dual-rail signal asynchronous transmission link system, and the improvement is that the system comprises: a plurality of cascaded transmission modules;
the asynchronous water station is used for generating a transmission signal based on the received transmission signal and a feedback signal; the received transmission signal is sent by an error correction unit of a previous transmission module or external sending equipment, and the feedback signal is sent by a backward response unit of a next transmission module or external receiving equipment;
the check unit is used for generating a check signal based on a transmission signal sent by the asynchronous flow station;
the error correction unit is used for correcting errors of transmission signals generated by the asynchronous pipeline station based on the check signals sent by the check unit and sending the transmission signals after error correction to the asynchronous pipeline station or external receiving equipment of the next-stage transmission module;
the detection unit is used for sending out a detection signal based on a check signal sent out by the check unit and a transmission signal sent out by the asynchronous flowing water station;
and the backward response unit is used for sending a feedback signal based on the detection signal sent by the detection unit.
Preferably, the asynchronous water flow station comprises: a first asynchronous latch, a second asynchronous latch, a third asynchronous latch, and a fourth asynchronous latch;
wherein each asynchronous latch comprises: a first C cell and a second C cell, each C cell comprising: a first input, a second input and an output;
the first input end of each C unit of each asynchronous latch is respectively connected with one output end of an error correction unit of the previous-stage transmission module or the output end of external sending equipment;
the second input end of each C unit of each asynchronous latch is connected with the output end of the backward response unit of the next-stage transmission module or the output end of the external receiving equipment;
and the output end of each C unit of each asynchronous latch is connected with the input end of the detection unit and the input end of the error correction unit.
Further, the verification unit includes: a first parity generator and a second parity generator;
wherein, the input end of the first check generator is connected with the output ends of the first asynchronous latch and the second asynchronous latch;
the input end of the second check generator is connected with the output ends of the third asynchronous latch and the fourth asynchronous latch;
the output end of each check generator is connected with the input end of the error correction unit and the input end of the detection unit.
Furthermore, each check generator is a double-rail adder composed of a seventh C unit, an eighth C unit, a ninth C unit, a tenth C unit, a seventh OR gate circuit and an eighth OR gate circuit;
the input end of each check generator is the input end of the seventh C unit, the eighth C unit, the ninth C unit and the tenth C unit;
the output end of each check generator is the output end of the seventh OR gate circuit and the eighth OR gate circuit;
the input end of the seventh OR gate circuit is connected with the output ends of the seventh C unit and the eighth C unit;
and the input end of the eighth OR gate circuit is connected with the output ends of the ninth C unit and the tenth C unit.
Preferably, the detection unit includes: a first or gate circuit, a second or gate circuit, a third or gate circuit, a fourth or gate circuit, a fifth or gate circuit, a sixth or gate circuit, a third C cell, a fourth C cell, a fifth C cell, a sixth C cell, and a seventh C cell;
wherein the first or gate circuit, the second or gate circuit, the third or gate circuit, the fourth or gate circuit, the fifth or gate circuit and the sixth or gate circuit all comprise: a first input, a second input, and an output, the third, fourth, fifth, sixth, and seventh C cells each comprising: a first input, a second input and an output;
the input end of each OR gate circuit in the first OR gate circuit, the second OR gate circuit, the third OR gate circuit and the fourth OR gate circuit is respectively connected with the output end of the asynchronous latch corresponding to the serial number of the asynchronous latch in the asynchronous flowing water station;
the first input end and the second input end of the third C unit are respectively connected with the output ends of the first OR gate circuit and the second OR gate circuit;
a first input end and a second input end of the fourth C unit are respectively connected with output ends of the third OR gate circuit and the fourth OR gate circuit;
a first input end and a second input end of the fifth C unit are respectively connected with output ends of the third C unit and the fourth C unit;
the input end of the fifth OR gate circuit is connected with the output end of the first check generator;
the input ends of the sixth OR gate circuits are connected with the output end of the second check generator;
a first input end and a second input end of the sixth C unit are respectively connected with output ends of the fifth OR gate circuit and the sixth OR gate circuit;
and the first input end and the second input end of the seventh C unit are connected with the output ends of the fifth C unit and the sixth C unit, and the output end of the seventh C unit is connected with the input end of the backward response unit.
Further, the error correction unit includes: a first error corrector, a second error corrector, a third error corrector, a fourth error corrector, a first error filter, a second error filter, a third error filter and a fourth error filter;
wherein an input terminal of the first error corrector is connected to an output terminal of the second asynchronous latch and an output terminal of the first parity generator;
the input end of the second error corrector is connected with the output end of the first asynchronous latch and the output end of the first check generator;
an input end of the third error corrector is connected with an output end of the fourth asynchronous latch and an output end of the second check generator;
an input end of the fourth error corrector is connected with an output end of the third asynchronous latch and an output end of the second check generator;
the input end of each error filter is connected with the output end of the asynchronous latch corresponding to the error filter number in the asynchronous pipelining station and the output end of the error corrector corresponding to the error filter number.
Furthermore, the first error corrector, the second error corrector, the third error corrector and the fourth error corrector are all double-rail adders consisting of an eleventh C unit, a twelfth C unit, a thirteenth C unit, a fourteenth C unit, a ninth OR gate circuit and a tenth OR gate circuit;
wherein, the input end of each error corrector is the input end of the eleventh C unit, the twelfth C unit, the thirteenth C unit and the fourteenth C unit;
the output end of each error corrector is the output end of the ninth OR gate circuit and the tenth OR gate circuit;
the input end of the ninth OR gate circuit is connected with the output ends of the eleventh C unit and the twelfth C unit;
and the input end of the tenth OR gate circuit is connected with the output ends of the thirteenth C unit and the fourteenth C unit.
Further, the first error filter, the second error filter, the third error filter, and the fourth error filter each include: a first C unit and a second C unit;
wherein each C unit comprises: a first input, a second input and an output;
the first input end and the second input end of the first C unit of each error filter are respectively connected with the output end of the first C unit of the asynchronous latch corresponding to the serial number of the error filter in the asynchronous pipelining station and the output end of the ninth OR gate circuit of the error corrector corresponding to the serial number of the error filter in the asynchronous pipelining station;
the first input end and the second input end of the second C unit of each error filter are respectively connected with the output end of the second C unit of the asynchronous latch corresponding to the serial number of the error filter in the asynchronous pipelining station and the output end of the tenth OR gate circuit of the error corrector corresponding to the serial number of the error filter in the asynchronous pipelining station;
and the output ends of the first C unit and the second C unit of each error filter are connected with the input end of an asynchronous latch corresponding to the serial number of the error filter in an asynchronous flow water station of the next-stage transmission module or the input end of external receiving equipment.
Preferably, the backward response unit includes: a NOT gate unit;
the input end of the NOT gate unit is connected with the output end of the detection unit, and the output end of the NOT gate unit is connected with the input end of the upper-stage transmission module asynchronous flowing water station or the input end of the external sending equipment.
Compared with the closest prior art, the invention has the following beneficial effects:
the invention relates to a double-track signal asynchronous transmission link system, which comprises: a plurality of cascaded transmission modules; the transmission module includes: the system comprises an asynchronous flow station, a detection unit, a verification unit, an error correction unit and a backward response unit; the asynchronous water station is used for generating a transmission signal based on the received transmission signal and a feedback signal; the received transmission signal is sent by an error correction unit of a previous transmission module or external sending equipment, and the feedback signal is sent by a backward response unit of a next transmission module or external receiving equipment; the check unit is used for generating a check signal based on a transmission signal sent by the asynchronous flow station; the error correction unit is used for correcting errors of transmission signals generated by the asynchronous pipeline station based on the check signals sent by the check unit and sending the transmission signals after error correction to the asynchronous pipeline station or external receiving equipment of the next-stage transmission module; the detection unit is used for sending out a detection signal based on a check signal sent out by the check unit and a transmission signal sent out by the asynchronous flowing water station; the backward response unit is used for sending a feedback signal based on the detection signal sent by the detection unit; the invention can tolerate 1 bit transient error on the double-track signal asynchronous transmission link, keeps the time sequence robustness, and has the characteristics of flexibility, configurability, high link utilization rate and small area overhead.
Drawings
FIG. 1 is a schematic diagram of a dual rail signal transmission link system according to the present invention;
FIG. 2 is a schematic diagram of a dual-rail signal transmission link system according to an embodiment of the present invention;
FIG. 3a is a schematic diagram of a first parity generator in an embodiment of the invention;
FIG. 3b is a schematic diagram of a second parity generator in an embodiment of the invention;
FIG. 4 is a schematic diagram of a detection unit in an embodiment of the invention;
FIG. 5a is a diagram of a first error corrector in an embodiment of the present invention;
FIG. 5b is a diagram of a second error corrector in an embodiment of the present invention;
FIG. 5c is a diagram of a third error corrector in an embodiment of the present invention;
FIG. 5d is a diagram of a fourth error corrector in an embodiment of the present invention;
FIG. 6 is a diagram of an error filter in an embodiment of the invention.
Detailed Description
The following describes embodiments of the present invention in further detail with reference to the accompanying drawings.
In order to make the objects, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are some, but not all, embodiments of the present invention. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
The invention provides a double-rail signal asynchronous transmission link system, which comprises: a plurality of cascaded transmission modules;
as shown in fig. 1, the transmission module includes: the system comprises an asynchronous flow station, a detection unit, a verification unit, an error correction unit and a backward response unit;
the asynchronous water station is used for generating a transmission signal based on the received transmission signal and a feedback signal; the received transmission signal is sent by an error correction unit of a previous transmission module or external sending equipment, and the feedback signal is sent by a backward response unit of a next transmission module or external receiving equipment;
the check unit is used for generating a check signal based on a transmission signal sent by the asynchronous flow station;
the error correction unit is used for correcting errors of transmission signals generated by the asynchronous pipeline station based on the check signals sent by the check unit and sending the transmission signals after error correction to the asynchronous pipeline station or external receiving equipment of the next-stage transmission module;
the detection unit is used for sending out a detection signal based on a check signal sent out by the check unit and a transmission signal sent out by the asynchronous flowing water station;
and the backward response unit is used for sending a feedback signal based on the detection signal sent by the detection unit.
To illustrate the object of the invention more clearly, a further explanation of the solution according to the invention is given below with reference to a specific embodiment.
In an embodiment of the present invention, the asynchronous waterflow station includes: a first asynchronous latch, a second asynchronous latch, a third asynchronous latch, and a fourth asynchronous latch;
wherein each asynchronous latch comprises: a first C cell and a second C cell, each C cell comprising: a first input, a second input and an output;
the first input end of each C unit of each asynchronous latch is respectively connected with one output end of the error correction unit of the previous-stage transmission module;
the second input end of each C unit of each asynchronous latch is connected with the output end of the backward response unit of the next-stage transmission module;
and the output end of each C unit of each asynchronous latch is connected with the input end of the detection unit and the input end of the error correction unit.
Wherein one input of the C-unit is the received transmission signal and the other input is the feedback signal.
In the implementation of the 4-segment handshake protocol, based on the dual-rail signal encoding protocol, data transmitted by the transmission system alternately undergoes a "set" and "reset" process, and the principle is as follows:
when the data is set, the output of one C unit of each asynchronous latch gradually changes to 1 according to the data to be transmitted and a dual-rail data coding protocol, and when the setting is completed, the output of one C unit of all the asynchronous latches in the current asynchronous pipelining station is turned from 0 to 1, the pipelining station receives a complete dual-rail data, and at the moment, the feedback signal value is 1;
when the reset is performed, the outputs of all the C units of the asynchronous pipelining station gradually become 0, and when the reset is completed, the outputs of all the C units of the pipelining station are 0, and at this time, the feedback signal value is 0.
As shown in FIG. 2, the output of each asynchronous latch is d1、d2、d3、d4，diIncluding di,0And di,1，i∈[1,4]，CD0Is a detection unit.
According to the fault-tolerant capability requirement target of asynchronous pipeline design, on the basis of a quasi-delay insensitive asynchronous transmission basic link system, a verification unit and an error correction unit supporting fault tolerance are added, and a detection unit is correspondingly modified, so that the system structure shown in figure 1 is obtained, and the fault-tolerant purpose can be realized.
In the embodiment of the invention, a check generator is added to the grouping of the dual-rail data words at the output end of the asynchronous pipeline station, and an addition operation is performed on each group of the dual-rail data words to generate check words which are also dual-rail encoded, wherein the dual-rail encoding mode is defined as the following table:
double-track coding and common binary representation comparison table
| Dual-track encoding | Ordinary binary |
| {0,0} | Interval symbol |
| {0,1} | 0 |
| {1,0} | 1 |
| {1,1} | Unlawful |
Wherein, the dual-rail code {0,1} represents binary 0, {1,0} represents binary 1, {1,1} is an illegal value, and {0,0} represents the interval between two dual-rail codewords and is used to reflect the "reset" state in the 4-segment handshake protocol. In this case, the negative value operation defining a dual-rail codeword remains itself; the addition for dual-rail encoding is defined as follows: suppose that two dual-track data words are a ═ a respectively1,a2B ═ b } and b ═ b1,b2And c is c ═ c1,c2Use'&"represents the operator for the 2-input C-cell function and" | "represents the operator for the 2-input OR gate function, then the solution for the sum C is: c. C1＝(a1&b1)|(a2&b2)，c2＝(a1&b2)|(a2&b1)。
Specifically, as shown in fig. 2, the verification unit includes: first check generator CG12And a second check generator CG34；
Wherein, the input end of the first check generator is connected with the output ends of the first asynchronous latch and the second asynchronous latch;
the input end of the second check generator is connected with the output ends of the third asynchronous latch and the fourth asynchronous latch;
the output end of each check generator is connected with the input end of the error correction unit and the input end of the detection unit.
As shown in fig. 2, the output end of each check generator is c{1,2}And c{3,4}，c{1,2}Comprising c{1,2},0And c{1,2},1，c{3,4}The method comprises the following steps: c. C{3,4},0And c{3,4},1。
Further, as shown in fig. 3, each of the check generators is a dual-rail adder composed of a seventh C unit, an eighth C unit, a ninth C unit, a tenth C unit, a seventh or gate circuit, and an eighth or gate circuit;
the input end of each check generator is the input end of the seventh C unit, the eighth C unit, the ninth C unit and the tenth C unit;
the output end of each check generator is the output end of the seventh OR gate circuit and the eighth OR gate circuit;
the input end of the seventh OR gate circuit is connected with the output ends of the seventh C unit and the eighth C unit;
and the input end of the eighth OR gate circuit is connected with the output ends of the ninth C unit and the tenth C unit.
Specifically, the seventh or gate circuit and the eighth or gate circuit each include: a first input, a second input, and an output, the seventh, eighth, ninth, and tenth C units each comprising: a first input terminal and a second input terminal;
a first input end of a seventh C unit of the first check generator is connected with an output end of the first C unit of the first asynchronous latch, and a second input end of the seventh C unit of the first check generator is connected with an output end of the first C unit of the second asynchronous latch;
a first input end of an eighth C unit of the first check generator is connected with an output end of a second C unit of the first asynchronous latch, and a second input end of the eighth C unit of the first check generator is connected with an output end of a second C unit of the second asynchronous latch;
a first input end of a ninth C unit of the first check generator is connected with an output end of the first C unit of the first asynchronous latch, and a second input end of the ninth C unit of the first check generator is connected with an output end of the second C unit of the second asynchronous latch;
a first input end of a tenth C unit of the first check generator is connected with an output end of a second C unit of the first asynchronous latch, and a second input end of the tenth C unit of the first check generator is connected with an output end of a first C unit of the first asynchronous latch;
the output ends of a seventh C unit and an eighth C unit of the first check generator are connected with the first input end and the second input end of the seventh OR gate circuit;
the output ends of the ninth C unit and the tenth C unit of the first check generator are connected with the first input end and the second input end of the eighth OR gate circuit;
the output ends of a seventh OR gate circuit and an eighth OR gate circuit of the first check generator are connected with the input end of the first error corrector, the input end of the second error corrector and the input end of the detection unit;
a first input end of a seventh C unit of the second parity generator is connected with an output end of the first C unit of the third asynchronous latch, and a second input end of the seventh C unit of the second parity generator is connected with an output end of the first C unit of the fourth asynchronous latch;
a first input end of an eighth C unit of the second parity generator is connected with an output end of the second C unit of the third asynchronous latch, and a second input end of the eighth C unit of the second parity generator is connected with an output end of the second C unit of the fourth asynchronous latch;
a first input end of a ninth C unit of the second parity generator is connected with an output end of the first C unit of the third asynchronous latch, and a second input end of the ninth C unit of the second parity generator is connected with an output end of the second C unit of the fourth asynchronous latch;
a first input terminal of a tenth C unit of the second parity generator is connected to an output terminal of the second C unit of the third asynchronous latch, and a second input terminal of the tenth C unit of the second parity generator is connected to an output terminal of the first C unit of the fourth asynchronous latch;
the output ends of the seventh C unit and the eighth C unit of the second check generator are connected with the first input end and the second input end of the seventh OR gate circuit;
the output ends of the ninth C unit and the tenth C unit of the second check generator are connected with the first input end and the second input end of the eighth OR gate circuit;
and the output ends of the seventh or gate circuit and the eighth or gate circuit of the second check generator are connected with the input end of the third error corrector, the input end of the fourth error corrector and the input end of the detection unit.
In FIG. 3a, c{1,2},0And c{1,2},1Are check generators CG respectively12The outputs of the seventh and eighth OR-gates, i.e. their check-generators CG12An output terminal of (a); in FIG. 3b, c{3,4},0And c{3,4},1Are check generators CG respectively34The outputs of the seventh and eighth OR-gates, i.e. their check-generators CG34To the output terminal of (a).
In an embodiment of the present invention, as shown in fig. 4, the detection unit includes: a first or gate circuit, a second or gate circuit, a third or gate circuit, a fourth or gate circuit, a fifth or gate circuit, a sixth or gate circuit, a third C cell, a fourth C cell, a fifth C cell, a sixth C cell, and a seventh C cell;
wherein the first or gate circuit, the second or gate circuit, the third or gate circuit, the fourth or gate circuit, the fifth or gate circuit and the sixth or gate circuit all comprise: a first input, a second input, and an output, the third, fourth, fifth, sixth, and seventh C cells each comprising: a first input, a second input and an output;
the input end of each OR gate circuit in the first OR gate circuit, the second OR gate circuit, the third OR gate circuit and the fourth OR gate circuit is respectively connected with the output end of the asynchronous latch corresponding to the serial number of the asynchronous latch in the asynchronous flowing water station; for example, a first OR-gate connected to the output d of the first asynchronous latch1；
The first input end and the second input end of the third C unit are respectively connected with the output ends of the first OR gate circuit and the second OR gate circuit;
a first input end and a second input end of the fourth C unit are respectively connected with output ends of the third OR gate circuit and the fourth OR gate circuit;
a first input end and a second input end of the fifth C unit are respectively connected with output ends of the third C unit and the fourth C unit;
the input end of the fifth OR gate circuit is connected with the output end of the first check generator;
the input ends of the sixth OR gate circuits are connected with the output end of the second check generator;
a first input end and a second input end of the sixth C unit are respectively connected with output ends of the fifth OR gate circuit and the sixth OR gate circuit;
and the first input end and the second input end of the seventh C unit are connected with the output ends of the fifth C unit and the sixth C unit, and the output end of the seventh C unit is connected with the input end of the backward response unit.
The error correction unit is a key module for realizing fault tolerance, and the principle is as follows: whether a transmission signal or a newly generated check signal is adopted, transient errors can occur in the transmission process, signal inversion is generated, so that the original correct double-track coding is in error, firstly 2 error correctors are added before an asynchronous pipelining station to carry out double-track subtraction operation on data words and check words in the same group, the check words are used as the subtracted numbers, one data word is the subtracted number, the difference is another data word under the condition that no error occurs, and only 1 error occurs between the 2 data words and the 1 check word under the condition that 1-bit transient error occurs: (1) if 1 data word is in error, then the correct data word can be obtained by subtracting another data word from the error-free check word, and an error filter is added after the error corrector, so that the error filtering can be realized, and the final correct data word can be obtained; (2) if the check word is wrong, although the generated differences are all wrong after the subtraction operation is performed, the original data words are all correct based on the assumption of 1-bit errors, and correct data words can be obtained through an error filter, so that the error correction is realized.
Further, as shown in fig. 2, the error correction unit includes: first error corrector EC1A second error corrector EC2A third error corrector EC3A fourth error corrector EC4A first error filter EF1A second error filter EF2A third error filter EF3And a fourth error filter EF4；
Wherein an input terminal of the first error corrector is connected to an output terminal of the second asynchronous latch and an output terminal of the first parity generator;
the input end of the second error corrector is connected with the output end of the first asynchronous latch and the output end of the first check generator;
an input end of the third error corrector is connected with an output end of the fourth asynchronous latch and an output end of the second check generator;
an input end of the fourth error corrector is connected with an output end of the third asynchronous latch and an output end of the second check generator;
the input end of each error filter is connected with the output end of an asynchronous latch corresponding to the serial number of the error filter in the asynchronous pipelining station and the output end of an error corrector corresponding to the serial number of the error filter, namely the input end of a first error filter is connected with the output end of a first asynchronous latch and the output end of the first error corrector;
the output end of each error filter is connected with the input end of the next-stage transmission module asynchronous flow station, specifically, the input end of the asynchronous latch with the corresponding serial number is connected with the output end of the next-stage transmission module asynchronous flow station.
Wherein, the check generator CG corresponding to the transmitting end122 error correctors EC are added at the receiving end1And EC2Respectively for check word c{1,2}And a data word d1、d2The subtraction is performed and the error corrector performs a dual-rail subtraction, formally denoted as c + a + b a-b, and thus EC1And EC2Are each d'1＝c{1,2}-d2＝c{1,2}+d2，d'2＝c{1,2}-d1＝c{1,2}+d1Both are dual-rail encoding. Similarly, the corresponding check generator CG342 error correctors EC are added at the receiving end3And EC4Their outputs are d'3＝c{3,4}-d4＝c{3,4}+d4，d'4＝c{3,4}-d3＝c{3,4}+d3。
Further, as shown in fig. 5, the first error corrector, the second error corrector, the third error corrector and the fourth error corrector are all double-rail adders consisting of an eleventh C unit, a twelfth C unit, a thirteenth C unit, a fourteenth C unit, a ninth or gate circuit and a tenth or gate circuit;
wherein, the input end of each error corrector is the input end of the eleventh C unit, the twelfth C unit, the thirteenth C unit and the fourteenth C unit;
the output end of each error corrector is the output end of the ninth OR gate circuit and the tenth OR gate circuit;
the input end of the ninth OR gate circuit is connected with the output ends of the eleventh C unit and the twelfth C unit;
and the input end of the tenth OR gate circuit is connected with the output ends of the thirteenth C unit and the fourteenth C unit.
Specifically, a first input end and a second input end of an eleventh C unit of the first error corrector are respectively connected to an output end of a ninth or gate circuit of the first check generator of the check unit and an output end of the first C unit of the second asynchronous latch;
a first input end and a second input end of a twelfth C unit of the first error corrector are respectively connected with an output end of a tenth OR gate circuit of the first verification generator of the verification unit and an output end of the second C unit of the second asynchronous latch;
a first input end and a second input end of a thirteenth C unit of the first error corrector are respectively connected with an output end of a ninth OR gate circuit of the first verification generator of the verification unit and an output end of a second C unit of the second asynchronous latch;
a first input end and a second input end of a fourteenth C unit of the first error corrector are respectively connected with an output end of a tenth OR gate circuit of a first verification generator of the verification unit and an output end of a first C unit of the second asynchronous latch;
the output ends of the eleventh C unit and the twelfth C unit of the first error corrector are connected with the first input end and the second input end of the ninth OR gate circuit of the first error corrector;
the output ends of the thirteenth C unit and the fourteenth C unit of the first error corrector are connected with the first input end and the second input end of the tenth OR gate circuit of the first error corrector;
the output ends of the ninth or gate circuit and the tenth or gate circuit of the first error corrector are connected with the input end of the first error filter. Similarly, the second, third and fourth error correctors are all connected to the corresponding check generator and error filter in fig. 2 by the same connection method as the first error corrector.
In FIG. 2, d'1、d′2、d′3、d′4For the output of correspondingly numbered error correctorsThe output ends comprise two output ends d 'shown in figures 5a to 5 d'i,0、d′i,1Which are the outputs of two OR gates of each error corrector, i ∈ [1,4 ]]。
Further, as shown in fig. 6, the first error filter, the second error filter, the third error filter, and the fourth error filter each include: a first C unit and a second C unit;
wherein each C unit comprises: a first input, a second input and an output;
the first input end and the second input end of the first C unit of each error filter are respectively connected with the output end of the first C unit of the asynchronous latch corresponding to the serial number of the error filter in the asynchronous pipelining station and the output end of the ninth OR gate circuit of the error corrector corresponding to the serial number of the error filter in the asynchronous pipelining station;
the first input end and the second input end of the second C unit of each error filter are respectively connected with the output end of the second C unit of the asynchronous latch corresponding to the serial number of the error filter in the asynchronous pipelining station and the output end of the tenth OR gate circuit of the error corrector corresponding to the serial number of the error filter in the asynchronous pipelining station;
and the output ends of the first C unit and the second C unit of each error filter are connected with the input end of an asynchronous latch corresponding to the serial number of the error filter in an asynchronous flow water station of the next-stage transmission module.
In FIG. 2, d ″)1、d″2、d″3、d″4The outputs of the correspondingly numbered error filters each comprise two outputs as in fig. 6, namely d ″i,0，d″i,1Which are the output terminals of the C units of the error filter, respectively.
In an embodiment of the present invention, as shown in fig. 2, the backward response unit includes: a NOT gate unit;
the input end of the NOT gate unit is connected with the output end of the detection unit, and the output end of the NOT gate unit is connected with the input end of the asynchronous flowing water station.
In summary, the present invention relates to a dual-rail signal asynchronous transmission link system, which includes: a plurality of cascaded transmission modules; the transmission module includes: the system comprises an asynchronous flow station, a detection unit, a verification unit, an error correction unit and a backward response unit; the asynchronous water station is used for generating a transmission signal based on the received transmission signal and a feedback signal; the received transmission signal is sent by an error correction unit of a previous transmission module or external sending equipment, and the feedback signal is sent by a backward response unit of a next transmission module or external receiving equipment; the check unit is used for generating a check signal based on a transmission signal sent by the asynchronous flow station; the error correction unit is used for correcting errors of transmission signals generated by the asynchronous pipeline station based on the check signals sent by the check unit and sending the transmission signals after error correction to the asynchronous pipeline station or external receiving equipment of the next-stage transmission module; the detection unit is used for sending out a detection signal based on a check signal sent out by the check unit and a transmission signal sent out by the asynchronous flowing water station; the backward response unit is used for sending a feedback signal based on the detection signal sent by the detection unit; the invention can tolerate 1 bit transient error on the transmission link, keeps the time sequence robustness, and has the characteristics of flexibility and configurability, high link utilization rate and small area overhead.
As will be appreciated by one skilled in the art, embodiments of the present application may be provided as a method, system, or computer program product. Accordingly, the present application may take the form of an entirely hardware embodiment, an entirely software embodiment or an embodiment combining software and hardware aspects. Furthermore, the present application may take the form of a computer program product embodied on one or more computer-usable storage media (including, but not limited to, disk storage, CD-ROM, optical storage, and the like) having computer-usable program code embodied therein.
The present application is described with reference to flowchart illustrations and/or block diagrams of methods, apparatus (systems), and computer program products according to embodiments of the application. It will be understood that each flow and/or block of the flow diagrams and/or block diagrams, and combinations of flows and/or blocks in the flow diagrams and/or block diagrams, can be implemented by computer program instructions. These computer program instructions may be provided to a processor of a general purpose computer, special purpose computer, embedded processor, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, create means for implementing the functions specified in the flowchart flow or flows and/or block diagram block or blocks.
These computer program instructions may also be stored in a computer-readable memory that can direct a computer or other programmable data processing apparatus to function in a particular manner, such that the instructions stored in the computer-readable memory produce an article of manufacture including instruction means which implement the function specified in the flowchart flow or flows and/or block diagram block or blocks.
These computer program instructions may also be loaded onto a computer or other programmable data processing apparatus to cause a series of operational steps to be performed on the computer or other programmable apparatus to produce a computer implemented process such that the instructions which execute on the computer or other programmable apparatus provide steps for implementing the functions specified in the flowchart flow or flows and/or block diagram block or blocks.
Finally, it should be noted that: the above embodiments are only for illustrating the technical solutions of the present invention and not for limiting the same, and although the present invention is described in detail with reference to the above embodiments, those of ordinary skill in the art should understand that: modifications and equivalents may be made to the embodiments of the invention without departing from the spirit and scope of the invention, which is to be covered by the claims.
Claims (9)
1. A dual rail signal asynchronous transmission link system, the system comprising: a plurality of cascaded transmission modules;
the transmission module includes: the system comprises an asynchronous flow station, a detection unit, a verification unit, an error correction unit and a backward response unit;
the asynchronous water station is used for generating a transmission signal based on the received transmission signal and a feedback signal; the received transmission signal is sent by an error correction unit of a previous transmission module or external sending equipment, and the feedback signal is sent by a backward response unit of a next transmission module or external receiving equipment;
the check unit is used for generating a check signal based on a transmission signal sent by the asynchronous flow station;
the error correction unit is used for correcting errors of transmission signals generated by the asynchronous pipeline station based on the check signals sent by the check unit and sending the transmission signals after error correction to the asynchronous pipeline station or external receiving equipment of the next-stage transmission module;
the detection unit is used for sending out a detection signal based on a check signal sent out by the check unit and a transmission signal sent out by the asynchronous flowing water station;
and the backward response unit is used for sending a feedback signal based on the detection signal sent by the detection unit.
2. The system of claim 1, wherein the asynchronous waterflooding station comprises: a first asynchronous latch, a second asynchronous latch, a third asynchronous latch, and a fourth asynchronous latch;
wherein each asynchronous latch comprises: a first C cell and a second C cell, each C cell comprising: a first input, a second input and an output;
the first input end of each C unit of each asynchronous latch is respectively connected with one output end of an error correction unit of the previous-stage transmission module or the output end of external sending equipment;
the second input end of each C unit of each asynchronous latch is connected with the output end of the backward response unit of the next-stage transmission module or the output end of the external receiving equipment;
and the output end of each C unit of each asynchronous latch is connected with the input end of the detection unit and the input end of the error correction unit.
3. The system of claim 2, wherein the verification unit comprises: a first parity generator and a second parity generator;
wherein, the input end of the first check generator is connected with the output ends of the first asynchronous latch and the second asynchronous latch;
the input end of the second check generator is connected with the output ends of the third asynchronous latch and the fourth asynchronous latch;
the output end of each check generator is connected with the input end of the error correction unit and the input end of the detection unit.
4. The system of claim 3, wherein each of the parity generators is a dual rail adder consisting of a seventh C cell, an eighth C cell, a ninth C cell, a tenth C cell, a seventh OR gate, and an eighth OR gate;
the input end of each check generator is the input end of the seventh C unit, the eighth C unit, the ninth C unit and the tenth C unit;
the output end of each check generator is the output end of the seventh OR gate circuit and the eighth OR gate circuit;
the input end of the seventh OR gate circuit is connected with the output ends of the seventh C unit and the eighth C unit;
and the input end of the eighth OR gate circuit is connected with the output ends of the ninth C unit and the tenth C unit.
5. The system of claim 3, wherein the detection unit comprises: a first or gate circuit, a second or gate circuit, a third or gate circuit, a fourth or gate circuit, a fifth or gate circuit, a sixth or gate circuit, a third C cell, a fourth C cell, a fifth C cell, a sixth C cell, and a seventh C cell;
wherein the first or gate circuit, the second or gate circuit, the third or gate circuit, the fourth or gate circuit, the fifth or gate circuit and the sixth or gate circuit all comprise: a first input, a second input, and an output, the third, fourth, fifth, sixth, and seventh C cells each comprising: a first input, a second input and an output;
the input end of each OR gate circuit in the first OR gate circuit, the second OR gate circuit, the third OR gate circuit and the fourth OR gate circuit is respectively connected with the output end of the asynchronous latch corresponding to the serial number of the asynchronous latch in the asynchronous flowing water station;
the first input end and the second input end of the third C unit are respectively connected with the output ends of the first OR gate circuit and the second OR gate circuit;
a first input end and a second input end of the fourth C unit are respectively connected with output ends of the third OR gate circuit and the fourth OR gate circuit;
a first input end and a second input end of the fifth C unit are respectively connected with output ends of the third C unit and the fourth C unit;
the input end of the fifth OR gate circuit is connected with the output end of the first check generator;
the input ends of the sixth OR gate circuits are connected with the output end of the second check generator;
a first input end and a second input end of the sixth C unit are respectively connected with output ends of the fifth OR gate circuit and the sixth OR gate circuit;
and the first input end and the second input end of the seventh C unit are connected with the output ends of the fifth C unit and the sixth C unit, and the output end of the seventh C unit is connected with the input end of the backward response unit.
6. The system of claim 3, wherein the error correction unit comprises: a first error corrector, a second error corrector, a third error corrector, a fourth error corrector, a first error filter, a second error filter, a third error filter and a fourth error filter;
wherein an input terminal of the first error corrector is connected to an output terminal of the second asynchronous latch and an output terminal of the first parity generator;
the input end of the second error corrector is connected with the output end of the first asynchronous latch and the output end of the first check generator;
an input end of the third error corrector is connected with an output end of the fourth asynchronous latch and an output end of the second check generator;
an input end of the fourth error corrector is connected with an output end of the third asynchronous latch and an output end of the second check generator;
the input end of each error filter is connected with the output end of the asynchronous latch corresponding to the error filter number in the asynchronous pipelining station and the output end of the error corrector corresponding to the error filter number.
7. The system of claim 6, wherein the first, second, third, and fourth error correctors are each a dual rail adder consisting of an eleventh C-unit, a twelfth C-unit, a thirteenth C-unit, a fourteenth C-unit, a ninth OR-gate, and a tenth OR-gate;
wherein, the input end of each error corrector is the input end of the eleventh C unit, the twelfth C unit, the thirteenth C unit and the fourteenth C unit;
the output end of each error corrector is the output end of the ninth OR gate circuit and the tenth OR gate circuit;
the input end of the ninth OR gate circuit is connected with the output ends of the eleventh C unit and the twelfth C unit;
and the input end of the tenth OR gate circuit is connected with the output ends of the thirteenth C unit and the fourteenth C unit.
8. The system of claim 7, wherein the first, second, third, and fourth error filters each comprise: a first C unit and a second C unit;
wherein each C unit comprises: a first input, a second input and an output;
the first input end and the second input end of the first C unit of each error filter are respectively connected with the output end of the first C unit of the asynchronous latch corresponding to the serial number of the error filter in the asynchronous pipelining station and the output end of the ninth OR gate circuit of the error corrector corresponding to the serial number of the error filter in the asynchronous pipelining station;
the first input end and the second input end of the second C unit of each error filter are respectively connected with the output end of the second C unit of the asynchronous latch corresponding to the serial number of the error filter in the asynchronous pipelining station and the output end of the tenth OR gate circuit of the error corrector corresponding to the serial number of the error filter in the asynchronous pipelining station;
and the output ends of the first C unit and the second C unit of each error filter are connected with the input end of an asynchronous latch corresponding to the serial number of the error filter in an asynchronous flow water station of the next-stage transmission module or the input end of external receiving equipment.
9. The system of claim 1, wherein the backward response unit comprises: a NOT gate unit;
the input end of the NOT gate unit is connected with the output end of the detection unit, and the output end of the NOT gate unit is connected with the input end of the upper-stage transmission module asynchronous flowing water station or the input end of the external sending equipment.
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