CN103955586B - Low-overhead fault tolerance circuit applied to low power consumption digital signal processing system - Google Patents
Low-overhead fault tolerance circuit applied to low power consumption digital signal processing system Download PDFInfo
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- CN103955586B CN103955586B CN201410199787.9A CN201410199787A CN103955586B CN 103955586 B CN103955586 B CN 103955586B CN 201410199787 A CN201410199787 A CN 201410199787A CN 103955586 B CN103955586 B CN 103955586B
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Abstract
The invention belongs to the technical field of low power consumption integrated circuit design, in particular to a low-overhead fault tolerance circuit applied to a low power consumption digital signal processing system.The circuit employs a two-stage fault tolerance structure, wherein the first stage employs an on-line time sequence monitoring mechanism to detect a soft fault and then selects output via a simple correction mechanism, and the second stage employs a mean filtering concept and comprises a predictor based on smooth filtering and an arbiter to realize fault detection and correction.Compared with the traditional single-stage fault tolerance circuit based on predication, the fault detection and correction capability of the two-stage fault tolerance circuit can be greatly improved.A fault tolerance technology is combined with a voltage over-scaling technology, performance of the system can be kept in a tolerant scope, and further voltage reduction is allowed, so that the power consumption of the system is greatly reduced.The circuit is simple in structure, low in overhead and high in correction capability, and is especially suitable for being applied to the low power consumption digital signal processing system based on the VOS (voltage over-scaling) technology.
Description
Technical field
The invention belongs to low power consumption integrated circuit technical field is and in particular to one kind is applied to low power consumption digital signal transacting
The low overhead fault tolerable circuit of system.
Background technology
With integrated circuit technique fast development, characteristic size constantly reduces, and chip integration is deferred to mole（Moore）Fixed
Rule improves constantly.During integrated circuit technique constantly development rapid raising with integrated level, it is main that people pay close attention to always
Problem is how to improve the operating rate of chip, reduces chip area and cost, and the consideration for circuit power consumption is often in
Relatively secondary position.But in recent years due to mobile device, portable electronic, communication and other consumption electronic product markets
The fast-developing and market demand makes this situation there occurs some basic changes.In a lot of applications, reduce power consumption
Through becoming an of paramount importance problem of Design of Digital System.
The market demand of low-power consumption has promoted the generation of a lot of Low-power Technology, and the Low-power Technology that current industry is commonly used has
Gated clock, gate voltage and multiple voltage domain design etc..Recent study personnel propose voltage and cross zoom technology（VOS:
Voltage Over Scaling）, its principle is artificially to reduce voltage to reduce power consumption, simultaneously because voltage reduces causes pass
Sequential and breaks rules in key path, and now carries out error correction by adding fault tolerable circuit technology again；Finally, Circuits System can be believed with certain
Make an uproar than sacrifice bring substantially reducing of power consumption.
Existing VOS fault tolerable circuit technology includes：Difference channel error correction, based on prediction error correction circuit, be based on low precision
The error correcting technique of stand-by circuit and self adaptation mistake cancellation technology etc..These technology often only have one-level, and error correcting capability has
Limit.The present invention is combined it is proposed that a kind of new two-stage is fault-tolerant by shadow register technology with based on the error correcting technique of prediction
Structure, can greatly improve error correcting capability, so that voltage and power consumption reduce further.
Content of the invention
It is an object of the invention to provide a kind of low overhead fault tolerable circuit being applied to low power consumption digital signal processing system,
To improve the error-detection error-correction ability of digital information processing system, thus allowing supply voltage to reduce further, finally realize low work(
Consumption.
The low overhead fault tolerable circuit being applied to low power consumption digital signal processing system proposed by the present invention, its overall structure frame
Figure is as shown in Figure 1.This fault tolerable circuit is by two-stage fault tolerable circuit（I.e. two-stage EDC error detection and correction circuit）Constitute；The fault-tolerant electricity of the first order
Road, the soft error leading to for detecting sequential to be unsatisfactory for（soft-error）Or time delay mistake（delay-error）If,
Error then utilizes previous output valve to correct the currency of error；Second level fault tolerable circuit, using the correlation of output, according to
Value through output produces the predicted value to current output, and with this predicted value detection mistake and corrects mistake.
The first order fault tolerable circuit of the present invention, as shown in Fig. 2 selected by the data of timing error monitoring module and alternative
Device is constituted；Wherein, timing error monitoring module prolonging using shadow register technology for detection critical path and secondary critical path
When whether exceed clock cycle of system, if beyond thinking that timing error occurs, and this error propagation is gone down, last
Output end by selector select previous right value as current erroneous value estimation export.Wherein, shadow register skill
Art is used for detecting that sequential breaks rules, and Fig. 3 gives the detects schematic diagram of bit-errors, when former register and shadow register result not
Then think that timing error occurs when the same.
In the present invention, described timing error monitoring module, it is made up of shadow register and rub-out signal propagation circuit；Shadow
The clock of register certain time by a time delay drives, and needs a certain combinational logic path ends of monitoring to be connected to shadow
The data input pin of register；The output of shadow register is contrasted by an XOR gate with former register output, if it is different,
Then think that sequential malfunctions, this error signal propagated by a propagation chain, propagation chain by OR gate and former clock-driven is posted
Storage is constituted, and propagates series consistent with the pipeline series of former data path；The error signal of afterbody passes through alternative number
Select current output according to selector, if error, select an output as the prediction to currency.
The second level fault tolerable circuit of the present invention, as shown in figure 1, the data selector by fallout predictor, moderator and alternative
Constitute；The input of fallout predictor is the front p value of currency；As the prediction to currency, moderator is according to ought for fallout predictor output
Front value and the predicted value of currency, export arbitrating signals, this arbitrating signals is as the control of the data selector of alternative
Signal, selects final output.
In the present invention, the schematic diagram of moderator as shown in figure 4, by subtracter, asking absolute value logical sum comparator to constitute, by
To fallout predictor, the predicted value exporting and currency do subtraction to subtracter, the absolute value of the difference that subtracter is obtained by comparator and thing
The threshold value first setting compares；If the absolute value of difference exceedes threshold value then it is assumed that currency is wrong, now moderator output choosing
Select signal, control alternative data selector to select the predicted value of fallout predictor as final output；If the absolute value of difference is little
In threshold value then it is assumed that currency does not have mistake, moderator exports selection signal, controls alternative data selector to select currency to make
For final output；The threshold value of comparator will determine according to application scenarios.
The course of work of this system is as follows：The timing error of first order fault tolerable circuit on-line checking critical path first, such as
Mistake in fruit, and the output end of this error propagation to streamline selects previous right value by alternative data selector
As output；Then second level fault tolerable circuit, based on the principle of smothing filtering, current using the output valve prediction before p
Output valve, if predicted value and currency deviation excessive then it is assumed that currency error, select predicted value as output.
Traditional fault tolerable circuit technology being applied to VOS typically adopts single-stage error correction, and limited error recovery capability, if for example only
Using the first order fault tolerable circuit in Fig. 1 although some mistakes can be corrected, but break rules when sequential also in shadow register
When, judge by accident, error correction effect occurs and significantly declines；The fault-tolerant circuit structure of two-stage proposed by the present invention can be very
Good this problem of solution, and the Cleaning Principle of two-stage circuit differing, are used in mixed way and can ensure that first order error correction energy
In the case of power declines, the fault-tolerant effect of integrated circuit is not affected substantially, so that circuit voltage reduces further, realizes
More low-power consumption.
Brief description
Fig. 1 is the two-stage fault tolerable circuit structural diagrams of the present invention.
Fig. 2 is timing error monitoring module diagram in first order fault tolerable circuit.
Fig. 3 illustrates for shadow register technology.
Fig. 4 is moderator structural diagrams in the fault tolerable circuit of the second level.
Fig. 5 illustrates for sequential monitoring module.
Fig. 6 for shadow register working waveform figure is.
Specific embodiment
Analyze the critical path distribution situation of original digital signal processing system first, the distribution according to critical path is designing
The monitoring chain of timing error and propagation chain.Fig. 2 gives timing error monitoring chain generally, will basis during practical application
Concrete condition designs this module.Fig. 5 gives the design example of a sequential monitoring module it is assumed that the data of primary circuit system is led to
The critical path on road is, its time delay is, the path being only second to critical path is successively,,, its time delay is respectively,,；Designing fault-tolerant ability is, and,, i.e. fault-tolerant design only allows,,
Malfunction in path, timing error monitoring module now can be designed according to shown in Fig. 5, notices that second level combinational logic does not have
Need the path of monitoring, therefore do not need shadow register it is only necessary to rub-out signal propagated by a register.
When reducing supply voltage, the maximum delay of critical path can exceed the clock cycle, and Fig. 6 gives in this case
Shadow register work wave schematic diagram it can be seen that first clock cycle, combinational logic rises in former clock clk1
Along having completed before to calculate, therefore former register and shadow register adopt identical value, illustrate do not have timing error to occur；
And in second period, combinational logic, after former clock clk1 rising edge, completes before time delay Δ t clock clk2 rising edge to count
Calculate, improper value adopted by therefore former register, and shadow register adopts right value, and the difference of the two leads to circuit when the 3rd
Error signal is put height by the clock cycle, illustrates now to occur timing error.
Because error propagation series is consistent with pipeline series, therefore rub-out signal can follow wrong data to propagate together,
And together reach final output end, now rub-out signal selects previous right value as output now by selector
Value, thus realize the error checking and correction (ECC) of the first order.
The work thought of second level fault tolerable circuit is by a low pass filter, using the correlation of output data, examines
Measure the data of drastically saltus step, and filter this out.As shown in figure 1, the main data choosing by fallout predictor, moderator and alternative
Select device to constitute；The input of predictor module is the front p value of currency, and fallout predictor output, as the prediction to currency, is arbitrated
Device, according to the predicted value of currency and currency, exports arbitrating signals, and this arbitrating signals selects as the data of alternative
The control signal of device, selects final output.The schematic diagram of wherein moderator is as shown in figure 4, by subtracter, seek absolute value logic
Constitute with comparator, the predicted value of fallout predictor output and currency do subtraction, by the absolute value of difference and the threshold value being previously set
Compare, if the absolute value of difference exceedes threshold value then it is assumed that currency is wrong, now moderator output selection signal, control
Alternative data selector selects the predicted value of fallout predictor as final output；If the absolute value of difference is less than threshold value, recognize
There is no mistake for currency, moderator exports selection signal, control alternative data selector to select currency as final output.
Being designed with 2 points and should be noted of second level fault tolerable circuit：First point is, as the low pass filter rank of fallout predictor
The selection of number p, is not that exponent number is the bigger the better, because exponent number leads to more greatly the general of improper value in the p value predicted
Rate increases, and so that prediction accuracy is declined it is therefore desirable to draw optimized exponent number by emulation.Second point is comparator threshold
Select it is determined that it is thus necessary to determine that threshold value after fallout predictor exponent number, different application scenarios threshold value settings is different, and its method is no
In the case of mistake, this fault tolerable circuit structure is emulated, currency is made the difference with predicted value, take absolute value and export, then absolutely
Threshold value is to the maximum of value.
Claims (3)
1. a kind of low overhead fault tolerable circuit being applied to low power consumption digital signal processing system it is characterised in that：Fault-tolerant by two-stage
Circuit is that two-stage EDC error detection and correction circuit is constituted；First order fault tolerable circuit, the soft error leading to for detecting sequential to be unsatisfactory for
Or time delay mistake, and correct the currency of error using previous output valve；Second level fault tolerable circuit, using the correlation of output
Property, the predicted value to current output is produced according to the value having exported, and with this predicted value detection mistake and corrects mistake；Its
In：
Described first order fault tolerable circuit, is made up of the data selector of timing error monitoring module and alternative；Timing error is supervised
Whether control module exceedes the clock week of system using the time delay of shadow register technology for detection critical path and secondary critical path
Phase, if exceeding, thinking that timing error occurs, and this error propagation is gone down, being selected by selector in last output end
Previous right value exports as the estimation of current erroneous value；
Described second level fault tolerable circuit, is made up of the data selector of fallout predictor, moderator and alternative；The input of fallout predictor is
The front p value of currency；Fallout predictor exports as the prediction to currency, and moderator is according to the prediction of currency and currency
Value, exports arbitrating signals, and this arbitrating signals as the control signal of the data selector of alternative, selects final defeated
Go out.
2. the low overhead fault tolerable circuit being applied to low power consumption digital signal processing system according to claim 1, its feature
It is：Described timing error monitoring module, is made up of shadow register and rub-out signal propagation circuit；Shadow register is by one
The clock of time delay certain time drives, and needs a certain combinational logic path ends of monitoring to be connected to the data of shadow register
Input；The output of shadow register is contrasted by an XOR gate with former register output, if it is different, then thinking that sequential goes out
Mistake, the signal of error is propagated by a propagation chain, and propagation chain is made up of OR gate and former clock-driven register, propagates
Series is consistent with the pipeline series of former data path；The error signal of afterbody is passed through alternative data selector and is selected to work as
Front output, if error, selects an output as the prediction to currency.
3. the low overhead fault tolerable circuit being applied to low power consumption digital signal processing system according to claim 2, its feature
It is：Moderator in the fault tolerable circuit of the described second level by subtracter, ask absolute value logical sum comparator to constitute, by subtracter pair
The predicted value of fallout predictor output and currency do subtraction, the absolute value of the difference that subtracter is obtained by comparator be previously set
Threshold value compares；If the absolute value of difference exceedes threshold value then it is assumed that currency is wrong, now moderator output selection signal,
Alternative data selector is controlled to select the predicted value of fallout predictor as final output；If the absolute value of difference is less than threshold value,
Then think that currency does not have mistake, moderator exports selection signal, control alternative data selector to select currency as final
Output.
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| CN201410199787.9A CN103955586B (en) | 2014-05-13 | 2014-05-13 | Low-overhead fault tolerance circuit applied to low power consumption digital signal processing system |
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Citations (4)
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| JP2001043259A (en) * | 1999-07-30 | 2001-02-16 | Toyooki Kogyo Co Ltd | Method for preparing power consumption while using computer system and computer readable recording medium storing program for realizing the method |
| US6606356B1 (en) * | 1997-06-13 | 2003-08-12 | Center For Advanced Science And Technology Incubation, Ltd. | Asynchronous digital system, asynchronous data path circuit, asynchronous digital signal processing circuit and asynchronous digital signal processing method |
| CN1794187A (en) * | 2004-12-21 | 2006-06-28 | 日本电气株式会社 | Computer system and method for dealing with errors |
| CN102436524A (en) * | 2011-10-19 | 2012-05-02 | 清华大学 | Fuzzy reasoning method for soft fault diagnosis for analog circuit |
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2014
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Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6606356B1 (en) * | 1997-06-13 | 2003-08-12 | Center For Advanced Science And Technology Incubation, Ltd. | Asynchronous digital system, asynchronous data path circuit, asynchronous digital signal processing circuit and asynchronous digital signal processing method |
| JP2001043259A (en) * | 1999-07-30 | 2001-02-16 | Toyooki Kogyo Co Ltd | Method for preparing power consumption while using computer system and computer readable recording medium storing program for realizing the method |
| CN1794187A (en) * | 2004-12-21 | 2006-06-28 | 日本电气株式会社 | Computer system and method for dealing with errors |
| CN102436524A (en) * | 2011-10-19 | 2012-05-02 | 清华大学 | Fuzzy reasoning method for soft fault diagnosis for analog circuit |
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| 面向低电压供电数字电路的容错计算系统结构设计;胡剑浩;《电子科技大学学报》;20131130(第6期);全文 * |
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