CN1763939A - Semiconductor package structure and producing method thereof - Google Patents
Semiconductor package structure and producing method thereof Download PDFInfo
- Publication number
- CN1763939A CN1763939A CNA2004100869653A CN200410086965A CN1763939A CN 1763939 A CN1763939 A CN 1763939A CN A2004100869653 A CNA2004100869653 A CN A2004100869653A CN 200410086965 A CN200410086965 A CN 200410086965A CN 1763939 A CN1763939 A CN 1763939A
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- China
- Prior art keywords
- substrate
- semiconductor package
- illusory
- welding block
- chip
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
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Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 65
- 238000000034 method Methods 0.000 title claims description 21
- 239000000758 substrate Substances 0.000 claims description 64
- 238000003466 welding Methods 0.000 claims description 43
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 claims description 26
- 239000002184 metal Substances 0.000 claims description 8
- 238000004519 manufacturing process Methods 0.000 claims description 4
- 238000000427 thin-film deposition Methods 0.000 claims description 4
- 239000000919 ceramic Substances 0.000 claims description 3
- 239000011521 glass Substances 0.000 claims description 3
- 238000003475 lamination Methods 0.000 claims description 3
- 229910000679 solder Inorganic materials 0.000 abstract description 5
- 238000005516 engineering process Methods 0.000 description 8
- 229910000831 Steel Inorganic materials 0.000 description 7
- 239000010959 steel Substances 0.000 description 7
- 238000005538 encapsulation Methods 0.000 description 5
- 239000006071 cream Substances 0.000 description 4
- 238000010586 diagram Methods 0.000 description 2
- 230000008020 evaporation Effects 0.000 description 2
- 238000001704 evaporation Methods 0.000 description 2
- 238000007747 plating Methods 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 1
- 239000011469 building brick Substances 0.000 description 1
- 238000007772 electroless plating Methods 0.000 description 1
- 238000009713 electroplating Methods 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 230000005855 radiation Effects 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/10—Bump connectors ; Manufacturing methods related thereto
- H01L24/11—Manufacturing methods
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/11—Manufacturing methods
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/14—Integrated circuits
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- Engineering & Computer Science (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Wire Bonding (AREA)
- Electric Connection Of Electric Components To Printed Circuits (AREA)
- Combinations Of Printed Boards (AREA)
Abstract
The semiconductor package structure on the first base comprises: a second base with first and second surfaces, a chip on first surface, a plurality of first solder balls on second surface and arranged in first direction, and at least one dummy solder block on second surface to avoid the incline of the structure. Wherein, connecting both first solder balls and dummy block to first base.
Description
Technical field
The present invention relates to a kind of semiconductor package, particularly relate to a kind of ball grid array (ball grid array, BGA) encapsulating structure with single tin ball (solderball).
Background technology
Generally speaking, integrated circuit (integrated circuit, IC) encapsulation can be divided into pin insert type (pinthrough hole, PTH) with surface installing type (surface mount technology, SMT), because SMT meets requirements such as high I/O number, high heat radiation and package dimension downsizing, so SMT had become the main flow of IC encapsulation technology already.In addition, SMT mainly comprises BGA Package (ball grid array, BGA) with chip-shaped encapsulation (chip scale package, CSP), BGA Package and chip-shaped encapsulation all are to replace pin (lead) with tin ball (solder ball), and chip-shaped encapsulation can be considered the BGA Package of minimal type.
Please refer to Fig. 1 and Fig. 2, Fig. 1 is the bottom view of existing semiconductor encapsulating structure, and Fig. 2 is a semiconductor package shown in Figure 1 generalized section along tangent line 2-2 '.As Fig. 1 and shown in Figure 2, semiconductor encapsulating structure 10 comprises that one has the substrate 12 of a upper surface 12a and a lower surface 12b, one chip 14 is arranged at the upper surface 12a of substrate, a plurality of weld pads (bonding pad) 18 are arranged at the lower surface 12b of substrate 12, and a plurality of tin balls (solder ball) 16, be arranged at each weld pad 18 surfaces respectively.Wherein, chip 14 is an image sensing chip (image sensor chip), Charged Coupled Device (charge coupled device for example, and chip 14 can utilize the mode of routing (wiring bonding) or flip-chip (flip chip) and be connected in substrate 12 CCD) or CMOS image sensing component (CMOS image sensordevice) etc..In addition, semiconductor package 10 can be electrically connected to a printed circuit board (PCB) (printed circuit board by each tin ball 16, PCB) 20, and the formation BGA Package, generally speaking, printed circuit board (PCB) 20 comprises a plurality of joint sheet (not shown)s, is located at respectively between each tin ball 16 and the printed circuit board (PCB) 20.
Along with the progress of semiconductor technology, the various electronic building bricks in the chip 14 are more and more littler, thereby make and the size microminiaturization day by day of chip 14 that is to say that the width W and the length L of chip 14 are dwindled gradually along with the progress of semiconductor technology.Therefore, in order to cooperate the microminiaturization of chip 16, semiconductor package 10 just must reduce the size of each tin ball 16 and dwindle distance between the adjacent two tin balls 16.Yet owing to reasons such as technologies, the distance between the size of tin ball 16 and each tin ball 16 can not unrestrictedly be dwindled, and therefore dwindles constantly when the size of chip 14, and the lower surface 12b of substrate 12 just can only form single tin ball 16 at last.But, as shown in Figure 3, when semiconductor package 10 is electrically connected to printed circuit board (PCB) 20 by single tin ball 16, single tin ball 16 makes semiconductor package 10 produce the situation of inclination easily on printed circuit board (PCB) 20, thereby can cause incidence angle deflection between incident light and the image sensing chip 14, and then influence the accuracy of sensing.
Summary of the invention
The purpose of this invention is to provide a kind of semiconductor package, to solve foregoing problems.
According to purpose of the present invention, the preferred embodiments of the present invention provide a kind of semiconductor package, semiconductor package is arranged on one first substrate, and semiconductor package comprises that one has second substrate of a first surface and a second surface, one is arranged at the chip of the first surface of second substrate, the a plurality of second surface of second substrate and first soldered balls that form a line along a first direction of being arranged at, and at least one illusory welding block that is arranged at the second surface of second substrate, wherein each first soldered ball and illusory welding block are used for second substrate is connected to first substrate, and illusory welding block tilts in order to avoid semiconductor package.
Because the present invention is provided with at least one illusory welding block in the second surface of second substrate, therefore can effectively avoid semiconductor package on first substrate, to produce the situation that tilts.
Description of drawings
Fig. 1 is the bottom view of existing semiconductor encapsulating structure.
Fig. 2 is a semiconductor package shown in Figure 1 generalized section along tangent line 2-2 '.
Fig. 3 is existing generalized section with semiconductor package of single tin ball.
Fig. 4 is the bottom view of the semiconductor package of first embodiment of the invention.
Fig. 5 is a semiconductor package shown in Figure 4 generalized section along tangent line 5-5 '.
Fig. 6 is a semiconductor package shown in Figure 4 generalized section along tangent line 6-6 '.
Fig. 7 is the bottom view of the semiconductor package of second embodiment of the invention.
Fig. 8 to Figure 11 is the manufacture method schematic diagram of semiconductor package of the present invention.
Figure 12 is the bottom view of the semiconductor package of third embodiment of the invention.
The simple symbol explanation
10 semiconductor packages, 12 substrates
12a upper surface 12b lower surface
14 chips, 16 tin balls
18 weld pads, 20 printed circuit board (PCB)s
30 semiconductor packages, 32 substrates
32a upper surface 32b lower surface
34 chips, 36 soldered balls
36a soldered ball 36b soldered ball
38 weld pads, 40 printed circuit board (PCB)s
42 illusory welding block 42a surfaces
44 illusory weld pad 46 steel plates
46a opening 48 tin creams
Embodiment
Please refer to Fig. 4 to Fig. 6, Fig. 4 is the bottom view of the semiconductor package of first embodiment of the invention, Fig. 5 is a semiconductor package shown in Figure 4 generalized section along tangent line 5-5 ', and Fig. 6 is a semiconductor package shown in Figure 4 generalized section along tangent line 6-6 '.As Fig. 4 and shown in Figure 5, semiconductor encapsulating structure 30 comprises that one has the substrate 32 of a upper surface 32a and a lower surface 32b, one chip 34 is arranged on the upper surface 32a of substrate, a plurality of weld pads 38 are arranged at the lower surface 32b of substrate 32, and a plurality of soldered balls (bonding ball) 36, be arranged at each weld pad 38 surfaces respectively.Wherein, chip 34 is an image sensing chip, for example CMOS image sensing component or Charged Coupled Device etc., and chip 34 can utilize the mode of routing or flip-chip and be connected in substrate 32.In addition, chip 34 be shaped as a strip, and each soldered ball 36 is along the long limit of chip 34 and form a line, the width of the minor face of chip 34 is less than 1000 microns (μ m).On the other hand, substrate 32 can be a lamination type printed circuit board (PCB), a co-fired ceramic substrate, a thin film deposition substrate or a glass substrate.
In addition, as Fig. 3 and shown in Figure 5, semiconductor package 30 also comprises an illusory weld pad (dummybonding pad) 44, is arranged at the lower surface 32b of substrate 32, and an illusory welding block (dummybonding bar) 42, is arranged at the surface of illusory weld pad 44.Wherein, illusory welding block 42 has a smooth surperficial 42a, and the height h of illusory welding block 42
2Approximate the height h of each soldered ball 36
1And semiconductor package 30 can be connected to a printed circuit board (PCB) 40 by each soldered ball 36 and illusory welding block 42, forms BGA Package.Generally speaking, printed circuit board (PCB) 40 also comprises a plurality of joint sheet (not shown)s, is located at respectively between each soldered ball 36 and illusory welding block 42 and the printed circuit board (PCB) 40.In addition, each soldered ball 36 and illusory welding block 42 constitute by tin metal.
It should be noted that because illusory welding block 42 has a smooth contact surface 42a, therefore when the surperficial 42a of illusory welding block 42 is connected to printed circuit board (PCB) 40, contacting between illusory welding block 42 and the printed circuit board (PCB) 40 to simultaneously contacting.And, again because the rough long limit, long limit (long side) of illusory welding block 42 perpendicular to chip 34, therefore illusory welding block 42 can make semiconductor package 30 keep a poised state on printed circuit board (PCB) 40, and then avoids chip 34 to produce the situation of inclination on printed circuit board (PCB) 40.In addition, the shape of illusory welding block 42, position and quantity are not limited to shown in Figure 3, that is the shape of illusory welding block 42, position and quantity can change according to arts demand.Therefore please refer to Fig. 7, Fig. 7 is the bottom view of the semiconductor package of second embodiment of the invention.As shown in Figure 7, semiconductor encapsulating structure 30 comprises a substrate 32, and a plurality of soldered balls 36 are arranged on the substrate 32, and two illusory welding blocks 42 are arranged on the substrate 32 and are interspersed between each soldered ball 36.
In addition, please refer to Fig. 8 to Figure 11, Fig. 8 to Figure 11 is the manufacture method schematic diagram of semiconductor package of the present invention, and Fig. 8 is drawn by the tangent line 8-8 ' along Fig. 4 to generalized section shown in Figure 11.As shown in Figure 8, a substrate 32 at first is provided, and, forms a plurality of weld pads 38 and an illusory weld pad 44 in the surface of substrate 32 by technologies such as multiple tracks thin film deposition, little shadow and etchings.Then, provide a metal steel plate 46, its light plate 46 has a plurality of opening 46a, and each opening 46a of steel plate 46 corresponds respectively to each weld pad 38 and illusory weld pad 44.Then, as shown in Figure 9, steel plate 46 is put on substrate 32 surfaces, and exposed each weld pad 38 and illusory weld pad 44, again tin cream 48 is coated subsequently within each opening 46a of steel plate 46, then steel plate 34 is separated with substrate 32.Afterwards, as shown in figure 10, substrate 32 is carried out a Technology for Heating Processing, so that tin cream 48 dissolves and forms each soldered ball 36 and illusory welding block 42.Wherein, the material of tin cream 48 can be leaded tin metal or lead-free tin metal, and its fusing point approximately is 180～235 ℃.In addition, in other embodiments of the invention, steel plate 46 can also replace it with a web plate.
At last, as shown in figure 11, utilize the mode of routing or flip-chip and chip 34 is connected on the substrate 32.In addition, each soldered ball 36 can utilize plating (electroplating), electrodeless plating (electroless plating), evaporation (evaporation) or laser methods such as (laser ball shooter) to form it with illusory welding block 42 in addition.
In addition, Fig. 4 extremely semiconductor package 30 shown in Figure 6 is not the unique execution mode of the present invention, below be other embodiments of the invention, and for convenience of description, the following description is represented identical assembly with identical label.Please refer to Figure 12, Figure 12 is the bottom view of the semiconductor package of third embodiment of the invention.As shown in figure 12, semiconductor encapsulating structure 30 comprises a substrate 32, and a plurality of soldered ball 36a and soldered ball 36b are arranged on the substrate 32, and at least one illusory welding block 42 is arranged on the substrate 32 wherein each soldered ball 36a and each soldered ball 36b setting interlaced with each other.
Compared to prior art, the present invention is provided with at least one illusory welding block 42 in the lower surface 32b of substrate 32.Because illusory welding block 42 has a smooth surperficial 42a, therefore when the surperficial 42a of illusory welding block 42 is connected to printed circuit board (PCB) 40, contacting between illusory welding block 42 and the printed circuit board (PCB) 40 to simultaneously contacting.And, again because the rough long limit, long limit of illusory welding block 42 perpendicular to chip 34, therefore illusory welding block 42 can make semiconductor package 30 keep a poised state on printed circuit board (PCB) 40, and then avoids chip 34 to produce the situation of inclination on printed circuit board (PCB) 40.
The above only is the preferred embodiments of the present invention, and is all according to equalization variation and modification that the present invention did, all should belong to the covering scope of patent of the present invention.
Claims (25)
1. semiconductor package, this semiconductor package is arranged on one first substrate, and it comprises:
One second substrate, it has a first surface and a second surface;
One chip is arranged at this first surface of this second substrate;
A plurality of first soldered balls that form a line along a first direction be arranged at this second surface of this second substrate, and those first soldered balls are used for this second substrate is connected to this first substrate; And
At least one illusory welding block is arranged at this second surface of this second substrate and is connected in this first substrate, tilts in order to avoid this semiconductor package.
2. semiconductor package as claimed in claim 1, wherein this second surface be shaped as a rectangle, and this first direction is parallel to the long limit of this second surface.
3. semiconductor package as claimed in claim 2, wherein the rough long limit perpendicular to this second surface of the Breadth Maximum of this illusory welding block tilts to avoid this semiconductor package.
4. semiconductor package as claimed in claim 3, wherein the width of the minor face of this second surface is less than 1000 microns.
5. semiconductor package as claimed in claim 1, wherein this illusory welding block comprises the 3rd a smooth surface, is connected in this first substrate, tilts to avoid this semiconductor package.
6. semiconductor package as claimed in claim 1, wherein this semiconductor package also comprises a plurality of first weld pads, be arranged at respectively respectively between this first soldered ball and this second surface, and at least one illusory weld pad, be arranged between this illusory welding block and this second surface.
7. semiconductor package as claimed in claim 5, wherein this semiconductor package also comprises a plurality of second weld pads, be arranged at this second surface of this second substrate, and a plurality of second soldered balls, be arranged at respectively on those second weld pads, and those second soldered balls and those first soldered balls are crisscross arranged.
8. semiconductor package as claimed in claim 7, the wherein height of this illusory welding block and this first soldered ball respectively and respectively the height of this second soldered ball is identical.
9. semiconductor package as claimed in claim 7, wherein respectively this first soldered ball, this second soldered ball and this illusory welding block includes leaded tin metal and fusing point approximately is 180～235 ℃ respectively.
10. semiconductor package as claimed in claim 9, wherein respectively this first weld pad, this second weld pad and this illusory weld pad includes lead-free tin metal and fusing point approximately is 180～235 ℃ respectively.
11. semiconductor package as claimed in claim 1, wherein this first substrate comprises a lamination type printed circuit board (PCB), a co-fired ceramic substrate, a thin film deposition substrate or a glass substrate.
12. semiconductor package as claimed in claim 1, wherein this chip is an image sensing chip.
13. the manufacture method of a semiconductor package, it comprises:
One substrate is provided, and it has a first surface and a second surface;
Form a plurality of first soldered balls on this first surface of this substrate, and those first soldered balls form a line along a first direction;
Form at least one illusory welding block on this first surface of this substrate; And
One chip is provided, and this chip is arranged at this second surface of this substrate, wherein this illusory welding block is used for avoiding this semiconductor package to tilt.
14. method as claimed in claim 13, wherein this method also comprises:
One printed circuit board (PCB) is provided, and this printed circuit board (PCB) is connected in this substrate via those first tin balls with this illusory welding block.
15. method as claimed in claim 14, wherein this illusory welding block comprises the 3rd a smooth surface, is connected in this printed circuit board (PCB), tilts to avoid this semiconductor package.
16. method as claimed in claim 13, wherein before forming those first soldered balls and this illusory welding block, this method also comprises:
Form a plurality of first weld pads on this first surface of this substrate, those first weld pads form a line along this first direction, in order to place respectively this first soldered ball; And
Form at least one illusory weld pad on this first surface of this substrate, in order to place this illusory welding block.
17. method as claimed in claim 16, wherein this method also comprises:
Form a plurality of second weld pads on this first surface of this substrate, those second weld pads form a line along this first direction, and those second weld pads and those first weld pads are crisscross arranged; And
Form one second soldered ball respectively in the surface of this second weld pad respectively.
18. method as claimed in claim 17, wherein respectively this first soldered ball, this second soldered ball and this illusory welding block includes leaded tin metal and fusing point approximately is 180～235 ℃ respectively.
19. method as claimed in claim 18, wherein respectively this first weld pad, this second weld pad and this illusory weld pad includes lead-free tin metal and fusing point approximately is 180～235 ℃ respectively.
20. method as claimed in claim 17, the wherein height of this illusory welding block and this first soldered ball respectively and respectively the height of this second soldered ball is identical.
21. method as claimed in claim 13, wherein this first surface be shaped as a rectangle, and this first direction is parallel to the long limit of this first surface.
22. method as claimed in claim 21, wherein the width of the minor face of this first surface is less than 1000 microns.
23. method as claimed in claim 21, the wherein rough long limit of the Breadth Maximum of this illusory welding block perpendicular to this first surface.
24. method as claimed in claim 13, wherein this chip is an image sensing chip.
25. method as claimed in claim 13, wherein this substrate comprises a lamination type printed circuit board (PCB), a co-fired ceramic substrate, a thin film deposition substrate or a glass substrate.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB2004100869653A CN100416807C (en) | 2004-10-20 | 2004-10-20 | Semiconductor package structure and producing method thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB2004100869653A CN100416807C (en) | 2004-10-20 | 2004-10-20 | Semiconductor package structure and producing method thereof |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN1763939A true CN1763939A (en) | 2006-04-26 |
| CN100416807C CN100416807C (en) | 2008-09-03 |
Family
ID=36747989
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CNB2004100869653A Expired - Fee Related CN100416807C (en) | 2004-10-20 | 2004-10-20 | Semiconductor package structure and producing method thereof |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN100416807C (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101267714B (en) * | 2007-03-14 | 2010-04-14 | 富士通株式会社 | Electronic device and electronic component mounting method |
Family Cites Families (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR0157906B1 (en) * | 1995-10-19 | 1998-12-01 | 문정환 | Bga package using a dummy ball and a repairing method thereof |
| JP3795600B2 (en) * | 1996-12-24 | 2006-07-12 | イビデン株式会社 | Printed wiring board |
| JP3801300B2 (en) * | 1997-03-21 | 2006-07-26 | セイコーエプソン株式会社 | Manufacturing method of semiconductor device |
| US6096576A (en) * | 1997-09-02 | 2000-08-01 | Silicon Light Machines | Method of producing an electrical interface to an integrated circuit device having high density I/O count |
| US6242815B1 (en) * | 1999-12-07 | 2001-06-05 | Advanced Semiconductor Engineering, Inc. | Flexible substrate based ball grid array (BGA) package |
| JP3619773B2 (en) * | 2000-12-20 | 2005-02-16 | 株式会社ルネサステクノロジ | Manufacturing method of semiconductor device |
| JP2003188210A (en) * | 2001-12-18 | 2003-07-04 | Mitsubishi Electric Corp | Semiconductor device |
| JP2004200197A (en) * | 2002-12-16 | 2004-07-15 | Seiko Epson Corp | Semiconductor device |
-
2004
- 2004-10-20 CN CNB2004100869653A patent/CN100416807C/en not_active Expired - Fee Related
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101267714B (en) * | 2007-03-14 | 2010-04-14 | 富士通株式会社 | Electronic device and electronic component mounting method |
Also Published As
| Publication number | Publication date |
|---|---|
| CN100416807C (en) | 2008-09-03 |
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Granted publication date: 20080903 Termination date: 20091120 |