CN1758830A - High speed circuitized substrate with reduced thru-hole stub, method for fabrication and information handling system utilizing same - Google Patents

High speed circuitized substrate with reduced thru-hole stub, method for fabrication and information handling system utilizing same Download PDF

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Publication number
CN1758830A
CN1758830A CN 200510105837 CN200510105837A CN1758830A CN 1758830 A CN1758830 A CN 1758830A CN 200510105837 CN200510105837 CN 200510105837 CN 200510105837 A CN200510105837 A CN 200510105837A CN 1758830 A CN1758830 A CN 1758830A
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China
Prior art keywords
substrate
conductive layer
layer
signal
hole
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Granted
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CN 200510105837
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Chinese (zh)
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CN1758830B (en
Inventor
本森·陈
约翰·M·劳弗尔
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Endicott Interconnect Technologies Inc
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Endicott Interconnect Technologies Inc
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Priority claimed from US10/955,741 external-priority patent/US6995322B2/en
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Publication of CN1758830B publication Critical patent/CN1758830B/en
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73253—Bump and layer connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA

Abstract

The invention discloses a circuitized substrate including a plurality of conductive and dielectric layers and also a plurality of conductive through holes therein for passing high speed signals, e.g., from one component to another mounted on the substrate. The substrate utilizes a signal routing pattern which uses the maximum length of each of the through holes, thereby substantially eliminating signal loss (noise) due to through holes ''stub'' resonance. The invention also provides a multilayered circuitized substrate assembly using more than one circuitized substrate, an electrical assembly using a circuitized substrate and one or more electrical components, a method of making the circuitized substrate and an information handling system incorporating one or more circuitized substrate assemblies and attached components.

Description

The high speed circuit substrate that the through hole short-term reduces, its manufacture method and utilize its information processing system
Technical field
The present invention relates to circuitized substrate, a main example is multilayer board (pcb), and it comprises a plurality of through holes that are used to provide the interconnection between difference conduction (for example, the signal) layer that forms a substrate part that are positioned at wherein.The present invention also relates to make the method for this kind substrate and can utilize the various products (for example, information processing system) of this kind substrate as its part.The most particularly, the present invention relates to this kind substrate, method and wherein said substrate is the product that is called as the high-speed type substrate.
Cross reference to common application case co-pending
The application's case is that name is called the 10/354th, No. 000 application case submitting in 30 days January in 2003 of " high speed circuit board and preparation method thereof " (inventor: the application case that continues of part B.Chan etc.).
Background technology
Along with to such as electronic building brick (semiconductor chip and comprise the module of semiconductor chip for example, its be fixed on such as on the circuitized substrate of chip carrier and printed circuit board (PCB) (pcbs) and the circuit by substrate be coupled in together) etc. the increase of job requirement of electronic structure, main substrate also must be able to compensate it.A kind of specific increase is to need the upper frequency between institute's installation component to connect, and as mentioned above, this kind connection is undertaken by following main substrate.This kind connection is subjected to the caused adverse effect of inherent characteristic of the known substrate wiring of this kind, for example signal degradation.For example, signal degradation is expressed " rise time " or " fall time " of the response of step variation by signal.Can use formula (Z 0* C)/deterioration of 2 pairs of signals quantizes, Z wherein 0Be transmission line characteristic impedance, and C is the path capacitance amount.12.5ps decling phase ratio with defined 0.5pf flush type path of the present invention in the parent patent application case mentioned above, have in the lead of standard 50 Ω transmission line impedances one, the plated-through hole via with 4 pico farads (pf) electric capacity will be represented 100 psecs (ps) rise time (or fall time) decay.With 800MHZ or faster in the system of frequencies operations (wherein having 200ps or the speed of coherent signal transition faster), this species diversity is significant.The substrate of institute's teaching can provide at least about 3.0 signal speeds to about 10.0 gigabit/sec (Gb/s) scope herein, and it shows the complexity that needs to increase this final structure.
Because the restriction that direct current (dc) resistance maximum is applied in the connection between the assembly (especially chip), standard high-performance (at a high speed) substrate (substrate that for example is used for known chip carrier and multilayer pcb) can not provide the wiring density that surpasses a specified point always.Similarly, high speed signal need be than the wideer circuit of normal pcb circuit, to minimize " kelvin effect " loss in the long transmission line.The pcb that production has all wide circuits will be unpractical, mainly be because the unnecessary thickness that the soleplate that is produced needs.From design angle, the thickness of this increase obviously is unacceptable.Illustrate as the example of being quoted in the patent that is hereinafter marked, people have used various substitute technologies to attempt providing this kind high speed signal to handle, but these technology also need substrate is made unacceptable modification usually, and this product to a large-scale production and/or a relative simple structure is unhelpful.Equally, the great majority in these technology have also increased the ultimate cost of manufactured goods.
As mentioned above, the present invention relates to utilization and will be called the circuitized substrate of " through hole " and the sub-assembly that is produced in this article.These through holes normally partly or entirely extend through substrate thickness be used for interconnecting each other plating (using such as metallurgy such as the copper) perforate of each layer and/or assembly.Each through hole can interconnect several this type of the layer and/or assembly.If only be positioned at sandwich construction inside, so this through hole is called " path " usually simply, and if these through holes extend desired depths from the one or more surface of substrate, they are known as " blind hole " so.If these through holes almost extend through total thickness from a surface to another surface, so this through hole is commonly referred to as " electroplating ventilating hole " (pth) in affiliated technology.Term used herein " through hole " is intended to comprise all this kind perforates of three types.According to above describing as can be known, comprise that the known substrate of this kind through hole is subjected to the influence of path capacitance-problem of signal attenuation mentioned above usually, if employed through hole has a development length and many signals only pass through the one partial-length by time on it, this problem can be amplified widely so.As follows face be right after more speak more bright.
Using through hole is the problem that is known as loss of signal that is caused by through hole " short-term " as another signal transmission issues of the multilayered circuitized substrate existence of its part.Obviously, it is necessary using above the through hole of the type that defines to be considered to for maximum operational capacity is provided to sandwich construction.Yet, when signal not when the whole length of through hole transmits (for example, these signals are sent to the internal electrically conductive layer that also is coupled to described through hole but only is coupled to described through hole with its partial depth), signal " conflict " can occur, another part will directly be sent to interior layer because part signal trends towards traveling through the residue length (" short-term ") of through hole.Because " bounce-back " of the ergodic part of signal, the result of this " conflict " is signal " noise " or loss.Such as herein explanation, the present invention can eliminate this kind loss basically.
The 5th, 638, in No. 287 United States Patent (USP)s, set forth multiple signal routing circuit (for example, on printed circuit card or plate), this signal routing circuit allegedly can diminish driver from one with the pulse signal with very short rise time and be routed to a plurality of devices.In these routing circuit, the conductor networks of a complexity branches out the conducting path that a plurality of (being three in the embodiment that is disclosed) are uneven in length from the common junction of a contiguous driver output.According to the present invention, the assemblage characteristic impedance phase of the internal driving of driver and individual path coupling, and harmless compensating circuit is attached to the shortest individual path.Compensating circuit transfers to branch's contact at driver place with the signal reflex that will be scheduled to form by the shortest branch through design.If there is not compensating circuit, then from shortest path provide to the reflection of branch's contact with provide from other individual paths to the reflection of this contact be different.Therefore, heavily reflect and be back to branch, cause the distortion of the detected signal in device place from contact.Yet,, provide to the reflection of contact from this branch to occur with the form that the reflection that provides with other branches is complementary if compensating circuit is connected in the shortest branch; And from the reflection of all branches then in the cancellation of driver contact.Therefore, because not heavily reflection, detected distorted signals obviously reduces at the device place.In a preferred embodiment, the compensating circuit printed circuit traces of being connected by the some electric capacity (or several somes electric capacity) with having predetermined capacitance (shape of decision compensatory reflex) with predetermined length (represent have the transmission line short-term that predetermined phase is delayed characteristic) is constituted.Extending beyond, the compensating circuit of short branches end is connected between the end and reference potential (for example, the earth) of this branch.The end of short branch also is attached to and need be used for detecting the device of the signal of this point now.Disclosed a kind of new method and polarization bridge device that is used in particular for analyzing this network (and totally being used to analyze transmission line effect).This method and device allow to observe exactly and relatively rise in the reflection that produces in the network branches of a shared contact, and accurately are identified for revising the suitable compensation of this reflection.
The 6th, 084, set forth integrated circuit encapsulation in No. 306 United States Patent (USP)s, its have first and second layer, a plurality of and ground floor formation one routing liner, the last downcomer (one of them upper conduit is electrically connected to a downcomer) on a plurality of upper and lower surface that is arranged at described ground floor respectively, a plurality ofly be arranged at liner on the second layer, a plurality ofly liner be electrically connected to the path of downcomer and be bonded in a chip (wherein at least one chip is electrically connected to a routing liner) on the second layer with weld pad.
The 6th, 353, set forth a kind of printed circuit board (PCB) in No. 539 United States Patent (USP)s, it comprises first assembly that is fixed on printed circuit board (PCB) first side.Second assembly has the pinout identical with first assembly.Second assembly is installed on second side of printed circuit board (PCB).First pad that first holding wire will be coupled to first contact on first assembly be coupled to second assembly on second pad of corresponding first contact be connected.The 3rd pad that the secondary signal line will be coupled to second contact on first assembly be coupled to second assembly on the 4th pad of corresponding second contact be connected.First holding wire equates with the secondary signal line length.This patent is discussed different path " short-term " length.
The 6th, 526, set forth a kind of apparatus and method that are used to reduce timing slip on the printed circuit board (PCB) in No. 519 United States Patent (USP)s, this printed circuit board (PCB) comprises the conductive trace of plurality of interconnected first node and Section Point.At least a portion that removes a printed circuit board trace is to cut off a trace and to stop signal to be sent to Section Point along cut trace from first node.By this way, the scalable signal path lengths is to reduce the timing slip in the circuit.Can be by using laser, CVD, diesinker, plasma or coming to remove the part trace from described trace by the weakness zone that makes enough electric currents pass trace.
The 6th, 541, set forth a kind of multilayer board in No. 712 United States Patent (USP)s, it comprises the path with the electric insulation mid portion between conduction top, conductive lower portion and top and the bottom.In one embodiment, the insulation mid portion of path is provided by an electroless coating layer of circuit board, and it can be made of PTFE.Path with continuous conduction coating can form by the spacer holes in the electroless coating layer, can be by inserting plated material (for example epoxy resin) or provide these spacer holes so that its electrodepositable is next by an electrodepositable inner surface by regulating the electroless coating material with chemical mode before the described plate of lamination in the hole.In another embodiment, the insulation mid portion of described path has one than the narrow diameter in conduction upper and lower.This patent is passed the selected portion of only electroplating described plate mesopore through discussion and also may be inserted a conduction " embolism " and eliminate resonance " short-term " noise in described hole.
The 6th, 545, set forth a kind of " technology " that is used for reducing the multilayer circuit board number of plies in No. 876 United States Patent (USP)s.Multilayer circuit board has a plurality of electrically conductive signal layers that at least one electronic building brick that is installed in described plate surface carries out signal of telecommunication routing that are used to be to and from.In one embodiment, described technology realizes that by form the first plural conductive path that extends to the first plural conductive signals layer from the multilayer circuit board surface in multilayer circuit board wherein the first plural conductive path forms a passage in arranging with the second plural conductive signals layer below the first plural conductive path.
The 6th, 570, set forth a kind of " device " of at least one circuit unit (for example to another circuit unit) to signal routing that be used to be to and from No. 271 United States Patent (USP)s, this at least one circuit unit has a plurality of I/O lead-in wires and is positioned on the surface of printed circuit board (PCB).Should " device " comprise supporting construction, be fit to the I/O lead-in wire of attaching circuit unit above described first side with first side and second side.It also comprises the signal routing band with first end and second end.First end of routing band goes between to be electrically connected to the circuit unit I/O through structure and adjustment, is to and from described circuit unit to be used for transmission signals.
The 6th, 601, set forth a kind of integrated circuit encapsulation that electrical interconnection is arranged on the first bus signals path on the printed circuit board (PCB) and is arranged on the second bus signals path on the printed circuit board (PCB) equally that is used in No. 125 United States Patent (USP)s.Described integrated circuit encapsulation can have a substrate, a little chip of integrated circuit by substrate supports.Interference networks can be used for the first bus signals path and the second bus signals path are electrically connected to a chip pad on the little chip.Therefore, the first bus signals path and the second bus signals path can be only by the interconnection circuit electrical interconnections.
The 6th, 608, set forth the high density routing is carried out in a kind of permission to holding wire integrated circuit encapsulation in No. 376 United States Patent (USP)s.The substrate of described encapsulation can comprise residently on it has upper surface that bonding refers to, it on the resident lower surface that solder ball arranged and on the signal conductor plane of the resident signal traces conductor of a dielectric spacing distance between upper surface and the lower surface.One path refers to bonding to be connected to the first of signal traces conductor from the upper surface vertical extent.One alternate path is connected to solder ball the second portion of signal traces conductor from the lower surface vertical extent.The routing of path and signal traces conductor causes holding wire to go from regional fan-in or the fan that integrated circuit encapsulation is fit to hold described integrated circuit.
The 6th, 662, set forth a kind of bus routing policy that is used for printed circuit board (PCB) in No. 250 United States Patent (USP)s.This routing policy guarantees to be coupled to the central area of the not routing of trace of a plurality of synchronous device through each encapsulation, and the length of every trace about equally in the assurance bus.This obviously helps to minimize the length that " neck contraction " takes place on it, and guarantees with this trace of no zig zag mode routing.Use this routing policy, the propagation time difference in each groups of traces allegedly is minimized.This patent mentions that also the printed circuit board (PCB) central area below each encapsulation can be for the path use that is connected to shunt capacitance.
The 6th, 681, set forth a kind of method and system that changes caused signal bias by one or more module substrate dielectric materials that is used for reducing in No. 338 United States Patent (USP)s.In one embodiment, the elongated modules substrate with a long axis comprises a plurality of signal routing layers that supported by module substrate.Such as memory device (such as DRAM) but etc. a plurality of devices support by module substrate and be connected with the signal routing layer with mode of operation.The position that a plurality of skews in the described module reduce (for example path) allows to be switched to a different signal routing layer at the signal of two or more many signal routing layer routings.The position that skew reduces can be arranged at least delegation of cardinal principle across the long axis of module substrate.The position row that described skew reduces can be arranged on each position on the described module.For example, the position that reduces of delegation skew can be arranged near described module position intermediate and be offset with effective counteracting.Switching signal differently repeatedly when propagate in described module with convenient signal other positions that the position that a plurality of skews reduce also can be set at described module.
The 6th, 720, set forth a kind of multilayer board in No. 501 United States Patent (USP)s, this printed circuit board (PCB) has cluster blind " path " (a part of degree of depth through hole is explained in more detail hereinafter having of this paper) to make things convenient for the routing of signal line in the signals layer in bus plane.The blind path of a part in the bus plane is combined in together to form a blind path cluster.Corresponding signal routing passage is set in signals layer and aims to allow passing blind path cluster signal traces or signal circuit are carried out routing with blind path cluster in the bus plane.A kind of method of making multilayer board comprises: assemble the first sub-portfolio part of a bus plane, the second sub-portfolio part that forms one group of trunking power supply path that passes the described first sub-portfolio part, assembling one signals layer, the combination first sub-portfolio part with the second sub-portfolio part so that the signal routing passage in the cluster via alignment second sub-portfolio part in the first sub-portfolio part, form the signal path that extends through the first and second sub-portfolio parts and plant crystalline substance or electroplate described power supply and signal path.
Various other circuitized substrate are set forth in the following patent:
4,902,610 C.Shipley
People such as 5,336,855 J.Kahlert
People such as 5,418,690 R.Conn
People such as 5,768,109 J.Gulick
People such as 5,891,869 S.Lociuro
People such as 5,894,517 J.Hutchison
6,023,211 J.Somei
6,075,423 G.Saunders
6,081,430 G.La?Rue
People such as 6,146,202 S.Ramey
People such as 6,222,740 K.Bovensiepen
People such as 6,246,010 R.Zenner
6,431,914 T.Billman
People such as 6,495,772 D.Anstrom
People such as US2002/0125967 R.Garrett
JP4025155A2 O.Takashi
The teaching content of all above-mentioned documents all is incorporated herein with way of reference.
From hereinafter recognizing, main purpose of the present invention provides a modified model circuitized substrate, this substrate provides the enhancing between the electronic building brick that is installed on the substrate to connect at a high speed by the enhanced signal routing system in the substrate, this substrate utilizes the maximum length of through hole, thereby has eliminated the loss of signal that is caused by through hole " short-term " basically.
It is believed that the electrical assemblies and that multilayered circuitized substrate assembly, that this substrate, is made the method, of this kind substrate and utilized two or more this kind substrates uses at least one circuitized substrate and at least one electric assembly is installed above it uses the information processing system of this kind substrate (and sub-assembly) will represent the major progress of described technology.
Summary of the invention
Therefore, main purpose of the present invention is by providing the substrate that can send a signal to the interconnection electronic building brick that is installed on the substrate at a high speed to come the intensifier circuit substrate technology.
Another object of the present invention provide a kind of make this substrate and by the multilayered circuitized substrate assembly of forming more than this kind substrate, have a circuitized substrate and on the electrical assemblies of at least one electronic building brick is installed and be fit to uses the method for the information processing system of this substrate.
According to an aspect of the present invention, it provides a kind of high speed circuit substrate, and it comprises: the plural conductive layer; A plurality of dielectric layers; Its positioned alternate described conductive layer selected between and conductive layer is electrically insulated from each other; And plurality of through holes, it is positioned in the substrate at interval and extends through the selected layer of described dielectric layer and conductive layer, be electrically interconnected to another layer of described conductive layer with selected layer, thereby allow between these interconnect conductive layers, to transmit the signal of telecommunication described conductive layer.The described signal of telecommunication passes the maximum length of described through hole so that eliminate the loss of signal that the through hole short-term causes basically.
According to a further aspect in the invention, it provides a kind of method of making the high speed circuit substrate, and described method comprises: the plural conductive layer is provided; Provide a plurality of dielectric layers and with the selected layer positioned alternate of described dielectric layer described conductive layer selected between so that conductive layer be electrically insulated from each other; In substrate, form plurality of through holes to be orientated at interval, so that plurality of through holes extends through the selected layer of described dielectric layer and conductive layer and is electrically interconnected to another layer of described conductive layer with the selected layer with described conductive layer, thereby allows to transmit the signal of telecommunication between these interconnect conductive layers.The described signal of telecommunication passes the maximum length of described through hole so that eliminate the loss of signal that is caused by the through hole short-term basically.
According to another aspect of the invention, it provides a kind of electrical assemblies that comprises a high speed circuit substrate, and this high speed circuit substrate comprises: the plural conductive layer; A plurality of dielectric layers, its positioned alternate described conductive layer selected between and these conductive layers are electrically insulated from each other; Plurality of through holes, it is positioned in the substrate at interval and the selected layer that extends through described dielectric and conductive layer is electrically interconnected to another layer of described conductive layer with the selected layer with described conductive layer, thereby allows to transmit the signal of telecommunication between these interconnect conductive layers.The described signal of telecommunication passes the maximum length of described through hole to eliminate the loss of signal that is caused by the through hole short-term basically.Described sub-assembly comprises that further at least one is positioned on the described circuitized substrate and is electrically coupled to the electric assembly of described circuitized substrate.
According to another aspect of the invention, it provides a kind of high speed circuit substrate assembly, described high speed circuit substrate assembly comprises: the first high speed circuit substrate, it comprise the first plural conductive layer and first a plurality of positioned alternate first conductive layer selected between and dielectric layer that described first conductive layer is electrically insulated from each other; The second high speed circuit substrate, it comprise the second plural conductive layer and second a plurality of positioned alternate second conductive layer selected between and dielectric layer that described second conductive layer is electrically insulated from each other, described second circuit substrate is bonded to described first circuitized substrate to form a circuit beggar sub-assembly; And plurality of through holes, it is positioned in the high speed circuit substrate sub-portfolio part and the selected layer of described first and second plural conductive layer of electrical interconnection transmits the signal of telecommunication with permission at the interconnect conductive interlayer.The described signal of telecommunication passes the maximum length of described through hole to eliminate the loss of signal that is caused by the through hole short-term basically.
According to another aspect of the present invention, it provides a kind of cabinet, that comprises to be positioned at the information processing system of the high speed circuit substrate in the cabinet, and described high speed circuit substrate comprises: the plural conductive layer; A plurality of dielectric layers, its positioned alternate described conductive layer selected between and these conductive layers are electrically insulated from each other; Plurality of through holes, it is positioned in the substrate at interval and extends through selected layer of another layer that is electrically interconnected to described conductive layer with the selected layer with described conductive layer of described dielectric layer and conductive layer, thereby allow transmitting the signal of telecommunication between the conductive layer of interconnection, the described signal of telecommunication passes the maximum length of described through hole to eliminate the loss of signal that is caused by the through hole short-term basically.This system comprises that further at least one is positioned on the described circuitized substrate and is electrically coupled to the electric assembly of described circuitized substrate.
Description of drawings
Fig. 1 is the side-looking vertical cross section of the part of the multilayered circuitized substrate (example that is defined in the above-mentioned parent patent application case is PCB) according to the one aspect of the present invention that is defined in the parent patent application case;
Fig. 2 is the side-looking vertical cross section according to the part of the multi-layer PCB on the other hand of the present invention in the parent patent application case;
Fig. 3 is the side-looking vertical cross section according to a multi-layer PCB of one aspect of the present invention in the parent patent application case;
Fig. 4 is the side-looking vertical cross section according to the multi-layer PCB on the other hand of the present invention in the parent patent application case;
Fig. 5 is the side-looking vertical cross section according to a multi-layer PCB of another aspect of the invention in the parent patent application case;
Fig. 6 is the side-looking vertical cross section according to a multi-layer PCB of another aspect of the invention in the parent patent application case;
Fig. 7 is a plan view from above, and its graphic extension can be used on according to the circuit pattern on the multi-layer PCB of one aspect of the present invention in the parent patent application case;
Fig. 8 is the side-looking vertical cross section along Fig. 7 center line 7-7 intercepting;
Fig. 9 is the side-looking vertical cross section of a high speed circuit substrate according to an embodiment of the invention;
Figure 10 one can utilize the front view of the electrical assemblies of one or more circuitized substrate of the present invention; And
Figure 11 one can use the perspective view of the information processing system of one or more circuitized substrate of the present invention (and may be electrical assemblies).
Embodiment
In order to understand the present invention and other and further purpose, advantage and ability better, this paper is in conjunction with the above-mentioned accompanying drawing following disclosure of reference and the claim of enclosing.Should be appreciated that, will use identical numbering to represent similar elements among each figure.
As mentioned above, term used herein " at a high speed " is meant high-frequency signal.Defined herein circuitized substrate can obtain and use herein, and the example of this kind signal frequency that method produced of teaching comprises about 3.0 to the interior frequency of about 10.0 gigabit/sec (Gb/s) scope.Yet these examples are not to be intended to limit the present invention, because can obtain to comprise this extraneous frequency of higher frequency yet.From hereinafter can further understanding, the circuit product of Sheng Chaning can be made of at least two independent layered portion that form before bonded to each other herein.Each this independent sector is with minimum at least one dielectric layer and conductive layer of comprising, most probable embodiment is that each part comprises that several layers of dielectric layer and conductive layer are as its part.Each part also can comprise one or more through holes, to aim at the associated through-holes in its other substrates that will be bonded to.The scope of the invention also contain form each other a plurality of this kind substrates (comprising the substrate that has through hole and do not have through hole) and then in bonding (lamination) sandwich construction (bonding) through hole is provided.The example that hereinafter provides not is to be intended to limit scope of the present invention nothing but the example (only as an example) and the number of plies shown and that describe.
This paper will use following term and should understand it has relative meaning.
Term " circuitized substrate (circuitized substrate) " be intended to comprise have at least two dielectric layers, two conductive layers and in most of the cases a plurality of substrates that are positioned at through hole wherein.In many cases, this kind substrate will comprise several dielectric layers, conductive layer and through hole.Example comprises the structure of making by such as dielectric materials such as glass fibre reinforcing ring epoxy resins (some is called as " FR-4 " dielectric material), polytetrafluoroethylene (Teflon), polyimides, polyamide, cyanate resin, Photoimageable material and other similar materials, wherein each conductive layer is by a metal level that constitutes such as suitable metallurgical materials such as copper (for example power supply, signal or ground connection), but it can comprise or comprise additional metals (for example, nickel, aluminium etc.) or its alloy.If be used for the dielectric material of described structure is the Photoimageable material, and then it manifests desired circuit pattern through photoimaging or light patternization and after developing, and comprises defined desired perforate (if desired) herein.This dielectric material can be coated with through curtain coating or net, or can be used as dry film and provide.The final curing of Photoimageable material provides a dielectric malleableize pedestal, to form desired circuit thereon.A kind of example of concrete Photoimageable dielectric combination comprises about 86.5% to about 89% solid matter, and this solid matter comprises: about 27.44% PKHC, a kind of phenoxy resin; 41.16% Epirez 5183, a kind of tetrabromobisphenol A; 22.88% Epirez SU-8, a kind of eight sense epoxy bisphenol-A formaldehyde resins; 4.85%UVE1014 light initiator; 0.07% ethyl violet dyestuff; 0.03%FC 430, a kind of fluorinated polyether non-ionic surface active agent from 3M company; 3.85%Aerosil 380, a kind of amorphous silicon that is used to provide described solid matter from Degussa.Existence one accounts for the solvent of total Photoimageable dielectric combination 11% to 13.5%.The dielectric layer of institute's teaching can be about 2 Mills usually to about 4 mil thick herein, but if desired also can be thicker.It should be noted that and as indicated above, can form the composite multi-layer structure of forming by a plurality of this kind substrates, wherein one or more substrates can have as its a part of through hole and other substrates do not have through hole and aim at and lamination after through hole is provided in final structure.These through holes that provide subsequently are extensible to be passed the whole thickness of final structure and/or only occupies wherein a desired depth.Also can form have several sandwich constructions that do not have the circuitized substrate that is pre-formed through hole and, at the through hole that this whole degree of depth or partial depth are provided in final structure behind the lamination.Further, formed herein this kind final structure can be formed by the independent circuitized substrate that wherein respectively has one or more through holes, and wherein substrate is aligned so that through-hole alignment, and (lamination) then bonds.The sandwich construction that is synthesized will comprise the through hole of several alignings and may comprise other inner through hole that forms (inner " path ").
Used herein term " circuitized substrate sub-assembly (circuitized substrate assembly) " is intended to comprise at least two these circuitized substrate in the bonding structure, one bonding example is the known traditional lamination procedure of affiliated technical field, and another example is to use conductive paste to couple two established substrates along a shared pattern of conductor (for example through hole).
Term used herein " electronic building brick (electronic component) " means such as semiconductor chip, resistor, capacitor and similar assembly, and these assemblies are fit to be positioned at such as on the outer conductive surface of substrates such as PCB and can use the inside of (for example) PCB and/or external circuit to be electrically coupled to other assemblies and electric coupling each other.
Term used herein " conductive paste (electrically conductive paste) " is intended to comprise that one can be coated with boning in the perforate that imposes on this paper institute teaching type (for example, can lamination) electric conducting material.The representative instance of electric conducting material of can boning is a conductive paste, and for example the trade mark of buying from E.I.duPont deNemours company is the epoxy paste that is filled with silver of CB-100, the Ablebond 8175 that buys from Ablestick company and contain transition liquid conduction particle or other are such as the thermosetting of metallics such as gold, tin, palladium, copper, alloy and combination thereof or the polymer-filled system of thermoplastic type.One particular instance is the copper cream through coating.Also can use the metal coated polymer particle that is arranged in the polymer substrate.
Term used herein " sticking tablet " is intended to comprise dielectric material, for example uses traditional preimpregnation glue material of (for example, passing through lamination usually) in traditional multilayer pcb structure.Other examples comprise product P yrolux and liquid crystal polymer (LCP) or other self-supporting films.These dielectric sticking tablets can bonding method be applied to two circuitized substrate one of them or two and go up to help bonding two these assemblies.If desired, also can (for example) by laser or photoimaging with these sticking tablet patternings.It should be noted that this kind sticking tablet also can comprise the current densities of a conductive plane (comprising signal, ground connection and/or power supply) with further increase Manufactured bonding product taught herein therein.It is thick that this kind sticking tablet can be generally 5 to 8 Mills (one thousandth).
Term used herein " electrical assemblies " means at least one circuitized substrate defined herein and at least one electric coupling and form the combination of the electric inter-module of a described sub-assembly part with it.The example of known this kind sub-assembly comprises and comprises the chip carrier of semiconductor chip as described electric assembly, described chip is positioned on the described substrate usually and is coupled to the wiring (for example, liner) on the described substrate outer surface or uses one or more through holes to be coupled to inner conductor.Perhaps this kind sub-assembly of knowing most of people is conventional pcb, and it has such as mounted thereto of resistor, capacitor, module (comprising one or more chip carriers) etc. and is coupled to several external modules of described pcb internal circuit.
Term used herein ' information processing system ' will refer to mainly to be designed for calculating, classification, processing, emission, reception, retrieval, initial, switch, store, show, manifest, measure, survey, write down, duplicate, handle or utilize any type of information, information or data for any instrument or the instrument combination that are used for commerce, science, control or other purposes.Example comprises that personal computer reaches such as bigger processors such as server, mainframe computers.This kind system generally includes one or more pcb chip carriers etc. as the one part.For example, a normally used pcb comprises mounted thereto a plurality of various assemblies, for example chip carrier, capacitor, resistor, module etc.One this type of pcb can be known as one " motherboard ", and can use suitable electric connector that various other circuit boards (or plug-in unit) are installed on the described motherboard.
In Fig. 1 and Fig. 2, two embodiment that shown multi-layer portion 20 and 20 ' respectively, when described multi-layer portion is bonded to another multi-layer portion, the described circuitized substrate (example of institute's reference is a printed circuit board (PCB) in the parent patent application case) of one embodiment of the present invention of being indicated in the parent patent application case listed above will be formed.Correspondingly, part 20 and 20 ' will be defined as second portion and other parts will be called as first (or pedestal) part in this article.Should be appreciated that according to wide aspect of the present invention, at least one second portion is bonded to described first so that this second portion is located along the exterior section of final products substantially.Also should be appreciated that, one or more these type of second portions can be bonded to described pedestal (first), comprise on the opposite side that is bonded to as the described pedestal of Fig. 3-6.The second portion particular design of it should be noted that most herein to be defined be used for such as chip module or or even install (for example soldering) to and/or otherwise be electrically coupled between the electronic building bricks such as simple chip separately of second portion and provide high frequency (at a high speed) to connect.Importantly, described first or base part will not necessarily need this kind ability but form with the employed usual manner of the current pcb of majority, above describe many this kind pcb in the listed document.Therefore, the present invention allows to utilize known pcb manufacturing technology to come the composite structure that production performance increases greatly so that can be connected and fixed thereon electronic building brick with the speed higher than the speed that can reach so far.This kind connection is considered to essential in the pcb technology of expansion rapidly, and its main cause is in corresponding increase to this class component requirement.That therefore, is defined in the parent patent application case the invention provides major progress in this technology.With respect to the teaching that forms equally in the parent patent application case, should be further appreciated that described teaching is applicable to and relevant many aspects of teaching of the present invention herein about substrate.The most important thing is, form relevant teaching such as (comprising circuitization), layer and substrate lamination, through hole formation with the layer of institute's teaching in the parent patent application case and be equally applicable to the present invention.
In Fig. 1, show that multi-layer portion 20 comprises that one is used as the center conductive plane 21 of power plane in a preferred embodiment.Plane 21 is surrounded by two layers of dielectric materials 23, and it is shown as a continuous structure because of two-layer all bondings (lamination) in the drawings to plane 21.Additional conductive plane 25 and 27 is positioned on the outer surface of dielectric material 23, and it comprises a series of signal line in a preferred embodiment of parent patent application case.Therefore, part 20 can be called as the 2S1P structure simply, and the meaning is that it comprises two signal plane and a power plane.Also provide conductive through hole 29 to connect upper signal plane 25 and lower flat 27.In a preferred embodiment, described conductive through hole is an electroplating ventilating hole (pth) that uses known techniques to form.The formation of part 20 is to use known pcb program to finish, and comprises lamination dielectric layer mentioned above and deposition (for example electroplating) external signal plane.Therefore believing does not need further technology to set forth.
As mentioned above, when forming part 20 in conjunction with another multi-layer portion when forming a final substrat structure, part 20 is designed for provides (high frequency) connection at a high speed between the electronic building brick that couples with it.Therefore, for providing this kind to connect at a high speed, define in the parent patent application case that independent holding wire in the part 20 (and 20 ') of (and can use in the present invention) is preferable to have about 0.005 inch extremely about 0.010 inch width and 0.0010 to about 0.0020 inch thickness.Corresponding dielectric layer in two inventions also have separately preferable about 0.004 inch to about 0.010 inch thickness, or more particularly, guarantee the thickness that desired signal line impedance is required.Plane 21,25 and 27 used materials are preferably copper, but can use other electric conducting materials.Preferred dielectric material 23 is a kind of low consumption dielectrics, and example is the polyclad LD621 that can buy from the Cookson electronics, inc. that is positioned at New Hampshire West Franklin.Other materials comprises the Nelco 6000SI that can buy from the Park Nelco company that is positioned at NewYork Newburgh and the Rogers 4300 that can buy from the Rogers company that is positioned at ConnecticutRogers.These materials have low-k and fissipation factor thinks that described structure provides best operational capability.Other have≤0.01 and the material of preferable dielectric loss less than＜.005 will be suitable for part 20 and 20 ' the two.Also can use the dielectric material of above discussing equally to replace this three described dielectric materials of example.
Should be appreciated that above-mentioned thickness and the material that is defined are not intended to limit the invention and the scope of the present invention of parent patent application case, as long as, also can use other thickness and material because reach the desired result of institute's teaching herein.In an example, when using above-mentioned thickness, width and material, can provide the second portion 20 (reaching 20 ') that can transmit signal with one about 3 signal frequency to about 10gps scope.This also is not intended to limit the present invention, because one or more above-mentioned materials, parameter etc. are made little relatively modification, higher frequency (for example 12gps) also is possible.According to an embodiment, the gross thickness of the part that defines 20 that is produced is less than about 0.140 inch.
Although be not parent patent and of the present invention one essential requirement, the above-mentioned width and the thickness that are used for conductive plane and dielectric layer usually will be thicker than the width and the thickness of part 20 and the 20 ' pedestal that will bond or first multi-layer portion.That is to say that base part will generally include littler thickness and width dimensions to be used for wherein employed conductive plane and dielectric, this kind width, thickness and material are representative width, thickness and the materials of employed known PCB structure today.Therefore, do not need to be further elaborated.
An embodiment of the printed circuit board (PCB) 30 of teaching has wherein utilized two second portions 20 in Fig. 3 graphic extension parent patent application case, and each of described second portion is positioned on the opposite side of shared first multi-layer portion 31.For simplicity, first 31 is shown as a single dielectric layer that comprises outer conducting layer 33 and 35 on it.In one embodiment, depend on the operation requirement of soleplate 30, layer 33 and 35 is power supply or ground plane.In a preferred embodiment, part 31 comprise several (for example, 20) signals of being positioned at wherein, and/or conductive plane and corresponding a plurality of (for example, 19) dielectric layer of capacity of power.In its simple form, part 31 (and 31 ' among Fig. 4-6) comprises with first fast frequency and transmits at least one signal plane of signal along it.Show conductive plane and dielectric layer that conductive plane that uses in first multi-layer portion 31 and dielectric layer are normally utilized as previously referred in traditional pcb.Therefore, in an example, part 31 can comprise having about 0.003 inch conductive signal wire to about 0.010 inch width and 0.0005 inch respective thickness.Dielectric layer respectively comprise one about 0.003 inch to about 0.010 inch original depth.First 31 with this kind sandwich construction is in turn laminated to together and forms described first 31 with several conduction dielectric layers that bond.In addition, form second portion 20 in a similar manner as independent, multilayer sub-portfolio part mentioned above.In next step, the opposite side of first 31 and another dielectric layer 43 being added on each of extreme outer surfaces of first 20 in the middle of dielectric layer 41 (for example, traditional preimpregnation glue material) is added into.Now use this structure of lamination treatment technology lamination of standard, single to form, multilayered circuitized substrate assembly (this example is a multilayer pcb in parent patent).Since on the architectural characteristic addressing herein to be explained, some signal plane in the second portion 20 and 20 ' can provide the signal higher than some the holding wire frequency in traditional at least first 31 and 31 ' to transmit at least.In the preferred embodiment of institute's teaching, compare with its signals layer with the first of bonding in the parent patent application case, all holding wires in the exterior section have the more superior ability of this kind.From hereinafter understanding, this is not of the present invention one essential requirement, and in the present invention, all signals can frequency identical or much at one pass described circuitized substrate.
For visiting the one or more external conductive plane on each part 20, externally provide perforate 45 in the dielectric layer 43.This preferably finishes by laser known in the affiliated field or the operation of light seal.Remove after the described dielectric material, in Fig. 3, (comprise in dielectric perforate) on the opposite side of structure and add an outer conductive layers 51.At this moment, the connection that is used for electric assembly of the holding wire that is coupled to part 20 is provided on printed circuit board (PCB) 30, and this will guarantee that successively high speed signal is sent to the second electric assembly (not shown) that in (for example) Fig. 3 observer left side also is coupled to the circuit of same section 20 along these holding wires (comprising the holding wire on the upper and lower surface of each part 20).As shown in Figure 3, this kind connection also can provide by the perforate in the electric conducting material 51.
Should be appreciated that in Fig. 3 two or more electric assemblies (for example chip carrier, capacitor, resistor or only semiconductor chip) can be installed on each opposite side of pcb30 and with high-frequency signal and be coupled in.Therefore, the operational capacity that the high-speed assembly that pcb that invents in the parent patent application case and circuitized substrate taught herein and substrate assembly can couple its counter surface (or if desired, same side) is uniquely had with the pcb (substrate sub-portfolio part) that guarantees to finish and component groups component is far above operational capacity known so far in the affiliated technical field.
Couple for additional, also can add another layer dielectric material 55 to cover conductive plane 51, in this case, can finish by similar perforate and electric conducting material 61 among Fig. 3 with being connected of electric conducting material 51 in the perforate 45, with the assembly on electric coupling pcb 30 1 sides.Can utilize electroplating ventilating hole (pth) 71 to extend through the whole thickness of pcb 30, shown in the right among Fig. 3.This through hole can use conventional art to form and will comprise that (for example) is positioned at its lip-deep one thin electric conducting material (for example, copper) electrodeposited coating.A conductive pin or similar assembly also can use this through hole to hold this add-on assemble if desired.Described pth 71 also can couple the inner conductive plane of one or more assemblies to the first 31.
The example of an electric assembly is described with shadow graphing among Fig. 3.As mentioned above, this assembly can comprise an electronic module (chip carrier) or only comprise a semiconductor chip 77 that uses solder ball 79 to be coupled to electric conducting material 61 (or another be chosen as, if do not utilize material 61, then directly be coupled on the material 51).Another is chosen as, and this assembly can comprise a metal lead wire that protrudes, and the metal lead wire of this protrusion will connect (for example soldering) again to material 61.This class component and connection means are known by people in affiliated technical field, and believing does not need to be further elaborated.
Get back to Fig. 2, part 20 ' comprise with Fig. 1 in like the component class of part 20 assembly but representative use teaching in this paper and the parent patent application case to form an alternate embodiment of a sandwich construction.Part 20 ' comprises and being positioned at wherein and as its a part of 2S1P part 20.On the counter surface of part 20, add dielectric layer 81, with after-applied (for example by electroplating) conductive layer 83.As shown in the figure, conductive layer 83 is preferably ground connection or power plane and is coupled in together by an electroplating ventilating hole 85.As part 20, in described second portion, utilize several this kind through holes that this kind connection is provided.Be the graphic extension purpose, in Fig. 1 and Fig. 2, only shown a through hole, but according to the embodiment among Fig. 9 show and more detailed description multi-through hole more.Preferably, dielectric layer 81 have with part 20 in the low-loss dielectric layer materials similar used.As part 20, use each layer of traditional lamination treatment process built-up section 20 '.
In Fig. 4, shown two second multi-layer portion 20 ' be bonded to one shared in the middle of multilayer first 31 ', in a preferred embodiment of parent patent and as indicated above, it comprises several inner conductive plane (not shown), and described inner conductive plane is bonded together to form the multilayered circuitized substrate assembly element of (being called pcb in the parent patent application case) by the independent dielectric layer (also not showing) of respective numbers.Owing to the lamination step that needs in the final operating period that bonds still less, therefore, the embodiment of Fig. 2 represents the more simple means of producing final PCB (30 ' among Fig. 4).That is to say, only need three shown among lamination Fig. 4 previous sandwich constructions 20 ' and 31 ' that form.Equally, according to more wide aspect of the present invention, it should be noted that and only an exterior section 20 ' to be bonded to following traditional pcb 31 '.After finishing lamination, can use to be similar among Fig. 3 to providing perforate 45 and electric conducting material 51 defined technology that one external dielectric layers 55 ' is added into described structure and a conduction perforate 51 ' being provided therein.If desired, electroplating ventilating hole 85 can be coupled to the random component that is connected to material 51 ' top and/or the bottom of part 20 '.For coupling the extreme outer surfaces of PCB 30 ', the through hole 71 that is similar among Fig. 3 provides a shared through hole 71 '.Preferably, this through hole will comprise with Fig. 3 in the plated conductive material 73 ' of plated conductive materials similar.
The more important thing is that through hole 71 and 71 ' can be respectively applied for the internal wiring that one or more electric electrical component is coupled to first multi-layer portion 31 and 31 ', the direct electrical connection between these assemblies and the intermediate structure is provided thus.Therefore, except that these assemblies are coupled to the inner conductive plane of the pedestal of total or first, the unique ability that the present invention also gives security and couples between the assembly on the side of described plate.The dual representative importance of the present invention that couples of this kind is because it causes final products to have the operational capacity bigger than known so far product.
In Fig. 5 and Fig. 6, shown two alternate embodiments 30 of parent patent application case invention respectively " and 30 .Pcb30 among Fig. 5 " similar shown structure in Fig. 4, but added a conductive through hole 91 that extends to a conductive plane of part 20 ' from an outer surface.Therefore, except that defined coupling the additional electronic components above, also can couple the assembly (being the pin 93 that shows among Fig. 5 and Fig. 6) of band pin.In the embodiment of Fig. 6, provide one to pass the prolongation perforate 95 that part 31 ' reaches than lower part 20 '.The reason that perforate 95 is provided is to provide suitable gap for inserting pin 93.With traditional " back drill " method forms contrast is to be pre-formed (boring system) perforate 95 to eliminate the untapped part of pth before final lamination on 31 ' and 20 '.The part of the removable PTH copper of back drill layer.When handling high speed signal, this has reduced the capacity effect of pth.Except that having improved the reliability factor that may increase of making product, back drill is considered to relatively costly and is difficult to usually implement, thereby also increases the cost relevant with formed product.Institute's teaching and do not need back drill and obtained identical effect among structure in the parent patent application case and Fig. 9 as the structure of a part of the present invention.
Fig. 7 and Fig. 8 have described a second portion 20 on the other hand of inventing in the parent patent application case " an embodiment.Can understand, Fig. 8 is the cutaway view along Fig. 7 center line 8-8 intercepting, and is used for graphic extension part 20 " the embodiment of respective width of upper surface upper conductor.The through hole that has also shown the associated end that is positioned at more wide degree conductor among the figure.In this kind layout, more wide degree conductor 101 is positioned at its electroplating ventilating hole 103 to set terminal as holding wire with interconnection.As a comparison, narrower width signal line 105 ties up between 101 pairs in the respective external broad circuit with paired pass and extends.In one embodiment, circuit 101 can have from about 0.003 inch to about 0.012 inch width, and corresponding inner narrower circuit can respectively have from 0.002 inch to about 0.010 inch width.These line segregations open one about 0.003 inch to about 0.012 inch distance.Provide suitable trace impedance control and signal shielding to minimize the noise that is coupled in the middle of the holding wire in the purpose that big width circuit 101 is provided on the opposite side of paired narrower holding wire 105.Can see that in Fig. 8 these holding wires are positioned at part 20 " opposite side on, and 105 of narrower holding wires that are positioned at conduction (for example, power supply) 106 outsides, plane in the middle of are coupled to center pth 103.This kind layout provides the favorable characteristics of continuous reference planes, and it can provide maximum signal shielding.This has realized the structure that the subgroup compound is more simplified, and has also realized having the part with different dielectric thickness that Z connects; For example, fast signal is to slow signal.
In Fig. 9, shown a multiple layer high speed circuitized substrate sub-assembly 121 according to an embodiment of the invention.Sub-assembly 121 comprises at least two (and preferable a plurality of) circuitized substrate 123,125 and 127 separately, its each all have a plurality of dielectric layers 128 that positioned alternate wherein has electron conduction layer 130.Similar with the conductive layer 130 in the part 20 and 20 ' that is above defined, conductive layer 130 is electrically insulated from each other by intermediate dielectric layer 128.Comprise plurality of through holes in each substrate, it can be in three types referred to above one or more.For example, comprise a plurality of electroplating ventilating holes 131 and a plurality of flush type (inside) path 133 in the intermediate substrate 125, and substrate 123 comprises a plurality of electroplating ventilating holes 131 and a blind path 135.Substrate 127 comprises a plurality of electroplating ventilating holes 131 and two flush type paths 133.Shown number of through-holes only is used for graphic extension and should be appreciated that: each substrate can comprise several through holes more than graphic extension.The illustrated conductive layer and the number of dielectric layer also are kindred circumstances.In an example of the present invention, each substrate 123,125 and 127 can comprise from two to 12 dielectric layers 128, from three to 13 conductive layers 130, and from the through hole of about 20,000 to 50,000 shown types, the latter shows and can use teaching of the present invention to reach high relatively density.As mentioned above, can to other substrates, form the substrate that wherein has one or more through holes in bonding (lamination).Another is chosen as, and under the situation of electroplating ventilating hole, described substrate can be in turn laminated to together to form the sub-assembly among Fig. 9 and some is provided this type of hole of (for example, use machine drilling or laser) to pass the whole thickness of described sub-assembly at least.Therefore several combinations of these three kinds of via arrangement are possible and in the scope that one of ordinary skill in the art understood thoroughly.
In the embodiment of Fig. 9, should be appreciated that: an intermediate dielectric layer 135 is separated first circuitized substrate 123 with intermediate circuit substrate 125, tertiary circuit substrate 127 and intermediate substrate 125 also are like this.This intermediate dielectric layer is preferably above defined sticking tablet and therefore provides a dielectric layer between corresponding substrate.For being electrically connected the exposed distal ends of illustrated electroplating ventilating hole 131, the conductive paste 137 of preferable use some.In Fig. 9, use the conductive paste of two these quantity only to use the conductive paste of this quantity to be electrically connected substrate 125 and substrate 127 so that two connections between substrate 123 and 125 to be provided.Provide this conductive paste linking number only to be used for the graphic extension purpose and be not to be intended to limit the present invention, because the conductive paste that requires to make several other types according to the final operation of manufactured goods connects.For example, tight electroplating ventilating hole in its lower section in the electroplating ventilating hole 131 of high order end in the substrate 123 and the substrate 125 can be coupled mutually.Certainly, this kind connection is essential for making signal be sent to other substrates by a substrate.In the illustrated example of Fig. 9, be not desirably in this last position conducted signal and therefore a connection is not provided.
In the invention of being defined in the parent patent application case of above being quoted, the frequency of the comparable signal that transmits in intermediate substrate 125 of frequency that the present invention cover the signal that transmits in the substrate 123 and 127 externally is big, and vice versa.Be appreciated that in the external substrate one or both can directly be coupled to the external module such as chip carrier and/or semiconductor chip.Shown two this kind assemblies (chip carrier 14) with dash area ground among Fig. 9 and only be positioned on the side (upside) of upper substrate 123.If the element shown in expectation couples on the side, sub-assembly 121 will have externally substrate 123 (and 127, if assembly is installed on the described substrate) to transmit the ability of signal than speed higher in the intermediate substrate 125 and therefore bigger frequency.As mentioned above, the present invention cover the assembly that couples on the opposite side and therefore provide similar fast frequency ability for external substrate.In this kind structure, these external modules will be coupled to each other on same side, and if expectation is coupled to each other the assembly of relative positioning together, also can form intermediate substrate and make it have high speed capability.Sub-assembly 121 is that uniqueness can provide all these may couple the sub-assembly of combination.It should be noted that, use one to be lower than the sub-assembly 121 that intermediate substrate at a high speed makes it possible to provide a lower cost, because intermediate substrate can be made up of traditional non-high speed signal and bus plane, reduce thereby compare its cost with the technology that making high speed substrate is utilized.
Assembly 140 (no matter being chip carrier, semiconductor chip or similar assembly) preferably uses the solder ball (now by numeral 143 representatives) that is above defined to be coupled to corresponding conductive gasket 141.If utilize opposite side assembly (not shown), so also preferably use this kind connection.Defined herein circuitized substrate sub-assembly 121 utilizes its whole thickness (all three substrates 123,125 and 127) two or more this kind assemblies with the electric coupling upside basically.Hereinafter the example of graphic extension promptly is used for this purpose.
As mentioned above, when high speed signal passed sub-assembly 121, each circuitized substrate 123,125 and 127 among Fig. 9 can transmit this a little high speed signals.In Fig. 9, purpose for explanation, describe four signal A-D and how in sub-assembly 121, to send back the example of another assembly 140, no matter second assembly 140 is to install near first assembly or with bigger distance on the MULTILAYER SUBSTRATE sub-assembly from an assembly 140 as these signals.Now explain and how to realize the example that this kind couples.Shows signal A is conveyed through blind via holes 135 downwards and is sent to another respective through hole (not shown) along a signal plane from the assembly 140 on Fig. 9 left side among the figure, sends back another assembly 140 then.As institute was specifically seen, signal A had utilized the through hole " short-term " of electroplating the maximum length of blind via hole and not having to cause signal attenuation.Similarly, signal D is sent to first signals layer the substrate 123 downwards from the right assembly 140, be sent to corresponding other conductors then, wherein may comprise another blind electroplating ventilating hole (not shown), upwards be back to another assembly or even be back to another contact on the same assembly 140 at this through hole signal.
When using the signal that in sub-assembly thickness, transmits basically, the best illustrated that on behalf of the through hole short-term, signal B and C perhaps eliminate basically.Shows signal B is conveyed through the almost whole length of electroplating ventilating hole 131 the whole thickness of substrate 123 and the intermediate substrate 125 downwards from the left side conductor of assembly 140 among the figure.Then, signal B is sent to the observer left side along substrate 125 than the low signal plane, and is upward through the topmost signals layer that adjacent electroplating ventilating hole 134 arrives substrate 125.In this case, signal B passes internal path through hole 133 then and is sent to secondary signal layer in the substrate 125 downwards.During this trip, signal B is conveyed through the maximum length of each electroplating ventilating hole basically to reduce short-term.Can see: signal B shown in Figure 9 is conveyed through a smaller length of the only remaining electroplating ventilating hole of each through hole wherein.Another is chosen as, and what signal B can be in the substrate 125 transmits and be sent to adjacent internal path through hole 133 than the low signal plane, and the low surface from substrate 125 upwards is sent to the secondary signal plane at internal path through hole 133 places then.So also eliminated the short-term interference basically, because only utilized the sub-fraction of whole electroplating ventilating hole 131.Therefore, short-term herein reduces to reduce greatly than the short-term in the alternative route of signal B mentioned above.
Shows signal C is conveyed through the whole thickness of sub-assembly 121 basically and is sent to the lowest signal layer that is formed at the substrate 127 from electroplating ventilating hole 131 (forming a continuous through hole) among the figure.Then, shows signal C is sent to the internal path 133 on the right among Fig. 9 among the figure, upwards is sent to the secondary signal layer in the substrate 127 at internal path 133 places.Therefore, in fact the transmission of signal C does not have the short-term loss, because the shared electroplating ventilating hole in the substrate of alignment only is left the short-term length of a minimum.Importantly, it is longer unlike a circuit (trace) width of the holding wire that is used for carrying signal equally not to be used for the remaining short-term of through hole that signal C transmits 131.Remaining signal path in the sub-assembly 121 also is like this.
Therefore, can see: each circuitized substrate 123,125 and 127 that forms sub-assembly 121 parts provides the high speed signal that in fact the short-term loss does not take place by wherein to transmit.This kind unique ability realizes by following manner: for the signal that is conveyed through described substrate provides new and unique routing path, so that these signals utilize signal to be conveyed through whole length of each through hole wherein basically, and importantly do not transmit along the through hole length longer than needed length.In some path in these paths, do not utilize the only sub-fraction (wide) of each through hole, therefore eliminated loss of signal basically no longer than a circuit.In most of paths, use whole length.Use above-mentioned various through hole, conventional dielectric and conductive layer and be used for the alternative means that various circuitized substrate are bonded together is realized that the uniqueness of institute's teaching herein transmits.In the example of Fig. 9, when using conductive paste to couple corresponding through hole and therefore coupling adjacent substrate, also still can reach these speed.Should be appreciated that: it only is representational and non-limiting the present invention that the signal of graphic extension herein transmits.Use teaching herein can easily obtain other combinations of several through holes and signal plane.
Scope of the present invention also contains to provide and wherein has the through hole that conductive paste transmits with the signal that guarantee to strengthen.This kind conductive paste that is similar to conductive paste 137 can be positioned in the corresponding through hole and to use lamination step referred to above will comprise the substrate of these through holes then bonded to one another.If form the sub-assembly 121 that the electroplating ventilating hole that passes the whole length of described sub-assembly wherein also is set subsequently, also can be defined purpose subsequently herein and in the electroplating ventilating hole that this kind forms subsequently, place conductive paste.Also should be appreciated that, of the present invention more wide aspect in, a circuitized substrate sub-assembly can only comprise two independent substrates (promptly 123 and 125).
Two of Figure 10 graphic extensions can be used the example of the electrical assemblies of teaching formation of the present invention.A sub-assembly (multiple layer high speed circuitized substrate sub-assembly 121) comprises a pcb 122 and a chip carrier 124, and described chip carrier 124 (having semiconductor chip 140 ' on it) is represented the second high speed circuit substrate assembly.Carrier 12 4 comprise the substrate assembly 121 ' of himself and use at least one semiconductor chip 140 that traditional solder ball 143 of the type that defines herein is installed on it '.Similarly, solder ball 143 is used for circuitized substrate sub-assembly 121 ' be coupled to pcb 122.Therefore, use teaching of the present invention can provide or only be mounted in the high speed signal of the assembly (not shown) on the pcb 122 from chip 140 ' to pcb 122 and other electrical assemblies.As mentioned above, use circuitized substrate sub-assembly 121 ' the preferred group component also be known as chip carrier and generally include the add ons of using conducting resinl 151 heat to be coupled to chip, for example radiator 150.Can provide a pair of distance piece 153 to guarantee the location of radiator, these distance pieces 153 also use suitable adhesive glue 155 to be bonded to the upper surface of carrier substrates.The chip carrier that shows among Figure 10 only is used for the graphic extension purpose, because other forms of chip carrier is known and within the scope of the invention by people in affiliated technical field.Known this kind chip carrier of a kind of crowd is sold with the title of HyperBGA (HyperBGA is the registered trade mark of EndicottInterconnect Technologies company) chip carrier by assignee of the present invention.Believing does not need to be further elaborated again.
Figure 11 graphic extension is an information processing system 201 according to an embodiment of the invention.As hereinbefore defined, information processing system 201 can be other kinds of information treatment systems in a personal computer, mainframe computer, computer server or the affiliated technical field.Usually, this kind system utilizes a cabinet 203 that wherein is positioned with the systemic-function assembly.As defined herein, this kind functional unit can be that an electrical assemblies that comprises a multilayered circuitized substrate assembly or (if possible) only are one and are positioned with one or more electric assemblies on it and as its a part of circuitized substrate.Show among the embodiment of Figure 11 to comprise the circuitized substrate sub-assembly 121 shown in Figure 10 that chip carrier shown in Figure 10 124 is installed on it, this whole sub-assembly all illustrates with numeral 160 in Figure 10 and Figure 11.As mentioned above, also preferable several add-on electrical assemblies that comprise mounted thereto of the multilayered circuitized substrate assembly 121 among Figure 11.Believing does not need to be further elaborated again.
Therefore this paper shows and has described circuitized substrate and multilayered circuitized substrate assembly, and the method for making described substrate reaches the product that is fit to use described substrate, it is except being coupled to various assemblies the inner conductor of substrate and/or being positioned at the assembly (if desired) on its opposite side, also provides the high speed of various assemblies (for example chip carrier and/or semiconductor chip and be positioned at same lip-deep other electric assemblies) to connect.In its simple form, circuitized substrate taught herein comprises a substrate that has a plurality of dielectric layers and conductive layer and plurality of through holes.In its simple form, multilayered circuitized substrate assembly comprises that at least two bond together forming the circuitized substrate of final sandwich construction, and this final sandwich construction itself will comprise and a plurality ofly be considered to couple corresponding conductive layer and guarantee that desired signal transmits necessary through hole at a high speed.In its simple form, information processing system taught herein will comprise at least one circuitized substrate and an assembly, but should be appreciated that: in many cases, described system will utilize substrate assembly to couple ability so that stronger high speed to be provided.The invention that this paper defined can couple the assembly on the single side of substrate, also can couple assembly on the opposite side.The method that is used to produce this structure taught herein has cost effectiveness and in substrate (especially pcb) is made technical staff's the limit of power in field.Therefore, the present invention can produce the low relatively cost of ultimate consumer.
Though this paper has shown and has set forth the current preferred embodiment of the present invention that the person skilled in art can obviously find out, can make various changes and modification to the present invention under the prerequisite that does not deviate from by the scope of the invention that claim defined of enclosing.

Claims (16)

1, a kind of high speed circuit substrate, it comprises:
The plural conductive layer;
A plurality of dielectric layers, its positioned alternate described conductive layer selected between and described conductive layer is electrically insulated from each other;
Plurality of through holes, its be positioned in the described substrate at interval and extend through described dielectric layer and described conductive layer in selected layer, transmit between described interconnect conductive layers to allow the signal of telecommunication with another layer that the selected layer in the described conductive layer is electrically interconnected in the described conductive layer, the described signal of telecommunication passes the maximum length of described through hole so that eliminate the loss of signal that is caused by the through hole short-term basically.
2, high speed circuit substrate as claimed in claim 1, the wherein said signal of telecommunication can pass described substrate to the speed of about 10.0 gigabit/sec with one about 3.0.
3, high speed circuit substrate as claimed in claim 1, wherein the number of conductive layer from about three to about 13, the number of dielectric layer from about two numbers to about 12 and through hole from about 20,000 to about 50,000.
4, high speed circuit substrate as claimed in claim 1, the described through hole in the wherein said substrate comprises a combination of internal path, blind path and electroplating ventilating hole.
5, a kind of method of making one high speed circuit substrate, described method comprises:
The plural conductive layer is provided;
Provide a plurality of dielectric layers and with the selected layer positioned alternate in the described dielectric layer in described conductive layer selected between so that described conductive layer be electrically insulated from each other;
In described substrate with an aligned formation plurality of through holes at interval, so that described plurality of through holes extends through selected layer another layer so that selected layer in the described conductive layer is electrically interconnected in the described conductive layer in described dielectric layer and the described conductive layer, thereby allow the signal of telecommunication to transmit between the conductive layer of interconnection described, the described signal of telecommunication passes the maximum length of described through hole to eliminate the loss of signal that is caused by the through hole short-term basically.
6, method as claimed in claim 5, it further comprises described plural conductive layer and described a plurality of dielectric layer is bonded together.
7, a kind of electrical assemblies, it comprises:
One high speed circuit substrate, it comprises: the plural conductive layer; A plurality of dielectric layers, its positioned alternate in described conductive layer selected between and described conductive layer is electrically insulated from each other; Plurality of through holes, its be positioned in the described substrate at interval and extend through described dielectric layer and described conductive layer in selected layer the selected layer in the described conductive layer is electrically interconnected to another layer in the described conductive layer, thereby allow the signal of telecommunication to transmit between the conductive layer of interconnection described, the described signal of telecommunication passes the maximum length of described through hole to eliminate the loss of signal that is caused by the through hole short-term basically; And
At least one is positioned on the described circuitized substrate and is electrically coupled to the electric assembly of described circuitized substrate.
8, electrical assemblies as claimed in claim 7, the wherein said signal of telecommunication can pass described substrate to the speed of about 10.0 gigabit/sec with one about 3.0.
9, electrical assemblies as claimed in claim 7, the number of wherein said conductive layer be from about three to about 13, and the number of described dielectric layer is from about two numbers from about 20,000 to about 50,000 to about 12 and described through hole.
10, electrical assemblies as claimed in claim 7, the described through hole in the wherein said substrate comprises a combination of internal path, blind path and electroplating ventilating hole.
11, electrical assemblies as claimed in claim 7, wherein said at least one electric assembly comprises the semiconductor chip.
12, electrical assemblies as claimed in claim 7, wherein said at least one electric assembly comprises a chip carrier.
13, a kind of information processing system, it comprises:
One cabinet;
One high speed circuit substrate, it is positioned in the described cabinet and comprises: the plural conductive layer; A plurality of dielectric layers, its positioned alternate in described conductive layer selected between and described conductive layer is electrically insulated from each other; Plurality of through holes, its be positioned in the described substrate at interval and extend through described dielectric layer and described conductive layer in selected layer, the selected layer in the described conductive layer is electrically interconnected to another layer in the described conductive layer, thereby allow the signal of telecommunication to transmit between the conductive layer of interconnection described, the described signal of telecommunication passes the maximum length of described through hole to eliminate the loss of signal that is caused by the through hole short-term basically; And
At least one is positioned on the described circuitized substrate and is electrically coupled to the electric assembly of described circuitized substrate.
14, information processing system as claimed in claim 13, wherein said information processing system comprises a personal computer.
15, information processing system as claimed in claim 13, wherein said information processing system comprises a mainframe computer.
16, information processing system as claimed in claim 13, wherein said information processing system comprises a computer server.
CN 200510105837 2004-09-30 2005-09-23 High speed circuitized substrate with reduced thru-hole stub, method for fabrication and information handling system utilizing same Expired - Fee Related CN1758830B (en)

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