CN1758312A - Light emitting display and data driver there of - Google Patents

Light emitting display and data driver there of Download PDF

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Publication number
CN1758312A
CN1758312A CNA2005101087107A CN200510108710A CN1758312A CN 1758312 A CN1758312 A CN 1758312A CN A2005101087107 A CNA2005101087107 A CN A2005101087107A CN 200510108710 A CN200510108710 A CN 200510108710A CN 1758312 A CN1758312 A CN 1758312A
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data
transistor
voltage
converter
current
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CNA2005101087107A
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CN100414591C (en
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权五敬
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Samsung Display Co Ltd
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Samsung SDI Co Ltd
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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3275—Details of drivers for data electrodes
    • G09G3/3283—Details of drivers for data electrodes in which the data driver supplies a variable data current for setting the current through, or the voltage across, the light-emitting elements
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
    • G09G3/3233—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix with pixel circuitry controlling the current through the light-emitting element
    • G09G3/3241—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix with pixel circuitry controlling the current through the light-emitting element the current through the light-emitting element being set using a data current provided by the data driver, e.g. by using a two-transistor current mirror
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0243—Details of the generation of driving signals
    • G09G2310/0248—Precharge or discharge of column electrodes before or after applying exact column voltages
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0294—Details of sampling or holding circuits arranged for use in a driver for data electrodes
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/02—Improving the quality of display appearance
    • G09G2320/0233—Improving the luminance or brightness uniformity across the screen

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Control Of Indicators Other Than Cathode Ray Tubes (AREA)
  • Control Of El Displays (AREA)

Abstract

An organic light emitting diode display being driven according to a current programming method. A digital/analog converter of a data driver sequentially converts data signals representing gray scales to data currents and sequentially transmits the data currents to an output stage. The output stage sequentially samples the data currents and concurrently transmits the data currents to data lines. A precharge voltage is applied to a wire between the digital/analog converter and the output stage before a respective one of the data currents is transmitted to the output stage. As such, the data currents may be properly transmitted to the output stage.

Description

Active display and data driver thereof
Technical field
The present invention relates to an active display, particularly relate to a data driver that is used for the output data electric current in this active display.
Background technology
Active display is a display device, and it uses a plurality of light-emitting components to come displayed image.Each light-emitting component is according to applying galvanoluminescence.Especially, an organic light emitting diode display uses an organic light-emitting units to have diode characteristics as this light-emitting component and this organic light-emitting units, and is referred to as Organic Light Emitting Diode (OLED).This organic light-emitting units comprises an anode, an organic film and a negative electrode.
According to addressing method, the method that drives organic light-emitting units is divided into passive matrix method and active matrix method.In the passive matrix method, with organic light-emitting units be formed in anode line and and the cathode line of this anode line square crossing between and by selecting each bar line to drive.In active matrix method, a thin film transistor (TFT) is connected to each pixel electrode (as an anode line), and drive this organic light-emitting units with voltage that the electric capacity that grid is connected of thin film transistor (TFT) is kept according to one.In addition, according to being applied to the signal format that this capacitor is used to keep this voltage, active matrix method can be divided into voltage-programming method and current programmed method.
Because the skew on thin film transistor (TFT) cut-in voltage and/or the electron drift, this skew is to cause by manufacturing process is inconsistent, is difficult to obtain high grade grey level according to an image element circuit of voltage-programming method.On the other hand, according to current programmed method, be assumed to this pixel one current source of electric current being provided is constant (i.e. all data lines) on whole front panel, even the driving transistors in each pixel has inconsistent voltage-to-current feature, also can obtain consistent indicating characteristic.
; in the active display that uses current programmed method; one data driver must be provided, and its data-signal with an expression gray level converts an analog current (hereinafter being referred to as " data current ") to, to be applied on the data line that is connected with this image element circuit.
This data driver needs a D/A, is used for converting digital data signal to simulated data electric current and an output stage, is used to cushion and export the data current after the conversion.Usually, in a horizontal cycle, data current is transferred to data line before, output stage must in this horizontal cycle, cushion with delegation in the corresponding data current of image element circuit., along with the resolution of active display uprises, horizontal cycle shortens.Therefore, when the amplitude of data current hour, output stage can not the buffered data electric current in horizontal cycle.Its result, data current may be transferred on the data line improperly.
Summary of the invention
One embodiment of the invention provide a data driver, be used for converting the data-signal of expression gray level to data current, and this data current is outputed on the data line.The embodiment of the invention also provides a data driver, is used for data current correctly is transferred to an output stage.
According to one embodiment of the invention, before data current is transferred to output stage, a lead precharge of output stage will be connected to.
One embodiment of the invention provide a data driver, are used for the data-signal that order receives a plurality of expression gray levels, a plurality of data currents are applied on many data lines that constitute on the viewing area of active display.Data driver comprises at least one converter, at least one output stage, at least one lead and precharge parts.Converter converts data-signal to data current that data current and output stage are received from the converter transmission in proper order, and with the received data current delivery to data line.This lead be connected between converter and the output stage and the precharge parts before the data current with correspondence is transferred to output stage, a pre-charge voltage is applied to this lead.
According to exemplary embodiment of the present invention, converter comprises a first transistor, the drain electrode that its data current with this correspondence flows into.The precharge parts comprise a transistor seconds, and it is connected to this first transistor as a current mirror, and will corresponding to this transistor seconds drain voltage, export as pre-charge voltage by the determined voltage of a data current of this correspondence.Here, the precharge parts also can comprise a unity gain amplifier, and it is connected between transistor seconds drain electrode and lead first end.
According to another exemplary embodiment of the present invention, pre-determine pre-charge voltage, and irrelevant with data current.
In accordance with a further exemplary embodiment of the present invention, converter comprises a first transistor, and first end and source electrode that its drain electrode is connected to lead are connected to one first power supply, so that one first voltage to be provided.Output stage comprises a transistor seconds, and its drain electrode is connected to lead second end and source electrode is connected to a second source, so that one second voltage to be provided.The precharge parts are exported a tertiary voltage between second voltage and first voltage as pre-charge voltage.
Another exemplary embodiment according to the present invention, the precharge parts will be defined as pre-charge voltage corresponding to a voltage of a corresponding data-signal.
The another exemplary embodiment according to the present invention, the precharge parts comprise a transformer, are used for from least one data bit generation pre-charge voltage of a plurality of data bit of a corresponding data-signal.
One embodiment of the invention provides an active display, and it comprises a viewing area, one scan driver and a data driver.The viewing area comprises many data lines, many first sweep traces, many second sweep traces and a plurality of pixel region.First and second sweep traces and data line vertical distribution and each pixel region are by a corresponding data line and the definition of corresponding one first sweep trace and at least one light-emitting component is arranged.Scanner driver is transferred to many first sweep traces with a plurality of selection signals selectively, and a plurality of emissioning controling signals is transferred to many second sweep traces selectively.Data driver comprises a converter, be used for order and receive a plurality of data-signals and convert a plurality of data-signals to a plurality of data currents and an output stage in proper order, be used for receiving data current in proper order and data current being transferred to many data lines from this converter.Before a corresponding data current is transferred to output stage from converter, a pre-charge voltage is applied on the lead that is connected between converter and the output stage.
Description of drawings
Fig. 1 represents an active display diagrammatic sketch of one exemplary embodiment according to the present invention;
Fig. 2 represents a data driver structural drawing of one first exemplary embodiment according to the present invention;
Fig. 3 represents a multiplexing processor structural drawing of data driver shown in Figure 2;
Fig. 4 represents the structural drawing of a digital-to-analogue (D/A) converter example;
Fig. 5 represents an output terminal of D/A converter in the data driver of first exemplary embodiment according to the present invention and an input end of an output stage;
Fig. 6,8 and 10 represents according to the present invention the input end of output terminal, precharge parts and the output stage of D/A converter in the data driver of second, third and the 4th exemplary embodiment respectively;
The switching sequence figure of precharge parts in Fig. 7, the 9 and 11 difference presentation graphs 6,8 and 10;
Figure 12 represents a voltage D/A converter example shown in Figure 10;
Figure 13 represents a data driver structural drawing of one the 5th exemplary embodiment according to the present invention.
Embodiment
In being discussed in more detail below, only by graphic representation and described some exemplary embodiment of the present invention.Recognize as those skilled in the art, can multitude of different ways revise the embodiment that describes, and can not depart from essence of the present invention or scope.Therefore, accompanying drawing and description should be used as is illustrative in essence, rather than restrictive.Same tag is represented same parts in the instructions.
Fig. 1 represents an active display diagrammatic sketch of one exemplary embodiment according to the present invention.
As shown in Figure 1, this active display comprises a viewing area 100, and the user regards it as a screen, one scan driver 200 and a data driver 300.
Viewing area 100 comprises many data line D 1To D m, many select sweep trace S 1To S n, many transmit scan line E 1To E n, and a plurality of sub-pixel 110.Data line D 1To D mExtend along column direction, and the data current of presentation image is transferred to corresponding sub-pixel 110.Select sweep trace S 1To S nFollow direction and extend, and transmission selection signal, be used for selecting and selecting sweep trace S 1To S nThe corresponding data line D that intersects 1To D mThereby, data current is applied to corresponding data and sweep trace D 1To D mAnd S 1To S nSub-pixel 110 on.Transmit scan line E 1To E nFollow direction and extend, and the transmission emissioning controling signal, it is luminous to be used to control sub-pixel 110.
One pixel region is by data line D 1To D mIn one and select sweep trace S 1To S nIn one define and on this pixel region, constitute a sub-pixel 110.For example, be connected to the sub-pixel 110 that the i bar is selected sweep trace and j bar data line, according to from selecting sweep trace S iThe selection signal, to from data line D jData current programming, and according to from transmit scan line E iEmissioning controling signal, the expression corresponding to a gray level that is programmed data current.Equally, suppose to constitute a pixel by the sub-pixel of emission red (R) coloured light, the sub-pixel of emission green (G) coloured light and the sub-pixel of blue (B) coloured light of emission.
Data driver 300 receives the data-signal of expression gray level from a timing controller (not shown) order, and the received data conversion of signals is become data current, and the data and the sweep trace D that are applied to and select signal to be applied in institute's translation data electric current 1To D mAnd S 1To S nSub-pixel 110 corresponding data line D 1To D mUse.Scanner driver 200 will be selected signal sequence to be applied to and select sweep trace S 1To S nOn and the emissioning controling signal order is applied to transmit scan line E 1To E mOn.
In one embodiment, scanner driver 200 and/or data driver 300 are constituted on integrated circuit (IC) and the substrate with this IC formation mounted thereto viewing area 100.Another way is, in one embodiment, this IC is installed on the soft connecting elements, such as thin-film package (TCP), flexible printer circuit (FPC) and depend on the soft connecting elements of connection substrate.On the other hand, the driving circuit that constitutes on the available substrate replaces scanner driver 200 and/or data driver 300, and it is by making with sweep trace, data line and transistor identical layer, to be used to drive this pixel.In addition, scanner driver 200 and/or data driver 300 can be installed in by circuit and be connected thereto on the printed circuit board (PCB) of the substrate that constitutes viewing area 100.
With reference to data driver 300 among Fig. 2 and 3 more detailed description Fig. 1.
Fig. 2 represents data driver 300 structural drawing of one first exemplary embodiment according to the present invention and the structural drawing of the multiplexing processor 330 that Fig. 3 represents data driver 300 shown in Figure 2.For exemplary purposes, Fig. 2 and Fig. 3 represent 300 data line D corresponding to 100 pixels 1To D 300, promptly 100 data lines corresponding to R sub-pixel, 100 data lines corresponding to G sub-pixel and 100 data lines corresponding to the B sub-pixel.That is, exemplary description contains the data driver 300 of 300 paths, and the present invention is not restricted to this.Equally, suppose and the data-signal corresponding to 100 pixels of delegation is input in the data driver 300 in proper order and will corresponding to R, the G of 3 sub-pixels of this pixel and the B data-signal is parallel be input in the data driver 300.
As shown in Figure 2, data driver 300 comprises a shift register 310, a latch 320, a multiplexing processor 330, a digital-to-analogue (claiming D/A afterwards) converting member 340, a control-signals generator 350 and an output stage 360.In Fig. 2, latch 320, multiplexing processor 330, D/A converting member 340 and the pairing R of output stage 360 parallel processings, one pixel, G and B data-signal or R, G and B data current.
Shift register 310 is shifted a sampled signal in proper order, so that a plurality of sampled signal SRH0 to SRH99 are transferred to latch 320.Latch 320 is sampled to R, G and B data-signal DR0 to DR99, DG0 to DG99 and DB0 to DB99 according to sampled signal SRH0 to SRH99 order and is kept, and comprises that a sample latch 321 and keeps latch 322.
More specifically, shift register 310 produces sampled signal SRH0 according to enabling signal IE, and with clock CLKH synchronizing sequence displacement sampled signal SRH0, export a plurality of sampled signal SRH0 to SRH99 with order.Like this, produce with delegation in 100 100 sampled signal SRH0 to SRH99 that pixel is corresponding.
Sample latch 321 is respectively according to sampled signal SRH0 to SRH99, and order is sampled to R, G and B data-signal DR0 to DR99, DG0 to DG99 and DB0 to DB99.That is, sample latch 321 is sampled to R, the G of (i+1) individual pixel correspondence and B data-signal DRi, DGi and DBi according to sampled signal SRHi (wherein ' i ' is the integer between 0 to 99).In one embodiment, if R, G and B data-signal DRi, DGi and DBi are respectively 10 bit data, sample latch 321 is each pixel sampling 30 bit data.The data-signal that keeps latch 322 to keep by sample latch 321 sequential samplings, up to the pairing data-signal of this row is sampled, and keep enabling data-signal DR0 to DR99, DG0 to DG99 and the DB0 to DB99 that signal DH output is sampled according to one.
As shown in Figure 3, multiplexing processor 330 comprises a shift register 331 and a multiplexer 332.Shift register 331 is enabled signal DAS by receiving a clock CLKL and, and order is exported multiplex signal MSW0 to MSW99 and shift signal SRL0 to SRL99.At this moment, the frequency that is applied to the clock CLKL of shift register 331 can be lower than the frequency of the clock CLKH that is applied to shift register 310, and enables signal DAS and keeps the signal DH that enables of latch 322 that identical sequential is arranged with being applied to.Export multiplex signal MSW0 to MSW99 and shift signal SRL0 to SRL99 from timing controller (not shown) synchronously with clock CLKL.In addition, multiplex signal MSW0 to MSW99 is transferred to multiplexer 332 in the multiplexing processor 330, and shift signal SRL0 to SRL99 is transferred to control-signals generator 350.
Multiplexer 332 in the multiplexing processor 330, according to each multiplex signal MSW0 to MSW99, each R, the G of self-sustaining latch 322 output and B data-signal DR0 to DR99, DG0 to DG99 and DB0 to DB99 are done multiplexed, and order is transferred to D/A converting member 340 with R, G and B data-signal DR0 to DR99, DG0 to DG99 and DB0 to DB99.That is, multiplexer 332 is transferred to D/A converting member 340 according to multiplex signal MSWi with R, G and B data-signal DRi, DGi and DBi.
D/A converting member 340 order converts R, G and B data-signal DR0 to DR99, DG0 to DG99 and DB0 to DB99 to data current R0 to R99, G0 to G99 and B0 to B99, and order outputs to output stage 360 with the translation data electric current R0 to R99 of institute, G0 to G99 and B0 to B99.Here, D/A converting member 340 comprise R, G and B D/A converter 341,342 and 343 and R, G and BD/A converter 341,342 and 343 convert R, G and B data-signal to R, G and B data current respectively.
Control-signals generator 350 receives shift signal SRL0 to SRL99 from multiplexing processor 330 orders, and produces sampled signal CHS0 to CHS99 so that they are outputed to output stage 360 in proper order.Produce sampled signal CHSi by shift signal SRLi, so that to be transferred to moment of output stage 360 synchronous with R, G that D/A converting member 340 is changed according to multiplex signal MSWi and B data current Ri, Gi and Bi.
Output stage 360 is sampled to R, G and B data current R0 to R99, G0 to G99 and B0 to B99 according to each sampled signal CHS0 to CHS99 order.That is, output stage 360 according to sampled signal CSHi to sampling from R, the G of D/A converting member 340 input and B data current Ri, Gi and Bi.Output stage 360 couples of pairing R of one-row pixels, G and B data current R0 to R99, G0 to G99 and B0 to B99 sample, and institute sampling R, G and B data current R0 to R99, G0 to G99 and B0 to B99 are outputed to corresponding data line D simultaneously 1To D 300On.
Below described a process, wherein the pairing R of one-row pixels, G and B data-signal have been input to data driver 300 converting data current to, and data current are outputed on the data line of viewing area 100.Data driver 300 couples of pairing R of all row pixels, G and B data-signal repeat this process, thereby convert the pairing data-signal of a frame to data current, and institute's translation data electric current is outputed on the data line of viewing area 100.In addition, according to first exemplary embodiment, D/A converter is not according to data line D 1To D mConstitute, but constitute according to the color of R, G and B data.Therefore, can reduce the quantity of D/A converter.
Below, with reference to D/A converting member 340 examples of using in Fig. 4 data of description driver 300.Fig. 4 represents the example structure figure of D/A converter 341.Among Fig. 4, R D/A converter 341 and not shown and/or more detailed description and roughly the same G and B D/ A converter 342 and 343 of R D/A converter 341 structures in the D/A converting member 340 are shown.
With reference to Fig. 4, D/A converter 341 comprises a transistor T B, and it is connected to a current source I B, 10 mirror image transistor T 0 to T9, switch SW 0 to SW9 and output terminal 341a (shown in Figure 5).Transistor T 0 to T9 is respectively 2 of transistor T B size as the size that current mirror is connected respectively to transistor T B and mirror image transistor T 0 to T9 0To 2 9Doubly.Here, transistor size is transistor channel width W and the ratio W/L of channel length L.More specifically, transistor T B connects as diode and source electrode is connected to a supply voltage VDD1, and drain electrode is connected to current source I BTransistor T j source electrode is connected to supply voltage VDD1, and grid is connected to transistor T B grid (here ' j ' is 0 to 9 integer).One switch SW j is connected between the drain electrode and output terminal 341a (Fig. 5) of transistor T j of D/A converter 341.
Afterwards, with electric current 2 0l BTo 2 9l B, it is respectively the electric current I that flows through transistor T B drain electrode B2 0To 2 9Doubly, respectively by 0 to the T9 drain electrode output of mirror image transistor T.According to the one digit number certificate among 10 R data-signal DRi of sequential delivery from the multiplexer 332 of multiplexing processor 330, each switch SW 0 to SW9 is connected.For example, when R data-signal DRi is " 0101000101 ",, thereby be transferred to D/A converter 341 output terminal 341a (Fig. 5) data current l with switch SW 0, SW2, SW6 and the SW8 connection of bit data ' 1 ' correspondence InBe (2 0+ 2 2+ 2 6+ 2 8) l B
As mentioned above, D/A converter converts R, G and B data-signal to R, G and B data current respectively, and respectively R, G and B data current is transferred to output stage 360 (shown in Figure 5) by lead 370.
Fig. 5 represents the output terminal 341a of D/A converter 341 in the data driver 300 of first exemplary embodiment according to the present invention and an input end 361 of output stage 360.Among Fig. 5, the input end 361 that the output terminal 341a of RD/A converter 341 only is shown and is connected to the output stage 360 of RD/A converter 341, roughly the 341a with RD/A converter 341 is identical with 343 output end structure with G and BD/A converter 342.In addition, output stage 360 has the input end that is connected to G and BD/ A converter 342 and 343 and has and be connected to 361 roughly the same structures of RD/A converter 341.
As shown in Figure 5, the output terminal 341a of D/A converter 341 comprises that the input end 361 of a current mirror M1 and M2 and output stage 360 also comprises a current mirror M3 and a M4.Among Fig. 5, the transistor M1 of D/A converter 341 current mirrors and M2 describe as nmos pass transistor and the transistor M3 and the M4 that will constitute output stage 360 current mirrors describes as the PMOS transistor with constituting.
In output terminal 341a, will be from the data current l of D/A converter 341 InBe transferred to the drain electrode of the transistor M1 that connects as diode and the source electrode of transistor M1 and be connected to a ground voltage.The source electrode of transistor M2 is connected to ground voltage, and the drain electrode that grid is connected to the grid of transistor M1 and transistor M2 is connected to the input end 361 of output stage 360 by lead 370.
In input end 361, the drain electrode of the transistor M3 that connects as diode is connected to a supply voltage VDD2 by output terminal 341a and the transistor M3 source electrode that lead 370 is connected to D/A converter 341.Transistor M4 source electrode is connected to the grid that supply voltage VDD2 and grid are connected to transistor M3.The electric current of the drain electrode of inflow transistor M4 is the input current of output stage 360.
2 transistor M1 and M2 have same size and 2 transistor M3 and M4 and have same size.Therefore, with the data current l of the drain electrode of inflow transistor M1 InAn onesize electric current is by the drain electrode of lead 370 from the drain electrode inflow transistor M2 of transistor M3.Therefore, with the data current l of D/A converter 341 InAn onesize electric current flows into the drain electrode of the transistor M4 of output stage 360.
In the same way, when when D/A converting member 340 order is exported the pairing R of one-row pixels, G and B data current, the output stage order is sampled to these R, G and B data current.Here, the pairing R of one-row pixels, G and B data current being transferred to output stage 360 required times roughly equates with horizontal cycle.That is, the pairing R of a pixel, G and B data current being transferred to 360 cycles of output stage (hereinafter referred to as " data transfer cycle ") is 1/100 of horizontal cycle., when parasitic component is big on the little and lead 370 of data current amplitude, in data transfer cycle, data current correctly can be transferred to output stage 360, thereby output stage 360 can't be sampled to required electric current.
Fig. 6 represents the output terminal 341a of D/A converter 341 in the data driver 300 of second exemplary embodiment according to the present invention and the input end 361 of output stage 360.
As shown in Figure 6, contrast first exemplary embodiment, data driver according to second exemplary embodiment also comprises precharge parts 380a, and it is connected between the input end (as input end 361) of the output terminal of R, G and BD/A converter 341,342 and 343 and output stage 360.Fig. 6 only represents to be connected to the precharge parts 380a of input end 361 of the output terminal 341a of RD/A converter 341 and output stage 360 and the precharge parts that its structure and precharge parts 380a is roughly the same are connected respectively to G and BD/ A converter 342 and 343.
Precharge parts 380a comprises transistor M5 and M6, switch SW 11 and SW12 and a unity gain amplifier 381.Among Fig. 6, transistor M5 is described as nmos pass transistor and transistor M6 is described as the PMOS transistor.
Grid and source electrode that the grid of transistor M5 is connected to transistor M1 are connected to ground voltage, and constitute a current mirror with transistor M1.Transistor M6 connects as diode and drains and is connected to the drain electrode of transistor M5, and source electrode is connected to supply voltage VDD2.Transistor M5 has identical with M3 with transistor M2 respectively size and characteristic with M6.The drain electrode of transistor M5 and M6 is connected to an input end of unity gain amplifier 381, and switch SW 11 is connected between one first end of output terminal of unity gain amplifier 381 and lead 370.Switch SW 12 is connected between one second end of the input end 361 of output stage 360 and lead 370.Here, the output voltage with unity gain amplifier 381 is applied on the lead 370 as a pre-charge voltage.
The operation of precharge parts 380a then, is also described with reference to Fig. 7.The switching sequence figure of Fig. 7 presentation graphs 6 precharge parts 380a.Among Fig. 7, show that pairing data transfer cycle of a pixel and high level and low level represent on-state and the off-state of each switch SW 11 and SW12 respectively.
With reference to Fig. 7, data transfer cycle comprises a precharge cycle Tp and a mirror image period T m.
In precharge cycle Tp, switch SW 11 is connected and switch SW 12 disconnects.Afterwards, with the data current l of the drain electrode that is transferred to transistor M1 InThe drain electrode of one electric current inflow transistor M5 of identical size and determine the drain voltage of transistor M5 by the drain current of transistor M5.That is, the opening resistor (on-resistance) by transistor M5 and M6 is with supply voltage VDD2 dividing potential drop, to become the drain voltage of transistor M5.Afterwards, unity gain amplifier 381 will be applied to the drain electrode of first end and the transistor M2 of lead 370 with the pre-charge voltage of the drain voltage same size of transistor M5.Correspondingly, because switch SW 12 disconnects, the drain voltage of voltage on the lead 370 and transistor M2 is substantially equal to this transistor drain voltage.
In mirror image period T m, switch SW 11 disconnects and switch SW 12 is connected.Owing to the drain voltage of voltage on the lead 370 being arranged to be substantially equal to transistor M2 at precharge cycle Tp, so when switch SW 12 was connected, the drain voltage of transistor M3 was substantially equal to the drain voltage of transistor M2.In this embodiment since the size of transistor M2 and M3 size and the characteristic with transistor M5 and M6 is identical respectively with characteristic, the drain voltage of transistor M2 and M3 equals the drain voltage of transistor M5 and M6.Correspondingly, when mirror image period T m began, the electric current of the drain electrode of inflow transistor M2 and M3 was substantially equal to the data current l of the drain electrode of inflow transistor M5 and M6 InThat is, when mirror image period T m begins, can be with data current l InReach the drain electrode of transistor M3 from the drain electrode transmission of transistor M1.
As mentioned above, according to second exemplary embodiment, even data transfer cycle is short, also can be with data current l InBe transferred to the input end 361 of output stage 360 from the output terminal 341a of D/A converter 341.
Fig. 8 represents output terminal 341a, a precharge parts 380b and the input end 361 of output stage 360 and the switching sequence figure of Fig. 9 presentation graphs 8 precharge parts 380b of D/A converter 341 in the data driver of the 3rd exemplary embodiment according to the present invention.Among Fig. 9, high level and low level are represented on-state and the off-state of each switch SW 13, SW14 and SW15 respectively.
As shown in Figure 8, except that precharge parts 380b, roughly the same structure is arranged according to the data driver and second exemplary embodiment of the 3rd exemplary embodiment.
Specifically, precharge parts 380b comprises resistance R 11 and R12 and switch SW 13, SW14 and SW15.With resistance R 11 with R12 is connected between supply voltage VDD2 and the ground voltage and resistance R 11 and R12 have roughly the same resistance value.Switch SW 13 is connected between the grid of the grid of transistor M1 and transistor M2, and switch SW 14 is connected between the drain electrode of second end of lead 370 and transistor M3.Switch SW 15 is connected between first end of the intersection point of resistance R 11 and R12 and lead 370.
With reference to Fig. 9, in a precharge cycle Tp ', switch SW 13 and SW14 disconnect and switch SW 15 is connected.Afterwards, by resistance R 11 and R12 with supply voltage VDD2 and ground voltage dividing potential drop, thereby half pairing voltage VDD2/2 of supply voltage VDD2 is applied to first end of lead 370 as pre-charge voltage.
Then, in a mirror image period T m ', switch SW 15 disconnects and switch SW 13 and SW14 connection.Afterwards, by the data current l that is between supply voltage VDD2 and the ground voltage InDetermine the drain voltage of transistor M2 and M3.Owing in precharge cycle Tp ', will be connected to the transistor M2 of lead 370 and the drain electrode of M3 is pre-charged to voltage VDD2/2, the drain voltage of transistor M2 and M3 is changed over and data current l rapidly therebetween, InCorrespondent voltage.Therefore, in an embodiment of the present invention, shortened data current l InBe transferred to the cycle of the drain electrode of transistor M3.
Although the resistance R 11 and the R12 that have described in the 3rd exemplary embodiment by same resistance value are pre-charged to voltage VDD2/2 with lead 370, resistance R 11 and R12 can have different resistance values, thereby lead 370 is pre-charged to another voltage.
Figure 10 represents output terminal 341a, a precharge parts 380c and the input end 361 of output stage 360 and the switching sequence figure that Figure 11 represents Figure 10 precharge parts 380c of D/A converter 341 in the data driver of the 4th exemplary embodiment according to the present invention.Among Figure 11, high level and low level are represented on-state and the off-state of each switch SW 16 and SW17 respectively.
As shown in figure 10, except that precharge parts 380c, roughly the same structure is arranged according to the data driver and second exemplary embodiment of the 4th exemplary embodiment.
Specifically, precharge parts 380c comprises a voltage D/A converter 382 and switch SW 16 and SW17.Voltage D/A converter 382 receives the R data-signal DRi that is transferred to D/A converter 341, and converts the reception R of institute data-signal DRi to a voltage.Switch SW 16 is connected between first end of output terminal of voltage D/A converter 382 and lead 370 and and is connected to second end of lead 370 and the input end 361 of output stage 360 switch SW 17.Can calculate as data current l InThe voltage of lead 370 when flowing into input end 361.That is, when the drain electrode of data current inflow transistor M2 and M3 the drain voltage of transistor M3 corresponding to the voltage of lead 370.Correspondingly, precharge parts 380c receives the data-signal DRi that is transferred to D/A converter 341, and converts data-signal DRi to a voltage, and it is equivalent to the voltage when the pairing data current of data-signal DRi flows into the input end 361 of output stage 360.In addition, precharge parts 380c is applied to institute's changing voltage first end of lead 370 as pre-charge voltage.
With reference to Figure 11, at precharge cycle Tp " in, switch SW 16 is connected and switch SW 17 disconnects.Afterwards, D/A converter 382 produces pre-charge voltage according to the data-signal DRi that is transferred to D/A converter 382, and by switch SW 16 pre-charge voltage is applied on the lead 370.That is, lead 370 is charged to pre-charge voltage.
Then, at mirror image period T m " in, switch SW 16 disconnects and switch SW 17 is connected." can be during beginning owing to lead 370 is charged to the pairing pre-charge voltage of data-signal DRi, at mirror image period T m with the drain electrode of the current delivery of the drain electrode of inflow transistor M1 to transistor M3.
As mentioned above, in the 4th exemplary embodiment, will work as the pairing data current l of data-signal DRi InThe drain voltage of transistor M3 during the drain electrode of inflow transistor M2 and M3 is as pre-charge voltage.
Usually, voltage D/A converter 382 uses the resistance of a plurality of series connection and a plurality of switches that are connected respectively to a plurality of resistance, to convert data-signal to pre-charge voltage.When data-signal DRi was 10 bit data, voltage D/A converter 382 needed a large amount of resistance and switch to handle 2 10Individual data-signal, thus the size of voltage D/A converter 382 increases.For reducing the size of voltage D/A converter 382, can determine pre-charge voltage by the high position of 10 bit data.
Figure 12 represents the example of voltage D/A converter 382 shown in Figure 10.Among Figure 12, expression voltage D/A converter 382 uses 3 high-order D of 10 bit data signals 0, D 1And D 2Determine pre-charge voltage.
As shown in figure 12, voltage D/A converter 382 comprises that a plurality of resistance R 1 to R7 and a plurality of switch S 10 are to S17, S20 to S23, S30 and S31.Resistance R 1 to R7 is connected between a supply voltage VDD3 and the ground voltage.6 points that 8 switch S 10 to S17 are connected respectively to that 2 adjacent in the intersection point, resistance R 1 to R7 of ground voltage and resistance R 1 resistance intersect and the intersection point of supply voltage VDD3 and resistance R 7.Switch S 20 is connected to the intersection point of switch S 10 and S11 and switch S 21 is connected to the intersection point of switch S 12 and S13.Switch S 22 is connected to the intersection point of switch S 14 and S15 and switch S 23 is connected to the intersection point of switch S 16 and S17.In addition, switch S 30 is connected to the intersection point of switch S 20 and S21 and switch S 31 is connected to the intersection point of switch S 22 and S23.The output voltage at the intersection point place of switch S 30 and S31 is pre-charge voltage Vpre.
Here, as highest significant position (MSB) D 0For switch S 30 connections of ' 1 ' time with as MSB D 0Be switch S 31 connections of ' 0 ' time.As the second high-order D 1Switch S 20 and S22 connect and as the second high-order D for ' 1 ' time 1Switch S 21 and S23 connect for ' 0 ' time.As the 3rd high-order D 2For ' 1 ' time, switch S 10, S12, S14 and S16 connect and as the 3rd high-order D 2For ' 0 ' time, switch S 11, S13, S15 and S17 connect.Afterwards, by 3 high-order D 0, D 1And D 2Determine the switch that a plurality of switch S 10 will be connected to S17, S20 to S23, S30 and the S31, thereby determine pre-charge voltage Vpre.For example, as 3 high-order D 0, D 1And D 2Be for ' 110 ' time, switch S 30, S20 and S11 connect, thereby export with supply voltage VDD3 dividing potential drop and as pre-charge voltage Vpre by resistance R 2 to R7 and resistance R 1.
As mentioned above,, R, G and BD/A converter are formed on the D/A converting member 340, also can use a D/A converter to convert R, G and B gray-scale data to electric current although in first to fourth exemplary embodiment.In this case, multiplexing processor 330 orders are given this D/A converting member 340 with the pairing R of a pixel, G and B data signal transmission.
In addition,, constitute a D/A converting member 340 on the data driver 300, can constitute a plurality of D/A converting members in the data driver although in first to fourth exemplary embodiment.That is, can be with many data line D 1To D mBe divided into many groups, and can constitute and a plurality of groups of corresponding respectively a plurality of D/A converting members.
Figure 13 represents a data driver structural drawing of one the 5th exemplary embodiment according to the present invention.Among Figure 13, the situation when constituting 2 D/A converting members on the expression data driver.
As shown in figure 13, the data driver 300 ' structure according to the 5th exemplary embodiment is roughly identical with first exemplary embodiment., compare 2 D/A converting member 340a of data driver 300 ' comprise and 340b, 2 multiplexing processor 330a and 330b and 2 output stage 360a and 360b with data driver 300 shown in Figure 2.
Specifically, the shift register (not shown) of multiplexing processor 330a is exported 50 multiplex signal MSW0 to MSW49 in proper order, and signal SRL0 to SRL49 is shifted.Multiplexer (not shown) among the multiplexing processor 330a, according to each multiplex signal MSW0 to MSW99, the the 1st to 50 R, G of self-sustaining latch 322 output and among B data-signal DR0 to DR49, DG0 to DG49 and the DB0 to DB49 each are done multiplexed, and order is transferred to D/A converting member 340a with R, G and B data-signal DR0 to DR49, DG0 to DG49 and DB0 to DB49.In the same way, the shift register (not shown) of multiplexing processor 330b is exported 50 multiplex signal MSW50 to MSW99 in proper order, and signal SRL50 to SRL99 is shifted.Multiplexer (not shown) among the multiplexing processor 330b, according to each multiplex signal MSW50 to MSW99, the the 51st to 100 R, G of self-sustaining latch 322 output and among B data-signal DR50 to DR99, DG50 to DG99 and the DB50 to DB99 each are done multiplexed, and order is transferred to D/A converting member 340b with R, G and B data-signal DR50 to DR99, DG50 to DG99 and DB50 to DB99.
D/A converting member 340a order converts R, G and B data-signal DR0 to DR49, DG0 to DG49 and DB0 to DB49 to data current R0 to R49, G0 to G49 and B0 to B49, and order outputs to output stage 360a with the translation data electric current R0 to R49 of institute, G0 to G49 and B0 to B49.In the same way, D/A converting member 340b order converts R, G and B data-signal DR50 to DR99, DG50 to DG99 and DB50 to DB99 to data current R50 to R99, G50 to G99 and B50 to B99, and order outputs to output stage 360b with the translation data electric current R50 to R99 of institute, G50 to G99 and B50 to B99.
Control-signals generator 350 receives shift signal SRL0 to SRL49 and SRL50 to SRL99 in proper order from multiplexing processor 330a and 330b, and produce sampled signal CHS0 to CHS49 so that they are outputed to output stage 360a in proper order, and produce sampled signal CHS50 to CHS99 so that they are outputed to output stage 360b in proper order.Output stage 360a according to each sampled signal CHS0 to CHS49 order to R, G and B data current R0 to R49, G0 to G49 with B0 to B49 samples and output stage 360b samples to R, G and B data current R50 to R99, G50 to G99 and B50 to B99 according to each sampled signal CHS50 to CHS99 order.
According to the 5th exemplary embodiment, because 2 pairing data-signals of pixel of parallel processing can increase data transfer cycle.Therefore, data current correctly can be transferred to output stage (as output stage 360a and 360b) from D/A converting member (as D/A converting member 340a and 340b).In addition, precharge parts 380a, 380b or the 380c that describes in second to the 4th exemplary embodiment can be applied in the 5th exemplary embodiment.
In first to the 5th exemplary embodiment, be used to export 300 data line D although described 1To D 300The data driver of pairing data current, this data driver needn't be subjected to the restriction of this incremental data line.In addition, data driver can be made an integrated circuit (IC) and can on active display, constitute a plurality of IC.In addition, constitute although a pixel is described as by R, G and B sub-pixel, a pixel also can be made of at least 2 sub-pixels, or a pixel can be made of 1 sub-pixel.
According to an exemplary embodiment of the present, can convert data-signal to data current, being transferred on many data lines and many data lines can be shared a D/A converting member, thereby minimize the size of D/A converting member.In addition, the data current from the output of D/A converting member correctly can be transferred to output stage.
Although described the present invention in conjunction with some exemplary embodiment, the technician in this field should understand the restriction that the present invention is not subjected to disclosed embodiment, on the contrary, purpose be to include claim and etc. in the spirit and scope of effect included difference revise.

Claims (35)

1. a data driver is used for the data-signal that order receives a plurality of expression gray levels, and a plurality of data currents are applied on many data lines that constitute on the viewing area of an active display, and this data driver comprises:
At least one converter is used for converting data-signal to data current;
At least one output stage is used for order and receives from the data current of described at least one converter transmission, and with the received data current delivery to described data line;
At least one lead, it is connected between described at least one converter and the described at least one output stage; And
One precharge parts are used for before the data current with correspondence is transferred to described output stage a pre-charge voltage being applied on the described lead.
2. according to the data driver of claim 1, wherein said converter comprises a first transistor, and it has the drain electrode that a corresponding data current flows into, and
Wherein said precharge parts comprise a transistor seconds, it is connected to described the first transistor as a current mirror, and will corresponding to described transistor seconds drain voltage, export as described pre-charge voltage by the determined voltage of a data current of correspondence.
3. according to the data driver of claim 2, wherein said precharge parts also comprise a unity gain amplifier, and it is connected between first end of the drain electrode of described transistor seconds and described lead.
4. according to the data driver of claim 3, wherein said precharge parts also comprise:
One first switch, it is connected between first end of output terminal of described unity gain amplifier and described lead; And
One second switch, it is connected between second end and described output stage of described lead, and
Wherein said first switch connection, and described second switch disconnects, so that described pre-charge voltage is applied on the described lead, and wherein said first switch disconnects, and described second switch is connected, so that a data current of correspondence is transferred to described output stage.
5. according to the data driver of claim 4, wherein said converter also comprises one the 3rd transistor, and it is connected to described the first transistor as a current mirror, and has the drain electrode of first end that is connected to described lead.
6. according to the data driver of claim 5, wherein said precharge parts also comprise one the 4th transistor, and it is connected between the drain electrode of one first power supply and described transistor seconds, and
Wherein said output stage also comprises one the 5th transistor, and it is connected between second end of described first power supply and described lead.
7. according to the data driver of claim 1, wherein pre-determine described pre-charge voltage, and irrelevant with described data current.
8. according to the data driver of claim 1, wherein said converter comprises a first transistor, and it has the drain electrode of first end that is connected to described lead and is connected to the source electrode of one first power supply that is used to provide one first voltage,
Wherein said output stage comprises a transistor seconds, and it has the drain electrode that is connected to described lead second end and is connected to the source electrode of a second source that is used to provide one second voltage, and
Wherein said precharge parts are exported the tertiary voltage between described second voltage and described first voltage as described pre-charge voltage.
9. data driver according to Claim 8, wherein said tertiary voltage is the average voltage of described first voltage and described second voltage.
10. data driver according to Claim 8, wherein said precharge parts comprise one first resistance and one second resistance, it is connected between described first power supply and the described second source,
Wherein with described first resistance and one first crossing first end that is connected to described lead of described second resistance.
11. according to the data driver of claim 10, the resistance value of wherein said first resistance equates with the resistance value of described second resistance.
12. according to the data driver of claim 10, wherein said converter also comprises one the 3rd transistor, it is connected to described the first transistor as a current mirror, and has the drain electrode that a corresponding data current flows into,
Wherein said precharge parts also comprise one first switch, it is connected between the grid of the described the 3rd transistorized grid and described the first transistor, a second switch, it is connected between the drain electrode of second end of described lead and described transistor seconds and one the 3rd switch, it is connected between first end of described lead and described first, and
Wherein said the 3rd switch connection, and described first and second switches disconnect, so that described pre-charge voltage is applied on the described lead, and described the 3rd switch disconnects, and described first and second switch connections are so that be transferred to described output stage with a data current of correspondence.
13. according to the data driver of claim 1, wherein said precharge parts will be defined as described pre-charge voltage with the corresponding voltage of a corresponding data-signal.
14. according to the data driver of claim 13, wherein said precharge parts comprise an electric pressure converter, are used for producing described pre-charge voltage from least one data bit of a plurality of data bit of a data-signal of correspondence.
15. according to the data driver of claim 14, wherein said electric pressure converter comprises a plurality of resistance, it is connected on one first power supply that one first voltage is provided and provides between the second source of one second voltage, and
Wherein said electric pressure converter is selected a selected element, be used for from one of described first power supply and a plurality of resistance crossing one first point, described second source and a plurality of resistance another one second point that intersects and with a plurality of resistance in adjacent 2 crossing a plurality of thirdly in the described pre-charge voltages of output.
16. according to the data driver of claim 14, wherein said at least one data bit comprises a highest significant position of a corresponding data-signal.
17. according to the data driver of claim 14, wherein said converter comprises:
One the first transistor is used to receive data current, and
One transistor seconds, it is connected to described the first transistor as a current mirror, and has the drain electrode of first end that is connected to described lead,
Wherein said output stage comprises one the 3rd transistor, and it has second end drain electrode that is connected to described lead.
18. according to the data driver of claim 17, wherein said precharge parts also comprise:
One first switch, it is connected between first end of output terminal of described electric pressure converter and described lead; And
One second switch, it is connected between second end and described the 3rd transistor drain of described lead,
Wherein said first switch connection, and described second switch disconnects, so that described pre-charge voltage is applied on the described lead, and wherein said first switch disconnects, and described second switch is connected, so that a data current of this converter of correspondence is transferred to described output stage.
19. the data driver according to claim 1 also comprises:
One latch is used in proper order a plurality of data-signals being sampled and keeping; And
One multiplexing processor is used for a plurality of data-signals that provide from described latch are done multiplexed, and order gives described converter with a plurality of data signal transmission,
Wherein said converter order converts a plurality of data-signals to a plurality of data currents, and in proper order a plurality of data currents is transferred to described output stage, and
Wherein said output stage order is sampled to a plurality of data currents, and a plurality of data currents are transferred on many data lines.
20. according to the data driver of claim 19, wherein a plurality of data-signals comprise a plurality of first data-signals of representing one first color, a plurality of second data-signals of expression one second color and a plurality of the 3rd data-signals of representing one the 3rd color, and
Wherein said converter comprises one first converter, is used to change described first data-signal, one second converter, is used to change described second data-signal and one the 3rd converter, is used to change described the 3rd data-signal.
21. according to the data driver of claim 19, wherein many data lines are divided into a plurality of groups, and described converter comprises and a plurality of groups of corresponding a plurality of converters.
22. according to the data driver of claim 1, wherein said active display uses an organic light-emitting units as a light-emitting component.
23. an active display comprises:
One viewing area, comprise many data lines, many first sweep traces, many second sweep traces and a plurality of pixel region, described first and second sweep traces extend on the vertical direction of described data line, each pixel region is defined by a described data line and corresponding described first sweep trace, and has at least one light-emitting component;
The one scan driver is used for selectively a plurality of selection signals being transferred to many first sweep traces, and a plurality of emissioning controling signals is transferred on many second sweep traces selectively; And
One data driver, comprise a converter, be used for order and receive a plurality of data-signals and convert a plurality of data-signals to a plurality of data currents and an output stage in proper order, be used for receiving data current in proper order and data current being transferred to many data lines from described converter
Wherein before a corresponding data current is transferred to described output stage from described converter, a pre-charge voltage is applied on the lead that is connected between described converter and the described output stage.
24. according to the active display of claim 23, wherein said converter comprises a first transistor, it is connected to first end of described lead, and output and the corresponding electric current of a corresponding data current,
Wherein said output stage comprises a transistor seconds, and it is connected to second end of described lead, and is used to receive an electric current that flows into described the first transistor,
Wherein said data driver also comprises precharge parts, and it comprises one the 3rd transistor and one the 4th transistor of serial connection, and
Wherein said precharge parts will be given described the 3rd transistor with the corresponding corresponding current delivery of a data current, and described pre-charge voltage is first the voltage that described the 3rd transistor and described the 4th transistor intersect.
25. according to the active display of claim 24, wherein said converter also comprises one the 5th transistor, it is connected to the described second and the 3rd transistor as a current mirror, and is used to transmit data current.
26. according to the active display of claim 24, wherein said precharge parts also comprise a unity gain amplifier, it is connected between first end of described first and described lead, and is used for described first voltage of locating is applied to described lead.
27. according to the active display in the claim 23, wherein said pre-charge voltage is determined by a data current of correspondence.
28. according to the active display of claim 23, wherein said pre-charge voltage be one first voltage that provides from one first power supply of described converter is provided and one second voltage that provides from a second source of described output stage between a voltage.
29. according to the active display of claim 28, wherein said converter comprises a first transistor, it is connected between first end and described first power supply of described lead, and is used to export and the corresponding electric current of a corresponding data current,
Wherein said output stage comprises a transistor seconds, and it is connected between second end and described second source of described lead, and is used to receive an electric current that flows into described the first transistor,
Wherein said data driver also comprises precharge parts, it is connected between described first power supply and the described second source, and comprise one first resistance and one second resistance of serial connection, with one first first end that is connected to described lead that described first resistance and described second resistance are intersected, and
Wherein said pre-charge voltage is described first voltage of locating.
30. according to the active display of claim 29, the resistance value of wherein said first resistance equates with the resistance value of described second resistance.
31. according to the active display of claim 29, wherein said converter also comprises one the 3rd transistor, it is connected to described the first transistor as a current mirror, and is used to transmit a corresponding data current.
32. according to the active display of claim 23, wherein said pre-charge voltage is and the corresponding voltage of at least one data bit of a corresponding data-signal.
33. according to the active display of claim 32, wherein said converter comprises a first transistor, it is connected to first end of described lead, and is used for output and the corresponding electric current of data current,
Wherein said output stage comprises a transistor seconds, and it is connected to second end of described lead, and is used to receive an electric current that flows into described the first transistor,
Wherein said data driver also comprises precharge parts, and it has a plurality of resistance that are serially connected between one first power supply and the second source, and
Wherein according at least one data bit of a data-signal of correspondence, the voltage of described first power source voltage and described second source is carried out dividing potential drop to described pre-charge voltage and dividing potential drop gained voltage is described pre-charge voltage.
34. according to the active display of claim 33, wherein said converter also comprises one the 3rd transistor, it is connected to described the first transistor as a current mirror, and is used to transmit a corresponding data current.
35. according to the active display of claim 23, wherein said light-emitting component is an Organic Light Emitting Diode.
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