CN1746870A - Flash array storage method and module for real-time data record in digital signal processor - Google Patents
Flash array storage method and module for real-time data record in digital signal processor Download PDFInfo
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Abstract
A method for storing flash memory array recording real time data of digit signal processor includes applying link port of SHARC DSP chip an information exchange channel between digit signal processor and module recording real time data of said processor, using NAND flash chip as storage media of flash memory array on module for recording real time data of said processor. The module for recording real time data of the process or consists of control circuit with SHARC DSP chip, storage circuit with 1-2 pieces of NOR flash memory chip and NAND flash memory array and interface circuit with socket and matching resistance.
Description
Technical field
The present invention relates to the data record method and the module thereof of digital signal processor, particularly the date storage method of data/signal processing systems such as radar, sonar signal processing, control in real time.
Background technology
Mass-memory unit can adopt CD, hard disk and electric board at present.Because the restriction CD of writing speed and shock resistance can not be used for the debugging and the real-time data record of digital signal processor, and hard disk can't satisfy the needs of digital signal processor debugging and data recording because it is also strict to the requirement of working temperature the more weak while of shock resistance.Present electric board technology does not require to design at the data in real time record of digital signal processor, and data transfer rate is slow between existence and the digital signal processor, and writing speed is slow, can not reclaim shortcomings such as " out-of-date " data automatically.In sum, need be at the new mass-memory unit of characteristics design of real-time data record in digital signal processor.
Summary of the invention
The object of the present invention is to provide a kind of flash array storage method and module thereof that is used for real-time data record in digital signal processor, it has reliability height, the fast characteristics of data transfer rate.
To achieve these goals, technical scheme of the present invention is: be used for the flash array storage method of real-time data record in digital signal processor, it is characterized in that:
(1). digital signal processor and be used for the link port (Link Port) that information exchanging channel between the module of real-time data record in digital signal processor adopts the SHARC dsp chip;
(2). the storage medium of flash array that is used for the module of real-time data record in digital signal processor is NAND (NANDFlash Memory) flash chip.
Form nand flash memory array by 2-64 sheet nand flash memory chip, nand flash memory array is divided into groups, every group of size is identical, before each the use, the record amount that requires according to digital signal processor is chosen the grouping of 2-32 number purpose and is used for record data, and inquiry NOR (NOR Flash Memory) flash memory, the grouping of finding out the requisite number purpose and not have at most use is used for record data, and every group operating position is kept in the NOR flash memory.
A kind of module that is used for real-time data record in digital signal processor that realizes said method mainly is made up of control circuit, memory circuit, interface circuit and power circuit, and power circuit provides power supply; It is characterized in that: control circuit comprises the SHARCDSP chip, the control chip that resets, programmable logic device (PLD), clock circuit; Memory circuit comprises 1-2 sheet NOR flash chip and nand flash memory array, and nand flash memory array is made up of 2-64 sheet nand flash memory chip; Interface circuit comprises the link port socket and the build-out resistor of SHARC dsp chip, and the link port socket of SHARC dsp chip is connected with build-out resistor, and build-out resistor is connected with the link port of SHARCDSP chip; The interface control protocol of control circuit generation NOR flash chip and nand flash memory chip is swap data with it.
The present invention adopts 2-64 sheet nand flash memory chip to form the extendible nand flash memory array of high capacity (storage array), carries out data communication by the high-speed link mouth of SHARC dsp chip.Under the driving of nand flash memory array supervisory routine, utilize memory circuit and control circuit to finish the data external memory.Data/signal processing systems such as data recording speed of the present invention is fast, power is low, no driver can be applicable to radar, sonar signal is handled, control in real time.Because data storage cell is made of solid-state devices, can under the gentle vibration grade of height environment, work reliably, satisfy in digital signal processor debugging, test and the course of work demands such as real-time data record.
Compare with prior art, the present invention has following advantage: adopt nand flash memory chip to constitute the nand flash memory array of vast capacity, capacity is big, can expand, volume is little, low in energy consumption, anti-adverse environment, reliability height; Data transmit and writing speed is fast and not fragile, data can preserve 10 years or more than; Flash chip erasable 1,000,000 times or more than; It is fast that the control that utilizes High Performance DSP to carry out data communication and flash array has speed, the efficient height, and volume is little, and is low in energy consumption, and the cost performance height is easy to a series of strong points such as exploitation.
Description of drawings
Fig. 1 is the hardware principle block diagram of the present invention's module of being used for real-time data record in digital signal processor
Fig. 2 is the software principle block diagram that the present invention is used for the module real-time data record of real-time data record in digital signal processor
Fig. 3 is that the present invention is used for the software principle block diagram that the module data of real-time data record in digital signal processor reads
Fig. 4 is the circuit theory diagrams (the 1st page, the control circuit part) that the present invention is used for the module of real-time data record in digital signal processor
Fig. 5 is the circuit theory diagrams (the 2nd page, the control circuit part) that the present invention is used for the module of real-time data record in digital signal processor
Fig. 6 is the circuit theory diagrams (the 3rd page, memory circuit part, interface circuit part) that the present invention is used for the module of real-time data record in digital signal processor
Fig. 7 is the circuit theory diagrams (the 4th page, the memory circuit part) that the present invention is used for the module of real-time data record in digital signal processor
Embodiment
The flash array storage method that is used for real-time data record in digital signal processor,
(1). digital signal processor and be used for the link port (Link Port) that information exchanging channel between the module of real-time data record in digital signal processor adopts the SHARC dsp chip;
(2). the storage medium of flash array that is used for the module of real-time data record in digital signal processor is NAND (NANDFlash Memory) flash chip.
Form nand flash memory array by 2-64 sheet nand flash memory chip, nand flash memory array is divided into groups, every group of size is identical, before each the use, the record amount that requires according to digital signal processor is chosen the grouping of 2-32 number purpose and is used for record data, and inquiry NOR (NOR Flash Memory) flash memory, and the grouping of finding out the requisite number purpose and not have at most use is used for record data, every group operating position is kept in the NOR flash memory, thereby realizes recycling of grouping.
Fig. 1 adopts SHARC DSP, nand flash memory and NOR flash memory to be configured for the hardware principle block diagram of the module of real-time data record in digital signal processor.
The module that is used for real-time data record in digital signal processor mainly is made up of control circuit, memory circuit, interface circuit and power circuit, and power circuit provides power supply; The interface control protocol of control circuit generation NOR flash chip and nand flash memory chip is swap data with it.
Control circuit comprises the SHARC dsp chip, the control chip that resets, programmable logic device (PLD), bus level conversion chip, clock circuit.
The SHARC dsp chip of U.S. Analog Devices company has the link port of six 4bit data lines, every Lu Keda 40Mbytes/sec, six the tunnel can reach 240Mbytes/sec, link port communication protocol is fairly simple, both can utilize other SHARC and the SHARC of storage in the mould to carry out high speed data transfer, and also in digital signal processor, utilize FPGA to realize that the link port agreement realizes and originally is used for exchanges data between the module of real-time data record in digital signal processor.
The control chip that resets produces power-on reset signal.
Programmable logic device (PLD) produces required control signal of SHARC DSP operate as normal and the required control signal of SHARC DSP visit memory circuit.
The bus level conversion chip converts the Transistor-Transistor Logic level of SHARC dsp chip external interface to LVTTL level that nand flash memory chip can receive.If the SHARC dsp chip of used LVTTL level can be without the bus level conversion chip.
Clock circuit comprises clock generation chip and clock signal shaping chip.Clock generation chip produces the required clock signal of SHARC dsp chip operate as normal, through giving SHARC dsp chip and programmable logic device (PLD) after the shaping.
Memory circuit comprises 1-2 sheet NOR flash chip and nand flash memory array, and nand flash memory array is made up of 2-64 sheet nand flash memory chip.NOR flash chip quantity is the 1-2 sheet, and the NOR flash memory also can replace with NVRAM.Nand flash memory array to be bunch being unit, and every bunch by 48 nand flash memory chip or be extended to 32 by 2 16 nand flash memory chip and constitute.Can adopt 1 bunch or a plurality of bunches to form nand flash memory array according to different applicable cases.Nand flash memory array is called for short flash array.
Interface circuit comprises the link port socket and the build-out resistor of SHARC dsp chip.Each link port socket is through being connected to a link port of SHARC dsp chip in inside modules after the build-out resistor.
Power circuit comprises voltage transitions chip and supply socket, and external direct current power supply provides 5V power supply by supply socket to this module, and the voltage transitions chip becomes 3.3V with the 5V voltage transitions.If all devices all are the 3.3V power supplies, can use the external direct current power supply of 3.3V, without the voltage transitions chip.
Introduce the workflow of the flash array storage method that is used for real-time data record in digital signal processor below.
At first introduce the relevant NOR flash chip and the storage chip of nand flash memory array.
The NOR flash memory:
The NOR flash memory manages according to the sector, and each sector is divided into some unit, and the sector number of the NOR flash chip of different model is not necessarily identical, and the unit number of every sector is also not necessarily the same.Can read any unit of NOR flash memory at random, also can be to the programming of the unit wiped arbitrarily, but can not programme once more to programmed cells.The NOR flash memory must be that unit is wiped with the sector.The NOR flash memory can not can replace the NOR flash memory to preserve the flash array parameter with NVRAM to writing also.
Nand flash memory:
Nand flash memory chip is by piece (block), page or leaf (page) and unit (cell) tissue, and every chip has some, and every has some pages or leaves, and every page has some unit.The chip of different model, " piece ", " page or leaf " are not necessarily identical with the number of " unit ".Nand flash memory chip must be that unit is wiped with piece (block), is that unit writes with the page or leaf.Write fashionable can be not from first unit of this page, but last writing unit must not surmount this page boundary.Every page is divided into memory block and spare area.
First of nand flash memory must be active block, and other piece may be invalid block (invalid block), just has invalid block when dispatching from the factory, in use the active block piece that also may neutralize.Decision rule to invalid block is that certain bit of certain unit (different flash chip element address differences) is ' 0 ' in the preceding two pages of spare areas of this piece.Reliable for what write down, invalid block can not be used for preserving data.Although invalid block may appear in nand flash memory, because the structure of each piece all is separate, so, do not influence the operation of system to active block as long as invalid block is discerned.In the process of using, must mark and wipe the invalid block that failure and program fail are produced in the spare area of nand flash memory.
Below be the introduction of real-time data record process:
The software principle block diagram of record data is seen Fig. 2.
In order to realize recycling of storage space, be that unit is divided into different groups with storage array with the piece of some according to different operating positions.Before the first use storage array, the SHARC dsp chip carries out division operation to storage array, generates the grouped record table and also is kept in the NOR flash memory.
After powering on, the SHARC dsp chip reads curing automatically from the NOR flash memory software begins to carry out.
The SHARC dsp chip is waited for the order that digital signal processor is sent from link port, and judges content.If data recording is just carried out in the real-time data record request, otherwise carry out other software function module.
The SHARC dsp chip carries out real-time data record and at first reads in the NOR flash memory about the grouped record of nand flash memory array, if just do not think that this system is a new system, regenerates grouped record, deposits the NOR flash memory in.The size of group is a unit with the piece of nand flash memory, and the deviser will determine the piece number that comprises of a group as the case may be.If the utilization factor of the excessive nand flash memory of size of group is low, if the size of group is too small, the record amount that the group number too much uses is big.
Wait for the data volume that digital signal processor is sent needs record again.This data volume both can be accurate data recording amount, also can be an estimation to want record data amount.But estimated value should be less than actual amount of data, otherwise may cause losing of data.If the group big or small smaller to the estimation accuracy requirement just than higher.
The SHARC dsp chip is made as N according to the required grouping number of data volume decision of need record.Read in the NOR flash memory historical operating position of each group then, find out N the grouping that not have use at most, and in the NOR flash memory record.Then, N grouping will using wiped,, only wipe all active blocks in these groupings, all active blocks are charged to the NOR flash memory successively for fear of the invalid block record that destroys the spare area.Begin data recording then.If wipe certain piece failure, to mark in the spare area of this piece, this part will be rejected from active block forever.If the record failure appears in certain piece in the record, the SHARC dsp chip also can be marked in the spare area of this piece.
Utilize the link port of SHARC dsp chip to receive data during record data, inquire about the active block record sheet in the NOR flash memory then, find the block address of the pairing nand flash memory in current record address.Write fashionable general-purpose storage or the storage on chip of can adopting the short run metadata cache is got up to be accumulated to one page write-once technology, also can adopt SHARC whenever to receive record data one time, just record method once.
After the data volume of record reached the data volume of this record, data recording finished.
Below be the introduction of data readout:
The software principle block diagram of reading of data is seen Fig. 3.
After powering on, the SHARC dsp chip reads curing automatically from the NOR flash memory software begins to carry out.
The SHARC dsp chip is waited for the order that link port is sent, and judges content.Read if data read request is just carried out data, otherwise carry out other software function module.
Before the SHARC dsp chip is carried out data and read, at first obtain the record batch of required reading of data from link port.The record batch general relative numbering of using.The grouping of the last record of 1 expression, the grouping that last registration is gone up in 2 expressions, and the like.Also can adopt other record Mission Number mode.The SHARC dsp chip reads in the NOR flash memory then about the grouping service recorder of nand flash memory array, finds out batch used grouping of this record.Inquire about the NOR flash memory again and obtain all effective record blocks that this grouping is used.The SHARC dsp chip is read the data of grouping by link port and is passed to digital signal processor or other treatment facility.
The present invention is used for the circuit theory diagrams of the module of real-time data record in digital signal processor, as Fig. 4, Fig. 5, Fig. 6, shown in Figure 7.
ADSP-21060KS-160 in the SHARC series DSP that dsp chip employing U.S. Analog Devices company releases.Flash memory adopts the AM29F040 NOR flash chip of U.S. AMD and the K9K4G08 nand flash memory chip of Korea S Samsung.AM29F040 is made of 8 sectors, each sector 64KB, monolithic capacity 512KB.K9K4G08 constitutes by 4096, and every 64 pages, every page adds that by the 2K byte 64 byte stand-by units constitute.Each storage unit of K9K4G08 has 8, and present embodiment is extended to the storage bunch of 512M * 32bit to 4 K9K4G08, and the storage array of 1G * 32bit, 4G byte altogether bunch are formed in the storage of 2 512M * 32bit.
Control circuit comprises SHARC dsp chip U1 (U1 that is numbered that refers to this chip in the embodiment circuit theory diagrams, down with), the control chip U3 that resets, bus level conversion chip U8 and bus level conversion chip U9, programmable logic device (PLD) U5, clock circuit.Wherein clock circuit comprises clock generation chip U2 and clock signal shaping chip U6.Can be if the external interface level of the SHARC dsp chip that adopts is identical with the external interface level of nand flash memory chip without the bus level conversion chip.
Memory circuit comprises NOR flash chip U7 and nand flash memory array.Nand flash memory array has 2 bunches.Form by nand flash memory chip U10, nand flash memory chip U12, nand flash memory chip U14, nand flash memory chip U16 for the 1st bunch, form by nand flash memory chip U11, nand flash memory chip U13, nand flash memory chip U15, nand flash memory chip U17 for the 2nd bunch.
Interface circuit comprises link port socket L1-L6, the build-out resistor row PR2-PR10 of SHARC dsp chip.
Power circuit comprises voltage transitions chip U4 and supply socket J2, and external direct current power supply provides 5V power supply by J2 to this module, and U2 becomes 3.3V voltage with the 5V voltage transitions.
Used main components and parts model of module embodiment of the present invention and parameter are as follows:
| Circuit symbol | Title | Specifications and models |
| U10-U17 | Nand flash memory chip | K9K4G08U0M |
| U1 | The SHARC dsp chip | ADSP-21060KS-160 |
| U7 | The NOR flash chip | AM29F040B |
| U8、U9 | The bus driver chip | SN74LVT162245DL |
| U6 | Reverser (not gate) | SN74AHC14 |
| U2 | Clock oscillator | 40MHz |
| U5 | Programmable logic device (PLD) | LC4128V-75T100C |
| L1-L6 | SHARC DSP link port socket |
| U3 | The reset generation chip | MAX811 |
| U4 | The DC voltage conversion chip | IB0503LD |
| S1 | Reset button |
Programmable logic device (PLD) LC4128V is used for cooperating the SHARC dsp chip to produce the interface protocol of each storage chip, makes SHARCDSP can read and write the data of memory circuit.It below is VHDL language source code to the LC4128 programming.
library ieee； use ieee.std_logic_1164.all； use ieee.std_logic_unsigned.all； entity device is port( PWRESET：in std_logic； RESET：out std_logic； Addr：in std_logic_vector(2 downto 0)； RD：in std_logic； WR：in std_logic； BMS：in std_logic； MS0：in std_logic； MS2：in std_logic； FLAG0：out std_logic； FLAG1：out std_logic； CE：out std_logic； SSD_RB0：in std_logic； SSD_RE0：out std_logic； SSD_CE0_N：out std_logic； SSD_WE0_N：out std_logic；4 SSD_RB1：in std_logic； SSD_RE1：out std_logic； SSD_CE1_N：out std_logic； SSD_WE1_N：out std_logic； SSD_WP_N：out std_logic； SSD_CLE：out std_logic； SSD_ALE：out std_logic； SSD_OE_N：out std_logic； <!-- SIPO <DP n="6"> --> <dp n="d6"/> SSD_DIR：out std_logic)； end； architecture behav of device is begin RESET＜＝PWRESET； FLAG0＜＝SSD_RB0； FLAG1＜＝SSD_RB1； CE＜＝BMS and MS2； SSD_WP_N＜＝’1’； SSD_RE0＜＝’0’when Addr＝2 and MS0＝’0’and RD＝’0’else’1’； SSD_RE1＜＝’0’when Addr＝6 and MS0＝’0’and RD＝’0’else’1’； SSD_CE0_N＜＝’0’when Addr(2)＝’0’and MS0＝’0’else’1’； SSD_CE1_N＜＝’0’when Addr(2)＝’1’and MS0＝’0’else’1’； SSD_WE0_N＜＝’0’when Addr(2)＝’0’and MS0＝’0’and WR＝’0’else’1’； SSD_WE1_N＜＝’0’when Addr(2)＝’1’and MS0＝’0’and WR＝’0’else’1’； SSD_ALE＜＝’1’when Addr(1 downto 0)＝0 and MS0＝’0’and WR＝’0’else’0’； SSD_CLE＜＝’1’when Addr(1 downto 0)＝1 and MS0＝’0’and WR＝’0’else’0’； SSD_OE_N＜＝MS0； SSD_DIR＜＝RD； end；
, can read the Control Software that is solidificated in the NOR flash memory after the SHARC dsp chip powers on and carry out after the LC4128 programming by this section code, also can pass through external memory area/MS2 corresponding address and visit the NOR flash memory.The reference address of nand flash memory is as follows:
| Address location | Function |
| 400000H* | Can only write, the interior element address of chip of first bunch of nand flash memory visiting is set |
| 400001H | Can only write, send out visit order to the chip of first bunch of nand flash memory |
| 400002H | Read-write, the data of first bunch of nand flash memory of read-write |
| 400004H | Can only write, the interior element address of chip of second bunch of nand flash memory visiting is set |
| 400005H | Can only write, send out visit order to the chip of second bunch of nand flash memory |
| 400006H | Read-write, the data of second bunch of nand flash memory of read-write |
* the back adds H, represents that this numeral is that 16 systems are represented value.
Whether the SHARC dsp chip knows nand flash memory " being ready to " by the state that reads the FLAG pin.FLAG0 is corresponding with first bunch of nand flash memory, and FLAG1 is corresponding with second bunch of nand flash memory.FLAG is that high level is represented " being ready to ", and low level is represented " doing ".
Claims (3)
1. be used for the flash array storage method of real-time data record in digital signal processor, it is characterized in that:
(1). digital signal processor and be used for the link port that information exchanging channel between the module of real-time data record in digital signal processor adopts the SHARC dsp chip;
(2). the storage medium of flash array that is used for the module of real-time data record in digital signal processor is a nand flash memory chip.
2. the flash array storage method that is used for real-time data record in digital signal processor according to claim 1, it is characterized in that: form nand flash memory array by 2-64 sheet nand flash memory chip, nand flash memory array is divided into groups, every group of size is identical, before each the use, the record amount that requires according to digital signal processor is chosen the grouping of 2-32 number purpose and is used for record data, and inquiry NOR flash memory, the grouping that finding out the requisite number purpose does not have to use at most is used for record data, and every group operating position is kept in the NOR flash memory.
3. a module that is used for real-time data record in digital signal processor that realizes the described method of claim 1 mainly is made up of control circuit, memory circuit, interface circuit and power circuit, and power circuit provides power supply; It is characterized in that: control circuit comprises the SHARC dsp chip, the control chip that resets, programmable logic device (PLD), clock circuit; Memory circuit comprises 1-2 sheet NOR flash chip and nand flash memory array, and nand flash memory array is made up of 2-64 sheet nand flash memory chip; Interface circuit comprises the link port socket and the build-out resistor of SHARC dsp chip, and the link port socket of SHARC dsp chip is connected with build-out resistor, and build-out resistor is connected with the link port of SHARC dsp chip; The interface control protocol of control circuit generation NOR flash chip and nand flash memory chip is swap data with it.
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Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7822912B2 (en) | 2005-03-14 | 2010-10-26 | Phision Electronics Corp. | Flash storage chip and flash array storage system |
| CN101901116A (en) * | 2010-07-26 | 2010-12-01 | 邓昕岳 | Method for expanding low-capacity NAND flash chips into high-capacity module |
| CN101957444A (en) * | 2010-09-30 | 2011-01-26 | 中国船舶重工集团公司第七二三研究所 | Multichannel radar amplitude and phase automatic correcting method and device |
| CN101689403B (en) * | 2007-05-31 | 2015-01-07 | 美光科技公司 | Resistive memory architectures with multiple memory cells per access device |
Family Cites Families (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1241746A (en) * | 1999-03-31 | 2000-01-19 | 五邑大学 | Universal speech control instruction generator |
| CN1147933C (en) * | 2002-04-22 | 2004-04-28 | 信息产业部电子第15研究所 | High speed and high-capacity flash solid memory structure and manufacture process |
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2005
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Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7822912B2 (en) | 2005-03-14 | 2010-10-26 | Phision Electronics Corp. | Flash storage chip and flash array storage system |
| CN101689403B (en) * | 2007-05-31 | 2015-01-07 | 美光科技公司 | Resistive memory architectures with multiple memory cells per access device |
| CN101901116A (en) * | 2010-07-26 | 2010-12-01 | 邓昕岳 | Method for expanding low-capacity NAND flash chips into high-capacity module |
| CN101957444A (en) * | 2010-09-30 | 2011-01-26 | 中国船舶重工集团公司第七二三研究所 | Multichannel radar amplitude and phase automatic correcting method and device |
| CN101957444B (en) * | 2010-09-30 | 2012-08-01 | 中国船舶重工集团公司第七二三研究所 | Multichannel radar amplitude and phase automatic correcting method and device |
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