CN1745468A - Large-area nanoenabled macroelectronic substrates and uses therefor - Google Patents
Large-area nanoenabled macroelectronic substrates and uses therefor Download PDFInfo
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- CN1745468A CN1745468A CN03825485.9A CN03825485A CN1745468A CN 1745468 A CN1745468 A CN 1745468A CN 03825485 A CN03825485 A CN 03825485A CN 1745468 A CN1745468 A CN 1745468A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01F—MAGNETS; INDUCTANCES; TRANSFORMERS; SELECTION OF MATERIALS FOR THEIR MAGNETIC PROPERTIES
- H01F1/00—Magnets or magnetic bodies characterised by the magnetic materials therefor; Selection of materials for their magnetic properties
- H01F1/01—Magnets or magnetic bodies characterised by the magnetic materials therefor; Selection of materials for their magnetic properties of inorganic materials
- H01F1/40—Magnets or magnetic bodies characterised by the magnetic materials therefor; Selection of materials for their magnetic properties of inorganic materials of magnetic semiconductor materials, e.g. CdCr2S4
- H01F1/401—Magnets or magnetic bodies characterised by the magnetic materials therefor; Selection of materials for their magnetic properties of inorganic materials of magnetic semiconductor materials, e.g. CdCr2S4 diluted
- H01F1/405—Magnets or magnetic bodies characterised by the magnetic materials therefor; Selection of materials for their magnetic properties of inorganic materials of magnetic semiconductor materials, e.g. CdCr2S4 diluted of IV type, e.g. Ge1-xMnx
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- Engineering & Computer Science (AREA)
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- Thin Film Transistor (AREA)
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Abstract
A method and apparatus for an electronic substrate having a plurality of semiconductor devices is described. A thin film of nanowires is formed on a substrate. The thin film of nanowires is formed to have a sufficient density of nanowires to achieve an operational current level. A plurality of semiconductor regions are defined in the thin film of nanowires. Contacts are formed at the semiconductor device regions to thereby provide electrical connectivity to the plurality of semiconductor devices. Furthermore, various materials for fabricating nanowires, thin films including p-doped nanowires and n-doped nanowires, nanowire heterostructures, light emitting nanowire heterostructures, flow masks for positioning nanowires on substrates, nanowire spraying techniques for depositing nanowires, techniques for reducing or eliminating phonon scattering of electrons in nanowires, and techniques for reducing surface states in nanowires are described.
Description
Technical field
The present invention relates to a kind of semiconductor device, the particularly use of nano wire film in semiconductor device.
Background technology
What come into the picture is the low-cost electronics of development industrial, especially low-cost, the large area electron device of development.The acquisition of this large area electron device may be the reform of the kind of the technical field from civilian to military.The example application of this device comprises drive circuit, large-scale library, credit card, the RFID tag that is used for expensive price and inventory tag, secure screen/supervision or highway communication surveillance, the large tracts of land sensor array etc. that are used for active matrix liquid crystal display (LCD) and other type matrix display.
Aspect physical size, electronics is towards two extreme development.According to the law of Moore ' s, microelectronic fast compactization has caused the rated output increase that cost is reduced.Simultaneously, develop at grand electronic applications, wherein electronic device is integrated on the large tracts of land substrate (for example, have according to square metre measurement size).Present grand electronics mainly is based on amorphous silicon on glass (a-Si) or polysilicon (p-Si) thin-film transistor (TFT), and in every field, find important application, comprise flat-panel monitor (FPD), solar cell, image sensor array and digital x-radial imaging device.
Yet present technology is restricted on using.For example, the substrate that plastics is used as grand electronics attracts much attention day by day, and this is that plastics have because various favorable characteristics comprise flexibility, impact resistance, low weight and low cost.Yet it is very difficult making high performance TFT on plastics, because processing step must carry out below the vitrification point of plastics.People have done the research of very big effort input to the new material that is suitable for TFT on the plastics (mixing as organic and organic and inorganic) or coming of new strategy, but only obtain limited achievement.Organic tft has the potential of the manufacturing process that is used to roll on plastic, but has only about 1cm
2The limited carrier mobility of/Vs (per weber of square centimeter).The restriction that is caused by material and/or substrate treatment temperature (particularly on plastics) causes low device performance, and device is restricted to low frequency applications.Therefore, the application of calculating, control or the communication function of needs even appropriateness can not be solved by existing TFT technology.
Industrial semiconductor nanowires (NW) and Single Walled Carbon Nanotube can be used for making and have the nanoscale field-effect transistor (FET) that can compare with the Electronic Performance of first water monocrystal material and surpass the Electronic Performance of first water monocrystal material in some cases.Particularly, need 300cm for p-SiNW
2The carrier mobility of/Vs needs 2000-4000cm for n-indium InP NW
2/ Vs, and need be up to 20000cm for Single Walled Carbon Nanotube
2The carrier mobility of/Vs.These nanometers FET extends Moore ' s law towards molecular level.But they are difficult to realize the product size nanoelectronics at present, and this is because the complexity of device fabrication and the restriction of scale.
Thereby, the method and system that needs a kind of more high performance conduction or semiconductive material and device and be used to make low cost, high-performance electronic device and element.
In addition, need a kind of high performance TFT that can be applied to plastics and need other substrate of reduction process temperature.
Also need a kind of ratio to can be used as the manufacturing scale method of the more senior manufacturing nano semiconductor device of high performance TFT.
Summary of the invention
Introduce a kind of method, system and equipment that is used to have the electronic substrate of formation one or more semiconductor device thereon.On substrate, form the thin-film transistor of semiconductor nanowires.The film of nano wire forms has enough nanowire density, so that realize exercisable current value.In the film of nano wire, limit a plurality of semiconductor regions.On semiconductor device region, form contact, provide thus and being electrically connected of a plurality of semiconductor device.
In first scheme of the present invention, form semiconductor device.With a plurality of nano wires of form of film deposit on substrate.First and second electrically contact and are formed on the substrate.At least one nano wire with first electrically contact be coupled to second electrically contact on.In the solution of the present invention, the nano wire of deposit can be semiconductive, magnetic, ferroelectric, thermoelectric, piezoelectricity, metallization or transition metal oxide nano line.
In another program of the present invention, make the film that is used for one or more semiconductor device.Form more than first nano wire that p mixes.Form more than second nano wire that n mixes.More than first nano wire and more than second nano wire are deposited on the substrate, thereby form nano wire film, it comprises that n mixes and the p doped nanowire.Nano wire film presents the characteristic of n doping and p doped nanowire.
In another program of the present invention, combining nano line heterostructure forms electronic device.Form a plurality of nano wires, make each nano wire have at least one first of mixing and at least one second portion that mixes with second dopant with first dopant along its major axis.The interval of each nano wire between the continuous knot between first and second parts is substantially equal to first distance.Formation is a pair of on substrate electrically contacts.Distance between electrically contacting approximates first distance greatly.A plurality of nano wires are deposited on the substrate.At least one nano wire of a plurality of nano wires with first electrically contact be coupled to second electrically contact on.
In another program of the present invention, in conjunction with receiving fan's heterostructure manufacturing light-emitting film.At least one light-emitting semiconducting material.A plurality of nano wires are formed by at least a light-emitting semiconducting material of selecting.Each nano wire that mixes makes each nano wire comprise at least one P-N knot.A plurality of nano wires are deposited on the substrate.
In another program of the present invention, nano wire is arranged on the target surface.The first surface of fluid mask and target surface closely cooperate, and make at least one raceway groove in the first surface be formed on the fluid mask cover the part on target surface.The flow of liquid that contains a plurality of nano wires is crossed at least one raceway groove.The nano wire that allows to be included in the liquid that flows through at least one raceway groove is set on the part on the target surface that is covered by at least one raceway groove.
In another scheme of the present invention, nano wire is applied to the target surface.Source of solvent provides nano-solution.Nano-solution comprises the liquid that contains a plurality of nano wires.Nozzle is coupled to source of solvent.Nozzle has at least one delivery outlet.The nozzle guide nano-solution is by delivery outlet and arrive on the target surface.The nano wire of nano-solution is directed on the target surface, thereby is aligned in parallel with each other basically on the described target surface, perhaps is orientated randomly each other.
In a scheme more of the present invention, design has the conducting nanowires of high electron mobility.Select semi-conducting material.Determine to provide the maximum gauge of the nano wire that forms by selected semi-conducting material of the base quantity restriction of electronics.In exemplary scenario, diameter is determined by following calculating maximum gauge:
Wherein:
H=Planck's constant=4.14 * 10
15EV-sec;
m
EffThe effective mass of=selected semi-conducting material
The N=pre-determined factor
k
b=Boltzmann ' s constant=8.62 * 10
-15EV ° of K; With
The T=working temperature;
Room temperature wherein, K
bT=.0259eV.
In another program of the present invention, use electronics as the conduction charge carrier thereby constitute nano wire, so that reduce or eliminate fully the phon scattering of the electronics in the nano wire basically.In a scheme,, use electronics as the conduction charge carrier thereby constitute with n type dopant material doped nanowire.In another program, with p type dopant material doped nanowire.By apply enough bias voltages to nano wire film, make nano wire with reverse mode work, thereby electronics is used as the conduction charge carrier.
In another scheme of the present invention, make nano wire with minimizing surface scattering.Select semi-conducting material.Form a plurality of nano wires by selected semi-conducting material.Apply the circumferential surface of each nano wire of a plurality of nano wires with insulating barrier.
In a scheme more of the present invention, make nano wire with minimizing surface scattering.Select semi-conducting material.Form a plurality of nano wires with selected semi-conducting material.Mix each nano wire of a plurality of nano wires makes each nano wire comprise core-shell material.Shell is the doping skin that surrounds each nano wire of each core.Make the charge carrier of each nano wire be limited to core basically thus during operation.
In another program, the invention provides and a kind ofly use the thin-film transistor of nano wire, nanometer rods or nano belt and be provided on various substrates making this transistorized manufacturing scale method.Particularly, have the thin-film transistor (TFT) that is parallel to line/tape spool, developed the intact completely new concept of grand electronics by using oriented semiconductor nano wire or nano belt film to make.These new TFT have the conducting channel that is formed by parallel a plurality of monocrystal nanowires (as former wooden bridge) or single crystal nano-belt, and this conducting channel intersects with all paths from source electrode to drain electrode for high carrier mobility.
In another scheme of the present invention, a kind of NW-TFT manufacture method is provided, wherein before active semi-conductor material puts on device substrate, carry out high temperature active semi-conductor material synthesis technique (for example, being used to form nano wire or nano belt).Afterwards, the NW-TFT that forms is put on device substrate through the solution packaging technology, be provided for to comprising that any substrate type of plastic applies the general technology of any semi-conducting material.
According to the solution of the present invention, can form p raceway groove and n channel TFT.In exemplary scenario, introduce a kind of compensated inverter here, it is to use nano wire and receives that the combination of fan band assembles by p raceway groove and n channel TFT.
According to other scheme of the present invention, introduce the system and method that further improves performance here.For example, the solution of the present invention allows the NW-TFT performance to cooperate or surpass the performance of body monocrystal material.In exemplary scenario, by making new core-shell NW structure and developing fully, can improve carrier mobility, thereby surpass the carrier mobility of body monocrystal material reducing the quantum electronic effect of size.In addition, according to the solution of the present invention, the scheme representative of making NW-TFT is used for the general platform of various grand electronic application.In the solution of the present invention, use the NW that makes by optics active material to make the active film of high-performance, optics that is used for many colors solid luminescent diode (LED) display with various band gap.In addition,, can for example use low cost, K cryogenic treatment, comprise little contact or inkjet technology according to the solution of the present invention, with NW-TFT from solution deposition to the large tracts of land substrate.
In another program of the present invention, can use the structure that comprises a plurality of nano wire film layers to form electronic device.More than first nano wire is deposited on the substrate, thereby forms the first nanometer thin rete.More than second nano wire is deposited on the first nanometer thin rete, thereby forms the second nanometer thin rete.On the crosspoint between the nano wire of first and second thin layers, form knot thus as p-n junction.Can form contact, thereby on the performance basis of knot, form electronic device.The preferred aligning parallel to each other of the nano wire of the first film layer, and the preferred aligning parallel to each other of the nano wire of second thin layer.Yet, in alternative, the nano wire random orientation of first and/or second thin layer.
In another program of the present invention, form electronic device, it comprises mixing nano crystal semiconductor structure.Form single crystal semiconductor bar/film.A plurality of nano wires are deposited on the top of bar.On the crosspoint between nano wire and the single crystal semiconductor bar, form knot, as p-n junction.Can form contact, thereby on the performance basis of these knots, make electronic device.The preferred aligning parallel to each other of the nano wire of a plurality of nano wires, but also can random orientation.
In the present invention again in the scheme, form and comprise the electronic device that mixes nano amorphous/poly semiconductor structure.Deposit amorphous or polycrystalline semiconductor thin film on substrate.A plurality of nano wires are deposited on this film pattern.On the joining between nano wire and the amorphous/polycrystalline semiconductor thin film figure, form knot, as p-n junction.On the basis of the performance of these knots, can form contact, thereby form electronic device.The preferred aligning parallel to each other of the nano wire of a plurality of nano wires, but also can random orientation.
In a scheme more of the present invention, the semiconductor nanowires of launching red, green and blue light with predetermined ratio can be blended in the solution.This line mixture is flow through monocrystalline, amorphous or poly semiconductor bar/film.Form contact, thereby make the luminous electron device.According to the mixture of Illuminant nanometer line, can launch the light of any color by the luminous electron device, comprise white light.
Like this, according to the solution of the present invention, nano wire, nanometer rods, nano belt and nano-tube film can be realized various new abilities.In scheme, these comprise: with microelectronics from single crystalline substrate moving to glass and plastic; In the integrated grand electronics of device level, microelectronics and nanoelectronics; With integrated different semi-conducting materials on a substrate.These schemes of the present invention have impact to the wide region of the existing application from the flat-panel monitor to the image sensor array, and have realized being used to calculate storage and the general flexibility of communicating by letter, brand-new scope wear-resisting, disposable electronics.
These and other objects, advantage and characteristics easier quilt from following detailed description of the invention is understood.
Accompanying drawing is described
The accompanying drawing of part combination here and that form specification is represented of the present invention, and is further used for explaining principle of the present invention and those skilled in the art are made and uses the present invention with explanatory note.
Fig. 1 represent to give an example schematic diagram of a part of nano wire film of embodiment according to the present invention.
Fig. 2 represents to comprise the semiconductor device of nano wire film of embodiment of giving an example according to the present invention.
Fig. 3 A-3D represents the nano wire that each embodiment that gives an example mixes according to the present invention.
Fig. 4 A and 4B represent the example of the semiconductor device that typical case's doping embodiment mixes according to the present invention.
Fig. 5 represents to provide the flow chart of exemplary steps that is used to make a plurality of semiconductor device according to the embodiment of the invention.
Fig. 6 A-6F represents each stage of manufacturing of substrate that is used for having a plurality of semiconductor device thereon according to the embodiment of the invention.
Fig. 7 represents the flow chart according to the exemplary steps that is provided for making the electronic device that comprises nano wire film of the present invention of the embodiment of the invention.
Fig. 8 A represents the close-up view of part for example according to the nano wire film of the homogeneous mixture embodiment of the invention, that comprise n doped nanowire and p doped nanowire.
Fig. 8 B represents to comprise the part for example of the nano wire film of n doped nanowire and p doped nanowire.
Fig. 8 C represents to comprise the film of the nano wire of n doped nanowire and p doped nanowire.
Fig. 9 represents according to the flow chart of the step for example embodiment of the invention, that be provided for making nano wire film of the present invention.
Figure 10 represent to give an example nano wire of embodiment as nano wire hetero structure according to the present invention.
Figure 11 A represents according to the typical two ends embodiment of the invention, that comprise a plurality of nano wires electronic device.
Figure 11 B represents to combine the p-n-p transistor example of nano wire hetero structure.
Figure 12 represents according to the flow chart of the step for example embodiment of the invention, that be provided for making the electronic device that combines nano wire hetero structure.
Figure 13 A represent according to the embodiment of the invention, have pair of electrodes, first and electrically contact discrete pixel or the light source that electrically contacts with second.
Figure 13 B represents to be similar to according to each of the embodiment of the invention a discrete pixel of row or a light source of pixel or light source.
Figure 13 C represents the large tracts of land light source according to comprising of the embodiment of the invention of a plurality of light source row.
Figure 14 represent according to the embodiment of the invention, be provided for making flow chart in conjunction with the exemplary steps of the luminescent device of Illuminant nanometer line heterostructure.
Figure 15 A and 15B represent the bottom and the profile of fluid mask for example according to the embodiment of the invention.
Figure 16 represent to give an example nano wire navigation system of embodiment in conjunction with the fluid mask according to the present invention.
Figure 17 A and 17B represent the to give an example plane graph and the profile of the nanometer linear flow that flows through the fluid mask of embodiment according to the present invention.
Figure 18 A represents the close-fitting semiconductor wafer for example of usefulness fluid mask according to the embodiment of the invention.
Figure 18 B represents to have owing to work of the present invention the part on surface of wafer of Figure 18 A of nano wire disposed thereon.
Figure 18 C represents to utilize owing to work of the present invention the array of the integrated circuit that nano wire disposed thereon forms on wafer.
Figure 19 A represents the integrated circuit according to the example of one of integrated circuit embodiment of the invention, that can be the wafer shown in Figure 18 C.
Figure 19 B represents the close-up view according to the part of the integrated circuit of Figure 19 A of the details embodiment of the invention, expression conductive trace for example.
Figure 19 C represents by operating fluid mask for example of the present invention the nano wire of deposit on the integrated circuit part of Figure 19 B.
Figure 19 D represents can be the integrated circuit of example of one of the integrated circuit of the wafer shown in Figure 18 C according to the embodiment of the invention.
Figure 19 E represents the close-up view according to the part of the integrated circuit of Figure 19 D of the details embodiment of the invention, expression conductive trace for example.
Figure 19 F represents by operating fluid mask for example of the present invention the nano wire of deposit on the integrated circuit part of Figure 19 E.
Figure 20 A represents to relate to the curve of Figure 19 A-C.
Figure 20 B represents to relate to the curve of Figure 19 D-F.
Figure 21 represents to use the fluid mask that the flow chart of step for example of nano wire is set on the target surface according to providing of the embodiment of the invention.
Figure 22 represents the block diagram according to the nano wire spray application system of giving an example of the embodiment of the invention.
Figure 23 represents the detail view that the nanometer linear flow is outputed to the lip-deep nozzle of target for example according to the embodiment of the invention.
Figure 24 and 25 expressions have the plane graph on the target surface of a plurality of nano wires disposed thereon owing to work of the present invention.
Figure 26 represent according to the embodiment of the invention with the electrically contacting of nano wire in have the plane graph on formation a plurality of target surfaces that electrically contact thereon.
Figure 27 represents that providing of the embodiment that gives an example according to the present invention use spraying technique that the flow chart of step for example of nano wire is set on the target surface.
Figure 28 represents to provide the maximum that is used for semi-conducting material according to an embodiment of the invention can allow diameter and effective mass m
EffBetween the curve of relation.
Figure 29 represents to have enumerated the form about the information of various semi-conducting materials of giving an example.
Figure 30 represents to provide the flow chart of step for example that is used to design the conducting nanowires with high electron mobility according to the embodiment of the invention.
Figure 31 represents to enumerate about about the form of the information of III-V semi-conductor type material for example.
Figure 32 and 33 expressions are provided for making the flow chart of step for example of nano wire of the surface scattering with minimizing of embodiment of giving an example according to the present invention.
Figure 34 A is the schematic diagram of amorphous or polycrystalline Si TFT.
Figure 34 B is the schematic diagram according to the nano wire TFT of the embodiment of the invention.
Figure 34 C is the schematic diagram according to the nano belt TFT of the embodiment of the invention.
Figure 35 A is the flow chart according to the method that is used for the NW-TFT manufacturing of the embodiment of the invention.
Figure 35 B is the optical microscopy camera figure according to the NW film of the embodiment of the invention.
Figure 35 C is the schematic diagram according to the NW-TFT with gold electrode of the embodiment of the invention.
Figure 35 D is the photo-optics figure according to the NW-TFT with the NW parallel array from source electrode to the drain electrode bridge joint of the embodiment of the invention.
Figure 36 A be expression according to the embodiment of the invention in each stage of the 1V of NW-TFT at different grid voltage (V
GS) following typical drain current (I
DS) and leakage-source bias voltage (V
DS) relation curve chart.
Figure 36 B is the I that be used for NW-TFT of expression according to the embodiment of the invention
DSWith V
GSThe curve of relation.
Figure 36 C is the curve chart of expression according to the block diagram of the threshold voltage distribution that is used for NW-TFT of the embodiment of the invention.
Figure 36 D be expression according to the embodiment of the invention as device (V during for the NW-TFT conducting
Gs=10V) for the curve chart of the linear-scale of drain current relation.
Figure 37 A is the schematic diagram according to the NW-TFT on the plastic of the embodiment of the invention.
Figure 37 B is the schematic diagram according to the several NW-TFT on the plastic of the embodiment of the invention.
Figure 37 C be expression according to the embodiment of the invention in each stage of the 1V of NW-TFT at different grid voltage (V
GS) following drain current (I
DS) and leakage-source bias voltage (V
DS) relation schematic diagram.
Figure 37 D be expression according to the embodiment of the invention before the slight deflection of plastic with the schematic diagram of the transfer characteristic of afterwards identical NW-TFT.
Figure 38 A is the schematic diagram according to the NW-TFT on the plastic with electrolyte grid of the embodiment of the invention.
Figure 38 B be according to the embodiment of the invention for the I of the NW-TFT on the plastic as the function of various electrolyte grid voltages
DS-V
DSThe curve chart of relation.
Figure 38 C be according to the embodiment of the invention for the NW-TFT on the plastic with electrolyte grid, V
DSI for 10mV
DS-V
GSThe curve chart of relation.
Figure 39 A is the schematic diagram according to the CdS nano belt TFT of the embodiment of the invention.
Figure 39 B be according to the embodiment of the invention for the I of CdS nano belt TFT as the function of each grid voltage
DS-V
DSThe curve chart of relation.
Figure 39 C be according to the embodiment of the invention for CdS nano belt TFT, for the V of 1V
DSI
DS-V
GSThe curve chart of relation.
Figure 40 is that the utilization according to the embodiment of the invention has the p raceway groove NW-TFT of gain characteristic and the schematic diagram of the compensated inverter that n raceway groove CdS nano belt TFT makes.
Figure 41 A represent to give an example scanning electron micrograph picture of synthetic silicon nanowires of embodiment according to the present invention.
Figure 41 B represent to give an example according to the present invention lattice of independent silicon nanowires of embodiment decomposes the transmission electronic micro-image.
Figure 42 being used for synthetic and realizing the flow chart of the transistorized technology of high mobility nano wire film of embodiment of representing to give an example according to the present invention.
Figure 43 represent to give an example silicon nanowires core-shell structure of embodiment with monocrystalline core and medium external coating according to the present invention.
Figure 44 A-C represents the schematic diagram by the thin-film transistor (TFT) of amorphous silicon, polysilicon and the manufacturing of aligning nano wire film.
Figure 45 represents the schematic diagram that is used for aiming at the element of fluid of nano wire on large tracts of land according to the embodiment of the invention.
Figure 46 represent to give an example according to the present invention use Langmuir-Blodgett film of embodiment is aimed at the schematic diagram of nano wire on large tracts of land.
Figure 47 represent the to give an example plane graph and perspective view of a nano-wire field effect transistor of embodiment according to the present invention.
Figure 48 A and 48B represent the transistorized perspective view of local grid nano wire film according to the embodiment of the invention.
Introduce the present invention with reference to the accompanying drawings.In the accompanying drawing, identical reference marker is represented element similar on identical or the function.In addition, this reference marker of Far Left numeral of reference marker at first appears at accompanying drawing wherein.
Embodiment
Foreword
Should be understood that, here shown in and described particular embodiment be example of the present invention, do not limit the scope of the invention.In fact, for the purpose of concise and to the point, can not describe other function scheme (with the element of the element that works alone of system) of conventional electrical, manufacturing, semiconductor device and nano wire (NW), nanometer rods, nanotube and nano belt technology and system here in detail.In addition, for purpose clearly, here as being suitable for introducing the present invention continually with nano wire and semiconductor transistor device.And when the interval of quantity that these nano wires are provided for the particular embodiment of being discussed and nano wire, these enforcements are not restrictive, can also use number of nanowires and wide region at interval.Although it should be understood that to be reference continually with the nano wire, technology described here is also applicable to nanometer rods, nanotube and nano belt.It should also be understood that manufacturing technology described here can be used for making any semiconductor device type and other electron component type.In addition, these technology should be suitable for the application in electronic system, optical system, consumer electronics device, industrial electronic device, the application of wireless system space or any other application.
As used herein, term " nano wire " generally refers to and comprises less than 500nm, preferably less than any elongated conduction or the semiconductive material (or other material described here) of at least one cross sectional dimensions of 100nm, and have greater than 10, be preferably greater than 50, the length-width ratio (long: wide) more preferably greater than 100.The example of this nano wire comprises as other elongated conduction or semiconductive structure in semiconductor nanowires, carbon nano-tube and the similar size described in No.WO02/17362, WO02/48701 and 01/03208.
As used herein, but term " nanometer rods " generally refers to any elongated conduction or the semiconductive material (or other material described here) that is similar to nano wire has the length-width ratio (long: wide) less than nano wire.It should be noted that two or more nanometer rods can be coupled along their longitudinal axis, thereby the nanometer rods that is coupled is crossed over all paths between the electrode.Perhaps, two or more nanometer rods can still not be coupled, thereby have little gap between the end of two or more nanometer rods basically along their longitudinal axis substantial registration.In this case, thus electronics crosses little gap and can flow to another nanometer rods from a nanometer rods by jumping to another nanometer rods from a nanometer rods.Two or more nanometer rods can substantial registration, makes them be formed for the path that electronics moves between electrode.
When the execution mode of giving an example described here mainly adopts CdS and Si, other types of material that is used for nano wire and nano belt also can be used, comprise semiconductive nano wire or nano belt, comprise being selected from following semi-conducting material, for example: Si, Ge, Sn, Se, Te, B, C (comprising diamond), P, B-C, B-P (BP6), B-Si, Si-C, Si-Ge, Si-Sn, Ge-Sn, SiC, BN/BP/BAs, AlN/AlPAlAs/AlAsSb, GaN/GaP/GaAs/GaSb, InN/InP/InAs/InSb, BN/BP/BAs, AlN/AlPAlAs/AlAsSb, GaN/GaP/GaAs/GaSb, InN/InP/InAs/InSb, ZnO/ZnS/ZnSe/ZnTe/CdS/CdSe/CdTe, HgS/HgSe/HgTe, BeS/BeSe/BeTe/MgS/MgSe, GeS, GeSe, GeTe, SnS, SnSe, SnTe, PbO, PbS, PbSe, PbTe, CuF, CuCl, CuBr, CuI, AgF, AgCl, AgBr, AgI, BeSiN
2, CaCN
2, ZnGeP
2, CdSAs
2, ZnSnSb
2, CuGeP
3, CuSi
2P
3, (Cu, and Ag) (Al, Ga, In, Tl, Fe) (S, Se, Te)
2, Si
3N
4, GeN
4, Al
2O
3, (Al, Ga, In)
2(S, Se, Te)
3, Al
2CO and two or more these semi-conductive suitable combination.
In certain aspects, semiconductor can comprise and is selected from following dopant: the p type dopant that is selected from III family in the periodic table of elements; Be selected from the n type dopant of V family in the periodic table of elements; Be selected from the p type dopant of B, Al and In; Be selected from the n type dopant of P, As and Sb; Be selected from the p type dopant of II family in the periodic table of elements; Be selected from the p type dopant of Mg, Zn, Cd and Hg; Be selected from the p type dopant of IV family in the periodic table of elements; Be selected from the p type dopant of C and Si; Or be selected from the n type dopant of Si, Ge, Sn, S, Se and Te.
In addition, nano wire or nano belt can comprise carbon nano-tube or the nanotube that is formed by conduction or semiconductive organic polymer material (for example, pentacene and transition metal oxide).
Therefore, although be used to represent purpose in the whole explanation of term " nano wire " here, the explanation here also comprises nanotube (structure that for example, has the nano wire class of the hollow tube that forms coaxially).Nanotube can form the combinations/thin films form of nanotube, as described for nano wire here, can make up separately or with nano wire, thereby performance and advantage described here is provided.
In addition, it should be noted that nano wire film of the present invention can be " heterogeneous " film, it combines its any combination of semiconductor nanowires and/or nanotube and/or nanometer rods and/or nano belt and/or different component and/or architectural characteristic.For example, " heterogeneous membrane " can comprise the nanowires/nanotubes and the nanotube of diameter with variation and length and/or be the nanotube with " heterostructure " of changing characteristic.
In literary composition of the present invention, although the focus that describes in detail relates to nano wire, nanometer rods, nanotube or nano belt film and uses on plastic, this substrate that these nanostructures will be fixed to the upper can comprise other material, include but not limited to " even substrate; the wafer of solid material for example is as silicon, glass, quartz, polymer etc.; The big rigid plate of solid material, for example glass, quartz, plastics as Merlon etc., perhaps can comprise add ons, on for example structural, the component, etc.Flexible substrate such as roll of plastic as polyolefin, acid amides and other, also can adopt transparent substrates or these combination of features.For example, substrate can comprise other circuit or the structural detail as the part of final device of wishing.The specific example of these elements comprises electronic circuit component, as electrically contact, other lead or conductive path, comprise the conducting element of nano wire or other nano-scale, optics and/or photoelectric cell are (for example, laser, LED etc.), and structural detail (for example, microcantilever, depression, post etc.).
Refer to by " aligning " or " orientation " basically in 30 degree of the longitudinal axis on single direction of most of nano wire in a large amount of or a group nano wire and be orientated.Although most of nano wire is considered to the number of nanowires greater than 50%, in each embodiment, 60%, 75%, 80%, 90% or the nano wire of other percentage can think so major part of orientation.In some preferred version, most of nano wire is orientation in 10 degree of predetermined direction.In additional embodiment, most of nano wire can be orientated in other quantity of predetermined direction or number of degrees scope, comprises random orientation and isotropic orientation.
It should be understood that, space used herein statement (for example, " top ", " following ", " on ", D score, " top ", " bottom " etc.) just in order to represent purpose, device of the present invention can carry out ground, space according to any orientation or mode and be provided with.
The material that is used for nano wire described here also has the intrinsic mechanical flexibility of high mobility semiconductor material, allows the actual flexible high-performance electronic device of making.Because minimum diameter and aspect are than (in some embodiments greater than 1000), nano wire has excellent mechanical flexibility and intensity.Independent nano wire can carry out bending with the radius of curvature of r＜10 μ m at an easy rate before breaking.Because each the independent nano wire on these high density substrates is aimed at equidirectional, but the physical correlation of circumferential wire has kept this flexibility in nano wire film of the present invention, comprise fine and close, inorganic and orientation nano line film (DION film).Even under the situation of the independent nano wire in not crooked device, each nano wire only be the long fact of the 100 μ m r that allows macroscopic view＜＜1mm.
The embodiment of nano wire film
The present invention aims to provide the use of nano wire in system and device, so that raising system and device performance.For example, the invention provides the use of nano wire in semiconductor device.According to the present invention, a plurality of nano wires form the high mobility film.This nano wire film is used in the electronic device, thus the performance of enhance device and manufacturability.
Fig. 1 represent to give an example close-up view of nano wire film 100 of embodiment according to the present invention.Can use semiconductor nanowires film 100 to replace amorphous silicon or organic film in the conventional electrical device, thereby realize improved device behavior, allow straight forward and cheap manufacturing process simultaneously.Although used nano wire film, the present invention is particularly suitable for making high-performance, low-cost device on big and flexible substrate.
It should be noted that nano wire film 100 can be formed in the wide region of possibility surface area as described herein.For example, nano wire film of the present invention can form and have greater than 1mm
2, greater than 1cm2, greater than 10cm
2, greater than 1m
2With in addition the function area of greater or lesser area.
As shown in Figure 1, nano wire film 100 comprises a plurality of independent nano wire that closely is set together.Nano wire film 100 can have the amounts of thickness variation of the thickness that is equal to or greater than single nano wire.In the example of Fig. 1, the nano wire of nano wire film 100 is aimed at, and makes that their major axis is parallel to each other basically.Notice in alternative embodiment, the nano wire misalignment of nano wire film 100, but can be each other randomly or alternate manner ground be orientated at different directions.In alternative embodiment, the nano wire of nano wire film 100 can isotropically be orientated, thereby provides high mobility in all directions.It should be noted that the nano wire of nano wire film 100 can be aimed at according to any way with respect to the electron stream direction, so that strengthen the required performance of special applications.
Fig. 2 represents the semiconductor device that comprises nano wire film 100 200 according to second embodiment of the invention.In Fig. 2, show as transistorized semiconductor device 200, it has source electrode 202, grid 204, the drain electrode 206 that is formed on the substrate 208.Nano wire film 100 is above a part of grid 204, in the source electrode 202 and the coupling between 206 that drains.Nano wire film 100 comes work as the transistorized channel region that is used for semiconductor device 200 basically, and allows semiconductor device 200 to improve characteristic work, as described further herein.Various substrate types applicable to substrate 208 here illustrate.
Should be noted that, be used to represent purpose, in Fig. 2, show semiconductor device 200 as transistor.Those skilled in the art are appreciated that from the instruction here, and nano wire film 100 can be contained in the semiconductor device type except transistor, comprises diode.
In an embodiment, the nano wire of nano wire film 100 is to stride across source electrode 202 and the single crystal semiconductor nano wire in all paths between 206 that drain.Therefore, electric charge carrier can transmit by monocrystal nanowire, produces high mobility, and this is in fact can not be obtainable with present amorphous and polysilicon technology.
As mentioned above, the nano wire of nano wire film 100 can be orientated or aim at.For example, the nano wire of nano wire film 100 shown in Figure 2 can be parallel to source electrode 202 and the channel length that drains between 206 is aimed at, and perhaps can aim at according to alternate manner.
In an embodiment, nano wire film 100 can form and have asymmetric mobility.For example, the nano wire that this can be by asymmetricly aiming at nano wire film 100 and/or by realizing according to the particular form doped nanowire.This asymmetric mobility may produce than second direction more at first direction.For example, asymmetric mobility can produce at the order of magnitude big 10,100,1000 and 10000 times on the first direction than on second direction, perhaps has between these values, is greater than or less than any other asymmetric mobilities of these values.
The nano wire of nano wire film 100 can mix according to variety of way, generally improves performance.Doped nanowire before can be in being included in semiconductor device 200 or after comprising.In addition, can be along the some parts of its major axis doped nanowire differently, and other nano wire that can be different from the nano wire film 100 mixes.Provide for independent nano wire and as follows for some examples of the doped scheme of nano wire film.Yet those skilled in the art are appreciated that obviously that from the instruction here nano wire and nano wire film can mix according to any compound mode of alternate manner and mode described here.
Fig. 3 A represents the nano wire 300 as the monocrystal nanowire that evenly mixes.This monocrystal nanowire can be doped to according to suitable control mode in p or the n N-type semiconductor N.The nano wire such as the nano wire 300 that mix present improved Electronic Performance.For example, this nano wire can be doped to and have and the comparable carrier mobility level of monocrystal material of replacing.The one dimension performance of the electron waves that cross in nanowire channel inside and the probability of scattering of minimizing in addition, and be unlimited to any particular theory of operation, owing to can be realized even the mobility higher than body monocrystal material for this nano wire.Up to 1500cm
2The carrier mobility value of/Vs shows for the capable Si of single p (silicon) nano wire, and shows up to 4000cm for n type InP nano wire
2The carrier mobility value of/Vs.
Fig. 3 B represents the nano wire 310 according to the core-shell structure doping.Shown in Fig. 3 B, nano wire 310 has doped surface layer 302, and it can change one-tenth-value thickness 1/10, includes only nano wire 310 lip-deep molecular monolayer.This surface doping can separate the conducting channel of impurity with nano wire, and the inhibition scattering events relevant with impurity, can increase carrier mobility greatly thus.For example, when according to the core-shell structure doped nanowire, " trajectory " transmission is the place that electric charge carrier transmits through nano wire under the situation that does not have resistance basically.The further details of the doping of nano wire will provide below.
Fig. 3 C represents according to the nano wire 320 even doping of another type of core-shell structure and that use layer of dielectric material 304 to apply.Layer of dielectric material 304 can be selected from various dielectric materials, as SiO
2Or Si
3N
4The use of layer of dielectric material 304 can be simplified the manufacturing of semiconductor device 200, as described herein.Layer of dielectric material 304 can be formed on the nano wire 320, as will be described as further below.
That Fig. 3 D represents to mix according to the usefulness doped surface layer 302 of the core-shell structure shown in Fig. 3 B and with the nano wire 330 of layer of dielectric material 304 coatings, shown in Fig. 3 C.
Fig. 4 A and 4B represent the to mix example of semiconductor device 200 of embodiment according to the present invention.Shown in Fig. 4 A, with the top surface of doped layer 402 coated substrate 208.Doped layer 402 comprises electron donor or electronics acceptor doping material.The performance of semiconductor device 200 can be controlled by introducing doped layer 402.Electronics is led or the electronics acceptor material is incorporated into negative electrical charge or positive charge in the nano wire, so that realize n or p type channel transistor respectively.Because dopant separates with actual conducting channel, therefore in this structure of semiconductor device 200, can realize very high mobility value.
Shown in Fig. 4 B, doped layer 402 covers the zone of the substrate 208 of localization around nano wire film 100 basically.In an embodiment, the doped layer 402 that puts on semiconductor device 200 can be patterned into and have according to different n or capable two or more the property doped zones of p.For example, in the embodiment of Fig. 4 B, doped layer 402 has with the property doped first 404 of n type and with the property doped second portion 406 of p type.In this embodiment,, comprise light-emitting diode (LED), can realize p-n junction according to the kind of electronics and photoelectric device.
As mentioned above, doped layer 402 can be incorporated on the substrate 208 before or after the actual manufacturing of semiconductor device 200.
Nano wire aggregation with these made is the useful foundation stone that is used for the high-performance electronic device.Nano wire aggregation in substantially the same direction orientation will have the high mobility value.In addition, nano wire is handled in solution flexibly, thereby makes marked downly.The aggregation of nano wire can be assembled on any kind substrate from solution at an easy rate, thereby realizes nano wire film.For example, the nano wire film that uses in the semiconductor device can form to such an extent that comprise 2,5,10,100 and between this tittle or greater than the nano wire of any other quantity of this tittle, is used for high-performance electronic equipment.
It should be noted that when nano wire and polymer/material such as organic semiconductor material combinations, nano wire can also be used to make high-performance composite materials, wherein said organic semiconducting materials can spray on the substrate of any kind flexibly.The nano wire/polymer compound can provide the performance that is better than the straight polymer material.The further details of nano wire/polymer compound will provide below.
As mentioned above, nano wire film aggregation or film can be aligned to parallel to each other basically, perhaps can keep misalignment or stochastic regime.Non-aligned aggregation or nano wire film provide and polycrystalline silicon material Electronic Performance comparable or that be better than it, and polycrystalline silicon material has usually at 1-10cm
2Mobility value in the/Vs scope.
The aggregation or the film of the nano wire of aiming at provide the material that has with monocrystal material performance comparable or that be better than it.In addition, nano wire aggregation or the film that comprises the trajectory nano wire (for example, the core shown in Fig. 3 B-shell nano wire) of aligning can provide the significantly improved performance that is better than monocrystal material.
According to the present invention, can the making according to variety of way of aligning with non-aligned and compound and non-compound nano wire film.To provide following for the assembling of the nano wire film of these types and the embodiment for example of manufacturing.
Can obtain the nano wire film of random orientation in various manners.For example, nano wire can be distributed in the suitable solution.Use spin coating then, drip-dry or dipping-drying means is deposited to nano wire on the desirable substrate.These processing can be carried out repeatedly, so that guarantee the height coverage rate.Nano wire film/the polymer complex of random orientation can utilize the same way as manufacturing, as long as wherein the solution of dispersing nanowires is polymer solution.
The nano wire film of aiming at can utilize variety of way to obtain.For example, the nano wire film of aligning can be made by using following technology: (a) the Langmuir-Blodgett film is aimed at; (b) fluid mobility program, described in the U.S. serial No.10/239000 (AttorneyDoket No.01-000540) that applies in October, 2002, and it is for reference to quote its full content here as proof; (c) apply mechanical shear stress.For example,, in the opposite direction move first and second surfaces then, thereby aim at nano wire, use mechanical shear stress thus by nano wire being placed between first and second surfaces.By using these technology, then desirable polymer is spun on the nano wire film of generation, thus the nano wire film that can obtain to aim at.For example, nano wire can be deposited in the liquid polymers solution, aims at according to one of these or other Alignment Process then, afterwards the nano wire film of aiming at is solidified (for example, UV solidifies, and is crosslinked etc.).Nano wire film/the polymer complex that can also obtain to aim at by the nano wire film/polymer complex that mechanically stretches random orientation.
Combine the manufacturing of the electronic device of nano wire film
To further introduce below to be used to make and combine according to the electronic device of nano wire film of the present invention and the embodiment of system.These embodiment described here are illustrative and not restrictive.Described as this part, electronic device of the present invention and system can utilize alternate manner manufacturing, and to be those skilled in the art be easy to accomplish from the instruction here for this.
Fig. 5 represents to be provided for making the flow chart 500 of step for example of a plurality of semiconductor device that combine nano wire film of the present invention.The step of Fig. 5 needn't according to shown in order carry out, this is to be easy to accomplish on those skilled in the art instruction basis here.Other structure embodiment also is clearly on following discussion basis to those skilled in the art.These steps will describe in detail below.
For example, in order to realize required working current density,, in nano wire film, can comprise the nano wire of minimum number for given area on the substrate.Therefore, the semiconductor device of each formation will have the nano wire of sufficient amount so that at the working current value loaded current.For example, the nano wire per unit area of requirement can comprise 5,10,100 or more for 1 nano wire, 2 nano wires and any other more substantial nano wire.
In step 504, in nano wire film, limit a plurality of semiconductor device zone.For example, with reference to single semiconductor device 200 shown in Figure 2, the whole nano wire film that forms in step 502 is patterned, thereby for each zone of substrate that is wherein forming semiconductor device, forms localization nano wire film 100.In alternative embodiment, nano wire film needn't be patterned.Notice that on specialized substrates the semiconductor device zone can all limit the same semiconductor device type, perhaps can limit two or more different semiconductor device type.
In step 506, in the semiconductor device zone, form contact (for example electrode) zone, be provided to the electrical connection of a plurality of semiconductor device thus.Any amount of required contact zone that to be electrically connected and to form in order to provide can be provided semiconductor device.For example, diode or other two terminal device can have the anode and the negative electrode of formation.For example, referring again to single semiconductor device 200 shown in Figure 2, form three contacts: source electrode 202, grid 2-4 and drain 206.Other semiconductor device can have the contact zone of more or less quantity of formation.
Should be noted that, in step 506, can form various contact zones type.The contact zone can be ohm and non-ohm.For example, the Schottky diode of non-ohm stops that contact can be used as electrode.When being difficult to make the high-quality gate dielectric, Schottky diode stops that contact is generally used for the III-V semi-conducting material.Source electrode 202, grid 204, drain electrode 206 are formed by electric conducting material such as metal, alloy, silicide polysilicon etc., comprise its combination, as apparent to those skilled in the art.
In some embodiments, the flow chart 500 of Fig. 5 can comprise the step of doped nanowire.Can or form film doped nanowire afterwards before forming film.Can be after being formed on the substrate doped nanowire film.Doped nanowire comprises described those modes with reference to Fig. 3 A-3D in various manners.For example, the core of nano wire can be doped and/or the shell of nano wire can be doped.In addition, independent nano wire and/or nano wire film can differently be mixed in zones of different along their length separately.
In addition, in some embodiments, the flow chart 500 of Fig. 5 can be included in the step that forms dielectric layer on the nano wire.Dielectric layer can form by the oxidation nanometer line or by forming dielectric layer.For example, other non-oxide high dielectric constant material be can use, silicon nitride, Ta comprised
2O
5, TiO
2, ZrO
2, HfO
2, Al
2O
3With other material.The nitrogenize of nano wire can utilize the similar fashion that adopts in the oxidation of nano wire to realize.These materials can be crossed coating mutually or be applicable to nano wire by spin coating suitable precursor on substrate simply by chemical vapor deposition (CVD), solution.Also can adopt other known technology.
The step of Fig. 5 is used in and makes single or multiple semiconductor device on the substrate.Fig. 6 A-6F represented according to each fabrication stage that has the substrate 600 of a plurality of semiconductor device on its of the embodiment of the invention.To mention the step of flow chart shown in Figure 5 500 when relating to technology shown in Fig. 6 A-6F below.
Fig. 6 A represents the perspective view of substrate 600.Substrate 600 can be any substrate type, comprises silicon, glass, quartz, polymer and any other substrate type described here or known.Substrate 600 can be large tracts of land or small size, and can be rigidity or flexibility, as flexiplast or film-substrate type.Substrate 600 can be opaque or transparent, and can be made of conduction, semiconductive or non-conducting material.
Fig. 6 B is illustrated in the composition of a plurality of grids 204 on the substrate 600.Grid 204 can for example use standard photoetching, ink jet printing or miniature contact printing process or come composition by other technology.The composition of a plurality of grids 204 shown in Fig. 6 B for example can carry out during the step 506 of flow chart shown in Figure 5 500.
Fig. 6 C represents the deposit of the dielectric layer 602 on the substrate 600.Dielectric layer 602 is with a plurality of grid 204 electric insulations.Dielectric layer deposited 602 can be used the solution casting of evaporation, polymer or oxidation dielectric and be undertaken by other technology on substrate 600.Notice that if will be deposited on nano wire on the substrate 600 by their dielectric layer insulation, then dielectric layer deposited 602 is not necessarily on substrate 600.For example, the nano wire shown in Fig. 3 C and the 3D 320 and 330 has the lip-deep layer of dielectric material 304 that is pre-formed at them.It is also contemplated that the direct contact devices that does not have dielectric layer.
Fig. 6 D is illustrated in depositing nanowires film 604 on the substrate 600.The deposit of nano wire film 604 can use various operations described here to carry out, and comprises rotary casting, Langmuir-Blodgett aligning, mechanical registeration and fluid technique of alignment.Carry out during the step 502 of flow process 500 that the deposit of the nano wire film 604 shown in Fig. 6 D for example can be shown in Figure 5.
Fig. 6 E represents nano wire film 604 is patterned into a plurality of nano wire films 100.The composition of nano wire film 604 can use various technologies to carry out, and comprises photoetching technique.It should be noted that shown in Fig. 6 D and 6E, the deposit of nano wire film 604 and composition can use various technologies such as ink jet printing or miniature method of contact printing and carry out simultaneously.A plurality of nano wire films 604 are patterned into a plurality of nano wire films 100 shown in Fig. 6 E for example can carry out during the step 504 of flow process shown in Figure 5 500.
Fig. 6 F represents a plurality of source electrodes 202 on the substrate 600 and the composition of a plurality of drain electrode 206, thereby forms a plurality of semiconductor device 200.Source electrode and drain electrode composition can use the technology that is used for a plurality of grids 204 of composition that is similar to shown in Fig. 6 B to carry out.The composition of a plurality of source electrodes shown in Fig. 6 F and drain electrode for example can carry out during the step 506 of flow process shown in Figure 5 500.
It should be noted that the order of grid 204, source electrode 202 and 206 compositions that drain can change.For example, grid 204, source electrode 202 and drain and 206 can carry out composition each other simultaneously or not carry out composition simultaneously.They are composition before or after depositing nanowires film 604 all.Source electrode 202 and drain electrode 206 can be carried out composition before depositing nanowires film 604, and grid 204 can carry out composition after this.Perhaps, grid 204 can carry out composition before depositing nanowires film 604, and source electrode 202 and drain electrode 206 can be at compositions after it.In source electrode 202 and the drain electrode 206 any one also can be before depositing nanowires film 604 composition, and another carries out composition after it.
Be noted that in some embodiments the above nano wire film of one deck can put on the substrate in the given area.Can allow multilayer for bigger conductivity, and multilayer can be used for revising the electrical characteristics of each semiconductor device.Multilayer can be same to each other or different to each other.For example, can in certain semiconductor devices, use the two-layer or more multi-layered nano wire film that has at different directions the nano wire of aiming at, differently mixing and/or differently insulate.The contact zone of certain semiconductor devices can be coupled to multi-layer nano line film any one or more layers.Be noted that if necessary nano wire film can form individual layer nano wire, sub-individual layer nano wire and greater than the nano wire of individual layer.
The grand electronics substrate of large tracts of land nano-material
As mentioned above, electronics and photovoltaic films can use by the nano wire of semiconductive material manufacturing and be formed on grand electronics (that is the large area electron) substrate.In addition, according to the embodiment of the invention, nano wire can be made of other material, and can use these nano wire utilizations mode identical with the nano wire that is made of semi-conducting material to form film.
In an embodiment of the present invention, nano wire can be by constituting as magnetic material, ferroelectric material, thermoelectric material, piezoelectric, metal/alloy and transition metal oxide material.In addition, Dui Ying film can be made of magnetic nanometer, ferroelectric nano-wire, thermoelectric nano-wire, piezoelectric nano line, metal/alloy and transition metal oxide nano line.Therefore these films present the performance to magnetropism, ferroelectric, thermoelectric, metallization or transition metal oxide material, and can be formed on the large tracts of land substrate, wherein this substrate can be flexibility or inflexibility.Therefore, can form new material/device fully according to the present invention.
For example, the nano wire shown in Fig. 3 A 300 can be the nano wire that is made of magnetic, ferroelectric, thermoelectric, piezoelectricity, metallization or transition metal oxide material.In addition, for example, therefore nano wire film 100 shown in Figure 1 can be magnetic nanometer film, ferroelectric nano-wire film, thermoelectric nano-wire film, piezoelectric nano line film, metallization nano wire film or transition metal oxide nano line film or its any combination.
For example, as described herein, the semiconductive nano wire film can be used in the electronic device, semiconductor device 200 as shown in Figure 2.Semiconductor device 200 is three end transistor devices, has source electrode 202, grid 204 and drains 206.As shown in Figure 2, nano wire film 100 is coupled to drain electrode 206 with source electrode 202.Grid 204 is adjacent to form with nano wire film 100.During operation, when enough voltage puts on grid 204, can the drain electrode 206 and source electrode 202 between conduction current.In alternative embodiment, grid 204 needn't exist, and device 200 is as two terminal device work, as diode.For example, in this alternative embodiment, source electrode 202 and drain electrode 206 can be negative electrode and anode.
In an embodiment, when nano wire film 100 was made of one of magnetic, ferroelectric, thermoelectric, piezoelectricity, metallization or transition metal oxide material, the electronic device duration of work that combines this film therein can present the particular nanowire properties of materials.
For example, in an embodiment, when electric current puts on the ferroelectric nano-wire film, in the ferroelectric nano-wire film, may produce the electric polarization of permanent or impermanent type.
In another gives an example embodiment, when electric current puts on piezoelectric nano line film, may in piezoelectric nano line film, produce stress, this can be used as the vibration of alteration of form, motion and/or piezoelectric nano line film and shows.This nano wire film for example can have the application in audio frequency and other technical field.The transition metal oxide material is the typical material that can be used for making the piezoelectric nano line.
In another gave an example embodiment, when electric current put on the thermoelectric nano-wire film, heat can pass the thermoelectric nano-wire film transfer.This thermoelectric nano-wire film can have a lot of application, as in temperature control and heating field, particularly, in the field of wishing space localized heating and/or cooling.
On magnetic nanometer can be coupled to for work and electrically contact.The magnetic nanometer film can form from the teeth outwards, thereby applies magnetic behavior for this surface.The size of this nano wire film can be determined according to application-specific.
Metal nanometer line can form film in the application that needs active conductor.In addition, electronic device such as inductor, transformer and electromagnet etc. can be formed by the metal nanometer line film.
Fig. 7 represents according to the flow chart 700 of the step for example embodiment of the invention, that be provided for making the electronic device that combines nano wire film of the present invention.Other structure embodiment it will be apparent to those skilled in the art that on following explanation basis.These steps will describe in detail below.
In step 704, on substrate, form first and second and electrically contact.For example, first and second to electrically contact can be source electrode 202 and drain electrode 206, as shown in Figure 2.In such an embodiment, grid also can be formed on the substrate.Perhaps, first and second to electrically contact can be negative electrode and anode.In other embodiments, first and second to electrically contact can be other contact type.In addition, can on substrate, form the contact/additional contact of other quantity.
Step 702 and 704 can be carried out according to arbitrary order.Step 702 and 704 effect be at least one nano wire with first electrically contact be coupled to second electrically contact on.Ensuing treatment step can carry out as required, as described herein those, comprise nano wire composition, nano wire doping with make/allow nano wire bonding/be fixed on the substrate and contact with electrically contacting.
With the grand electronic material of the large tracts of land in high mobility conduction electron and hole
In the time can being doped to two kinds of p and n dopant in the semiconductor, as silicon, in same material, exist two types of charge carriers to cause the compound of charge carrier and extinction, cause bad mobility for any charge carrier.Like this, p dopant in semiconductor and n dopant are undesirable by the combination of conventional means.
According to embodiments of the invention, p doped nanowire and n doped nanowire can separately be made, and are deposited on the surface with the homogeneous mixture form, as grand electronic substrate.On macroscopic scale, the material that obtains shows as two kinds of n and the p dopant that contains high concentration.Yet independent carrier type physically separates (that is, they are different nano wires) each other, and the result is, their do not interact basically (that is, charge carrier are not annihilated basically each other).Like this, by producing the mixture of this p and n doped nanowire, are responses that n and p mix as them, can make grand electronic device.For example, comprise that the final nano wire film of n and p doped nanowire can present the characteristic of n and p doped nanowire.
For example, described here or known diode, transistor and other electronic device can manufacture the combination that comprises p doped nanowire and n doped nanowire.For example, semiconductor device 200 shown in Figure 2 can comprise nano wire film 100, and this nano wire film 100 comprises the combination of p doped nanowire and n doped nanowire.N doped nanowire and p doped nanowire can make up in film in various manners.Some modes in these modes are as described below.
For example, Fig. 8 A represents to comprise the close-up view of part for example of nano wire film 800 of the homogeneous mixture of n doped nanowire 802 and p doped nanowire 804.Film 800 can be used in the various electronic device types.Be noted that in the example of Fig. 8 A n doped nanowire 802 and p doped nanowire 804 can form and mix, and perhaps may be mixed in on the substrate before being deposited on the substrate.And, the nano wire random orientation has been shown among Fig. 8 A, the present invention includes partly the use with the nano wire of substantially parallel orientation, as mentioned above.
In another gave an example embodiment, Fig. 8 B represented to comprise the part for example of the nano wire film 810 of n doped nanowire 802 and p doped nanowire 804.For example, film 810 can be formed on the substrate.Shown in Fig. 8 B, the first area of film 810 comprises a plurality of n doped nanowire 802, and the second area 814 of film 810 comprises a plurality of p doped nanowire 804.In the example of Fig. 8 B, first area 812 and second area 814 are non-overlapped basically.Like this, shown in the example of Fig. 8 B, n doped nanowire 802 and p doped nanowire 804 can utilize on the space or the zone on separate mode, basically or even all be deposited on the substrate discretely.N doped nanowire and p doped nanowire on can the space or regional ground in any structure, separate, be included in the lightning strip that forms n doped nanowire and p doped nanowire on the substrate, spot etc.
In another gave an example embodiment, Fig. 8 C represented to comprise the nano wire film 820 of n doped nanowire 802 and p doped nanowire 804.Shown in Fig. 8 C, first sublayer 822 of film 820 comprises a plurality of n doped nanowire 802, and second sublayer 824 of film 820 comprises a plurality of p doped nanowire 804.Like this, shown in the example of Fig. 8 C, n doped nanowire 802 and p doped nanowire 804 can be deposited on the substrate with the form of two or more separating layers.
In an embodiment of the present invention, in any combination, n doped nanowire 802 can mix in one deck with p doped nanowire 804, regional separate and/or be divided into separating layer.
Fig. 9 represents to provide the flow chart 900 of step for example that is used to make nano wire film of the present invention according to the embodiment of the invention.The step of Fig. 9 needn't according to shown in order carry out, this is conspicuous on the instruction basis here for those skilled in the art.On following discussion basis, other structure embodiment also is conspicuous to those skilled in the art.These steps will describe in detail below.
In step 904, form more than second nano wire that n mixes.For example, more than second nano wire is n doped nanowire 802, shown in Fig. 8 A-8C.The n doped nanowire can form according to any way, as described herein or known.For example, the n doping intrinsic nano wire that the n doped nanowire can be used as is afterwards grown, and perhaps can grow from the n doped semiconductor materials.In addition, the n doped nanowire can all be to be made of same semiconductor material (for example, all being the n doped silicon), perhaps can be the nano wire (that is, some n doped silicon nano wire and n doping CdS nano wire) that is made of different semi-conducting materials.
In step 906, more than first nano wire and more than second nano wire are deposited on the substrate, comprise that n mixes and the nano wire film of p doped nanowire thereby form.For example, in an embodiment, more than first and second nano wire can separate or deposit simultaneously.More than first and second nano wire can mix the single or multilayer homogeneous mixture of formation.Perhaps, more than first and second nano wire can be deposited on two or more separated regions of substrate, and/or is deposited in two or more separation sublayers of film.
In an embodiment, when n doped nanowire and p doped nanowire were in the separating layer, flow process 900 can comprise the steps: wherein to form another layer material between n doped nanowire layer and p doped nanowire layer.For example, the intermediate layer can be an insulating barrier, as plastic layer, glassy layer, air layer or other insulating barrier type.
Like this, semiconductor device/material can form and have p doping and n doping characteristic.In an embodiment, this device/material can be regarded as has n and p characteristic on the length dimension greater than coefficient X, and wherein X depends on nanowire size, nanowire density and/or other factors.Before the present invention, this device/material does not exist.
Grand electronic device with the nano wire hetero structure manufacturing
In another embodiment of the present invention, can make electronic device such as p-n diode, transistor and other electronic device type with nano wire hetero structure.As described herein, nano wire hetero structure is the nano wire that generally includes along a plurality of p-n junctions of nanowire length.In other words, nano wire hetero structure comprises along the alternating segments or the section of their different length.For example, nano wire hetero structure can have differently the alternating segments that mixes and/or be made of different materials.
By the nano wire that formation has different piece, can simplify the manufacturing of semiconductor device greatly.For example, in the embodiment of these parts of differently mixing, because the nano wire that mixed, therefore needn't use expensive photoetching or the ion implantation technology fixedly zone of the substrate of nano wire of mixing on it, as routine.In addition, compare, can improve ohmic contact with substrate by the nano wire that use to mix with the intrinsic nano wire.In addition, compare with conventional nano wire, nano wire hetero structure needn't be arranged on the substrate carefully, because they are longer than the distance between electrodes on the substrate usually.Therefore, with respect to conventional nano wire, major part will be crossed over distance between electrodes in them, therefore contact with electrode.
Have among the embodiment of different materials in described part, a lot of application all are feasible.For example, nano wire hetero structure can comprise the first heavy p doped silicon part, second heavy n Doped GaN part and the triple n doped silicon parts.This will be used to be simplified to the electrical connection of GaN LED.Can in nano wire hetero structure, adopt any other combination of doping and material.
In first embodiment, the grow nanowire heterostructure is so that have a plurality of p-n junctions along their length.(notice that following discussion will be applicable to other difference along nanowire length, comprise different materials etc.In order to represent purpose, discuss mainly concentrating on the different doped portions.) for example, Figure 10 represent to give an example nano wire 1000 of embodiment as nano wire hetero structure according to the present invention.As shown in figure 10, nano wire 1000 has a plurality of n doped portion 1010a, b and a plurality of p doped portion 1020a, b.Therefore, a plurality of p-n junction 1030a, b, c are present on the intersection area of p doped portion 1010 and n doped portion 1020.In addition, each doped portion of nano wire 1000 has length 1002.
In an embodiment, the length of the doped portion of nano wire 1000 can be uniform or uneven.Preferably, the doped portion of nano wire hetero structure of the present invention has the length (that is, in other words, p-n junction is isolated) that approximates the distance between electrodes in the resulting devices greatly, will use nano wire hetero structure in resulting devices.For example, in an embodiment, the length of doped portion can equal distance between electrodes, perhaps less times greater than distance between electrodes.In this way, when being deposited to nano wire hetero structure on the substrate, fifty-fifty, a p-n junction of each nano wire hetero structure will be between the electrode of resulting devices, and each nano wire hetero structure can be crossed over distance between electrodes.In addition, because the quantity of the doped portion in each nano wire, the total length of each nano wire hetero structure will be tending towards being far longer than distance between electrodes.These attributes will produce effective p-n diode between each electrode pair, produce red electronic device.In addition, make restriction by using nano wire hetero structure to reduce, because nano wire hetero structure can be deposited on the substrate with required very little precision, and even deposit at random.The repetitive structure of nano wire hetero structure allows enough p-n junctions of the nano wire hetero structure of deposit at random will be between electrically contacting on statistics, thereby makes exercisable device.This manufacturing advantage of nano wire hetero structure will further specify below.
Use nano wire hetero structure, can make macroscopical heterostructure electronic device.For example, Figure 11 A represents the two ends electronic device 1100 for example according to comprising of the embodiment of the invention of a plurality of nano wires 1000.Shown in Figure 11 A, according to non-aligned mode nano wire 1000a-e is deposited on first and electrically contacts on 1102 and second electrically contact on 1104.For example, device 1100 can be a diode, and first and second to electrically contact 1102 and 1104 can be negative electrode and anode.As shown in the embodiment of Figure 11 A, first electrically contacts 1102 and second distance that electrically contacts between 1104 is substantially equal to length 1002 (for example, between center to center or the inward flange), and this is the length of the doped portion of nano wire 1000a-e.In addition, the overall length of nano wire 1000a-e electrically contacts 1102 and second distance that electrically contacts between 1104 greater than first.Shown in Figure 11 A, nano wire 1000c, 1000d and 1000e do not electrically contact 1102 and 1104 with first and second and are coupled.Yet because their position, nano wire 1000a and 1000b electrically contact 1102 and 1104 with first and second and are coupled.In addition, nano wire 1000a and 1000b have each p-n junction that electrically contacts between 1102 and 1104 first and second.Like this, device 1100 can be used as the diode operation that constitutes as Figure 11 A.
It should be noted, in the example of Figure 11 A, the p-n junction 1030a of nano wire 1000a and 1000b and 1030b sensing opposite each other respectively.In other words, the n doped portion of nano wire 1000a electrically contacts 1102 with the p doped portion of nano wire 1000b and first and contacts, and the p doped portion of nano wire 1000a electrically contacts 1104 with the n doped portion of nano wire 1000b and second and contacts.Like this, the p-n junction 1030a of nano wire 1000a and 1000b and 1030b are respectively conduction and non-conductive on opposite directions.This set of nano wire 1000a and 1000b may for example take place during being deposited to nano wire hetero structure on the substrate at random.Yet in some applications, first and second electrically contact 1102 and 1104 will have certain voltage, and this voltage is applied to and only allows electric current to flow in a direction, only allow one of the p-n junction 1030a of nano wire 1000a and 1000b and 1030b work respectively.For example, nano wire 1000a and 1000b can be Illuminant nanometer line (as further specifying below).Like this, put on first when electrically contacting 1102 when sufficiently high voltage electrically contacts 1104 with respect to second, the p-n junction 1030b of nano wire 1000b will conduct electricity and be luminous.When electrically contacting 1102 when removing high voltage from first, any one is not luminous among nano wire 1000a and the 1000b.Like this, in this application, having at the extra nano wire hetero structure with current opposite in direction direction orientation can not influence work.Yet present embodiment produces novel light-emitting diode, even it is also luminous when reverse bias (, when p-n junction 1030a forward bias and p-n junction 1030b are not luminous).Yet, in other is used, do not wish to have the p-n junction of the nano wire hetero structure of reverse direction.Like this, in these are used, wish to utilize the mode depositing nanowires of the p-n junction that reverse direction does not take place.
For example, in another embodiment, nano wire 1000 can be aimed at relative to one another and with respect to the predetermined electrode figure, makes their p-n junction 1000 aim at.For example, this can realize by patterned substrate chemically, thereby 1000 of nano wires are bonding or be fixed to and limit on the position.In addition, this can otherwise realize.
Utilize and the similar mode of manufacturing two terminal device, can form more complex devices by making nano wire hetero structure, as p-n-p or n-p-n bipolar transistor, wherein said nano wire hetero structure has according to the isolated p-n-p repeated segments of cycle that equals the distance between source electrode and the drain electrode.In one embodiment, have the device of an above interface, wish that when nano wire hetero structure had the built-in cycle of the distance between electrodes of being substantially equal to, the total length of the device in each cycle was very little with respect to full span for each device.This will help to reduce the quantity of nano wire, and these nano wires only utilize in half p-n-p section of every end rather than in the whole p-n-p section at middle part and come gap between the bridged electrodes.
For example, Figure 11 B represents to combine nano wire hetero structure and has the p-n-p transistor 1150 of the drain electrode 1152, grid 1154 and the source electrode 1156 that separate according to the distance that equals length 1002 (for example, this distance is the Center-to-Center distance of adjacent contact/electrode usually).Shown in Figure 11 B, p-n junction be present in the drain electrode 1152 and grid 1154 between each nano wire 1000a-c in.In one embodiment, for example, grid 1154 can be separated by medium/insulating barrier (not shown among Figure 11 B) with nano wire 1000a-c.Like this, by at electrode 1152,1154 and 1156 top electrode nano wire hetero structures, can form p-n-p transistor 1150.
Use nano wire hetero structure, can form the electronic device of any kind in fact with any material.For example, use the nano wire hetero structure that is formed by any material can make device, wherein said material comprises electronics, semiconductive, optics, photoelectricity, piezoelectricity, thermoelectricity, ferroelectric and other material.
As mentioned above, can the grow nanowire heterostructure.Perhaps, can use photoetching, ion injection or other doping process to make the different doped regions of nano wire hetero structure, thereby form macroscopical p-n junction.In an embodiment, be accompanied by the manufacturing of these electrodes, this technology can be used as the part of composition technology and carries out.
Notice that in an embodiment, nano wire hetero structure can have two or more different dopant type.For example, nano wire 1000 has two repeated dopant agent type part: n doping and p doped portion (that is, repeating n:p doping figure).In addition, nano wire hetero structure can be the repeated dopant agent type part of other quantity, comprising: p:n:p, n:p:n, p:i:p, n:i:n, p
+: p:n, n
+: p:p, p
+: n:p, n
+: p:n and any other repetitive pattern.
Figure 12 represents the flow chart 1200 of step for example that is provided for making the electronic device that combines nano wire hetero structure according to the embodiment of the invention.The step of Figure 12 needn't according to shown in order carry out, as what be easy to expect on those skilled in the art instruction basis here.Other structure embodiment also is clearly on following discussion basis to those skilled in the art.These steps will describe in detail below.
In step 1204, formation is a pair of on substrate electrically contacts, and the distance between wherein electrically contacting is substantially equal to first distance.For example, in an embodiment, electrically contacting is first and second to electrically contact 1102 and 1104, shown in Figure 11 A.Shown in Figure 11 A, first and second distances that electrically contact between 1102 and 1104 are substantially equal to length 1002.Perhaps, in an embodiment, a pair of to electrically contact be drain electrode 1152 and grid 1154 shown in Figure 11 B.
In step 1206, a plurality of nano wires are deposited on the substrate, wherein at least one nano wire of a plurality of nano wires with first electrically contact be coupled to second electrically contact on.For example, shown in Figure 11 A, a plurality of nano wire 1000a-e are deposited on the substrate.Shown in Figure 11 B, a plurality of nano wire 1000a-c are deposited on the substrate.Can utilize described here or known any way is deposited to a plurality of nano wires on the substrate.Then can according to any fixed form with a plurality of nano wires be fixed to electrically contact on.
Use the light-emitting film of the red electronics of nano wire
In an embodiment, nano wire by fluorescence semiconductor material, phosphorescence, electroluminescence, cathodoluminescence or other luminescent material manufacturing can be deposited on glass, plastics or other substrate types, thus the light of permission low cost, large area light emitting, emission white light or any other color.For example, be used for this purpose, the aligning individual layer of semiconductive nano wire can be formed on the substrate.These nano wires can be by the fluorescent material manufacturing, as CdSe, GaN, InP or any other tradition or non-traditional electroluminescence semi-conducting material.
Yet, in order to form light-emitting diode (LED), must be in each nano wire, between each electrode pair, have p-n junction.Inject each nano wire that mixes on a macro scale if for example must use the back to make ion, then manufacturing is very difficult and costliness.
Like this, according to the present invention, can according on regard to the described mode of nano wire hetero structure and nano wire formed/grow into and in them, have p-n junction.As mentioned above, each nano wire can form and have one or more p-n junctions.P-n junction is preferably with spaced apart with the roughly the same distance of interelectrode distance, and wherein they will be fixed on the described electrode in final demonstration/illuminating device.Like this, as mentioned above, when a large amount of nano wire hetero structures were deposited on the substrate, the p-n junction that will have between electrode distributed, but neither one p or n doped region will be crossed over the whole distance between the electrode.Fifty-fifty, each nano wire will be crossed over whole gap or the distance between the electrode, and will have a p-n junction between electrode.This produces effective LED in each nano wire, wherein p-n orientation only correct biased direction for grand electronics LED.By the array of composition anode and negative electrode, perhaps source/drain, this can be on very big area, carry out on flexible substrate, if desired.Should be noted that, if special scheme of the present invention is: if depositing nanowires, make that the position of end is at random, then roughly half the nano wire on the particular surface will have the p-n junction in proper orientation, therefore will produce light when specific direction applies biasing, second half will be not luminous simultaneously.When in the opposite direction setovering, for the different piece of nano wire, play the role and be inverted, make that the second half parts of nano wire are luminous, and the first half parts are not luminous.Like this, this technology has realized bipolar LED.By using aforesaid part end alignment, use the present invention also can make traditional one pole LED.
Depend on the type of material of making nano wire and the diameter of nano wire at least in part by the color of the light of nano wire emission or wavelength.In an embodiment, be used for the nano wire that uses at demonstration/illuminating device, can make monochromatic source by using single kind nano-material and nanowire diameter.In another embodiment, by using mixture, can make polychromatic source by the nano wire different materials manufacturing and/or that have different-diameter.For example, if in this mixture, comprise red, blue and green nano wire, then can make white light source.
Illuminant nanometer line film of the present invention allows higher-quality colour purity light emission and allows to be better than the improved color index of conventional optical transmitting set.In an embodiment of the present invention, for these factors of Illuminant nanometer line film OLED base type far above the film light reflector, this is because mix the ability of a lot of pure colors.
Quantum limit effect in the nano wire can advantageously adopt, so that control the emission wavelength of electroluminescence nano wire as the function of diameter, keeps the same material component simultaneously.This can be used to simplify and being electrically connected of this hybrid films, because the component of each light-emitting component in the hybrid films is identical.
It should be noted that the electrode of Illuminant nanometer line heterostructure can be arranged to any figure, as desirable for display or lighting figure.For example, Figure 13 A represents that they have pair of electrodes according to the discrete pixel of the embodiment of the invention or light source 1300, and promptly first electrically contacts 1302 and second and electrically contact 1304.First and second to electrically contact 1302 and 1304 can be anode and the negative electrode of LED, perhaps can be the pair of electrodes of lighting transistor.A plurality of Illuminant nanometer line 1310a-e also are present in the light source 1300.And it is that the nano wire 1000 of Figure 10 mixes in the same manner and be coupling in first and second by the Illuminant nanometer line 1310a-e of luminescent material manufacturing and electrically contact between 1302 and 1304.When enough voltage electrically contacts 1304 and put on first when electrically contacting 1302, the p-n junction 1320 emission light of each Illuminant nanometer line 1310a-e with respect to second.Although the nano wire 1310a-e that aims at has been shown in Figure 13 A, in alternative embodiment, nano wire 1310 needn't be aimed at, for example can random distribution.
In another gave an example embodiment, Figure 13 B represented respectively to be similar to a discrete pixel of row or a light source 1300a-c of pixel or light source 1300.Utilize same way as, any amount of pixel or light source 1300 can be arranged to row, column or be arranged to two-dimensional array, thereby are used in the display that for example has big quantity/a plurality of pixels.It should be noted that shown in Figure 13 B, if desired, light source 1300a-c can have public second and electrically contact 1304, and can electrically contact 1302a-c by first respectively and control independently.Perhaps, independently second to electrically contact also be feasible.
In another gave an example embodiment, Figure 13 C represented the large tracts of land light source 1320 according to the embodiment of the invention, and it comprises a plurality of light source row 1350.Light source 1320 comprises that elongated first and second electrically contact 1324 and 1326, and they are arranged to shine the p-n junction among the multiple row 1350a-c (or row), thereby the illumination on the large tracts of land is provided.First and second electrically contact 1324 and 1326 can have any length, can have any amount of bending and/or track " finger piece ", and interlocking in can and/or going at any amount of row, so that allow the nano wire bridge joint they, thereby providing light (and/or other diode functions) on the large tracts of land relatively.
It should be noted, can be for the interval between the best electrical property selection electrode.The length of electrode can be long arbitrarily, thereby make the quantity of total fluorescence/illumination output maximum and the required treatment step of minimizing.
In another embodiment, nano wire 1310 can relative to each other and with respect to predetermined electrode be aimed at, thereby their p-n junction 1320 is aimed at.For example, this can realize by patterned substrate chemically, thereby makes 1310 of nano wires bonding or be fixed to and limit on the position.This can make more effective luminescent device, and produces less statistical variation between the light source device that forms.Perhaps, nano wire 1310 deposit randomly or isotropically orientation.In such embodiments, few relatively effective luminescent device (for example, nano wire 1310 still less can be coupled on the electrode, can not operate thus) can be produced, and many relatively statistics variations can be between the light source device that forms, produced.
In addition, light source can comprise nano wire 1310, sub-individual layer nano wire 1310 or the multi-layer nano line 1310 in the film of the individual layer (that is nano wire thick-layer) that is formed on as nano wire 1310.
In addition, can make luminescent film and need in nano wire, not make p-n junction.This can realize by back deposit photoetching and injection or by making Schottky diode at semiconductor-electrode interface place.
Figure 14 represents to provide and is provided for making the flow chart 1400 of step for example in conjunction with the luminescent device of Illuminant nanometer line heterostructure according to the embodiment of the invention.The step of Figure 14 needn't according to shown in the order carry out, as what be readily appreciated that on those skilled in the art instruction basis here.Other structure embodiment also is that those skilled in the art are readily appreciated that on following discussion basis.These steps will describe in detail below.
It should be noted that some material is luminous under nano-scale, although this material is not luminous when large scale more.These materials are suitable for use in the Illuminant nanometer line.For example, some semiconductor material body is not luminous, but the nano-scale particle of same material is luminous.This comprises silicon, the normally non-luminous semiconductor of silicon, but beginning is luminous below certain critical dimension.These light-emitting semiconducting material types any all applicable to the present invention.
Should be noted that flow process 1400 can randomly comprise the step of selecting nanowire diameter.
In step 1404, form a plurality of nano wires by at least a light-emitting semiconducting material of selecting.For example, a plurality of nano wires are nano wire 1310a-e, as shown in FIG. 13A.Notice,, can make any amount of Illuminant nanometer line, comprise 10s, 100s, 1000s, millions of quantity and other quantity for specific operation.In an embodiment, notice that step 1404 can comprise the step of the one or more nano wires that form a plurality of nano wires with selected diameter.
In step 1406, each nano wire that mixes makes each nano wire comprise at least one p-n junction.In an embodiment, each nano wire is doped to and has a plurality of alternately n and p doped portions.For example, utilize and identical mode doped nanowire shown in nano wire 1000 shown in Figure 10 and the nano wire 1310a-e shown in Figure 13 A.Nano wire can be doped to has any amount of alternately n and p doped portion.
It should be noted that in an embodiment, step 1404 and 1406 is carried out simultaneously, wherein when grow nanowire, in nano wire, form n and p doped region.Perhaps, step 1404 and 1406 can separately be carried out.In addition, in an embodiment, each nano wire forms the distance between the continuous knot with the alternating-doping part that is substantially equal to first distance.
In step 1408, a plurality of nano wires are deposited on the substrate.For example, a plurality of nano wires are deposited on the substrate, shown in Figure 13 A-13C.This nano wire can carry out deposit according to any way, and can be deposited to described here or known any substrate type on.Substrate can be a virtually any size, comprise little or big, as the grand electronic substrate of large tracts of land.In an embodiment, substrate has formation first and second electrically contacting thereon.In an embodiment, at least one nano wire of a plurality of nano wires with first electrically contact be coupled to second electrically contact on.In addition, electrically contacting can be spaced apart with the distance between the p-n junction in the nano wire.
Should be noted that, in alternative embodiment, nano wire is deposited on the substrate for luminous semiconductor device, it with first electrically contact be coupled to second electrically contact on.First and second at least one that electrically contact are Metal Contact.At the luminescent device duration of work, because Schottky effect, utilize the mode identical with the Schottky diode working method, light is penetrated from binding up one's hair of electrically contacting of nano wire and metal.In such an embodiment, the nano wire that is used in this device needs not to be nano wire hetero structure, if desired, can be the nano wire of even doping/non-doping.
Nano wire solution fluid mask embodiment
As mentioned above, a lot of electronics and other types of devices can the combining nano lines.In this subdivision, need a kind of technology of accurately locating nano wire.
Under the large scale manufacturing environment, for the device of a large amount of manufacturings, needing a kind of nano wire that technology is set.For example, for each device of making, nano wire must be arranged on the surface of device and electrically contact so that make on demand.Yet these devices must utilize commerce/economic practice mode to make.Nano wire must accurately be located, and is placed on the surface with enough number/density.In some cases, nano wire must be placed to aligned with each other.Like this, wish the technology of placing nano wire according to these manufacturing demands according to commerce/economic practice mode.
In addition, under the quality control environment, after making nano wire, wish the nano wire of some manufacturings of test.For example, wish whether fully conduction of test nano wire, thereby measure the impedance of nano wire and/or other electricity/mechanical attributes of measurement nano wire.Like this, wish to utilize the business practice mode with surface that test electrode contacts on place nano wire.
According to the present invention, the nano wire in the solution flows from the teeth outwards.Nano wire solution flows on this surface in such a way: one or more nano wires of solution keep or bond on the surface.Remove the nano wire flow of solution then, and one or more nano wire stays on this surface, thereby form one or more electric contacts and/or other connection type.
In one embodiment, use the fluid mask that the nanometer linear flow is directed on the indicating section on surface.The fluid mask allows on the indicating section on surface nano wire to be set thus.In an embodiment, use the fluid mask, nano wire is set aligned with each otherly.In other embodiments, do not utilize the fluid mask to place nano wire.
In an embodiment, the present invention allows to utilize the low probability of little parallel circuit that nano wire is set.In other words, the present invention allows with desirable density depositing nanowires, thereby forms electrical connection by a nano wire, if desired.In addition, provide device, these devices also can be implemented in the line in wet-chemical and the dried environment and the quick measurement of contact resistance.
This part has introduced fluid technique example and the fluid mask embodiment that is used for being provided with from the teeth outwards nano wire.For in electronic device, in the electrical testing structure and the use in any other device or system, nano wire can be by the fluid mask alignment on semiconductor wafer, electronic substrate or any other surface.Provide specific embodiment described here this be purpose in order to represent, and do not provide constraints.Be easy to realize on the basis of instruction here for those skilled in the art about other embodiment of fluid mask.These alternative embodiments all are in the scope and spirit of the present invention.
Figure 15 A and 15B represent the bottom and the profile of fluid mask 1500 for example according to the embodiment of the invention.Shown in Figure 15 A and 15B, fluid mask 1500 comprises main body 1502.Main body 1502 comprises input port 1510 and output port 1520.The first surface 1504 of main body 1502 constitutes with the target surface and matches.For example, the target surface can be the surface of wafer, the surface of substrate, as macroscopical electronic substrate, or the surface of any other structure.For example, the target surface can be the surface with semiconductor wafer of formation integrated circuit (IC) array thereon.Fluid mask 1500 is applicable to semiconductor wafer surface, thereby locatees nano wire on any or all integrated circuit.The size of fluid mask 1500 can cover entire wafer, perhaps covers its any part.
Shown in Figure 15 A, first surface 1504 has a plurality of raceway groove 1506a-1506e that are formed on wherein.Raceway groove 1506 can be parallel to each other basically, and shown in Figure 15 A, perhaps they can form on one or more different directions, and are desirable as the deposit for nano wire.Shown in Figure 15 A, first surface 1504 also has first and second feeder raceway groove 1530a and the 1530b that are formed on wherein.。The first feeder raceway groove 1530a is the input feeder raceway groove that is coupling between first end of input port 1510 and raceway groove 1506.The second feeder raceway groove 1530b is coupling in second end of raceway groove 1506 and the output feeder raceway groove between the output port 1520.The first and second feeder raceway groove 1530a and 1530b randomly exist.In addition, when existing, the first and second feeder raceway groove 1530a and 1530b can be exposed to that first surface 1504 (shown in Figure 15 A) is gone up or can be in the inside of fluid mask 1500.In not having one or two the embodiment of the first and second feeder raceway groove 1530a and 1530b, each raceway groove 1506 can be directly coupled to input port 1510 and/or output port 1520.Perhaps, each raceway groove can have input port 1510 and/or output port 1520.
Shown in Figure 15 A and 15B, input port 1510 is coupled to first end of raceway groove 1506a-e by the first feeder raceway groove 1530a, and second port one 520 is coupled to second end of raceway groove 1506a-e by the second feeder raceway groove 1530b.Input port 1510 is formed in the main body 1502, so that carry the nanometer linear flow for raceway groove 1506a-e.Output port 1520 is formed in the main body 1502, so that remove the nanometer linear flow from raceway groove 1506a-e.Like this, the nanometer linear flow is introduced to the input port 1510 of main body 1502, and flows through the first feeder raceway groove 1530a.The first feeder raceway groove 1530a looses the nano wire flow point to raceway groove 1506a-e.The second feeder raceway groove 1530b collects the nanometer linear flow from raceway groove 1506a-e.The nanometer linear flow flows to output port 1520 from the second feeder raceway groove 1530b, removes the nanometer linear flow from fluid mask 1500 there.When first surface 1504 matched with the target surface, each raceway groove 1506a-e covered the part on target surface.In first surface 1504, form raceway groove 1506a-e, thereby allow the nano wire of nanometer linear flow to be arranged on the part on the target surface that is covered by raceway groove 1506a-e.
The length of raceway groove 1506, width and/or the degree of depth can be selected so that control the nanometer linear flow, and optimization/the be controlled at placement and the orientation of the lip-deep nano wire of target.These parameters can be to the length-specific/width optimization of nanometer linear flow.In addition, these parameters can be for the lip-deep special target conductive path optimization of target.For example, fluid mask 1500 can have the raceway groove of any width, be included in several, tens, the width of hundreds of and several thousand microns.For example, for the long nano wire of 15 μ m, channel width can comprise 100 μ m, 500 μ m, 700 μ m and other width raceway groove therebetween etc. in the 1-1000 mu m range.In addition, raceway groove 1506 can comprise a plurality of channel segments that the conduit (that is pipe or the tunnel in the fluid mask 1500) that extend into fluid mask 1500 inside separates.In this way, raceway groove 1506 can be arranged on nano wire on the zone discrete, that separate on target surface along raceway groove 1506.
According to embodiments of the invention, various systems can be used to locate nano wire in conjunction with fluid mask 1500.For example, Figure 16 represents according to the nano wire navigation system 1600 that combines fluid mask 1500 of embodiment for example of the present invention.As shown in figure 16, system 1600 comprises fluid mask 1500, target surface 1602, nano wire source of solvent 1604 and nano wire solution container 1606.In addition, as shown in figure 16, nano wire source of solvent 1604 contains nano wire solution 1650.Nano wire solution 1650 normally contains the liquid solution of a plurality of nano wires.The composition of nano wire solution 1650 can be selected to transmit nano wires by fluid mask 1500 to target surface 1602 from nano wire stream so that help.
As shown in figure 16, the first surface 1504 of fluid mask 1500 cooperates with target surface 1602.Fluid mask 1500 constitutes with target surface 1602 and cooperates, so that form leak-tight seal basically betwixt.Like this, when flowing through, nano wire solution 1650 will be comprised in the shell that is formed between fluid mask 1500 and the target surface 1602 basically.In an embodiment, the first surface 1504 of fluid mask 1500 is (when existing, not the comprising raceway groove 1506 and feeder raceway groove 1530) on smooth or plane basically, so that match with smooth or flat target surperficial 1602, thereby forms sealing.Yet in alternative embodiment, the profile of first surface 1504 can match with target surface 1602.In addition, fluid mask 1500 and target surface 1602 can have interlocking sheet and groove, thereby allow their cooperation/alignings suitably each other.Fluid mask 1500 and target surface 1602 be optics and/or cooperation/aligning mechanically alternately.Encapsulant can be used between fluid mask 1500 and the target surface 1605, so that help to keep sealing, although do not need this encapsulant in all are used.
Nano wire source of solvent 1604 is coupled to the input port 1510 of fluid mask 1500, and nano wire source of solvent 1604 is carried nano wire solution 1650 to input port 1510, thereby by fluid mask 1500, pass target surface 1602 and carry the nanometer linear flows.Nano wire solution container 1606 is coupled to the output port 1520 of fluid mask 1500, thereby receives and remove the nanometer linear flow from fluid mask 1500, and in an embodiment, can store the nano wire solution 1650 that receives.In an embodiment, nano wire source of solvent 1604 can be by the pressurized stream of fluid mask 1500 conveying nano wires.In addition, in an embodiment, nano wire source of solvent 1604 can accurately be controlled the flow velocity of nano wire solution 1650 by fluid mask 1500.
Figure 17 A and 17B represent the to give an example plane graph and the profile of the nanometer linear flow 1702 that flows through fluid mask 1500 of embodiment according to the present invention.Direction/path of flowing through the stream 1702 of fluid mask 1500 is generally represented with arrow.In addition, some nano wires of additional arrows 1710 expression nanometer linear flows 1702 leave nano wire solution 1650 and are positioned on the target surface 1602.In an embodiment, nano wire is positioned on the target surface 1602 by raceway groove 1506 according to the orientation of the direction that is arranged essentially parallel to stream 1702.
The plane graph (only showing the raceway groove position of fluid mask 1500 among Figure 18 A) of semiconductor wafer 1800 for example that Figure 18 A represents to cooperate with fluid mask 1500.The position with respect to wafer 1800 of the raceway groove 1506a-e of fluid mask 1500 is illustrated by the broken lines.Each raceway groove 1506a-e is arranged to a corresponding part 1802a-e of cover wafers 1800.
Figure 18 B represents because work of the present invention and at the lip-deep nano wire region 1810a-e (that is nano wire deposit district) of the wafer 1800 with nano wire disposed thereon.
Figure 18 C represents to form the further detail view of wafer 1800 examples of position of the array of integrated circuit 1820a-n thereon.Integrated circuit 1820 can be any integrated circuit type and virtually any size, comprises 0.5cm
2Shown in Figure 18 C, the part of each integrated circuit 1820a-n is covered by the part of one of nanowire region 1810a-e.Like this, nano wire is arranged on the part of each integrated circuit 1820a-n by fluid mask of the present invention.For example, integrated circuit can respectively comprise a plurality of conductive traces.The nano wire of nanowire region 1810a-e forms one or more connections between the conductive trace of each integrated circuit 1820.
For example, Figure 19 A represents it can is the integrated circuit 1900 of example of one of integrated circuit 1820.Shown in Figure 19 A, the part 1802 of integrated circuit 1900 is covered by the raceway groove of fluid mask.Figure 19 B represents the close-up view of the part 1920 of integrated circuit 1900, the detail view of the example of expression conductive trace 1902.Figure 19 C is illustrated in the schematic diagram that is operated in the part 1920 after the depositing nanowires 1910 in the nanowire region 1810 by fluid mask 1500.Shown in Figure 19 C, after fluid mask 1500 work, nano wire 1910 is arranged in to form between each trace of conductive trace 1902 and is electrically connected.For example, shown in Figure 19 C, the trace that nano wire 1910a forms earth signal trace 1904 refer to and trace finger piece 1956 between connection.
It should be noted that the density that is deposited on integrated circuit or other lip-deep nano wire 1910 can be controlled in various manners, comprising: change flow velocity by the nano wire of fluid mask 1500; Select the density of the nano wire in the nano wire solution 1650; The composition of control nano wire solution 1650 (for example, selecting alkaline solution type etc.); Selection applies the time span of nanometer linear flow etc.Can control the density of nano wire 1910 thus, thereby the control of statistics ground will allow how many nano wires 1910 to form each connection on integrated circuit 1900.In addition, the width of the thickness of the interval between the electrode, electrode, raceway groove 41506 etc. can be used for control and will allow 1910 each connection of formation of how many nano wires.
In addition, notice and utilize fluid mask 1500 that nano wire 1910 is deposited on the substrate before or after being formed on the substrate at the figure of integrated circuit 1900.For example, if depositing nanowires 1910 at first, then then at the trace that forms integrated circuit 1900 on the substrate, on nano wire 1910.
Figure 20 A represents to relate to the curve 2000 of Figure 19 A-C.Curve 2000 expressions are according to the various probability that relate to the electrical connection that forms integrated circuit 1900 of the present invention.The Y-axis of curve 2000 is represented probability, and the X-axis of curve 2000 is represented the quantity (l/ μ m) of the nano wire on every length.The example of curve 2000 relates to the nano wire of the length example of the 15 μ m that put on integrated circuit 1900 in the nano wire depositing region, and wherein said integrated circuit 1900 has the trace interval of 12 μ m.The probability of line 2002 expression open circuits.Line 2004 is illustrated in the probability that forms the single nano wire of conductive path between the conductive trace.Line 2006 is illustrated in the probability that forms the more than one nano wire of conductive path between the conductive trace.Shown in the line among Figure 20 A 2004, trace interval for 12 μ m, and nano wire with average length of 15 μ m, for the maximum probability of the single nano wire that forms the conductive path between the conductive trace about 0.35, in the scope of the 0.3-0.4 nano wire/length that applies nano wire solution, wherein:
Density (the l/ μ m of the nano wire in nano wire/length (1 μ m)=nano wire solution
2) * electrically contact width (μ m).
Figure 19 D represents the integrated circuit 1950 of another example, and it can be the example of integrated circuit 1820.Shown in Figure 19 D, the part 1802 of integrated circuit 1950 is covered by the raceway groove of fluid mask.Figure 19 E represents the close-up view of the part 1960 of integrated circuit 1950.Figure 19 F represents the schematic diagram by operating fluid mask 1500 part 1960 after the depositing nanowires 1910 in nanowire region 1810.Shown in Figure 19 F, after fluid mask 1500 work, nano wire 1910 is set, be electrically connected thereby between each trace of the conductive trace 1952 of integrated circuit 1950, form.For example, nano wire 1910a formation trace refers to the connection between 1954 and 1956.
Figure 20 B representation class is similar to the curve that relates to Figure 19 D-19F 2050 of curve 2000.The probability of the line 2052 expressions formation single nano wire of the conductive path between conductive trace/electrode.Line 2054 is illustrated in the above probability of a nano wire that forms conductive path between the conductive trace.Shown in the line among Figure 20 B 2052, trace interval for 4 μ m, with the nano wire of the average length with 15 μ m, the maximum probability of the single nano wire of the conductive path between the formation conductive trace is about 0.06, on the about 0.05 nano wire/length of the nano wire solution that applies.Electrically contact at interval by change, nanowire length and/or other parameter can change the probability shown in Figure 20 A and the 20B, and for the special applications optimization.
Notice that for example, for being used in the final products, said integrated circuit can be the integrated circuit (IC)-components of any kind.Perhaps, these integrated circuits can be used to test the nano wire of manufacturing.For example, nano wire can use fluid mask of the present invention and be arranged on integrated circuit (or on other circuit types), thereby whether the test nano wire fully conducts electricity, measures the impedance of nano wire and/or other electricity/mechanical attributes of measurement nano wire.For example can use and 4 test probe devices to measure nano wire on the integrated circuit at 2.For example, the integrated circuit 1950 of Figure 19 D can be used in the four test probe systems.Test probe can be coupled near the outward flange of integrated circuit 1950 two pads, thus the nano wire that test is coupled the trace of corresponding two pads.The resistance between the measurement pad or a pair of probe of other parameter can be coupled on the pad owing to nano wire, use another that probe is carried measuring current simultaneously.Utilize same way as, the integrated circuit of Figure 19 A can be used in two test probe systems, and wherein the trace shown in Figure 19 C is coupled on ground or other reference potential.Perhaps, integrated circuit 1900 and 1950 can be used as electronic device, and wherein nano wire flows thereon, thereby makes electrical connection, diode, transistor etc.
Figure 21 represents to provide give an example according to the present invention use fluid mask of embodiment to locate the flow chart 2100 of the step example of nano wire on the target surface.Other structure and operation embodiment are obviously on following discussion basis to those skilled in the art, and these steps will describe in detail below.
Flow process 2100 starts from step 2102.In step 2102, the fluid mask matches with the target surface.For example, in an embodiment, the fluid mask is the fluid mask 1500 shown in Figure 15 A and the 15B.Shown in Figure 16 A, the first surface 1504 of fluid mask 1500 cooperates with target surface 1602.
In step 2104, the flow of liquid that contains a plurality of nano wires is crossed at least one raceway groove in the fluid mask surface.For example, shown in Figure 17 A and 17B, the liquid that contains a plurality of nano wires is nano wire solution, as nano-solution 1650.Shown in Figure 17 A, nano wire solution 1650 is crossed fluid mask 1500 at the direction upper reaches of stream 1702.Nanometer linear flow 1702 flows through one or more raceway grooves, the raceway groove 1506a-e as shown in the fluid mask 1500 of Figure 15 A.Shown in Figure 18 A, raceway groove 1506 covers the part 1802 of target surface example.
In step 2106, the nano wire that allows to be comprised in the liquid that flows through at least one raceway groove is arranged on the part target surface that is covered by at least one raceway groove.For example, as represented, allow nano wire to be arranged on the target surface 1602 from flowing 1702 by the arrow among Figure 17 B 1710.In an embodiment, be arranged on nano wire on the target surface 1602 and form at least one electrical connection between the conductive structure on the target surface 1602.In an embodiment, the nanowire density in the nano wire solution can be selected, thereby allows the nano wire of capacity to be arranged on being capped on the part of target surface, is electrically connected so that form.
In step 2108, the flow of liquid by at least one raceway groove is discontinuous.In this way, allow nano wire to keep being arranged on the part on target surface.For example, shown in Figure 18 B, nano wire keeps being arranged on the part target surface 1602, shown in nanowire region 1810.
In an embodiment, flow chart 2100 can comprise additional step, wherein makes nano wire fix (or bonding) on target surface 1602.For example, nano wire solution can solidify on target surface 1602, thereby nano wire is bonded on the target surface 1602.Perhaps, add epoxy resin or other adhesive material can for the nano wire on the target surface 1602, make them fixed thereon.
On substrate, spray nano wire
As mentioned above, wish on the substrate, the technology of location nano wire on the large tracts of land substrate particularly.A reason of this requirement is that conventional photoetching technique is applied on the large tracts of land substrate is unusual maybe can not implementing of difficulty.
According to embodiments of the invention, use spraying technique that nano wire is fixed on the surface, comprise the large tracts of land substrate.Nano wire can be ejected on the surface, thus the electrical connection between the formation electrode, or be used for other reason.Nano wire can be ejected into lip-deep electrically contact on, perhaps can at first nano wire be ejected on this surface, can metallize then or directly form thereon electrically contacts.
According to embodiments of the invention, use spraying technique the nanometer linear flow to be directed to the indicating section on surface.For example, use nozzle that nano wire solution is sprayed onto on the surface, thereby nano wire is positioned on the indicating section on surface.In an embodiment, use spraying technique, nano wire is located aligned with each otherly.In other embodiments, spray nano wire solution misalignment nano wire.
This part introduction is used for placing from the teeth outwards and locatees the spraying technique of nano wire and the nozzle embodiment that gives an example.Can nano wire be positioned at by nozzle be used in the electronic device, on semiconductor wafer, electronic substrate or any other surface in electrical testing structure and any other device or the system.Specific embodiments described here provides in order to represent purpose, and does not provide constraints.The alternative embodiment that is used for nozzle/spraying technique is clearly on the basis of instruction here to those skilled in the art.These alternative embodiments all are in the scope and spirit of the present invention.
Figure 22 represents to spray according to the nano wire of giving an example of the embodiment of the invention block diagram of application system 2200.System 2200 comprises nozzle 2202, target surface 2204, nano wire source of solvent 2206 and nano wire solution conduit 2208.System 2200 also can have other structure, and this is that those skilled in the art are readily appreciated that.
As shown in figure 22, nano wire source of solvent 2206 contains nano wire solution 2210.Nano wire solution 2210 normally contains the liquid solution of a plurality of nano wires.The composition of nano wire solution 2210 can be selected to flow to nanometer linear flow optimization on the target surface 2204 so that make by solution conduit 2208 and/or nozzle 2202.For example, can select the viscosity of nano wire solution 2210, flow on the target surface 2204 thereby strengthen nano wire.The composition of nano wire solution 2210 can be selected according to the size of the nano wire in the nano wire solution 2210.Target surface 2204 can be the surface of wafer, the surface of substrate, and as macroscopical electronic substrate, or surface described here or known any other structure.
Nano wire source of solvent 2206 provides nano wire solution 2210 by nano wire solution conduit 2208 to nozzle 2202.Nano wire solution conduit 2208 can be the conduit that is used for any kind of fluid or solution, comprises pipe, pipeline and/or valve.It should be noted in some embodiments, be directly coupled in nano wire source of solvent 2206 under the situation of nozzle 2202, do not need nano wire solution conduit 2208.
Control pressurization, aerosol or injection source can be used to make the nanometer linear flow to spray with predetermined flow velocity from nozzle 2202.Can applying-applying the basis with specific speed from the required pressure of nozzle ejection nano wire determines.
Figure 24 represents owing to applying the plane graph that the present invention has the target surface 2204 of location a plurality of nano wires 2402 thereon.Nano wire 2202 by nozzle 2203 from 2302 deposits of nanometer linear flow.As shown in figure 24, with single, uniformly nano wire distributes nano wire 2402 is positioned on the target surface 2204 basically.Nano wire 2402 can by an opening 2304 in the use nozzle 2202 or by using a plurality of openings 2304 in the nozzle 2202 to be positioned on the single distribution area, wherein said a plurality of openings 2304 have the adjacent or overlapping area coverage on target surface 2204.In addition, nano wire 2402 is positioned on the target surface 2204 with alignment so (that is, parallel to each other).In an embodiment, by using nozzle 2202 to make nano wire 2402 aligned with each other.Nano wire 2402 can be by [nozzle 2202 is aimed at, and this depends on the size of the opening 2304 in the nozzle 2202, the viscosity of nano wire solution 2210, the size of nano wire 2402 and other factors described here.For example, the drop that puts on the nano wire solution 2210 on target surface 2204 can have the surface tension of aiming at nano wire 2202.
Figure 25 represents owing to applying the plane graph that the present invention has the target surface 2204 of a plurality of nano wires 2502.Nano wire 2502 by nozzle 2202 from 2302 deposits of nanometer linear flow.As shown in figure 25, nano wire 2502 is positioned on the target surface 2204 among a plurality of distributed areas 2504a-d.Can by use in the nozzle 2202 opening or by using a plurality of openings 2304 in the nozzle 2202 that nano wire 2502 is positioned among a plurality of distributed areas 2504a-d, thereby a wherein said opening 2304 is directed/moves depositing nanowires in a plurality of Non-overlapping Domain, and described a plurality of openings 2304 have the non-adjacent or non-overlapped overlay area on target surface 2204.In addition, nano wire 2502 is positioned in the target surface 2204 according to alignment so (that is, parallel to each other).In an embodiment, opening 2304 can constitute and make nano wire aim at (that is, non-essential parallel to each other) randomly on target surface 2204.
Can on target surface 2204, form before or after by nozzle 2202 depositing nanowires 2402 and electrically contact.Figure 26 represents to have the plane graph on target surface 2204 of Figure 24 of the formation a plurality of 2602a-e of electrically contacting that electrically contact with nano wire 2402 thereon.Nano wire 2402 is electrically connected adjacent formation between electrically contacting 2602a-e.Electrically contacting 2602 can be any contact type.For example, electrically contacting of phase adjacency pair 2602 can be anode and negative electrode.Perhaps, three adjacent electrically contact 2602 and can be used as transistor drain, grid and source electrode.
Can use spraying technique of the present invention to come deposit nano wire described here or known any kind.Can control the density of the nano wire in the nano wire solution 2210 so that produce the desirable nanowire density that is deposited on target surface 2204.In addition, in case used spraying technique that nano wire is deposited on the target surface 2204, then can utilize described here or known any way solidifies nano wire/nano wire solution or is arranged on the target surface 2204.After nano wire being deposited on the target surface 2204, can use any processing of the feature that is used for limiting the nano wire film on the target surface 2204, for example comprise photoetching and cleaning technique.In addition, can prepare/handle target surface 2204, so that utilize cementability/tack described here or known any way enhancing nano wire.
The dimension/diameter of opening 2304 can constitute and strengthen the nanometer linear flow flow on the target surface 2204, as according to the alignment so depositing nanowires.In an embodiment, the width of one or more openings 2304 can be more than or equal to the length of the nano wire that will spray deposit.Perhaps, the width of one or more openings can be less than the length of nano wire.In an embodiment, the width of opening 2304 can be at 1 μ m in the scope of 1000 μ m, although also can use this scope width in addition, this depends on special applications.In addition, opening 2304 can have Any shape, comprises circle, ellipse, rectangle or other shape.
Figure 27 represent to give an example flow chart 2700 of step for example that is provided for location nano wire on the target surface of embodiment according to the present invention.Other structure and operation embodiment are readily appreciated that on following discussion basis to those skilled in the art.These steps will describe in detail below.
In step 2704, at least one delivery outlet of process nozzle is directed to nano wire solution on the target surface.For example, Figure 23 represents that the opening 2304a-e by nozzle 2202 is directed into the nanometer linear flow 2302 on the target surface 2204, and it comprises nano wire solution 2210.
In step 2706, nano wire is attached on the target surface.For example, step 2706 can comprise that wherein nano wire solution 2210 comprises curable materials and step of curing on target surface 204.In an embodiment, electric charge can put on target surface 2204, produces electrostatic attraction, help nano wire is bonded on the target surface 2204 from nano-solution 2210, and the nano wire solution in step 2704 remains on original position during applying.Electropolymer, chemical substance, pigment or reagent also can put on this surface.For example, material can be put on the substrate, thus the substrate of generation positively charged.The substrate of positively charged attracts electronegative nano wire, as using oxide (for example, SiO
2) silicon nanowires that applies.Can put on the surface as many lysines of aminopropyl-triethoxy monosilane (APTES), positively charged amino, the amine that contains the amine of silane or contain polymer, thereby produce this effect, as put on the substrate that contains silicon or other material.
In an embodiment, step 2704 comprises the step that nano wire is aimed at basically in parallel with each other on the target surface.For example, Figure 24 represents to have owing to the present invention the target surface 2204 of a plurality of nano wires 2402 disposed thereon aligned with each otherly.
In an embodiment, step 2704 comprises the step that nano wire solution is directed to the lap on target surface.For example, Figure 24 represents to be positioned at a nano wire 2402 in the distributed areas.Perhaps, step 2704 can comprise the step that nano wire solution is directed to a plurality of non-overlapped parts on target surface.For example, Figure 25 is illustrated in the nano wire 2502 that is positioned among a plurality of non-overlapped distributed areas 2504a-d on the target surface 2204.
In an embodiment, step 2704 can comprise and exerting pressure so that force nano wire solution to flow to the lip-deep step of target by at least one delivery outlet of starving of nozzle.
In an embodiment, target surface 2204 can be very large surface, as large tracts of land macroscopic view electronic substrate.In such an embodiment, the target surface can be used as the continuous slab on conveyor-type system or other substrate feed system and is received.Like this, in an embodiment, flow process 2700 can comprise the step with respect to the position of nozzle governing plate.For example, this plate can be carried from being fed continuously through the roller of nozzle 2202.This relatively moving between nozzle 2202 and the target surface 2204 for example can be used for aiming at nano wire on target surface 2204.
By selecting the nanowire semiconductor material to reduce the phon scattering of the electronics in the nano wire
Silicon is the suitable semiconductor material that is used for nano wire, in part because of its compatibility in semi-conductor industry.Yet silicon has surface state (～10
10Cm
-2) defective in vogue, and restricted to the linear diameter of the required nano wire realized of the phon scattering of eliminating electronics.
Like this, according to the present invention, the alternate material that is used to make nano wire is disclosed.This material described here has advantage, comprises the nano wire phon scattering of minimizing and the diameter range of increase.
There is dual mode at least to reduce or eliminate the phon scattering of electronics.In order to reduce or eliminate the phon scattering in the nano wire, should be that (1) is greater than phonon energy at the isolated energy of the subband of nano-material; (2) greater than 3*K
bT, wherein K
bIt is Maxwell constant (8.62 * 10
-5EV/ ° of K.), " 3 " are pre-determined factor, and T is the absolute temperature of nano-wire devices work.In order at room temperature to work, the requirement that (2) are normally stricter is because the phonon energy of most of semi-conducting materials is less than 3*K
bT
Rt, T wherein
RtBe room temperature, K
bT
Rt=.0259eV, thereby 3*K
bT
Rt=.0777.
The quantum limit of the electronics in the semi-conducting material relates to the restriction of the electronics in the subband in the conduction band of semi-conducting material.Electronics in this material is limited to the special energy level of subband.Yet electronics can move to another sub-band energy level from a sub-band energy level.Interval between the subband or energy difference can calculate.For having isotropism electronics (or hole) effective mass m
EffNano-material, the energy bite between ground state and the first excited state is provided by following formula:
Wherein:
H=Planck's constant ÷ 2 π
m
EffThe effective mass of=selected semi-conducting material; With
R is the radius of nano wire.
Can not be between subband during scattering when electronics, the quantum limit of the electronics in the semi-conducting material remains unchanged.Yet the phon scattering in the semi-conducting material makes electronics scattering between the subband of semi-conducting material, and this can reduce the mobility of the electronics in the nano wire.In order to keep the quantum limit of electronics, must prevent the phon scattering of the electronics in the semi-conducting material, so that prevent electronics scattering between subband.As described below, by selecting to have known effective mass m
EffSemi-conducting material and form nano wire so that have and stop electronics because sound self-scattering and the diameter that between sub-band energy level, moves by this semi-conducting material, can keep the quantum limit of electronics.
Different semi-conductive effective mass m
EffSome more preferably is used to reduce or eliminate phon scattering than other to make them.In addition, has less effective mass m
EffNano wire allow to have than major diameter.During nanowire growth, controlling better of nano wire than the major diameter permission, and the additional strength of nano wire is provided.
Equal Nk by the equation 1 that is provided with
bT
Rt, can form following equation, this equation is used for calculating by having effective mass m
EffThe maximum gauge of the nano wire made of semi-conducting material, thereby have the phon scattering that reduces basically or eliminate.
Wherein:
H=Planck's constant ÷ 2 π
＝6.626×10
-34J-sec÷(2×3.1416)
(or 4.14 * 10
-15EV-sec ÷ 2 * 3.1416)
＝1.0545×10
-34J-sec(6.589×10
-16eV-sec)；
m
EffThe effective mass of=selected semi-conducting material;
The N=pre-determined factor;
K
b=Maxwell constant=1.38 * 10
-23J/ ° of K (8.62 * 10
-5EV/ ° of K); With
The T=working temperature;
Wherein at room temperature, k
bT=4.144 * 10
-21J (.0259eV).
Like this, equation 2 can be rewritten as:
Pre-determined factor N can select so that the coefficient of the assurance on the statistics that relates to electronics restriction and phon scattering minimizing is provided.For example, pre-determined factor N can be selected so that have greater than zero any value.In an embodiment, select pre-determined factor N to make it have value more than or equal to 3.In another embodiment, select pre-determined factor N to make it have value more than or equal to 5.
The maximum of the curve 2800 expression semi-conducting materials shown in Figure 28 allows diameter and effective mass m
EffMaximum for nano wire can allow diameter (nm) to represent on Y-axis, and standardization effective mass m has been shown in the Y-axis of curve 2800
Eff/ m
0Shown in curve 2800, along with standardization effective mass m
Eff/ m
0Reduce, the maximum of nano wire can allow diameter to increase.Along with standardization effective mass m
Eff/ m
0Be reduced to below 0.2, the maximum of nano wire can allow diameter sharply to increase.
Table 2900 shown in Figure 29 has been enumerated the various semi-conducting materials for example in first row 2902.What enumerate in secondary series 2904 is the effective mass of the semi-conducting material of first row 2902, and what enumerate in the 3rd row 2906 is the energy gap of the semi-conducting material of first row 2902.As mentioned above, has less relatively effective mass m
EffSemi-conducting material be favourable because their allow big nanowire diameter.As the favourable selection of giving an example in the table 2900, GaAs, InSb (being used for infrared detector) and InAs are more outstanding, and they respectively have relatively little effective mass m
Eff, therefore allow big relatively nanowire diameter.
For example, apply the data of row 2904 for the curve 2800 of Figure 28, the maximum that then is used to have silicon (Si) nano wire of the phon scattering that reduces basically or eliminate can allow diameter to be～6mn.For GaAs (GaAs), the maximum with nano wire of the phon scattering that reduces or eliminates basically can allow diameter to be～20mn.
In addition, the data of table 2900 can put on equation 2, thereby calculate suitable nanowire diameter for particular semiconductor material.For example, as in the row 2904 for shown in the GaAs, m
Eff/ m
0Equal .067, wherein m
0It is free electron residual mass (9.11 * 10
-31Kg).This value puts on equation 2, and is as follows:
Wherein
m
0=free electron residual mass=9.11 * 10
-31Kg; With
N＝3。
Like this,, can use diameter, reduce or eliminate phon scattering simultaneously up to 16.14 for GaAs.
Like this, can use nano wire individually, perhaps in group/film, use nano wire, wherein nano wire forms and has the diameter that is less than or equal to the maximum gauge of determining for the semi-conducting material of nano wire, thereby allow the quantum limit (that is, reducing or eliminated fully the phon scattering of electronics basically) of the basic electronics of each nano wire maintenance.
In addition, in an embodiment, each nano wire can form has the length that is less than or equal to (≤) predetermined length, thereby can produce the ballistic transport of electronics by each nano wire.
Figure 30 represent to give an example flow chart 3000 of step for example that is provided for designing conducting nanowires of embodiment with high electron mobility according to the present invention.Other structure and operation embodiment are readily appreciated that on following discussion basis to those skilled in the art.These steps will describe in detail below.
In step 3004, determine the maximum gauge of the nano wire made by selected semi-conducting material, the basic quantum limit of electronics is provided.For example, can select diameter by the curve 2800 of observation Figure 28 or by using equation 2 to calculate maximum gauges.
In step 3006, form a plurality of nano wires by selected semi-conducting material, each nano wire of a plurality of nano wires form have less than or the diameter of the predetermined maximum gauge of lamp signal.
Use the strategy that mixes to reduce the phon scattering of the electronics in the nano wire
According to the present invention, the phon scattering of the electronics in the nano wire can reduce or eliminate by the nanowire semiconductor strategy that mixes.Mixing, whether (being n type or p type) effect may influence the phon scattering of the electronics in the nano wire, and the physical strength of line.In an embodiment of the present invention, as will be described as further below, can mix has as the electronics of conduction charge carrier or the semiconductor in hole, thereby improves performance.
Most of semiconductors have the band of degeneration on the valence band maximum, it has heavy hole and light hole.Least energy between the valence band is at interval from the heavy hole with big effective mass.Accordingly, in a preferred embodiment, nano wire is configured so that electronics becomes the conduction charge carrier in the nano wire, because the effective mass in hole is greater than the effective mass of electronics.
Constitute nano wire so that use electronics as the conduction charge carrier, this can mix and/or apply the biasing grid voltage on p doping line and realize by nano wire directly being carried out n.Table 3100 shown in Figure 31 has been enumerated the III-V semiconductor type material for example in the row 3102.Row 3104 contain the corresponding effective mass of the electronics of the material that is useful on row 3102. Row 3106 and 3108 contain the corresponding effective mass that is respectively applied for light hole and heavy hole of the material that is useful on row 3102.For all semi-conducting materials of enumerating in the table 3100, the effective mass of the electronics shown in the row 3104 is less than the effective mass that is included in row 3106 that is used for light hole and heavy hole.Like this, the n of the nano wire of being made by these semi-conducting materials mixes and will cause the lower phon scattering of mixing than p.
Notice that it is in order to represent purpose that the table 3100 of enumerating III-V semiconductor type material is provided, and the present invention is applicable to the semi-conducting material type except the III-V semiconductor type.
In addition, the mechanical strength of n doped silicon is greater than the mechanical strength of p doped silicon, and this mixes for the n that selects nano wire and mixes more favourable than the p that selects nano wire.For further details, can be with reference to B.Busham and X.Li, Journal of Material Research, Vol.12, the 54th page (1997).
Perhaps, nano wire can mix with p type dopant material, and nano wire can constitute and makes electronics become the conduction charge carrier.For example, by apply enough bias voltages to nano wire film, can be in conjunction with the nano wire film of p doped nanowire according to reverse mode work.This can make electronics be used as conduction charge carrier in the p doped nanowire, reduces or eliminates the phon scattering in the p doped nanowire.For example, in transistor embodiment, bias voltage can be used as transistorized grid bias and puts on a plurality of nano wires, thereby makes nano wire with reverse mode work.
Use the surface state in the core shell material minimizing nano wire
Towards realizing increasing electron mobility, comprising that another factor of the electron-trajectory transmission in the nano wire is the minimizing of surface and body (that is nanowire core) impurity scattering.In nano wire, surface scattering is especially obvious, wherein has bigger surface and body ratio.
Can reduce surface scattering by the skin that forms nano wire,, and/or use core-shell structure with nano wire as passivation anneal by nano wire.For example, Fig. 3 B represents the example according to the nano wire 310 of core-shell structure doping.On nano wire, can form insulating barrier, as oxide coating as shell.In addition, for example, for silicon nanowires, at hydrogen (H with oxide coating
2) in nano wire annealed can significantly reduce surface state.In another example, for nano wire with the compound semiconductor in nanowire core, as GaAs, use the AlGaAs same compound of other compound semiconductor type (or be used for) shell can limit the electron waves function effectively, and be used to reduce surface state.
In an embodiment, core-shell constitutes to satisfying following restriction: (1) shell energy level should be higher than core level, thereby the conduction charge carrier is limited in the core; (2) core and shell material should have excellent lattice matching, have seldom surface state and surface charge.
It should be noted that in an embodiment, the thickness of shell and linear diameter can change, so that improve the carrier mobility in the nano wire and reduce surface state.
What Figure 32 represented to give an example according to the present invention embodiment is provided for making the flow chart 3200 of step for example with the nano wire that reduces surface scattering.Other structure and work embodiment are readily appreciated that on following discussion basis to those skilled in the art.These steps will describe in detail below.
In step 3204, form a plurality of nano wires by selected semi-conducting material.For example, can or form nano wire with selected semiconductor material growing.
In step 3206, apply the circumferential surface of each nano wire of a plurality of nano wires with insulating barrier.For example, in an embodiment, insulating barrier can be a dielectric material.In another embodiment, insulating barrier can be an oxide.Each nano wire can be oxidized, thereby form insulating barrier.In an embodiment, can anneal to each oxidized nano wire.For example, can under the H2 environment, anneal to each oxidized nano wire, thus the dangling bonds on the interface of the oxide layer of each oxidation nanometer line of passivation and non-oxide part.For example, can carry out oxidation, thereby produce SiO silicon nanowires
2Oxide skin(coating).In another example, nano wire that can oxidation is formed by compound semiconductor materials in oxygen or oxygen composition, thereby wherein oxygen or oxygen composition be conduction on material, form oxide.For example, can under oxygen and arsenic environment, carry out oxidation, thereby produce oxide layer, as As the GaAs nano wire
2O
3Layer.Other compound semiconductor materials can be oxidized equally, or oxidation otherwise.
Figure 33 represents another flow chart 3300 that is provided for making the step of giving an example with the nano wire that reduces surface scattering according to embodiment for example of the present invention.Other structure and work embodiment are readily appreciated that on following discussion basis to those skilled in the art.These steps will describe in detail below.
In step 3304, form a plurality of nano wires with selected semi-conducting material.For example, can or form nano wire with selected semiconductor material growing.
In step 3306, each nano wires of a plurality of nano wires is mixed, thereby make each nano wire comprise core-shell structure, its mesochite is the doping skin of each nano wire that surrounds each core of each nano wire.For example, nano wire is a nano wire 310, shown in Fig. 3 B.The doping skin is a doped surface layer 302.In an embodiment, the effect of step 3306 is that the charge carrier of each nano wire is limited on the core of axially setting basically.
In an embodiment, step 3306 can be included as the outer dopant material of selecting of doping of each nano wire, makes the skin that mixes will have the energy level higher than the energy level of each core.
In an embodiment, step 3306 can comprise the steps: wherein outerly to select dopant material to mixing, thereby the outer field lattice structure of mixing is complementary with the lattice structure of core basically.
Nano wire and nano wire film transistor
Figure 34 A-34C represents to relate to the notion of high mobility nano wire and nano belt TFT.Figure 34 A represents amorphous (a-Si) or polysilicon (poly-Si) TFT.As seeing from Figure 34 A, electric charge carrier must pass a plurality of crystal boundaries, causes low carrier mobility.Figure 34 B represents the NW-TFT according to the embodiment of the invention.Different with a-Si or poly-Si, wherein charge carrier must pass a plurality of crystal boundaries and cause low mobility, and NW-TFT has the conducting channel that is formed by parallel a plurality of monocrystalline NW path (being similar to the logic bridge).Like this, electrons/ source electrode to the drain electrode between all paths in, in monocrystalline, move with high mobility.Equally, shown in Figure 34 C,, also can use single crystal semiconductor nanometer to bring and make to have high performance TFT with the characteristic that is similar to a plurality of parallel nanowires according to embodiments of the invention.
The manufacturing of NW-TFT device
Figure 35 A represents the flow chart 3500 of step for example that is provided for making NW-TFT according to the embodiment of the invention.Other structure and work embodiment are readily appreciated that on following discussion basis to those skilled in the art.These steps will describe in detail below.
In step 3520, nano wire suspends in solution.In the embodiment that gives an example, can use sonication that synthetic nano wire is transferred in the ethanol, thereby obtain stabilized nano line suspension.Perhaps, nano wire can be sent in other appropriate solution type and be suspended in wherein.
In step 3530, set of nanowires is dressed up film.In this example, in being distributed to solution after, use fluid stream that set of nanowires is installed on the selected substrate, thereby obtain the nano wire film of orientation with the alignment methods guiding.Allow nanowire suspended liquid by being formed on the fluid channel structure between poly dimethyl silane oxygen (PDMS) mould and the planar substrate surface, thereby obtain the NW array from the teeth outwards.Control average N W space in the film by changing NW concentration in the solution and/or total flowing time.Utilize this scheme, by using long or big flow channel mould, aligning can be at an easy rate at 4 inches wafers or even more extend on the large tracts of land.This fluid channel example of structure is as mentioned above like that as the fluid mask 1500 shown in Figure 15 A and 15B.
Figure 35 B represents to have the light micrograph of nano wire film for example of parallel-oriented nano wire individual layer, and average nano wire is spaced apart about 500-1000nm.The microphoto of Figure 35 B is also represented the roof intersection of several nano wires at nano wire film, although in alternative embodiment, film can be made for the nano wire that does not have in the roof intersection of nano wire film.Scale rod shown in Figure 35 B is that 100 μ m are long.Illustration 3502 among Figure 35 B provides high power more and comprises the scale rod of 20 μ m.
In step 3540, make film transistor device.Film transistor device combines the nano wire film of making in step 3530.The film transistor device of any kind can be made.
In step 3550, the integrated thin-film transistor device for special macroscopical electronic application.In the embodiment that gives an example, can carry out standard photoetching or E electron beam printing technology to the NW film, thereby limit source electrode and drain electrode and on grand electronic substrate, make TFT.
Figure 35 C represents TFT for example, and wherein the scale rod is 100 μ m.Different materials can be used for these electrodes, comprises gold electrode, and it is being used for TFT device for example shown in Figure 35 C, and as light belt look rod.For the Curie TFT3504 shown in the illustration among Figure 35 C, wherein show the back of the body grid type device architecture on the silicon substrate.Following silicon is used as back grid, the silicon nitride (SiN that 100nm is thick
x) be used as gate dielectric materials, and use Ti/Au (60nm/60nm) film of e beam evaporation device deposit to be used as source electrode and drain electrode.
Figure 35 D provides the optical photograph of NW-TFT, the NW parallel array of expression bridge joint source electrode and drain electrode 3506 and 3508.Scale rod among Figure 35 D is that 5 μ m are long.
Performance characteristics-P channel silicon nano wire film transistor (NW-TFT)
In following example, the ammeter that at room temperature carries out NW-TFT under air ambient, in magazine neutralization is levied.Figure 36 A is illustrated in the grid voltage (V of variation
GS) under leakage current (I
DS) and drain-source bias voltage (V
DS) curve chart, wherein said grid voltage is with the stepped change of 1V, and starts from having V
GSThe upper curve of=-10V.In this example, TFT is made of 91 substantially parallel 20nm diameter nano wires, and has 5 μ m channel lengths.Figure 36 A is illustrated in leakage current I
DSAt low V
DSDown along with V
DSLinear increase also is tending towards at higher V
DSWhen saturated, with the typical p channel transistor behavior of accumulative means work.By applying minus gate voltage, along with main charge carrier (hole) increases in raceway groove, leakage current increases.Applying positive gate bias has exhausted the hole in the raceway groove and device is turn-offed.
Shown in Figure 36 B at V
DSI during=-1V
DSWith V
GSCurve representation does not have electric current to flow through when grid voltage is corrected than threshold point, and as grid voltage I when negative direction increases
DSApproximately linear ground increases.The linearity of linear zone is inferred the threshold voltage that causes 0.45V.Insertion curve 3602 expression shown in Figure 36 B with index measure draw at V
DSDuring=-1V-I
DSWith V
GSFigure 36 B makes and approaches 10
8Enablement and disablement than and approximately the sub-threshold value swing of 500mV/s become highlight bar.V at 500mV/s
GSScan rate is collected down the linearity curve data, and at the V of 15mV/s
GSScan rate is collected the exponential curve data down, is loading the electric current minimum thereby make than the capacitive under the high gate voltage.Obvious threshold voltage in the insertion curve is owing to hysteresis effect is displaced to 3.5V.
Usually at the I of the electric current of NW-TFT
DS-V
GSIn observe hysteresis effect.Can eliminate this hysteresis effect or it is minimized with device fabrication by strictness control NW is synthetic, thereby make ionic contamination minimum.Hysteresis has effect when determining threshold voltage.Because hysteresis effect, significantly threshold voltage can change according to the voltage history of this device experience before measuring condition and the measurement.
In order to make the threshold voltage variable minimum that causes owing to hysteresis effect, use the same terms (the grid voltage sweep speed of the 500mV/s that use is very big relatively makes movably, and ionic effect minimizes) test component.By three grid voltages of at first before collecting the data of each device, circulating at least (from 10 to-10V), also can make voltage history variable minimum.In this way, can determine proper threshold voltage distribution (the main curve plotting of Figure 36 B and Figure 36 C).On the other hand, in order to measure the cut-off state electric current exactly, use slower grid voltage sweep speed (15mV/s), thereby make the capacitance current minimum.In this case, the high positive grid voltage of this device (approximately 5-10 minute) experience in cycle time expand and make obvious threshold value to more on the occasion of skew illustration Figure 36 B).
For macroscopical electronic application, a large amount of crucial transistor parameters are represented the TFT performance, comprise mutual conductance, mobility, conduction and cut-off current ratio, threshold voltage and the swing of sub-threshold value.High transconductance is very important for transistor performance and for the voltage gain of transistor base device, and described device comprises amplifier and logical circuit.-I
DSWith V
GSLinear zone in slope be illustrated in V
DSThe mutual conductance of about 11 μ S during=-1V, g
m=dI
DS/ dV
GSSuppose that effective channel width equals the NW diameter d and multiply by digital N, i.e. NWs:W
Eff=Nd=1.8 μ m.Contrast a-Si TFT and poly-Si TFT can obtain the standardization mutual conductance of about 6 μ S/ μ m.This is the mutual conductance that significantly is better than non-crystalline silicon tft and p raceway groove poly-Si TFT, and wherein the mutual conductance of non-crystalline silicon tft is about 0.01 μ S/ μ m,
The mutual conductance of p raceway groove poly-Si TFT is approximately 0.3 to 0.8 μ S/ μ m.In addition, this can compare with the mutual conductance of monocrystalline p raceway groove silicon-on-insulator (SOI) MOSFET, and wherein the mutual conductance of monocrystalline p raceway groove silicon-on-insulator (SOI) MOSFET is about 5-12 μ S/ μ m.It should be noted that uses high dielectric constant can further improve NW TFT mutual conductance than thin-medium.
Use standard MOSFET equation adds simulation, thus the carrier mobility among the NW TFT that further evaluation is being studied.At I
DS-V
GSIn the low biasing linear zone of curve, hole mobility μ h can derive from following equation:
G
DS＝I
DS/V
DS＝μ
hC
G(V
GS-V
th-V
DS/2)L
2，
C wherein
GBe grid capacitance and
L is a channel length.
Grid capacitance comprises the SiN on the substrate
xThe electric capacity of the electric capacity of medium and Si oxide shell.Yet calculating these electric capacity is non-trivial.(for example, from the Metamesh of FieldPrecision, simulation http//www.fieldp.com) produces the total capacitance of about 27fF, causes about 130cm to use the encapsulation of 3D finite element
2The hole mobility of/Vs.This hole mobility is than being p type polysilicon (about 12cm
2/ Vs) best values of report is also high, and can with p type monocrystal material such as SOIMOSFET (about 180-250cm
2/ Vs) hole mobility is compared, and in addition, for example, also is feasible by reducing doped level and/or making the minimum carrier mobility that further improves of the lip-deep trapped state of NW.
The I of index measure is pressed in illustration curve 3602 expressions among Figure 36 B
DS-V
GSCurve chart, expression leakage current are reduced to the following and transistor of threshold voltage exponentially to have and approaches 10
8The enablement and disablement current ratio.This be expressed as the maximum enablement and disablement reported from the transistor of chemical synthesis nano material assembling than and can compare with the enablement and disablement ratio of monocrystalline silicon device.The index decreased of electric current defines crucial transistor parameter, sub-threshold value swing S=-dV
GS/ dIn|I
DS|, will about 600mV/ ten in this device.In conventional MOSFET, S is by S=(k
BT/e) Ln{ (10) (1+ α) } determine that wherein T is a temperature, k
BBe Maxwell constant, e is the element electric charge, and α depends on the electric capacity of device and when grid capacitance was far longer than other electric capacity such as interface trapped state electric capacity, α was 0.Therefore the minimum theoretical limit of S is S==(k
BT/e) Ln{ (10) perhaps at room temperature is approximately 60mV/ ten.
Generally speaking, for low threshold voltage and low-power consumption, wish the swing of boy's threshold value.In the embodiment of NW device of the present invention, approximately the sub-threshold value swing of 600mV/ ten is significantly better than conventional amorphous Si TFT or organic semiconductor TFT, they usually from 1 in a lot of volts/ten scope.In addition, this can compare with most of poly-Si TFT, at that time basically greater than best poly-Si TFT (approximately 200mV) and monocrystalline silicon device (approximately 70mV).
The big relatively sub-threshold value swing of observing NW device of the present invention may mainly be owing to exist surperficial trapped state and geometric effect to produce, this can pass through passivated surface (for example, hydrogenation or use core-shell structure) and/or use top gate type or on every side grating structure significantly improve.
Geometric effect is to be produced by the NW that intersects on other NW in NW-TFT.The NW film still has several NW to intersect on other NW usually by constituting near individual layer NW once in a while.When NW intersected on other NW, it separated with substrate surface, and experience is from the littler electric field of back of the body grid, therefore than conducting or the shutoff more lentamente of other NW in the device.This has increased the sub-threshold value swing of NW-TFT on the whole.Much less, and be very important, around using conformal electrolysis grid verified little sub-threshold value swing to about 70mV/ ten, as described below.
In actual applications, the changeability of threshold voltage in each device is to determine the variable key factor of technology.For this reason, on 20 individual devices, test according to embodiment of the invention manufacturing.Figure 36 C represents the block diagram of the threshold voltage distribution of these devices.Gauss is mated the standard deviation that expression has only 0.22V.In addition, the best of structure and manufacturing process may cause distributing more closely.
Specifically, by developing various NW core-shell structures, utilizing a lot of modes can further improve the performance of NW-TFT.At first, among the NW-TFT on plastics, enablement and disablement is than the AlO that is subjected to low amount e beam evaporation
xThe restriction of gate dielectric.By using the core-shell NW structure that constitutes by single crystal semiconductor core and high-quality gate dielectric shell can overcome this problem potentially.Although Si NW has core-shell structure usually, thin native oxide layer is not sufficiently high quality for bearing high electric field.Natural oxide can replace or replenishes with high-quality silica shell, and wherein said high-quality silica shell produces by controlled thermal oxidation, chemical vapor deposition or other appropriate technology.Core-shell NW structure is very suitable on plastics making high-performance NW-TFT, and this is because high-temperature process, comprises that the synthetic and high-quality gate dielectric formation of semi-conducting material etc. separates with the resulting devices substrate to carry out.In addition, this core-shell structure can also cause the passivation of surperficial trapped state, further improves performance.
Secondly, owing to making present back of the body grid NW-TFT, geometric effect on performance, is restricted relatively.This geometric effect can overcome by using more complicated NW core-shell structure, and this NW-TFT core-shell structure comprises the core of single crystal semiconductor, the inner casing of gate dielectric and the shell of conformal gate.This for example can pass through at Si/SiO
xCore-shell structure (above-mentioned) the highly doped amorphous silicon of deposit one deck is on every side realized as outer grid shell.
The 3rd, can further improve the performance of NW-TFT potentially by the quantum electronic effect among the exploitation minor diameter NW, thereby surpass the performance of monocrystal material.In simulation, can imagine a plurality of cores-shell NW structure so that separate dopant, thereby realize superelevation mobility TFT from active conducting channel to conventional bidimensional semiconductor superlattice and 2D electrons/gas.
The quantity of NW in the major parameter of device performance (as charge carrier and threshold voltage) and the conducting channel is relevant.Like this, design and the manufacturing with NW-TFT of predetermined properties is feasible.For example, by changing the quantity (changing effective channel width) of the NW in the conducting channel, can design and make NW-TFT so that at predeterminated level delivery electric current.(V when Figure 36 D is illustrated in break-over of device
GsThe linear dimension relation of the drain current of=-10V).The on-state current of the function of two effective channel widths of curve representation conduct.Lower curve has V
DS=-1V, upper curve has V
DS=-8V.The average diameter of the corresponding NW of effective channel width and the product of NW quantity.As desired, on-state current is along with effective width linear change (quantity of the NW in the conducting channel).Realized on-state current greater than 0.5mA by having less than the device of effective channel width of 5 μ m.Have design device parameters NW-TFT can make again with predictable assembly be very important.
NW-TFT on the plastics
An important aspect of NW film notion is at present: whole NW-TFT manufacturing process can mainly at room temperature be carried out, and except the NW synthesis step, this step is what to separate with the device manufacturing.Therefore, the assembly of high-performance NW-TFT is easy to put on low-cost glass and the plastic.In order to prove the NW-TFT on the plastic, use different device architectures.Figure 37 A represents device architecture.For the device of shop drawings 37A, at first on polyether etherketone (PEEK) plate (50 or 100 μ m are thick, Goodfellow company), revolve and annotate thick SU-8 (MicroChem Corp.) photoresist layer of 1-2 μ m and make its curing, thereby guarantee micro-smooth surface.Cr/Au (10/30nm) bar is defined as grid array, and uses e beam evaporation method deposit 30nm layer aluminium oxide as gate dielectric.The Ti/Au (60/80nm) of the NW film of deposit aligning, and qualification from the teeth outwards source electrode-drain electrode, thus TFT formed.Figure 37 B represents to have the example of the plastic device of NW-TFT.Source electrode, grid and the drain electrode of the NW-TFT of the scale rod that equals 5 μ m represented to have in the bottom of Figure 37 B.
Utilizing mode same as described above to carry out electrical transmission characterizes.Figure 37 C represents I
DS-V
DSCurve representation is taken advantage of the identical behavior of device on the ground with SiNx/Si.The curve representation I of Figure 37 C
DS-V
DSRelation, wherein V
GSVariable and from V
GS=-8V begins and increases with the stride of 1V.The threshold voltage of the about 3.0V of IDS-VGS relation expression and greater than 10
5The conducting cutoff.
Figure 37 D is illustrated in before the slight bending of plastic and the transmission characteristic of identity unit afterwards.3702 pairs of the illustrations of Figure 37 D are greater than 10
5The conducting cutoff and the sub-threshold value swing of 500-800mV/ ten carry out highlighted demonstration.It is 40nm and 17 NWs parallel with 3 μ m grid lengths with 6 μ m channel lengths that device under test has diameter.Two curve representations have confirmed the mechanical flexibility of the NW TFT on the plastics in slight bending plastic (radius of curvature is about 55nm) before and the transmission characteristic of identity unit afterwards.
Relatively little conducting cutoff is (with SiN
x/ Si substrate is compared) be because: (1) is because the local gated device structure of non-the best causes hanging down the conducting electric current; (2) be subjected to AlO by the e beam evaporation
xThe higher cut-off current of the low electric leakage of the grid flow restriction that the low quality of medium causes; Can significantly increase with core-shell NW structure of utilizing improved device architecture and advanced person.
The sub-threshold value swing that reduces mainly causes owing to two factors.At first, electrolyte produces excellent conformal gate, therefore eliminates or has reduced any geometric effect of widening sub-threshold value swing.Secondly, utilize the electrolyte conformal gate, grid capacitance is greater than of back of the body gate device more than the order of magnitude (for the device of about 160 NW, approximately 0.77pF and about 0.05pF).Therefore, compare with grid capacitance, the relative importance of other electric capacity has reduced, and causes S=(k
BT/e) significantly reducing of the α value among the Ln (10) (1+ α), thereby sub-threshold value swing S also reduces.
The mainspring that drives plastic electronic research is a mechanical flexibility.Importantly, the slight bending with plastics of NW-TFT device can significantly not change the device behavior.As mentioned above, Figure 37 D provides two curves of this feature of expression.Shown in Figure 37 C, the linear zone in the IDS-VGS relation is at V
DSThe mutual conductance of 0.45 μ S is provided during=-1V.Yet, be difficult to estimate the accurate hole mobility in the device, because the grid capacitance of estimating in the local grid type device architecture is very difficult.
In order to measure the resulting devices performance of the NW-TFT on carrier mobility and the plastics, after tested electrolyte grid type TFT structure.Figure 38 A represents the electrolyte grid type NW-TFT structure of testing.This scheme is used to study independent carbon nano-tube FET.This testing scheme is carried out following steps.On the TFT device on the plastic, place the droplet of 1mM salting liquid, cover whole TFT device, comprise source electrode, drain electrode, NW film and additional isolation gold electrode.Voltage V
GSPut on the isolation gold electrode, thereby in electrolyte, set up electrochemical potentials with respect to the NW-TFT device.For the voltage range less than ± 0.9V, the leakage current between the source electrode of electrolyte and NW, the drain electrode can be ignored.Electrolytical function is as trap iknsulating liquid grid.Special benefits is that electrolyte produces the useful encirclement conformal gate of all NW that are used for the TFT raceway groove, has reduced or eliminated undesirable geometric effect and surface charge, provides effective structure thus so that the final performance of test NW-TFT.
Figure 38 B represents as with the 0.1V stride and start from having V
GSThe I of the function of each electrolyte grid voltage of the top curve of=-0.9V
DS-V
DSRelation.The NW-TFT of test comprises the NW of 162 the 20nm diameters parallel with 5 μ m channel lengths.
Figure 38 C represents the V for 10mV
DSI
DS-V
GSRelation.Whole whole result is similar to the result of the TFT that makes as mentioned above on silicon substrate.But, especially, in this device, drain current I
DSThe easier response of variation to the electrolyte grid voltage.Sub-threshold value swing also significantly reduces (70-110mV/10), shown in the illustration 3802 of Figure 38 C.Utilize lock-in amplifier (for example can obtain) to determine I by Stanford Research
DS-V
GSRelation.Measure for this, use 10-Hz sine wave in 10-mV RMS amplitude.
In addition, the special structure of solution grid experiment may be underestimated the performance of desirable device, because source electrode also contacts with solution with drain electrode.The electrochemical potentials that source electrode and drain potential may influence the real solution current potential and compromise and set up by grid is reduced to below the voltage that puts on grid the NW actual current potential that applies on every side.Therefore, utilize improved plan (for example, using the canonical reference electrode) to set up grid potential, can realize even littler sub-threshold value swing.Simultaneously, the result has confirmed to be used for the high performance current potential of the TFT on the plastics, this can (for example improve by the grid structure of further these devices of optimization, can realize solid-state conformal gate on every side in multicore-shell NW structure, described core-shell NW structure is made of the inner casing of single crystal semiconductor core, gate dielectric and the shell of conformal gate).
Each characteristic by checking device feature is the performance of the electrolyte grid TFT device on the analyzing plastics further.At first check grid capacitance.In this case, total capacitance comprises the series capacitance of electrolyte electric capacity and NW shell capacitive oxide, although because the former can ignore the former much larger than the latter.Consider to have monocrystalline core and the average approximately NW of 2.5nm amorphous silicon oxide shell of 20nm.Grid capacitance can be passed through following technological evaluation: C
G=2N π ε ε
0L/ln (1+t
Ox/ r), wherein N is the quantity of the NW in the raceway groove, ε and t
OxBe respectively the dielectric constant and the thickness of amorphous oxides, r is the radius of NW.Based on the electric capacity and following relationship formula: the G that calculate
DS=I
DS/ V
DS=μ
hC
G(V
GS-V
Th-V
DS/ 2)/L
2, hole mobility μ
hCan be defined as about 150cm2/Vs.This result meets for having the SiN of identical NW
xThe mobility that identity unit the obtained on/Si substrate.This shows that the mobility of NW-TFT is the intrinsic of NW own, is subjected to the influence of plastic or electrolyte grid not obviously.
N raceway groove CdS nano belt TFT
Top discussion has confirmed that high-performance NW-TFT can be assembled on the cold plastics substrate from p type Si NW.In addition,, therefore comprise that the material of the semi-conductive wide region of III-V and II-VI family can be developed as the TFT channel material, produce the chance of wide region because NW is synthetic relevant with the resulting devices substrate.As an example, high performance TFT also can be assembled from II-VI family cadmium sulfide (CdS) nano belt at an easy rate.CdS is the low surperficial trapped state of intrinsic.Use the synthetic thickness of vacuum vaporization transmission method to reach the monocrystalline CdS nano belt of 10-200 μ m as 0.5-5 μ m and length as 30-150nm, width.
Specifically, a small amount of CdS powder (approximately 100mg) is transferred in the end of vacuum tube and sealing.The heating, vacuum pipe make the end with CdS remain 900 ℃, and the other end of vacuum tube remains on about temperature below 50 ℃.In two hours, most of CdS are transferred to cold junction and are deposited on the tube wall.The material that obtains mainly is that thickness is that 30-150nm, width are that 0.5-5 μ m and length are the nano belt of 10-200 μ m.The TEM image shows that nano belt is the monocrystalline that has low defective in all paths to edge surface.
Nano belt can be used for TFT, because their unique physical aspect is similar to the physical aspect of conventional monocrystal thin films.Use is similar to the CdS nano belt TFT that above-mentioned scheme manufacturing has the monocrystalline conducting channel.Figure 39 A represents CdS nano belt TFT.The micro-geomorphology image of 3D atomic force of the illustration 3902 expression nano belt TFT of Figure 39 A.
The electrical transmission that is used for CdS nano belt TFT is measured the typical n channel transistor characteristic of expression.The behavior of n raceway groove is consistent with the previous research about CdS body material and NW.Figure 39 B provides the I when the different grid voltage for CdS nano belt TFT
DS-V
DSRelation.Figure 39 B is illustrated in low source electrode and drain bias and at the saturated linear zone of higher biasing.V at 1V
DSThe time I
DS-V
GSRelation table is shown in the threshold value V of 2.0V
GSAbove substantial linear behavior.Slope in the linear zone provides the mutual conductance of about 2.4 μ S/ μ m when VDS=1V.Suppose parallel plate model, use C
G=ε ε
0It is 1.9fF that LW/h calculates grid capacitance, and wherein L and W are respectively channel length and width, and h is a dielectric thickness.Utilize the electric capacity that calculates, use I
DS/ V
DS=μ
eC
G(V
GS-V
Th-V
DS/ 2)/L
2Can release electron mobility is about 300cm
2/ Vs.Importantly, the mobility of this mobility value and monocrystalline CdS (about 300-350cm
2/ Vs) approximate match.
In addition, the exponential curve of IDS-VGS provides greater than 10
7Conducting cutoff and little sub-threshold value swing S to 70mV/10, shown in Figure 39 C and illustration thereof, approach the theoretical limit of 60mV/10.There is not geometric effect the swing of observed high carrier mobility and boy's threshold value ascribes high-crystal quality and the low surface state in these materials greatly to and resembles among the Si NW-TFT in CdS nano belt TFT.
Compensation logic
The ability of making p and n channel TFT is the key of building compensate for electronic, is well known that compensate for electronic is better than the circuit that is made of p or n channel transistor on performance.For this reason, constitute compensated inverter (logic M, NOT door) by be connected in series n raceway groove and p channel TFT.This compensated inverter is to form by p raceway groove Si NW-TFT that is connected in series (being made of 15 parallel NW) and n raceway groove CdS nano belt TFT.Device 4002 is shown among Figure 40.Figure 40 also provides the output-input (V of this inverter
Out-V
In) voltage response and the low constant high voltage output of importing of expression utilization.When input was increased to about 1.5V, output became 0V fast, and remains on low state than high input voltage the time.The most significant is that compensated inverter presents high voltage gain.The V that measures
Out-V
InThe difference of relation is represented greatly the voltage gain to 27, shown in the illustration among Figure 40 4004.This big gain confirms the high-performance of our device and the interconnection of the logic circuit array used for various large area electrons is crucial, need not recover at the signal in each stage simultaneously.At last, should be noted that, at the V that measures inverter in the output under without any the situation of load
Out-V
InRelation.When device is loaded in the side circuit, gain and to reduce.But, consider reproducibility and prophesy property with NW-TFT device described here of characteristic shown in Figure 36 A-D, the devices/circuits design by careful should realize the desirable voltage gain in the practical application.
NW-TFT during display and other are used
In the past twenty years, flat-panel monitor (FPD) appears in the modern electronic devices more prosaically.FPD is indispensable in a lot of new products, comprises cell phone, individual digital auxiliary system, digital camera, Portable gamma camera and notebook.In addition, expand greatly in expectation market, replace desktop PC and TV (TV) cathode ray tube (CRT) display because FLD is balanced.Active matrix liquid crystal display (AMLCD) is the flat display technology on the primary commercial, the roughly whole large-area flat-plate of domination monitor market.AMLCD also is called active matrix thin film transistor (AMTFT) sometimes, because the large area film transistor is the key technology that realizes the AMLCD of today.
Before the point-contact junction transistor through inventing thin-film transistor (TFT) in 13 years.Be published on Lilienfield in 1933 about first United States Patent (USP) of TFT.Up to 1960 early stage, a lot of industrial research laboratories comprise GE, RCA, IBM, Zenith, Westinghouse and Philips, have cooperated the TFT research and development effectively.Yet about 19th century the mid-1960s, mos field effect transistor (MOSFET) occurs, and becomes focus.Soon, the TFT research and development is dropped in the key industry laboratory.Because most of semiconductor technologies of today comprise the MOSFET technology, are the single-crystal wafer bases, so the size of substrate is determined by the size of obtainable wafer.So far, obtainable maximum wafer be～12 ".Therefore, this substrate dimension can not be suitable for the application of the big Substrate Area of needs.
At 19th century the mid-80, the appearance of LCD (LCD), particularly AMLCD has recovered the interest of TFT technology, and wherein said AMLCD need be positioned at the drive circuit on the big glass substrate.The early stage effort of TFT mainly concentrates on the II-VI semi-conducting material.This technology does not almost exceed outside the research laboratory, and this is because be difficult to control the II-VI semi-conducting material.For example, generally speaking, compare, more be difficult to form the crystalline phase of compound semiconductor with element.In addition, the doping of II-VI material such as CdSe is very difficult.The reliable dielectric material of deposit also is very difficult on the II-VI material.
Simultaneously, amorphous silicon hydride (a-Si:H) film has attracted big attentiveness, because it is as the potential application of the solar cell and the imaging sensor material of doing evil.When W.E.Spear and P.G.LeComber confirm that amorphous silicon material can mix, occurred changing in 1975.Soon, become the selection of the driving element of AMLCD, although bad transistor performance is arranged based on the TFT of a-Si:H.This technology almost is used in the commercial AMLCD display of large-screen of today exclusively.In the AMLCD display, a-Si TFT is fabricated on the glass substrate under the LCD pixel, and is used as the switch of changing pixel conducting/shutoff from the instruction of integrated circuit (IC) drive circuit by receiving.The IC drive circuit is installed in the periphery of substrate.Use the plasma auxiliary chemical vapor deposition method at an easy rate a-Si film crystalline substance to be deposited on the big relatively glass substrate at low temperatures.Should make use cheap glass substrate become possibility by low deposition temperature.Glass substrate is necessary, because the substrate transparency is that to be used for the backlight technology of this technology necessary.
Usually the field-effect mobility of a-Si FET is～1cm
2About/Vs, this has limited the performance of display.By a-Si is crystallized into polycrystal film, worldwide drops into a large amount of effort interiorly and studies towards the direction of improving a-Si TFT.The field-effect mobility of multi-crystal TFT and has been reported the value that has up to hundreds of between the mobility of a-Si TFT and single crystal silicon pipe.Polycrystalline is handled and need be reached 24 hours annealing to a-Si at 600 ℃ usually at present, has 10-50cm so that make
2The transistor of/Vs mobility.Except direct heat annealing, can study several method and convert the a-Si film to polycrystalline, comprise rapid thermal annealing, laser induced crystallization and transition metal induction annealing.For each emission cycle time, rapid thermal annealing uses the higher temperature from 700 ℃ to 800 ℃.Short cycle makes the latent lesion minimum to substrate.Yet, for this purpose, can not use cheap glass substrate.Laser annealing allows the small size amorphous silicon is heated rapidly to very high temperature, and the while is heated substrate indistinctively.Unfortunately, because small beam size, manufacturing is invalid to this method for large tracts of land.In addition, this technology is very difficult to control.
The crystallization of metal induction has in recent years attracted the very big attentiveness of people.Ni-based technology has appearred.Generally speaking, Ni-based technology has reduced the required annealing temperature of low heat treatment from about 600 ℃ to 500 ℃ and 550 ℃, and annealing time was reduced to several hours from～24 hours.Yet metal induction crystallization needs extra step transition metal to be deposited on the top of a-Si.The quality of metal film is depended in crystallization.The fault of construction of residual metal, metal silicide and complicated crystal boundary may cause the high leakage current in the transistor.
Many TFT can not replace the a-Si technology, because not compatible mutually with cheap glass substrate feasible polysilicon processing.The performance of multi-crystal TFT can not solve these problems of the device of being made by traditional monocrystalline silicon, because the difficulty of crystal boundary conduction and preparation high-quality polysilicon.Therefore, from various viewpoints, limited present obtainable TFT technology based on a-Si or p-Si.
New in recent years thin-film transistor technologies-organic tft-attracted a lot of attentivenesss of people.Have up to～1cm
2The organic tft of/Vs field-effect mobility is confirmed.By its performance, the K cryogenic treatment on organic transistor and the plastic is compatible mutually, although most of workpiece has used glass or oxide-coated silicon to carry out as substrate.Hold and, unfortunately, the performance of organic transistor is at present not near the performance of silicon.Therefore, the zone of the transistorized application of organic group is restricted.Silicon is prevented the satisfactory result that goes out that trial on plastics do not have, mainly be because two committed steps are the temperature required too high for the plastic with maximum glass transition temperature of silicon deposit and gate dielectric material deposit, be difficult to bear wherein above-mentioned two steps even be used to make amorphous silicon transistor.
Breakthrough in recent years in the Prof.Charles of Harvard university Lieber ' s laboratory is that the main investigator Dr.XiangfengDuan by this program carries out basically, has shown that semiconductor nanowires is learned for nanoscale electric and optoelectronics is excellence or desirable building block.ProfLieber ' s laboratory is verified utilizes control and adjustable chemical composition, physical size (for example diameter and length) and Electronic Performance (for example doping type and concentration), can synthesize the wide region of IV, III-V and II-VI family semiconductor nanowires in theory with the monocrystalline form.The diameter of nano wire can be controlled and change in the 2-100nm scope.The length of nano wire is in the 10-100 mu m range (Figure 41) usually.
Figure 41 A represent to give an example scanning electron microscopy picture of synthetic silicon nanowires of embodiment according to the present invention.The nano wire of Figure 41 A has the diameter of ten nanometer scale and reaches tens microns length.Scale rod shown in Figure 41 A is that 5 μ m are long.Figure 41 B represent to give an example according to the present invention lattice of independent Si nano wire of embodiment decomposes the transmission electronic micro-image.The nano wire example of Figure 41 B has monocrystalline core and the amorphous oxides cover layer that can control synthetically, and wherein the monocrystalline core has the continuous lattice along they whole length.
Longitudinal size that prolongs and the lateral dimension that reduces have nano wire to be used for the minimum dimension material of effective transmission of electric charge carrier.In addition, nano wire can be operated and use electric field or minisize fluid to flow scheme in solution flexibly and be assembled on the substrate, therefore various nanoscale electric and optoelectronics device and device array have been proved, comprise single nano-wire field effect transistor (FET), intersection nano-wire fet and logical circuit string, as logic OR, AND, NOT, NOR door and logic half adder circuit and storage array, and light-emitting diode, photoelectric detector and super-sensitive chemical/biological sensors.
Particularly, about the research of single nano-wire fet verified the field-effect mobility of Si nano wire up to 1500cm
2The field-effect mobility of/Vs, GaN nano wire is～1000cm
2The field-effect mobility of/Vs and n type InP nano wire is～4000cm
2/ Vs, all mobilities can be compared with their the monocrystalline counter pairs with simple doping content or be better than them.Observed high mobility value high brightness has shown the high-quality of this new material in nano-material.In addition, believe that these observed mobility value have only represented the low value of nano-material,, and can increase mobility value greatly by the passivation nanowire surface because almost do not attract much attention for surface passivation etc.Research proposal can suppress scattering events greatly owing to the quantum mechanical performance in the one dimension line of modulation doping.For example, Theoretical Calculation has foretold that for selecting its mobility of Doped GaAs nano wire be 3 * 10
8Cm
2/ Vs.Like this, if dopant is separated (for example, the molecule that mixes from shell surface doping or from core shell nano thread structure of nano wire) from conducting channel, then can realize high carrier mobility.
In a word, nano wire represents to be used for the building block of high mobility thin-film transistor.The nano wire film of random orientation has the carrier mobility comparable with polycrystalline silicon film material, and orientation nano line film presents comparable or be better than its mobility value with monocrystal material.
TFT is the key of a lot of modern electronic technologies of development.At present, be subjected to the driving in flat-panel monitor (FPD) market about the research and development of TFT, based on active matrix liquid crystal display (AMLCD).The true silicon of new TFT technology-on cheap large-area glass or plastic can be reformed present FPD technology, and opens the gate of the new industry of making the novel electron device.According to the present invention, the TFT that combines nano wire film has realized previous irrealizable target.
The thin-film transistor that is based on the oriented semiconductor nano wire (TFT) described here, and be formed on cheap glass or the flexible plastic substrate, have and the transistor comparable properties of making by monocrystalline silicon:
Field-effect mobility:
1500cm
2/V·s。
I
on/I
off＝10
7。
Threshold value＜2.5V.
Usually, use nano material to reduce the size of electronic device.Yet embodiments of the invention use nano material to make electronic device faster and/or bigger.Although the mobility of nano wire is very high separately, single nano wire can not provide macroscopical electronic application required enough current densities.In order advantageously to utilize the high mobility of nano wire,, make a lot of nano wires that comprise hundreds of or several thousand nano wires cross over (for example between source electrode and the drain electrode) between the electrode with orientation nano line thin film fabrication transistor.This has realized high mobility and high current density transistor on the big flexible substrate.
Figure 42 being used for synthetic and realizing the flow chart of the technology of high mobility thin-film transistor of embodiment of representing to give an example according to the present invention.High mobility nanometer monocrystalline wire material at high temperature is synthesized, and aims on desirable substrate then, thereby forms orientation nano line film.Further it is carried out photoetching process then, thereby form thin-film transistor with the conducting channel that is parallel to bobbin.Monocrystalline conducting channel along nanowire length has guaranteed that the TFT that obtains has high mobility.
In this scheme,, can make silicon nanowires core-shell structure, as shown in figure 43 with monocrystalline core and dielectric passivation (shell) according to embodiment for example of the present invention.At first chemical vapor deposition (CVD) method and the direct oxidation afterwards of the gold nano grain catalysis by using development in recent years come the synthesis of nano line.This method comprises silicon (Si) and GaAs (GaAs) applicable to various semiconductor nanowires.Here with silicon nanowires as a reference in order to represent purpose.Nanowire suspended in solvent with what chemically synthesize, as ethanol, allow afterwards technology and processing.From the formulations prepared from solutions individual layer nano wire film of these nano wires that suspending, it has the line that is arranged essentially parallel to substrate orientation.At last, can apply the Metal Contact that is used for source electrode, drain and gate, thereby make nano wire tft array with the conducting channel that is parallel to bobbin by photoetching treatment.
The invention provides new substantially strategy, and caused the innovation of technology kind and processing, feature performance benefit towards high performance thin film transistor development:
The monocrystalline conducting channel: in this TFT device, a plurality of nano wires are present in all paths from source electrode to drain electrode (being similar to the logic bridge) abreast, thereby the monocrystalline conducting channel of charge carrier is provided.This causes the high carrier mobility that can compare with the body monocrystal material, and this utilizes amorphous or polycrystalline silicon material not to realize.This mainly is because near the trapped state of the prolongation the crystal boundary causes near remarkable carrier depletion crystal boundary and crystal boundary scattering (referring to Figure 44 A-44C) for these materials.
Figure 44 A-44C represents the schematic diagram by the thin-film transistor (TFT) of amorphous silicon (Figure 44 A), polysilicon (Figure 44 B) and aligning nano wire film (Figure 44 C) manufacturing.In a-Si and poly-Si base technology, electric charge carrier has experienced repeatedly crystal boundary scattering, therefore limited attainable carrier mobility (carrier mobility of a-Si for～＜1cm
2/ Vs, the carrier mobility of poly-Si is～＜100cm
2/ Vs).On the other hand, in nano wire base technology of the present invention, electric charge carrier passes the transmission of TFT raceway groove along a plurality of monocrystalline path, and has realized thus having near monocrystal material (～1000cm
2/ Vs) the TFT of carrier mobility.
Outer (off-substrate) high-temperature process of substrate: at high temperature outside substrate, prepare semiconductor nanowires and gate dielectric, at room temperature it is put on the substrate then.Therefore, the hot property of substrate will can not become the limiting factor of high-temperature process.Therefore, allow high quality crystal material and gate dielectric, this is the key of high-performance reliable devices function.In addition, by combination gate dielectric shell as thin as a wafer around each independent nano wire, rather than on device in conjunction with the external gate oxide of one deck, can simplify processing significantly, simultaneously owing to reduced required conducting voltage as thin as a wafer and near perfect shell performance.
The solution handlability: different with the body semiconductor wafer, nano wire can be suspended in the solution, then with its deposit be fixed on the actual any substrate of large tracts of land.Like this, realized high-performance semiconductor material on the important substrate (for example, plastics, glass) of a lot of technology.This further can carry out the rolling manufacturing of high-performance electronic device by ink-jet or screen printing technique.
Mechanical flexibility: because minimum diameter and aspect be than (＞1000), nano wire with for example little to 10 microns radius of curvature and have excellent mechanical flexibility.Be deposited on the substrate of big flexibility by the dense film with the nano wire of mechanical flexibility orientation, the structure that obtains has the excellent electrical that can compare with bulk single crystal semiconductor, and can extend on the large tracts of land arbitrarily, and the same with optical fiber flexible.In addition, the mechanical flexibility of nano wire can form the high-performance electronic device on coarse relatively substrate such as most of plastics, and it almost is impossible wherein using amorphous or polysilicon membrane.
Minimize device size: the intrinsic minor diameter of nano wire and length allow control TFT channel width and length easily.Can realize reducing the transistor of size, this is restricted under the situation of polycrystalline silicon device.In addition, it is reduced in size that the intrinsic high mobility of nano-material allows transistor to form, and still keeps the current value of function simultaneously, and allow the high density on the large tracts of land substrate integrated, and this is impossible for traditional amorphous silicon or polycrystalline silicon material.
Processing applicable to other high mobility material such as GaAs nano wire: the ability of silicon nanowires can prolong and put on other intrinsic high mobility material, as III-V family material, comprises GaAs and InAs nano wire.Like this, the superelevation mobility material is feasible, and a lot of new application also is feasible.Can realize even higher mobility by the trajectory conduction that utilizes potential quantum effect-nano wire, as described further herein.
Nano wire is synthetic: in some embodiments, use the nano wire with even physical size and chemical dopant distribution can realize the behavior of reliable and reproducible TFT device.This control is confirmed in very small dimensions in 1 inch pipe furnace.Have 8 inches semiconductor pipe furnaces, they can make large-sized nano wire.More difficult in control uniformity on the large volume than control uniformity on small size.The control diameter of silicon nanowires and diameter distribute and distribute definite by the diameter of gold colloid and diameter.Can use commercially available gold colloid.The length of nano wire depends on the time of growth conditions-temperature, vapour pressure and growth.The problem of these problems and crystallization and doping content can solve by change and meticulous adjustment growth conditions.
Dielectric oxide/nitride coatings: the quality of gate dielectric coating is very important for nano wire TFT performance.In the planar semiconductor technology, there is the technology that is used to form the high-quality gate dielectric.Yet the free of pinholes gate dielectric that forms uniform thickness under the situation of unqualified crystallographic direction around nanowire surface is a challenge technically.This problem can solve from different viewpoints.By after silicon nanowires growth, directly carrying out slow thermal oxidation, can use technology to produce silica coating less than～2nm.The key of controlled oxidation thing coating is the nano wire with level and smooth with consistent surface texture.Suboxides is handled and is helped to avoid focus and produce the free of pinholes shallow layer.Perhaps, the plasma that has applied the nano wire of silica assists direct nitrogenize can be used for producing nitrogen oxidation or nitrogenize coating on nanowire surface.
Surface state and catch electric charge: because its high surface and body atomic ratio, surface state, catch electric charge and dangling bonds influence nano wire, this has significantly limited device performance.Can use a large amount of strategies that surface state is minimized, be included under the inert atmosphere or the direct heat under hydrogen/formation gas atmosphere annealing and after thermal annealing, in hydrogen plasma, annealing.These and other strategy has further been introduced in the above.
Large-area nano line thin film deposition: the development that is used on the large tracts of land substrate the scalable scheme of preparation orientation nano line film is very important to the final successful implementation of this new technology.For example, can adopt fluid Alignment Process or LangmuirBlogette film scheme that the individual layer nano wire is placed on glass or the plastic.
Ohmic contact: because small area of contact and complicated interface state, carry out reliable ohmic contact with nano wire and be very difficulty.Surface chemistry between Metal Contact and the silicon and physical property are the important technology zones about ohmic contact.Successful key is accurately to control metallization process and metallization process surface clean technology before.Can use three kinds of possible metallization scheme one to utilize e beam evaporation Ti-Au, Ni and Al.Can adopt various other technologies, comprise that ion gun cleaned or HF remove surface dielectric before being etched in the metallization of source electrode-drain electrode.
The present invention allows the innovation and development on large area electron is learned, and has size and the flexible film TFT that the performance that can compare with inorganic single-crystal semiconductor material and plastic electronic learn electronic device of new generation is provided by providing.
The TFT nano-wire transistor can manufacture has the transistorized performance characteristics that approaches by traditional monocrystalline silicon manufacturing, the most significant is can be manufactured on very big glass or the plastic, and this will realize that the oversize high density is integrated and true silicon is provided on plastics technology.The potential application of this technology is very widely, comprises nano wire TFT is attached in the LCD (LCD).Nano wire TFT has much smaller than the footprint of a-Si TFT, permission increase picture element density-for example, the super-high density display.Less TFT has also stopped less light and has had higher aperture ratio.Utilize nano wire TFT, peripheral drive circuit can be integrated on the edge of glass substrate simultaneously, has simplified manufacturing process greatly and has reduced cost.Nano wire TFT needing to go for miniscope, digital projector and the high density imaging device of high picture element density.In addition, silicon technology has been realized development light, the high information density electronic device on the actual plastics.For example, the present invention has realized calculating and the demonstration on single plate, and has realized wear-resisting electronic device, this to the police, to be operated in soldier on first-aider in the place, the battlefield and space and remote probe all be extremely important.
In the broader sense, the present invention allows the engineer to develop the electronic material of performance and material behavior with any industrial related semiconductor material on any backing material.This technology makes the engineer be totally independent of architectural characteristic (that is, its flexibility, shape, size and treatment characteristic) and the function/characteristic (that is, electric conductivity, doping, mobility and conducting voltage) of design electronic material.Electronic Performance has been determined in the selection of the physical characteristic of semiconductor nano-wire devices (for example, composition, diameter, length, crystallinity and density); Performance, the physical property of the substrate that can fully independently select.Simultaneously, the high-performance of nano wire film, the property handled and potential low cost produce general flexible electronic platform easily, and the drive circuit, RFID tag, the large tracts of land biology sensor that not only can be used for high density display and microcosmic display array, and can be used for a lot of new application the on the plastics, as small card, logic be used for the memory of abrasion-proof computer, and be used for a lot of prior application that will be identified.
Three developing stage are described below: (1) silicon nanowires is synthetic; (2) orientation nano line thin film deposition; (3) nano wire film transistor (TFT) is made.
(1) silicon nanowires is synthetic
Step 1: following introduction is used for the synthetic upgradeable technology of silicon nanowires.
For the purpose of representing, provide the example of nanowire suspended liquid, nano wire type and nano wire concentration: the 1mg/100cc in ethanol, p and n doping 60nm diameter silicon nano wire have core-shell structure.Nanowire core is a monocrystalline silicon.The nano wire shell is～thick free of pinholes Si oxide of 2nm or nitrogen oxide covering the length of～20-50 μ m.
The synthetic CVD technology of using gold nano grain catalysis.Under the total pressure of 20-50 torr, make pre-definite precursor gas mixture, SiH in He
4And B
2H
6Or PH
3Through being deposited on the catalyst gold grain on the oxide coating silicon substrate, simultaneously gold nano grain is heated to～450 ℃ temperature.By contact SiH with gold nano grain
4/ B
2H
6Decompose, and Si and B atom diffusion are in gold nano grain and produce liquid alloy and drip.In case reach supersaturation, the Si/B deposited atom comes out and begins to carry out nanowire growth.Supply with SiH continuously
4And B
2H
6Allow nano wire to grow continuously, till stopping intentionally, perhaps till " death " by local condition's variation generation.The quality of nano wire depends on control and the growth conditions that the quality of gold nano grain, the gold nano grain on substrate distribute, and comprises temperature, SiH
4And B
2H
6Or PH
3Ratio, SiH
4Dividing potential drop and time of in reactor, stopping of precursor gases.
In the current embodiment that gives an example, control 8 uses a computer " the semiconductor stove realized growth.4 " silicon wafer of coating silica is used as substrate.
Be presented in 4 below " technology of deposit gold nano particle equably on the wafer.
Use the gold colloid of commercially available 60 nanometer diameters.Target is in order to realize the even deposit of gold nano grain with the density between every micron sq of 2-4 particle.Key is to minimize the gold grain group to form.Particle swarm may cause undesirable bigger diameter nanowire growth.Deposit can be adopted spin coating and self-assembling method.
Spin coating is quite simple technology.Deposit density can be by changing gold grain concentration in the precursor colloid, silicon wafer surface chemistry manipulation and change rotary speed and control.The defective of spin coating can be the low utilization ratio of gold colloid solution.If of course, can use the recirculating process of fabrication stage.
Self assembly relates to some purposes of setting up chemical.4 " surface that applies the wafer of silica can utilize that (3-aminopropyl trimethoxysilane (APTMS) or (3-sulfydryl propyl group)-trimethoxy silane (MPTMS) come functionalization, contact with 60 nm of gold colloidal solution then.Gold grain is assembled on the surface.The difference between two kinds of different chemical materials relatively, and can adopt the possibility of controlling gold grain density by control time of contact and the gold grain concentration in contacting solution.
Step 2: optimization nanowire growth condition: the necessary optimization of growth parameter(s) comprises SiH
4And B
2H
6Or PH
3Ratio, growth temperature and growth time.The diameter of silicon nanowires distributes and can be distributed by the diameter of gold nano grain to determine.Commercially available 60 nm of gold colloids can have ± and 10% diameter distributes.Identical distribution is our target to nano wire.Gold nano grain can split into littler nano particle in the nanowire growth of minor diameter more, and this depends on growth conditions.Growth conditions can be optimized so that this incident is minimum.Given growth conditions can be by changing growth time class control nanowire length.The crystallinity of silicon nanowires is also relevant with growth conditions with concentration of dopant.They can be with other important nano-meter characteristic optimization and control.
Another problem is the SiH under growth conditions
4And B
2H
6Thermal decomposition so that the growing high-quality silicon nanowires.This decomposition may produce undesirable nano silicon particles in product.In their small size growth, be not easy to eliminate thermal decomposition, but can it minimized by changing growth conditions.
Step 3: be used for the processing that dielectric film applies: the quality of dielectric coated is to determine the key factor of the performance of nano wire TFT.For plane monocrystalline silicon, again for non-clean and polysilicon, set up the method that is used for the high quality dielectric coating well and consolidated the principles of science afterwards.Generally speaking, method can be divided into the direct oxidation/nitrogenize that is used for the silicon oxide/nitride medium and be used for the CVD deposit of the dielectric coated of all kinds.The specialized structure performance of silicon nanowires causes selecting direct oxidation/nitrogenize rather than deposition process.Yet deposition process also can be used as system of selection.
Can used thickness be～the silicon dioxide shallow layer of 2nm.The direct oxidation of 60 nanometer diameter silicon nanowires can be carried out in the nanowire growth stove.Finish after the nanowire growth, reaction gas mixtures may from reaction tube exhaust and under the temperature below 150 ℃ the mixture with oxygen (5%) and helium additional.Make the temperature of stove be elevated to value between 300 ℃ and 800 ℃ lentamente then.Oxidizing temperature and oxygen are with the ratio of helium, the dividing potential drop of oxygen and the thickness that oxidization time is determined the silica of generation.These conditions can be optimized, till the thickness of acquisition～2nm.Wish to carry out eremacausis, so that make defective, dangling bonds minimum, wherein these defectives and dangling bonds will cause catching electric charge and state.
If the performance of silica shallow layer is dissatisfied, can adopts the direct nitrogenize of the nano wire of silica-coated, thereby produce the nitrogen oxide coating.Higher dielectric constant makes nitrogen oxidation and nitrogenize produce more attractive coating.Also can adopt and use NO or NH
3The auxiliary direct nitridation method of plasma of gas.
Step 4.The technology that is used to remove surface state and catches electric charge: surface state may be a serious problem with catching electric charge for nano wire, because their surface and body atomic ratio are very high.The technology that is used for addressing this problem is known in the semi-conductor industry that is used for plane treatment, and these technologies are suitable for nano wire.At first, we can use the test of single nano-wire devices to anneal in hydrogen as the feedback of constrained optimization.
Step 5.The nanowire suspended liquid of preparation in the ethanol: with dielectric coated apply and annealing after, from 4 " (or other size) wafer takes out silicon nanowires and suspends ethanol by ultrasonic wave.Nano wire can condense and be precipitated out.Surfactant such as TritonX-10 can be used for stabilisation.
Step 6.Nano wire characterizes: the structure of nano wire and electrical property can be characterized.Can use SEM and AFM to be used for their length and the sign that distributes of diameter, high-resolution TEM be used for the dielectric film coating thickness and uniformity, transmission measurement, be used for the EFM scanning grid AFM of their electrical property.Characterization result can feed back, and is used for meticulous adjustment synthesis program and condition.
(2) orientation nano line thin film deposition
The scale method that is used for the deposit of orientation nano line single thin film will illustrate below.
Result: 4 " * 4 " aligned single-layer 60nm silicon nanowires film on glass or plastics such as the polystyrene.
The orientation nano linear array is to guarantee the critical condition of source electrode and the monocrystalline conducting channel between the drain electrode of nano wire TFT, and this just makes high field-effect mobility become possibility.In order on large tracts of land, to obtain height-oriented nano wire film, can adopt two basic schemes as parallel strategy, fluid mobility program and Langmuir-Blodgett film scheme.
Step 1.The general chemical substance that is used for the nanowire surface modification: the target of this task is that a kind of one group of general technology of development is used for the modification surface of silicon nanowires, thereby be manufactured on the stabilized nano line suspension in the non-polar solven, this is necessary in order to put into practice Langmuir-Blodgett film scheme.We can adopt alkyl-trimethoxy silane, thus on nanowire surface fixing hydrophobic alkyl, as octyl group.This can make nano wire can be suspended in organic solvent such as the octane.These surface bases may have adverse effect to the electrical property of nano wire.When needed, can develop the method (for example, oxygen plasma or ozone clean technology) that after nano wire film forms, is used for removing organic molecule from surface of silicon nanowires.
Step 2: be used for the technology that substrate surface is handled: it is very important that the surface chemistry of substrate bonds on the substrate nano wire.Under the situation of glass substrate, this expropriation of land of nano wire has good viscosity, because the nano wire of glass and silica-coated also has identical surface chemistry.Can carry out routine cleans and rapid plasma body oxygen plasma etch.For the hydrophobic plastic substrate, we can at first carry out the oxygen plasma oxidation, use 3 aminopropyl trimethoxysilane that 3-aminopropyl individual layer is fixed on the surface then.Can at first test this rigid polystyrene plate.If flexible membrane such as a slice polypropylene can be then used in success.
Step 3: fluid stream is aimed at: aim at for fluid, we use the nano wire that is suspended in the ethanol.Fluid stream scheme has been used to utilize hundreds of micron width and a few inchage to aim at nano wire on yardstick.In principle, fluid stream is aimed at and can be extended to very large area, as the log of korneforos.In order to be implemented in the aligning on the large tracts of land, can to use fluid channel with the lateral dimension that can compare with substrate dimension.The height of raceway groove can control to less than 500 μ m, thus the close substrate of the major part of nano wire solution, and near the shear flow substrate surface has been realized along the aligning of the nano wire of flow direction.Figure 45 represents the schematic diagram of aiming at the element of fluid of nano wire on large tracts of land according to the embodiment of the invention.The detailed method and system example that is used for this element of fluid alignment scheme was described with reference to fluid mask 1500 in front, shown in Figure 15 A and 15B.The entrance and exit of element of fluid should careful design, so as to guarantee along with pass whole fluid channel and carry out evenly flowing.
Can use various nano wire solution concentrations and flowing time to control nanowire surface density/coverage rate on the substrate.When wishing, substrate can be functionalized, so that strengthen the compensating action between substrate and the nano wire, thereby realizes higher surface coverage.System research can be carried out so that be implemented in the deposit of lip-deep reproduction nano wire.Can utilize light microscope and/or scanning electron microscopy to study surface coverage, and can develop rational statistical project so that characterize surface coverage quantitatively.These researchs are at first carried out on glass substrate and the functionalization plastic are implemented.
Should note and control several critical problems carefully: 1) being used for rubber seal (dimethyl silicone polymer) fluid channel that small size aims at can not apply on inch to tens inch size, because this raceway groove is because the flexible characteristic of PDMS and may be potentially at central region sinking.Can or apply the periphery that the PDMS thin layer seals raceway groove with the O ring.2) on this large scale yardstick, pass and along whole raceway groove fluid can not be uniformly, deposit is undesirable for the even line for this.In order to realize evenly flowing, should pay special attention to design and control flows bulk channel entrance and exit.Also should careful attention arrive design solution traffic program.Programmable automatic syringe pump can be used for guaranteeing constant solution travelling speed.Realizing there is the high-tech risk aspect the deposit of lip-deep even line.For example, may under the situation of careless design raceway groove inlet, in aiming at, the micro-raceway groove fluid of being everlasting observe this phenomenon than having higher nanowire density near the zone outlet near the zone of raceway groove inlet.Variable density can compensate by alternately be inverted flow direction during Alignment Process.Perhaps, can adopt the Langmuir-Blodgett membrane technology, this can be provided in the even aligning on the large tracts of land.Yet, the initial testing that the result who aims at from fluid stream can still be used for the device manufacturing and characterize.
Step 4.Langmuir-Blodgett film:, can use large scale assembling scheme based on Langmuir-Blodgett (L-B) film in order to realize the even aligning on the large tracts of land.Langmuir-Blodgett aims at the film that has been used to form nano particle and aims at nanometer rods.This scheme can extend to the aligning of nano wire, so that make orientation nano line film.Figure 46 schematic diagram that the nano wire of use Langmuir-Blodgett film on large tracts of land of embodiment aimed at of representing to give an example according to the present invention.
In this scheme, nano wire at first is functionalized and is suspended in (above-mentioned steps 1) in the non-polar solven.Then this nonpolar nanowire suspended liquid is transferred on the wafer surface in the L-B groove.Under fully low density, nano wire forms has the isotropic distribution of random orientation.Along with compressive surfaces, becoming is difficult to more point out that random direction and nano wire have experienced to the more regular anisotropy transition mutually with non axial symmetry, thereby has to row or smectic phase (seeing Figure 46).In fact, in Monte-Carlo simulation be used for having observed this point in the actual experiment (for example, length-width ratio=length/diameter＜10) that the case of film nano rod aims at.Therefore can realize the aligning of nano wire on wafer surface on the large tracts of land.In addition, the formation of the parallel alignment and the orientation nano line film of direction capillary force between the nano wire and van derWaals attraction further enhancing nano wire.Because the remarkable big length-width ratio (for example greater than 500) of nano wire, nano wire may experience significant bigger resistance, thereby rotate to parallel to each other from random orientation.This potential problem can for example solve by certain prealignment of induction before surface compression.Can also adopt a large amount of strategies to realize this target.For example, fluid technology can make up so that realize some prealignment.Electric field can also be applied so that the aligning of splicing thread.Then the aligning nano wire on the wafer is transferred on the desirable substrate.Nanowire density can be controlled by the ratio of surfactant and nano wire with by the surface compression amount.On wafer surface, form and aim at after the nano wire film, it can be transferred on any substrate.Can use different host-host protocols to avoid interference aligning during the transmission.Surface coverage can use above-mentioned same approach to characterize.
(3) TFT makes and characterizes
Make silicon nanowires TFT in present example, it has～1000cm
2The field-effect mobility of/Vs, greater than 10
7Conduction and cut-off than and less than the threshold voltage of 2.0V, as described below.
Result: 1000 * 1000 arrays of the silicon nanowires TFT on glass substrate and polystyrene substrate.
Although used single nano wire to confirm FET as conducting channel, these FET apply the big-difference that exists in usually between each device.This difference may be because the synthetic control of shortage, the reliable means that forms ohmic contact and the surperficial trapped state of big face cause.Realize that reliable and controllable electrical characteristics all are crucial for any practical application of TFT.In order to realize the high level control of device property, the Electronic Performance of nano wire must be highly reproducible and controllable separately.The electron mass control of nano wire can use single nano-wire fet structure to characterize and optimization.Utilize the Electronic Performance of control well, can on the different substrates that comprise glass and plastics, make the nano wire film transistor device.
Step 1.Use single nano-wire fet to be used for the technology that reliable metal flower is handled:
Single nano-wire transistor FET device can be used as the test media thing, so that develop reliable metalized.Can use electron beam printing or photoetching at SiO
2Make single nano-wire fet device on the/Si surface.Substrate silicon can be spherical back of the body grid, and two metal electrodes can be used as source electrode and drain electrode (Figure 47).The metallization before, can carry out suitable surface clean operation, thus from nano wire film remove oxide and guarantee nano wire and contacting metal between good contact.The planar silicon technology can be used as the reference point of selecting suitable contacting metal and technology agreement.Various strategies comprise ion gun cleaned, or the HF etching is removed surface dielectric before being used in the metallization of source electrode-drain electrode.Can make the test of deposited by electron beam evaporation or sputtering technology and optimize different metallization scheme (for example, Ti/Au, Ni/Au, Al).Have been noted that the surface treatment (through the annealing of thermal annealing and hydrogen plasma) of nano wire and to the influence of Electronic Performance.The device behavior can use the semiconductor analysis instrument to characterize.Comprise that the two ends relevant with grid are measured and each measurement structure and the electric power microscope of four-terminal measurement can be used for the characterizing device behavior.Can strict in theory analogue device structure, thus all crucial transistor parameters obtained, comprise that carrier concentration and mobility, threshold voltage, conduction and cut-off compare etc.The result who is produced by electrical testing and theoretical modeling can further feed back, thereby optimizes metalized, till obtaining reliable process.This may be the standard metallization that is used to make nano wire TFT.Single nano-wire fet also can be used for the nano wire qualification test.In view of the synthesis condition of nano wire and electronic parameter can the composition data storehouses, and this database can be further used for guiding more controlled synthetic and device fabrication.
Figure 47 represent the to give an example plane graph and perspective view of single nano-wire field effect transistor of embodiment according to the present invention.Single nano-wire fet is used as basic device geometries, so that characterize and optimize the electrical transmission performance of independent nano wire.Scanning electron microscopy (SEM) image of each perspective representation typical device shown in Figure 47.In this device, silicon substrate can be used as back of the body grid, and two metal electrodes can be used as source-drain contact.
Step 2.Spherical back of the body grid type nano wire TFT: the target of this task is in order to confirm and to characterize the nano wire TFT that uses above-mentioned identical device architecture to be made by the nano wire film with different surfaces density.The reliable protocol that is used to make single nano-wire devices identification can be applicable to the nano wire film transistor.Can use nano wire film to make the TFT device, thereby utilize the nano wire of the variable of bridge joint source electrode and drain electrode to realize independent TFT device with different surfaces density.Can use the semiconductor analysis instrument to characterize device behavior as the function of nano wire film density, as current value, conduction and cut-off ratio, threshold voltage and grid leakage current, and the analogue device behavior comprises mobility value so that calculate critical device parameters in theory.And then the simulation can be used for the guide device structure Design, thereby realize desirable device function.These researchs can use silicon as carrying on the back grid at SiO
2Study on/Si the substrate, because this is relatively easy mode for device manufacturing and simulation.When this task termination, can form reliable agreement, so that make TFT with variable nanowire density and controllable devices behavior.
Step 3.Local grid type nano-wire fet on glass and the plastics: for example be presented in and make nano wire TFT and tft array on glass and the plastics, target is realization～1000cm
2Mobility about/Vs.Adopted the TFT of the grid that uses local composition.Use Si/SiO
2Or Si/Si
3N
4Core-shell nano wire is made local grid TFT structure, wherein SiO
2Or Si
3N
4Shell can be used as gate dielectric, and additional metal electrode can be used as grid (Figure 48).
Figure 48 A and 48B represent the transistorized perspective view of local grid nano wire film according to the embodiment of the invention.Figure 48 A represents to have the grid that forms and the source electrode that forms from the top of nano wire film and the cross structure of drain electrode below nano wire film, wherein removed dielectric passivation.Figure 48 B represents to have the TFT structure of all contacts that form at the nano wire film top.
Can test bottom contact and contact grid structure, thereby assurance lowermost switch voltage, maximum conduction and cut-off compares and leakage current of the end with the top.All these tests are all at first carried out on glass substrate, put on plastics then.The result is, can be with controllable devices characteristic (carrier mobility～1000cm on glass and plastic
2/ Vs, controlled threshold value (less than 2.5V), current value (1 μ A-1mA) and conduction and cut-off are than (greater than 10
6)) the independent nano wire TFT of manufacturing.
Step 4.Integrated nano wire tft array: discern reliable agreement owing to utilizing desirable device property to be used on glass and selected plastics making independent local grid TFT, so it can be applied to 4 * 4 " make integrated TFT device array on glass and the plastic.Can use multistage photoetching to come patterning nano line film and the source-leakage, the grid that are formed for integrated tft array.Should pay special attention to accurate device architecture design and device fabrication design.The mature technology of amorphous silicon and multi-crystal TFT can be used as the reference point of this design.When finishing, can make 1000 * 1000 nano wire tft array, and further constitute logical circuit, thereby make logic function.
The electronic device that comprises nano wire layer is with the nano wire layer of monocrystalline, amorphous and polycrystalline semiconductor material combination
In another program of the present invention, can use the structure that comprises a plurality of nano wire film layers to make electronic device.In other words, can the stacked multilayer nano wire film, as above-mentioned each embodiment, thereby make device.
For example, in an embodiment, more than first nano wire of deposit on substrate, thus the first nano wire film layer formed.More than second nano wire of deposit on first nano wire film, thus the second nano wire film layer formed.Any amount of additional a plurality of nano wires also can be deposited on the nano wire film layer of front, so that form the additional film layers of piling up.
In order to represent purpose, with reference to two thin layer embodiment, first and second layers nano wire differently mixes.For example, ground floor can comprise the nano wire that p mixes, and the second layer can comprise the nano wire that n mixes.On the joining/intersection area between the nano wire of first and second thin layers, form like this, thus as knots such as p-n junctions.
Can form contact, thereby on the knot performance basis, form electronic device.For example, in diode embodiment, the contact of first on the nano wire that is coupled to the first film can be formed, and second contact of the nano wire that is coupled to second film can be formed.Like this, can form two ends p-n diode.Can utilize same way as to form three ends and other terminal number measuring device spare, as transistor.
Notice the preferred aligning parallel to each other of nano wire of the first film layer, and the preferred aligning parallel to each other of the nano wire of second thin layer.But in selection scheme, the nano wire of first and/or second thin layer can random orientation.
In another embodiment, form electronic device, comprise and mix the nano wire single crystalline semiconductor structure.For example, form single crystal semiconductor bar/film.For example, can pass through etched wafer,, form the monocrystalline bar as silicon-on-insulator (SOI) wafer.In addition, single crystal semiconductor bar/film can form and have according to special application required Any shape or size.At a plurality of nano wires of the deposited on top of bar.On the joining between nano wire and the single crystal semiconductor bar, form knot, as p-n junction.For example, can utilize first kind of mode doped single crystal semiconductor bar (for example n or p mix), and with different modes (for example, p or n doping) doped nanowire.Like this, can form p-n junction in the intersection area of bar and nano wire.
Can form contact, so that based on the performance of these knots and make electronic device.For example, in diode embodiment, can form and be coupled to the contact of first on the single crystal semiconductor bar, and can form second contact of being coupled to nano wire film.Like this, can form two ends p-n diode.Can utilize same way as to form three ends and other terminal number measuring device spare, as transistor.
The preferred aligning parallel to each other of the nano wire of a plurality of nano wires, but also can random orientation.
In another embodiment, form the electronic device that comprises mixing nano wire-amorphous/poly semiconductor structure.For example, amorphous or polycrystalline semiconductor thin film can be deposited on the substrate.A plurality of nano wires are deposited on the film pattern.On the joining/intersection area between nano wire and the amorphous/polycrystalline semiconductor thin film figure, form knot, as p-n junction.For example, can utilize first mode (for example n or p mix) doping amorphous or polycrystalline semiconductor thin film, and with different modes (for example, p or n doping) doped nanowire.Like this, can form p-n junction in the intersection area of amorphous or polycrystalline semiconductor thin film and nano wire.
Can form contact, so that based on the performance of these knots and make electronic device.For example, in diode embodiment, can form and be coupled to the contact of first on amorphous or the polycrystalline semiconductor thin film, and can form second contact of being coupled to nano wire film.Like this, can form two ends p-n diode.Can utilize same way as to form three ends and other terminal number measuring device spare, as transistor.
The preferred aligning parallel to each other of the nano wire of a plurality of nano wires, but also can random orientation.
In the embodiment that gives an example, can use these structures to make luminescent device.For example, can select the luminescent semiconductor nanocrystal line in the predetermined ratio of nano wire, as the luminescent semiconductor nanocrystal line of emission red, green and blue light.The nano wire of selecting in predetermined ratio may be combined in the solution.The nano wire mixture flows through monocrystalline, amorphous or poly semiconductor bar/film.As mentioned above, can form contact, thereby make the luminous electron device, as the light-emitting diode in the two contact/end-apparatus spares.According to the selected mixture of Illuminant nanometer line, can launch the light of any color by the luminous electron device, comprise white light.
Application of the present invention
According to embodiments of the invention, each electronic device and system can be in conjunction with the semiconductor with nano wire film or other types of devices.Introduction is used for example application more of the present invention below, and this is that example just is used to represent purpose, rather than restriction.Application described here can comprise the aligning or the non-aligned film of nano wire, and can comprise the compound or the non-laminated film of nano wire.
Semiconductor device of the present invention (or other types of devices) can be coupled on the signal of other electronic circuit, and/or can integrate with other electronic circuit.Semiconductor device of the present invention can be formed on the big substrate, and it can separate or cut into littler substrate afterwards.In addition, on big substrate (that is, basically greater than the substrate of conventional semiconductor wafer), semiconductor device formed according to the present invention thereon can interconnect.
The present invention can be combined in the application that needs single semiconductor device and be attached in a plurality of semiconductor device.For example, the applicable especially large tracts of land of a plurality of semiconductor device, the macroscopical electronic substrate of forming thereon of the present invention.This electronic device can comprise the circuit of display driving that is used for active matrix liquid crystal display (LCD), organic LED display, field emission type display.Other active display can be formed by nano wire polymer, quanta polymer compound (this compound can be used as emitter and active driving matrix).The present invention also can be applicable to small library, credit card, large tracts of land sensor array and radio-frequency (RF) identification (RFID) label, comprises small card, small-sized inventory tag etc.
The present invention also uses applicable to digital and analog circuit.Particularly, can be applicable to need ultra-large integrated application on the large tracts of land substrate in the present invention.For example, the hungry nano wire film embodiment of the present invention can implement in logical circuit, memory circuit, processor, amplifier and other digital and analog circuit.
The present invention can put on photovoltaic applications.In these are used, use the electrically conducting transparent substrate to strengthen the photoelectric properties of specific light electric device.For example, this electrically conducting transparent substrate can be used as flexibility, the large tracts of land alternative of tin indium oxide (ITO) etc.Substrate can apply with nano wire film, these nano wire films form to such an extent that have a large band gap, promptly greater than visible light, thereby she should be non-absorbent, has the HOMO or the LUMO that aim at the active material of the photoelectric device that will be formed on its top and is with but should form.Transparent conductor can be positioned on the both sides of absorbing light electric material, thereby electric current is transported from photoelectric device.Can select two kinds of different nano-materials, a kind of have a HOMO that aims at photoelectric material HOMO band, and another kind has the LUMO that aims at the LUMO of photoelectric material.The band gap of two kinds of nano-materials can select to make its band gap much larger than photoelectric material.According to present embodiment, can the light dope nano wire, so that reduce the resistance of nano wire film, allow substrate to keep not absorbing basically simultaneously.
Therefore, military and wide region consumer products can be in conjunction with nano wire film embodiment of the present invention.For example, these products can comprise pilot, phone (for example honeycomb and standard), radio system, television set, electronic game computer and games system in personal computer, work station, server, network devices, operating electronic device such as PDA and the palm, home security system, automobile, aircraft, ship, other family expenses and the commercial device etc. of using.
Conclusion
The front by the agency of each embodiment of the present invention, it should be understood that they just for example, do not play the qualification effect.Those skilled in the art obviously can understand under the situation that does not break away from the spirit and scope of the present invention can carry out various modifications in form and details.Like this, scope of the present invention should not be subjected to the restriction of any above-mentioned exemplary embodiments, but should just limit according to appended claims and equivalents thereof.
Claims (233)
1, a kind of method of making electronic device comprises:
(A) with a plurality of nano wires of form of film deposit on substrate; With
(B) on substrate, form first and second and electrically contact,
Wherein at least one nano wire of film with first electrically contact be coupled to second electrically contact on.
2, according to the process of claim 1 wherein that a plurality of nano wires comprise a plurality of thermoelectric nano-wires, wherein step (A) comprising:
The a plurality of thermoelectric nano-wires of form deposit on substrate with the thermoelectric nano-wire film;
This electronic device presents pyroelecthc properties during operation thus.
3, according to the process of claim 1 wherein that a plurality of nano wires comprise a plurality of piezoelectric nano lines, wherein step (A) comprising:
The a plurality of piezoelectric nano lines of form deposit on substrate with piezoelectric nano line film;
This electronic device presents piezoelectric property during operation thus.
4, according to the process of claim 1 wherein that a plurality of nano wires comprise a plurality of magnetic nanometers, wherein step (A) comprising:
The a plurality of magnetic nanometers of form deposit on substrate with the magnetic nanometer film;
This electronic device presents magnetic characteristic during operation thus.
5, according to the process of claim 1 wherein that a plurality of nano wires comprise a plurality of ferroelectric nano-wires, wherein step (A) comprising:
The a plurality of ferroelectric nano-wires of form deposit on substrate with the ferroelectric nano-wire film;
This electronic device presents ferroelectric properties during operation thus.
6, according to the process of claim 1 wherein that a plurality of nano wires comprise a plurality of metal nanometer lines, wherein step (A) comprising:
The a plurality of metal nanometer lines of form deposit on substrate with the metal nanometer line film.
7, according to the process of claim 1 wherein that a plurality of nano wires comprise a plurality of transition metal oxide nano lines, wherein step (A) comprising:
The a plurality of transition metal oxide nano lines of form deposit on substrate with transition metal oxide nano line film.
8, according to the process of claim 1 wherein that step (B) comprising:
Forming first and second on a plurality of nano wires of at least a portion on the substrate electrically contacts.
9, according to the process of claim 1 wherein that step (A) comprising:
In step (B), form first and second on the substrate and electrically contact a plurality of nano wires of deposit on substrate afterwards.
10, to electrically contact be source electrode according to the process of claim 1 wherein first, and second to electrically contact be drain electrode, and wherein step (B) comprising:
On substrate, form source electrode and drain electrode.
11, according to the method for claim 10, also comprise:
(C) on substrate, form grid.
12, according to the method for claim 11, wherein step (C) comprising:
On at least a portion of a plurality of nano wires on the substrate, form grid.
13, according to the method for claim 11, wherein step (A) comprising:
In step (C), on substrate, form after the grid a plurality of nano wires of deposit on substrate.
14, to electrically contact be negative electrode according to the process of claim 1 wherein first, and second to electrically contact be anode, and wherein step (B) comprising:
On substrate, form negative electrode and anode.
15, according to the process of claim 1 wherein that step (A) comprising:
The a plurality of nano wires of deposit on substrate make nano wire aim at randomly with respect to their major axis.
16, according to the method for claim 1, also comprise:
(E) aim at nano wire, make their major axis substantially parallel.
17, a kind of electronic substrate with a plurality of electronic devices comprises:
Substrate;
Be formed on the nano wire film on the described substrate, wherein said nano wire film limits a plurality of semiconductor device zone; With
The a plurality of contacts that are formed in the described semiconductor device zone are right, provide electrical connectivity to semiconductor device thus, and wherein each contact is to having at least one nano wire of the nano wire film that is coupling in therebetween.
18, according to the electronic substrate of claim 17, wherein nano wire film comprises a plurality of thermoelectric nano-wires.
19, according to the electronic substrate of claim 17, wherein nano wire film comprises a plurality of piezoelectric nano lines.
20, according to the electronic substrate of claim 17, wherein nano wire film comprises a plurality of magnetic nanometers.
21, according to the electronic substrate of claim 17, wherein nano wire film comprises a plurality of ferroelectric nano-wires.
22, according to the electronic substrate of claim 17, wherein nano wire film comprises a plurality of metal nanometer lines.
23, according to the electronic substrate of claim 17, wherein nano wire film comprises a plurality of transition metal oxide nano lines.
24,, wherein contact at least a portion that is formed on a plurality of nano wires on the substrate according to the electronic substrate of claim 17.
25, according to the electronic substrate of claim 17, wherein on substrate, form many contacts to after, on substrate, form nano wire film.
26, according to the electronic substrate of claim 17, wherein each contact is to comprising source electrode and drain electrode.
27, according to the electronic substrate of claim 26, wherein grid be formed on the substrate and corresponding each contact right.
28, according to the electronic substrate of claim 27, wherein grid is formed on the nano wire film.
29, according to the electronic substrate of claim 27, wherein on substrate, form after the grid, on substrate, form nano wire film.
30, according to the electronic substrate of claim 17, wherein each contact is to comprising negative electrode and anode.
31, according to the electronic substrate of claim 17, wherein the nano wire of nano wire film is aimed at each other randomly.
32, according to the electronic substrate of claim 17, wherein the nano wire of nano wire film is aimed at, and makes their major axis substantially parallel.
33, a kind of manufacturing is used in the method for the film in one or more semiconductor device, comprising:
(A) form more than first nano wire that p mixes;
(B) form more than second nano wire that n mixes; With
(C) more than first nano wire and more than second nano wire are deposited on the substrate, thereby form the nano wire film that comprises n doping p and doped nanowire;
Nano wire film presents the characteristic of n doping and p doped nanowire thus.
34, according to the method for claim 33, also comprise:
(D) allow the mixture of n doping and p doped nanowire fixing on substrate.
35, according to the method for claim 34, also comprise:
(E) in the presumptive area of substrate, form at least the first and second and electrically contact,
Wherein step (D) comprises that allowing n to mix fixedly contacts with at least the first and second each that electrically contact with the p doped nanowire.
36, according to the method for claim 33, wherein step (C) comprising:
(1) more than first nano wire of deposit in the first area of substrate; With
(2) more than second nano wire of deposit on the second area of substrate;
Wherein nano wire film is included in the n doping and the p doped nanowire of the regional segmentation on the substrate.
37, according to the method for claim 33, wherein step (C) comprising:
(1) more than first nano wire of deposit on substrate, thereby first sublayer of formation nano wire film; With
(2) more than second nano wire of deposit on first sublayer, thus second sublayer of nano wire film on first sublayer, formed.
38, according to the method for claim 33, wherein step (C) comprising:
(1) more than second nano wire of deposit on substrate, thereby first sublayer of formation nano wire film; With
(2) more than first nano wire of deposit on first sublayer, thus second sublayer of nano wire film on first sublayer, formed.
39, according to the method for claim 33, wherein step (C) comprising:
More than first nano wire and more than second nano wire are mixed; With
Deposit mixes on substrate more than first and more than second nano wire, thus nano wire film formed.
40, according to the method for claim 33, wherein said step (A) and (B) respectively comprise:
The core of doped nanowire.
41, according to the method for claim 33, wherein said step (A) and (B) respectively comprise:
The shell of doped nanowire.
42, according to the method for claim 33, wherein said step (A) and (B) respectively comprise:
The core of doped nanowire and shell.
43, a kind of semiconductor device with operating characteristic of n and p dopant material comprises:
Substrate;
What form on substrate a plurality ofly electrically contacts; With
Bond on the substrate and the film of n doped nanowire that contacts with a plurality of each that electrically contact and p doped nanowire.
44, according to the semiconductor device of claim 43, wherein the film of n doping and p doped nanowire comprises:
The first area that comprises a plurality of n doped nanowire that bond to substrate;
The second area that comprises a plurality of p doped nanowire that bond to substrate;
Wherein first area and second area are nonoverlapping basically.
45, according to the semiconductor device of claim 43, wherein the film of n doping and p doped nanowire comprises:
First sublayer that comprises a plurality of n doped nanowire; With
Second sublayer that comprises a plurality of p doped nanowire.
46, according to the semiconductor device of claim 43, wherein the film of n doping and p doped nanowire comprises:
The mixture of n doped nanowire and p doped nanowire.
47, a kind of method of making electronic device comprises:
(A) form a plurality of nano wires, each nano wire is had along at least one first that usefulness first dopant of its major axis mixes and at least one second portion that mixes with second dopant, and each nano wire has the interval between the continuous knot of first and second parts that is substantially equal to first distance;
(B) formation is a pair of on substrate electrically contacts, and the distance between wherein electrically contacting is substantially equal to first distance; With
(C) a plurality of nano wires of deposit on substrate,
At least one nano wire in wherein a plurality of nano wires with first electrically contact be coupled to second electrically contact on.
48, according to the method for claim 47, wherein step (A) comprising:
Each nano wire of growing, wherein said growth step comprises:
(1) major axis of each nano wire forms the alternative graphic of doping first and doping second portion.
49, according to the method for claim 48, wherein step (1) comprising:
Alternating Transportation comprises the first nano wire source material of first dopant and comprises the second nano wire source material of second dopant.
50, according to the method for claim 47, wherein step (A) comprising:
Each nano wire of growing; With
Each nano wire of doped growing makes it have doping first and doping second portion alternately along its major axis.
51, a kind of method of making electronic device on substrate comprises:
(A) form a plurality of nano wires, each nano wire has a plurality of repetitive patterns of doped portion along its major axis, and each figure of repetitive pattern has the length that is substantially equal to first distance;
(B) form on substrate and a plurality ofly electrically contacts, the distance between wherein a plurality of a pair of in electrically contacting electrically contact is substantially equal to first distance;
(C) a plurality of nano wires of deposit on substrate, wherein a plurality of nano wires bond to a plurality of electrically contact on.
52, according to the method for claim 51, wherein step (A) comprising:
(1) each nano wire of growing, thus comprise along a plurality of repetitive patterns of the doped portion of its major axis series connection.
53, according to the method for claim 52, wherein step (1) comprising:
(i) according to first figure each nano wire of growing, wherein first figure comprises the first and the second portion of series connection, and wherein first comprises that first dopant and second portion comprise second dopant; With
(ii) repeating step (i) at least once, thereby repeat first figure along the major axis of each nano wire.
54, according to the method for claim 52, wherein step (1) comprising:
(i) according to first figure each nano wire of growing, wherein first figure comprises first, second portion and the third part of series connection, wherein first and third part comprise first dopant; With
(ii) repeating step (i) at least once, thereby repeat first figure along the major axis of each nano wire.
55, according to the method for claim 54, wherein step (i) comprising:
The growth second portion, thus comprise second dopant.
56, according to the method for claim 54, wherein step (i) comprising:
The growth second portion, making it is intrinsic.
57, according to the method for claim 51, wherein step (A) comprising:
Each nano wire of growing; With
Each grown nano wire of mixing, thus have along the repetitive pattern of the doped portion of its major axis.
58, according to the method for claim 57, wherein step (1) comprising:
(i) according to first figure each grown nano wire of mixing, wherein first figure comprises the first and the second portion of series connection, and wherein first comprises first dopant, and second portion comprises second dopant; With
(ii) repeating step (i) at least once, thereby repeat first figure along the major axis of each grown nano wire.
59, according to the method for claim 57, wherein step (1) comprising:
(i) according to first figure each grown nano wire of mixing, wherein first figure comprises first, second portion and the third part of series connection, wherein first and third part comprise first dopant; With
(ii) repeating step (i) at least once, thereby repeat first figure along the major axis of each grown nano wire.
60, according to the method for claim 59, wherein step (i) comprising:
With the second dopant doping second portion.
61, according to the method for claim 59, wherein step (i) comprising:
Allowing second portion is intrinsic.
62, according to the method for claim 51, wherein a plurality of electrically contact comprise anode and negative electrode, wherein step (B) comprising:
On substrate, form anode and negative electrode, thereby have the distance therebetween that is substantially equal to first distance.
63, according to the method for claim 51, wherein a plurality of electrically contact comprise drain electrode, grid and source electrode, wherein step (B) comprising:
On substrate, form drain and gate, thereby have the distance therebetween that is substantially equal to first distance; With
On substrate, form source electrode, thereby make the distance between source electrode and the grid be substantially equal to first distance.
64, a kind of electronic device comprises:
Substrate;
Being formed on first and second on the described substrate electrically contacts; With
A plurality of nano wires, wherein each nano wire has along the p doped portion of its major axis and the alternative graphic of n doped portion, each nano wire has the interval between the continuous knot of the described p doped portion that is substantially equal to first distance and described n doped portion, wherein at least one nano wire with described first electrically contact be coupled to described second electrically contact on;
Wherein said first electrically contacts and second the distance between electrically contacting is substantially equal to described first distance.
65, according to the device of claim 64, wherein said first to electrically contact be source electrode, and described second to electrically contact be grid, also comprises:
Be formed on the source electrode on the described substrate, wherein the distance between source electrode and the grid is substantially equal to described first distance.
66, according to the device of claim 64, wherein said first to electrically contact be negative electrode, and described second to electrically contact be anode.
67, a kind of method of making light-emitting film comprises:
(A) select at least a luminescent semiconductor nanocrystal wire material;
(B) form a plurality of nano wires with selecteed at least a luminescent semiconductor nanocrystal wire material;
(C) each nano wire that mixes makes each nano wire comprise at least one P-N knot;
(D) a plurality of nano wires of deposit on substrate.
68, according to the method for claim 67, also comprise:
(E) on substrate, form first and electrically contact and second electrically contact, wherein at least one nano wire with first electrically contact be coupled to second electrically contact on.
69, according to the method for claim 68, wherein step (D) is carried out before in step (C):
70, according to the method for claim 68, wherein step (E) comprising:
Forming first and second at least a portion of a plurality of nano wires on the substrate electrically contacts.
71, according to the method for claim 68, wherein first to electrically contact be source electrode, and second to electrically contact be drain electrode, also comprises:
(F) on substrate, form grid.
72, according to the method for claim 68, first to electrically contact be negative electrode, and second to electrically contact be anode, and wherein step (E) comprising:
(F) on substrate, form negative electrode and anode.
73, according to the method for claim 67, wherein step (C) comprising:
Each nano wire that mixes makes it have alternating N and P doped portion, and each nano wire has the interval between the continuous knot between the alternating-doping part that is substantially equal to first distance.
74, according to the method for claim 73, also comprise:
(E) on substrate, form first and electrically contact and second electrically contact, wherein at least one nano wire with first electrically contact be coupled to second electrically contact on, wherein first and second the distances between electrically contacting are substantially equal to first distance.
75, according to the method for claim 67, wherein at least a light-emitting semiconducting material of selecting in step (A) comprises at least a in fluorescence, phosphorescence, electroluminescence and the cathodoluminescence material, and wherein step (B) comprising:
Form a plurality of nano wires with the selected at least a material in fluorescence, phosphorescence, electroluminescence and the cathodoluminescence material.
76, according to the method for claim 67, wherein at least a light-emitting semiconducting material of selecting in step (A) comprises multiple fluorescent material, and wherein step (B) comprising:
Form a plurality of nano wires with selected multiple fluorescent material.
77, according to the method for claim 67, wherein step (B) comprising:
Form a plurality of nano wires, make each nano wire have about equally diameter.
78, according to the method for claim 67, wherein step (B) comprising:
Form a plurality of nano wires, make it comprise nano wire with a plurality of diameters.
79, according to the method for claim 67, wherein step (A) comprising:
(1) selects multiple luminescent semiconductor nanocrystal wire material, make every kind of selected luminescent semiconductor nanocrystal wire material emission be different from the light of the color of other selected luminescent semiconductor nanocrystal wire material.
80, according to the method for claim 79, wherein step (1) comprising:
Select multiple luminescent semiconductor nanocrystal wire material, thereby by this film emission white light.
81, according to the method for claim 67, wherein step (A) comprising:
Select at least a luminescent semiconductor nanocrystal wire material, thus, purple pink, red, orange, yellow, green, blue, dark blue purple, pansy, brown, infrared ray, near infrared ray or ultraviolet light by film emission.
82, according to the method for claim 67, wherein step (D) is carried out before in step (C).
83, according to the method for claim 67, wherein step (C) is carried out before in step (D).
84, a kind of method of making luminous semiconductor device comprises:
(A) select at least a luminescent semiconductor nanocrystal wire material;
(B) form a plurality of nano wires with selecteed at least a luminescent semiconductor nanocrystal wire material;
(D) a plurality of nano wires of deposit on substrate; With
(E) on substrate, form first and electrically contact and second electrically contact, wherein at least one nano wire with first electrically contact be coupled to second electrically contact on;
Wherein at the device duration of work, penetrate light from binding up one's hair of one of electrically contacting of nano wire and first and second.
85,4 method according to Claim 8 wherein one of electrically contacts to go up and forms Schottky diode by at least one nano wire being coupled to first and second.
86, a kind of luminous semiconductor device comprises:
Substrate;
Being formed on first and second on the described substrate electrically contacts; With
A plurality of nano wires, each nano wire comprise at least one luminescent semiconductor nanocrystal wire material, wherein at least one nano wire with first electrically contact be coupled to second electrically contact on;
Wherein said a plurality of nano wire is fixed on the described substrate and electrically contacts and contact with two.
87,6 device according to Claim 8 wherein at the device duration of work, is penetrated light from binding up one's hair of one of electrically contacting of nano wire and first and second.
88,6 device according to Claim 8, each nano wire that wherein mixes makes it have p-n junction.
89,6 device according to Claim 8, wherein said a pair of distance between electrically contacting is substantially equal to first length;
Each nano wire that wherein mixes makes it have a plurality of p-n junctions along its each major axis, and each nano wire has the interval between the adjacent p-n junction that is substantially equal to described first length.
90,6 device according to Claim 8, wherein said each nano wire comprises the fluorescence nano wire material.
91, according to the device of claim 90, wherein said fluorescence nano wire material comprises GaN.
92, according to the device of claim 90, wherein said fluorescence nano wire material comprises CdSe, InP, CdS, CdTe, ZnS, ZnSe, ZnO; At least a among PbSe, PbTe, PbS, HgTe, HgSe and the HgS.
93,6 device according to Claim 8, wherein said a plurality of nano wires comprise a plurality of fluorescence nano wire materials.
94,6 device according to Claim 8, all nano wires of wherein said a plurality of nano wires have essentially identical diameter.
95,6 device according to Claim 8, wherein said a plurality of nano wires comprise the nano wire with a plurality of diameters.
96,6 device according to Claim 8, wherein pink, red, orange, yellow, green, blue, the purple of semiconductor device emission, dark blue purple, pansy, brown, infrared ray, near infrared ray or ultraviolet light during operation.
97,6 device according to Claim 8, wherein semiconductor device is launched white light during operation.
98, a kind of method of locating nano wire on the target surface comprises:
(A) make the first surface and the target surface engagement of fluid mask, make at least one raceway groove in the first surface that is formed on the fluid mask cover the part on target surface;
(B) make the flow of liquid that contains a plurality of nano wires cross at least one raceway groove; With
(C) nano wire that allows to be included in the liquid that flows through at least one raceway groove is positioned on the part on the target surface that is covered by at least one raceway groove.
99, according to the method for claim 98, also comprise:
(D) make described liquid flow through at least one raceway groove discontinuously, thereby allow nano wire to remain positioned on the part on target surface.
100, according to the method for claim 98, wherein at least one raceway groove comprises a plurality of raceway grooves that are formed in the first surface, and wherein step (B) comprising:
Make the flow of liquid that contains a plurality of nano wires cross a plurality of raceway grooves.
101, according to the method for claim 100, wherein each raceway groove of a plurality of raceway grooves covers the appropriate section on target surface, and wherein step (C) comprising:
The nano wire that allows to be included in the liquid that flows through a plurality of raceway grooves is positioned on the appropriate section on the target surface that is covered by each raceway groove of a plurality of raceway grooves.
102, according to the method for claim 98, its surface that hits has formation a plurality of conductive structures thereon, and wherein step (C) comprising:
Between the conductive structure of a plurality of conductive structures and at least one nano wire, form at least one contact.
103, according to the method for claim 98, wherein step (B) comprising:
Make nano wire on the part on target surface, location be arranged essentially parallel to the flow direction of the liquid that flows through at least one raceway groove and be orientated.
104, according to the method for claim 98, also comprise:
(D) density of the nano wire in the selection liquid.
105, according to the method for claim 104, wherein step (D) also comprises:
Select the density of the nano wire in the liquid, thereby in step (C), allow the nano wire of q.s to be positioned on the cover part on target surface, be electrically connected so that on the cover part on target surface, form.
106, a kind of equipment that is used for location nano wire on the target surface comprises:
Main body with first surface constitutes and the target surface engagement;
Be formed at least one raceway groove in the described first surface;
Be formed on the input port in the described main body, thereby carry the nanometer linear flow for described at least one raceway groove; With
Be formed on the delivery outlet in the described main body, thereby remove the nanometer linear flow from described at least one raceway groove;
Wherein said at least one raceway groove form when the described first surface of described main body and target surface engagement, allow the nano wire of described nanometer linear flow to be positioned on the part on the target surface that is covered by described at least one raceway groove.
107, according to the equipment of claim 106, wherein said at least one raceway groove comprises a plurality of raceway grooves that are formed in the described first.
108, according to the equipment of claim 106, wherein said target surface is a semiconductor wafer surface.
109, according to the equipment of claim 108, wherein said semiconductor wafer surface comprises formation integrated circuit (IC) array thereon.
110, according to the equipment of claim 106, wherein said target surface is a substrate surface.
111, according to the equipment of claim 106, wherein said nanometer linear flow comprises the liquid that contains a plurality of nano wires.
112, according to the equipment of claim 106, its surface that hits has formation a plurality of conductive traces thereon, and wherein said at least one raceway groove allows the nano wire of described nanometer linear flow to form at least one contact between the conductive trace of described a plurality of conductive traces.
113,, wherein be positioned at the flow direction that the lip-deep described nano wire of part target is arranged essentially parallel to by described at least one raceway groove and be orientated according to the equipment of claim 106.
114, according to the equipment of claim 106, the channel width of wherein said at least one raceway groove at 1 μ m in the scope of 1000 μ m.
115, a kind of system that is used for applying to the target surface nano wire comprises:
The source of solvent of nano wire solution is provided, and wherein said nano wire solution comprises the liquid that contains a plurality of nano wires; With
Be coupled to the nozzle of described source of solvent, wherein said nozzle has at least one delivery outlet;
Wherein said nozzle guide nano wire solution passes described at least one delivery outlet and arrives on the target surface, and the described nano wire of described nano wire solution is directed on the target surface, thereby aims in parallel with each other basically on described target surface.
116, according to the system of claim 115, wherein said nozzle has a plurality of delivery outlets.
117, according to the system of claim 116, wherein said a plurality of delivery outlets apply nano wire solution to the lap on target surface.
118, according to the system of claim 116, wherein said a plurality of delivery outlets apply nano wire solution to a plurality of non-overlapped part on target surface.
119, according to the system of claim 115, the delivery outlet width of wherein said at least one delivery outlet at 1 μ m in the scope of 1000 μ m.
120, according to the system of claim 115, the delivery outlet width of wherein said at least one delivery outlet is more than or equal to the length of described a plurality of nano wires.
121, a kind of method that applies nano wire on the target surface comprises with being used for substantial registration:
(A) provide nano wire solution, wherein nano wire solution comprise the liquid that contains a plurality of nano wires and
(B) at least one delivery outlet by nozzle is directed to nano wire solution on the target surface;
Wherein step (B) comprises and makes nano wire step of aligning parallel to each other basically on the target surface.
122, according to the method for claim 121, wherein step (B) also comprises:
Nano wire solution is directed to the lap on target surface.
123, according to the method for claim 121, wherein step (B) also comprises:
Nano wire solution is directed to the non-overlapped part on target surface.
124, according to the method for claim 121, wherein step (B) also comprises:
Exert pressure, so that force the nano wire flow of solution to cross at least one delivery outlet of nozzle and arrive on the target surface.
125, according to the method for claim 121, its surface that hits is a substrate, and wherein step (B) also comprises:
At least one delivery outlet by nozzle is directed to nano wire solution on the substrate.
126, according to the method for claim 121, its surface that hits is a wafer,
Wherein step (B) also comprises:
At least one delivery outlet by nozzle is directed to nano wire solution on the wafer.
127, according to the method for claim 121, its surface that hits is continuous basically plate, and wherein step (B) also comprises:
At least one delivery outlet by nozzle is directed to nano wire solution on this plate;
Wherein this method also comprises:
(C) adjust the position of plate with respect to nozzle.
128, according to the method for claim 121, also comprise:
(C) nano wire is fixed on the target surface.
129, according to the method for claim 128, wherein step (C) comprising:
The lip-deep nano wire solution of target is solidified.
130, according to the method for claim 121, wherein step (C) comprising:
Apply electric charge for the target surface.
131, a kind of manufacturing has the large tracts of land of a plurality of semiconductor device, the method for grand electronic substrate, comprising:
(A) at least one delivery outlet by nozzle is directed to nano wire solution on the substrate, the nano wire film that has the enough density of nano wire with form, thus realize working current density;
(B) a plurality of nano wire films are carried out composition, thereby limit a plurality of semiconductor device zone; With
(C) in the semiconductor device zone, form ohmic contact, be provided to the electrical connection of a plurality of semiconductor device thus.
132, according to the method for claim 131, wherein step (A) comprising:
Make the nano wire substantial registration of nano wire film.
133, according to the method for claim 131, also comprise:
(D) nano wire film is solidified.
134, according to the method for claim 131, also comprise:
(D) apply electric charge for the target surface.
135, a kind of design has the method for the conducting nanowires of high electron mobility, comprising:
(A) select semi-conducting material; With
(B) determine the maximum gauge of the nano wire made by the semi-conducting material of selecting, make it that electronics quantum limit of essence is provided.
136, according to the method for claim 135, wherein step (B) comprising:
Following calculating maximum gauge:
Wherein:
H=Planck's constant ÷ 2 π
＝6.626×10
-34J-sec÷(2×3.1416)
(or 4.14 * 10
-15EV-sec ÷ 2 * 3.1416)
＝1.0545×10
-34J-sec(6.589×10
-16eV-sec)；
m
EffThe effective mass of=selected semi-conducting material;
The N=pre-determined factor;
K
b=Maxwell constant=8.62 * 10
-5EV/ ° of K; With
The T=working temperature;
Wherein at room temperature, k
bT=.0259eV.
137, according to the method for claim 135, comprising:
(C) form a plurality of nano wires by selected semi-conducting material, each nano wire of a plurality of nano wires forms to have and is less than or equal to predetermined maximum gauge.
138, according to the method for claim 135, wherein step (1) comprising:
The selection semi-conducting material is a kind of among Si, Ge, AlN, AlSb, GaN, GaP, GaAs, InN, InP, InAs, InSb, ZnO and the ZnS.
139, according to the method for claim 135, wherein step (C) comprising:
Formation has each nano wire of a plurality of nano wires of predetermined length, and wherein each nano wire allows by the transmission of nano wire electron-trajectory.
140, according to the method for claim 136, wherein pre-determined factor N is more than or equal to 3.
141, according to the method for claim 140, wherein pre-determined factor N is more than or equal to 5.
142, a kind of manufacturing has the method for the conducting nanowires of high electron mobility, comprising:
(A) select semi-conducting material; With
(B) form a plurality of nano wires with selected semi-conducting material, wherein each nano wire forms to have to be less than or equal to and is used for the maximum gauge that selected semi-conducting material is determined, thereby allows each nano wire to keep the quantum limit of electronics in fact.
143, according to the method for claim 142, wherein step (B) comprising:
Following calculating maximum gauge:
Wherein:
H=Planck's constant ÷ 2 π
＝6.626×10
-34J-sec÷(2×3.1416)
(or 4.14 * 10
-15EV-sec ÷ 2 * 3.1416)
＝1.0545×10
-34J-sec(6.589×10
-16eV-sec)；
m
EffThe effective mass of=selected semi-conducting material;
The N=pre-determined factor;
K
b=Maxwell constant=1.38 * 10
-23J/ ° of K (8.62 * 10
-5EV/ ° of K); With
The T=working temperature;
Wherein at room temperature, k
bT=4.144 * 10
-21J (.0259eV).
144, according to the method for claim 142, wherein step (1) comprising:
The selection semi-conducting material is a kind of among Si, Ge, AlN, AlSb, GaN, GaP, GaAs, GaSb, InN, InP, InAs, InSb, ZnO and the ZnS.
145, according to the method for claim 142, wherein each nano wire has and is less than or equal to predetermined length, thereby can produce the ballistic transport of electronics by nano wire.
146, according to the method for claim 143, wherein pre-determined factor N is more than or equal to 3
147, according to the method for claim 146, wherein pre-determined factor N is more than or equal to 5.
148, according to the method for claim 142, also comprise:
(C) constitute a plurality of nano wires, thus with electronics as the conduction charge carrier, reduced the phon scattering of the electronics in the nano wire of a plurality of nano wires thus.
149, according to the method for claim 148, wherein step (C) comprising:
(1) with n type dopant material a plurality of nano wire that mix.
150, according to the method for claim 148, wherein step (C) comprising:
(1) with p type dopant material a plurality of nano wire that mix; With
(2) by applying enough bias voltages for a plurality of nano wires, make a plurality of nano wires with reverse manner work, thereby make electronics become the conduction charge carrier.
151, according to the method for claim 150, wherein a plurality of nano wires are coupling between transistorized source electrode and the drain electrode, and wherein step (2) comprising:
Be applied for the bias voltage of transistor gate bias voltage for a plurality of nano wires.
152, a kind of conductor with high electron mobility comprises:
Nano wire film with enough nanowire density, thereby realization working current value, each nano wire comprises that semi-conducting material is less than or equal to the diameter that is used for the definite maximum gauge of described semi-conducting material with having, thereby allows described each nano wire to keep the electronics quantum limit of essence.
153, according to the conductor of claim 152, wherein said maximum gauge calculates according to following formula:
Wherein:
H=Planck's constant ÷ 2 π
＝6.626×10
-34J-sec÷(2×3.1416)
(or 4.14 * 10
-15EV-sec ÷ 2 * 3.1416)
＝1.0545×10
-34J-sec(6.589×10
-16eV-sec)；
m
EffThe effective mass of=selected semi-conducting material;
The N=pre-determined factor;
K
b=Maxwell constant=1.38 * 10
-23J/ ° of K (8.62 * 10
-5EV/ ° of K); With
The T=working temperature;
Wherein at room temperature, k
bT=4.144 * 10
-21J (.0259eV).
154, according to the conductor of claim 152, wherein said semi-conducting material is a kind of among Si, Ge, AlN, AlSb, GaN, GaP, GaAs, GaSb, InN, InP, InAs, InSb, ZnO and the ZnS.
155, according to the conductor of claim 152, wherein each nano wire has the length that is less than or equal to predetermined length, thereby can produce the ballistic transport of electronics by nano wire.
156, according to the conductor of claim 153, wherein pre-determined factor N is more than or equal to 3
157, according to the conductor of claim 156, wherein pre-determined factor N is more than or equal to 5.
158, according to the conductor of claim 152, wherein constitute a plurality of nano wires, thus with electronics as the conduction charge carrier, reduced the phon scattering of the electronics in the nano wire thus.
159, according to the conductor of claim 158, wherein use n type dopant material doped nanowire, use electronics as the conduction charge carrier thereby constitute.
160, according to the conductor of claim 158, wherein use p type dopant material doped nanowire and
Wherein, make nano wire film with reverse manner work, thereby make electronics become the conduction charge carrier by applying enough bias voltages for a plurality of nano wire films.
161, according to the conductor of claim 160, wherein a plurality of nano wires are coupling between transistorized source electrode and the drain electrode, are applied for the bias voltage of transistor gate bias voltage wherein for a plurality of nano wires.
162, a kind of manufacturing has the method for the nano wire that reduces surface scattering, comprising:
(A) select semi-conducting material;
(B) form a plurality of nano wires with selected semi-conducting material; With
(C) apply the circumferential surface of each nano wire of a plurality of nano wires with insulating barrier.
163, according to the method for claim 162, wherein insulating barrier comprises dielectric material, and wherein step (C) comprising:
Apply each nano wire of a plurality of nano wires with dielectric material.
164, according to the method for claim 162, wherein insulating barrier comprises oxide, and wherein step (C) comprising:
Each nano wire of a plurality of nano wires of oxidation, thus a plurality of oxidation nanometer lines produced.
165, according to the method for claim 164, also comprise:
(D) each oxidation nanometer line of a plurality of oxidation nanometer lines is annealed.
166, according to the method for claim 165, wherein step (D) comprising:
Under the H2 environment, each oxidation nanometer line is annealed, thereby make the dangling bonds passivation at the interface of the oxide layer of each oxidation nanometer line and non-oxide part.
167, a kind of manufacturing has the method for the nano wire that reduces surface scattering, comprising:
(A) select semi-conducting material;
(B) form a plurality of nano wires with selected semi-conducting material; With
(C) each nano wire of a plurality of nano wires of doping makes each nano wire comprise core-shell structure, and its mesochite is the doping skin that surrounds each nano wire of each core;
Wherein step (C) comprising:
Make the charge carrier of each nano wire be restricted to core basically during operation.
168, according to the method for claim 167, wherein step (C) comprising:
Be the outer dopant material of selecting of doping of each nano wire, make the skin that mixes to have the energy level higher than the energy level of each core; With
Use mix each nano wire of a plurality of nano wires of selected dopant material.
169, according to the method for claim 167, wherein said doping step comprises:
Be the outer dopant material of selecting that mixes, the outer field lattice structure of mixing is cooperated with the lattice structure of core basically; With
Use mix each nano wire of a plurality of nano wires of selected dopant material.
170, a kind of semiconductor device with minimizing surface scattering comprises:
A plurality of conducting nanowires, wherein each nano wire comprises:
Comprise semi-conducting material core and
Surround the shell of each core, wherein said shell comprises the described semi-conducting material that mixes with dopant material;
Wherein during operation, described doped semiconductor materials makes the charge carrier of described each nano wire be restricted to each described core basically.
171, according to the semiconductor device of claim 170, wherein said dopant material makes described shell have the energy level higher than the energy level of described each core.
172, according to the method for claim 170, wherein said dopant material makes described shell have the lattice structure that fully cooperates with the lattice structure of described each core, thereby makes the described charge carrier of described each nano wire be limited to described each core basically during operation.
173, a kind of electronic substrate with a plurality of semiconductor device comprises:
Substrate;
Be formed on nano wire film on the described substrate with enough nanowire density, thereby reached working current value, wherein said nano wire film limits a plurality of semiconductor device region; With
Contact in that described semiconductor device region forms is provided to the electrical connection of a plurality of semiconductor device thus.
174, according to the semiconductor device of claim 173, wherein time group semiconductor device comprises transistor at least, wherein said contact comprise be formed on the described nano wire film or under grid, source electrode and drain electrode, wherein said nano wire film is formed between described source electrode and the described drain electrode.
175, according to the semiconductor device of claim 173, wherein time group semiconductor device comprises diode at least, and described contact comprise be formed on the described nano wire film or under anode and negative electrode.
176, according to the semiconductor device of claim 175, wherein said nano wire film forms p-n junction between described anode and negative electrode.
177, according to the semiconductor device of claim 175, wherein said diode comprises light-emitting diode.
178, according to the semiconductor device of claim 173, wherein time group semiconductor device comprises logical device at least.
179, according to the semiconductor device of claim 173, wherein time group semiconductor device comprises memory device at least.
180, according to the semiconductor device of claim 173, wherein time group semiconductor device comprises active matrix driving circuit at least.
181, according to the semiconductor device of claim 173, wherein said nano wire substantial registration is parallel to their major axis.
182, according to the semiconductor device of claim 174, wherein the nano wire rough alignment is parallel to the axle between source electrode and the drain electrode.
183, according to the semiconductor device of claim 174, wherein said grid is formed on the substrate, and described nano wire film is formed on the described grid, and described source electrode and described drain electrode are formed on the described nano wire film.
184, according to the semiconductor device of claim 174, wherein said source electrode and described drain electrode are formed on the described substrate, and described nano wire film is formed in described source electrode and the described drain electrode, and described grid is formed on the described nano wire film.
185, according to the semiconductor device of claim 174, wherein said grid, source electrode and drain electrode are formed on the described substrate, and described nano wire film is formed in described grid, source electrode and the drain electrode.
186, according to the semiconductor device of claim 174, wherein said grid, source electrode and drain electrode are formed on the described nanowire surface.
187,, also be included in the interconnection between time group semiconductor device according to the semiconductor device of claim 173.
188, according to the semiconductor device of claim 173, wherein said substrate comprises fexible film.
189, according to the semiconductor device of claim 173, wherein said substrate comprises transparent material.
190, according to the semiconductor device of claim 173, wherein said substrate comprises transparent material.
191, according to the semiconductor device of claim 173, wherein said nano wire is a monocrystal nanowire, and wherein electric charge carrier utilization can be passed described monocrystal nanowire transmission with the mobility that the electric charge carrier that transmits is compared in the device that is formed by the conventional planar single-crystal semiconductor material.
192, according to the semiconductor device of claim 174, wherein said nano wire film comprises the nano wire of capacity, thus have greater than 10 receive the peace raceway groove in the on-state current value.
193, according to the semiconductor device of claim 174, wherein said raceway groove comprises more than one nano wire.
194, according to the semiconductor device of claim 174, wherein time described grid of group comprises more than one nano wire film at least.
195, according to the semiconductor device of claim 174, wherein time group raceway groove comprises p-n junction at least, and thus during operation, p-n junction is luminous.
196, according to the semiconductor device of claim 173, wherein said nano wire is doped.
197, according to the semiconductor device of claim 173, wherein time described nano wire of group has the doping core at least.
198, according to the semiconductor device of claim 173, wherein time described nano wire of group has the doping shell at least.
199, according to the semiconductor device of claim 173, wherein time described nano wire of group has doping core and shell at least.
200, according to the semiconductor device of claim 174, wherein time described nano wire of group is oxidized at least, thereby forms gate dielectric.
201, according to the semiconductor device of claim 173, wherein time group semiconductor device is electrically coupled on other circuit at least.
202, according to the semiconductor device of claim 201, wherein said circuit is a logical circuit.
203, according to the semiconductor device of claim 201, wherein said circuit is a memory circuitry.
204, according to the semiconductor device of claim 201, wherein said circuit is an active matrix driving circuit.
205, according to the semiconductor device of claim 173, wherein time group semiconductor device physically is coupled to other circuit at least.
206, according to the semiconductor device of claim 205, wherein said circuit is a logical circuit.
207, according to the semiconductor device of claim 205, wherein said circuit is a memory circuitry.
208, according to the semiconductor device of claim 205, wherein said circuit is an active matrix driving circuit.
209, according to the semiconductor device of claim 173, wherein said nano wire is patterned.
210, according to the semiconductor device of claim 209, wherein said patterning nano line is by photoetching composition.
211, according to the semiconductor device of claim 209, wherein said patterning nano line is screen printed.
212, according to the semiconductor device of claim 209, wherein said patterning nano line is by ink jet printing.
213, according to the semiconductor device of claim 209, wherein said patterning nano line is by miniature contact print.
214, according to the semiconductor device of claim 173, wherein nano wire is revolved notes.
215, according to the semiconductor device of claim 173, wherein nano wire is mechanically aimed at.
216, according to the semiconductor device of claim 173, wherein nano wire is aimed at by fluid.
217, according to the semiconductor device of claim 173, wherein nano wire is sheared the power aligning.
218, according to the semiconductor device of claim 173, wherein said nano wire comprises enough density, thereby has the statistical probability that realizes device on any position on the substrate.
219,, also comprise one deck oxide at least a portion that is deposited on described nano wire according to the semiconductor device of claim 173.
220, according to the semiconductor device of claim 173, wherein said nano wire is the ballistic conductor that has greater than the mobility of single-crystal semiconductor material.
221, according to the semiconductor device of claim 173, wherein said nano wire is orientated randomly.
222, according to the semiconductor device of claim 173, wherein said nano wire forms monofilm, inferior monofilm or multilayer film.
223, according to the semiconductor device of claim 174, wherein at least one raceway groove of described raceway groove, first end of at least two nano wires of described nano wire is electrically coupled in first contact of described raceway groove, and second end of described at least two nano wires is electrically coupled in second contact of described raceway groove.
224, a kind of manufacturing has the method for the electronic substrate of a plurality of semiconductor device, comprising:
(a) utilize the nanowire density of capacity on substrate, to form nano wire film, thereby realize working current value;
(b) in nano wire film, limit a plurality of semiconductor device region; With
(c) in semiconductor device region, form contact, electrical connection is provided for thus a plurality of semiconductor device.
225,, also comprise the major axis aligning nano wire that is arranged essentially parallel to them according to the method for claim 224.
226, according to the method for claim 224, wherein step (c) comprises formation source electrode and drain electrode, and nano wire forms the raceway groove with the length between corresponding source electrode and drain electrode thus.
227, according to the method for claim 226, also comprise the step that forms grid.
228, according to the method for claim 224, wherein step (c) comprises formation anode and negative electrode.
229, according to the method for claim 226, wherein the nano wire rough alignment is parallel to the axle between source electrode and the drain electrode contact.
230, according to the method for claim 227, wherein grid is formed on the substrate, and nano wire film is formed on the grid, and source electrode and drain electrode are formed on the nano wire film.
231, according to the method for claim 227, wherein source electrode and drain electrode are formed on the substrate, and nano wire film is formed in source electrode and the drain electrode, and grid is formed on the nano wire film.
232, according to the method for claim 227, wherein grid, source electrode and drain electrode are formed on the substrate, and nano wire film is formed in grid, source electrode and the drain electrode.
233, according to the method for claim 227, wherein grid, source electrode and drain electrode are formed on the nano wire film.
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| US41432302P | 2002-09-30 | 2002-09-30 | |
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| US47406503P | 2003-05-29 | 2003-05-29 | |
| US60/474,065 | 2003-05-29 | ||
| US48880103P | 2003-07-22 | 2003-07-22 | |
| US60/488,801 | 2003-07-22 | ||
| PCT/US2003/030721 WO2004032193A2 (en) | 2002-09-30 | 2003-09-30 | Large-area nanoenabled macroelectronic substrates and uses therefor |
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| CN1745468B CN1745468B (en) | 2010-09-01 |
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| CN 03825281 Pending CN1703730A (en) | 2002-09-30 | 2003-09-30 | Integrated displays using nanowire transistors |
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| CN 03825281 Pending CN1703730A (en) | 2002-09-30 | 2003-09-30 | Integrated displays using nanowire transistors |
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