CN1743933A - Pixel structure and its manufacturing method - Google Patents
Pixel structure and its manufacturing method Download PDFInfo
- Publication number
- CN1743933A CN1743933A CN 200510105758 CN200510105758A CN1743933A CN 1743933 A CN1743933 A CN 1743933A CN 200510105758 CN200510105758 CN 200510105758 CN 200510105758 A CN200510105758 A CN 200510105758A CN 1743933 A CN1743933 A CN 1743933A
- Authority
- CN
- China
- Prior art keywords
- electrode
- layer
- pixel structure
- substrate
- pixel
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Images
Landscapes
- Liquid Crystal (AREA)
- Thin Film Transistor (AREA)
Abstract
This invention provides a pixel structure and making method, said structure containing a substrate, a protection layer and a pixel electrode, wherei the substrate including an active element region and a capacitance region with plurality of opens, said film transistor set in active element region, capacitor set in capacitance region and conformally formed in open, protection layer covered on film transistor and capacitor, pixel electrode set on protection layer and connected with transistor and capacitor. Said invention reduces the capacitor occupied area on substrate without influencing capacitance value and raises the opening rate of display area.
Description
Technical field
The present invention relates to a kind of dot structure and manufacture method thereof, and particularly relate to a kind of dot structure and manufacture method thereof with high aperture.
Background technology
General Thin Film Transistor-LCD is made of a thin-film transistor array base-plate, a subtend substrate and the liquid crystal layer that is sandwiched between aforementioned two substrates.Wherein, thin-film transistor array base-plate mainly comprises substrate, arrayed dot structure, the sweep trace (Scanning line) and data line (Date line) on substrate.Aforesaid dot structure mainly is made of thin film transistor (TFT), pixel electrode (PixelElectrode), storage capacitors (Cst).Generally speaking, sweep trace can transfer to signal corresponding dot structure with data line, to reach the purpose of demonstration.In addition, dot structure can pass through the auxiliary of its storage capacitors, and keeps normal demonstration.
Fig. 1 is the schematic top plan view of existing dot structure, and Fig. 2 be among Fig. 1 dot structure along the synoptic diagram of A-A ' profile line.Please also refer to Fig. 1 and Fig. 2, existing dot structure 100 comprises substrate 110, thin film transistor (TFT) 120, pixel electrode 130 and storage capacitors 140, and above-mentioned dot structure 100 drives by sweep trace 10 and data line 20.Wherein, thin film transistor (TFT) 120 is that the mode with bottom-gate is disposed on the substrate 110, and it comprises a grid 120g, one source pole 120s, drain electrode 120d, semi-conductor layer 120c, a gate insulation layer 120i and a protective seam (passivation layer) 122.
In addition, storage capacitors 140 comprises a lower electrode layer 142 and a upper electrode layer 144, and wherein, lower electrode layer 142 is disposed on the substrate 110, and above-mentioned gate insulation layer 120i cover grid 120g and lower electrode layer 142, and gate insulation layer 120i is between lower electrode layer 142 and upper electrode layer 144.In addition, protective seam 122 covers source electrode 120s, drain electrode 120d, semiconductor layer 120c and upper electrode layer 144.And upper electrode layer 144 is electrically connected with pixel electrode 130 by the contact hole W1 that is formed in the protective seam 122, and upper electrode layer 144 is electrically connected with drain electrode 120d and be same rete.
What merit attention is, because storage capacitors 140 is positioned at dot structure 100 zones, and the bottom electrode 142 of storage capacitors 140 is formed by metal material with top electrode 144.Therefore, bottom electrode 142 can stop penetrating of light with top electrode 144.In other words, the area that storage capacitors 140 is positioned at dot structure 100 zones is bigger, can cause the aperture opening ratio of viewing area to descend, and then influence the display quality of Thin Film Transistor-LCD.
Summary of the invention
In view of this, purpose of the present invention is providing a kind of dot structure exactly, and it can reduce reservior capacitor shared area and do not influence its capacitance on substrate.
A further object of the present invention provides a kind of one pixel structure process method, and it is suitable for producing the reservior capacitor of a special construction, and then promotes the aperture opening ratio of viewing area.
The present invention proposes a kind of one pixel structure process method, and the method comprises the following steps: at first, and a substrate is provided, and it has an active member district (active device area) and a capacitive region.Then, in the capacitive region of substrate, form a plurality of openings, then, in the active member district, form a grid and in capacitive region, form one first electrode layer, and first electrode layer conformally (conformably) be formed in the opening.In addition, on substrate, form a gate insulation layer, its cover gate and first electrode layer.Then, on the gate insulation layer of grid top, form semi-conductor layer.Then, form an one source pole and a drain electrode on semiconductor layer, and form a second electrode lay in capacitive region, it covers gate insulation layer.In addition, form a protective seam on substrate, it covers source electrode, drain electrode and the second electrode lay.At last, on protective seam, form a pixel electrode, and pixel electrode can be electrically connected with drain electrode, and pixel electrode is electrically connected with the second electrode lay.
According to the one pixel structure process method of preferred embodiment of the present invention, the method that wherein forms opening comprises: at first, form a patterned barrier layer on substrate.Then, substrate is carried out an etching technics to form opening.At last, remove patterned barrier layer.
According to the one pixel structure process method of preferred embodiment of the present invention, wherein the material of patterned barrier layer comprises photoresist.
According to the one pixel structure process method of preferred embodiment of the present invention, wherein the material of patterned barrier layer comprises silicon nitride.
According to the one pixel structure process method of preferred embodiment of the present invention, wherein etching technics comprises dry etching.
According to the one pixel structure process method of preferred embodiment of the present invention, the mode that wherein removes the restraining barrier comprises wet etching.
According to the one pixel structure process method of preferred embodiment of the present invention, wherein the radius of each opening for example is 0.5～3 micron.
According to the one pixel structure process method of preferred embodiment of the present invention, wherein the degree of depth of each opening for example is 5～10 microns.
According to the one pixel structure process method of preferred embodiment of the present invention, the method that wherein forms protective seam comprises the spin-on glasses mode.
According to the one pixel structure process method of preferred embodiment of the present invention, before forming pixel electrode on the protective seam, comprise also in protective seam, forming a contact window earlier wherein that it exposes drain electrode and the second electrode lay.
According to the one pixel structure process method of preferred embodiment of the present invention, wherein formed the second electrode lay and drain electrode link together.
According to the one pixel structure process method of preferred embodiment of the present invention, before forming pixel electrode on the protective seam, comprise also in protective seam, forming a contact window earlier wherein that it exposes the second electrode lay.
One pixel structure process method according to preferred embodiment of the present invention, the method that wherein forms the grid and first electrode layer comprises the following steps, at first, carry out a depositing operation, to form a metal level, wherein depositing operation comprises organometallic chemistry vapour deposition process, molecular layer brilliant method of heap of stone or atomic layer chemical vapor deposition method.At last, carry out a photoetching process and an etching technics, with patterned metal layer.
One pixel structure process method according to preferred embodiment of the present invention, the method that wherein forms source electrode, drain electrode and the second electrode lay comprises the following steps, at first, carry out a depositing operation, to form a metal level, wherein depositing operation comprises the following steps, at first, carry out a depositing operation, to form a metal level, wherein depositing operation comprises organometallic chemistry vapour deposition process, molecular layer brilliant method of heap of stone or atomic layer chemical vapor deposition method.At last, carry out a photoetching process and an etching technics, with patterned metal layer.
The present invention proposes a kind of dot structure in addition, and it comprises a substrate, a thin film transistor (TFT), a capacitor, a protective seam and a pixel electrode.Wherein, substrate has an active member district and a capacitive region, and has been formed with a plurality of openings in capacitive region.In addition, thin film transistor (TFT) is disposed in the active member district, and capacitor arrangements is in capacitive region, and conformally (conformably) is formed in the opening.In addition, protective seam cover film transistor AND gate capacitor, and pixel electrode is disposed on the protective seam, and pixel electrode can be connected with thin film transistor (TFT) and capacitor electrode.
According to the dot structure of preferred embodiment of the present invention, wherein the radius of each opening for example is 0.5～3 micron.
According to the dot structure of preferred embodiment of the present invention, wherein the degree of depth of each opening for example is 5～10 microns.
In dot structure of the present invention, because of on substrate, being formed with a plurality of openings, and in these openings, forming capacitor and store area with the electric capacity that improves capacitor.Thus, can before the capacitance that does not influence capacitor, put and dwindle capacitor shared area on substrate, and then promote the aperture opening ratio of viewing area.
Description of drawings
Fig. 1 is the schematic top plan view of existing dot structure;
Fig. 2 be among Fig. 1 dot structure along the synoptic diagram of A-A ' profile line;
Fig. 3 A～3H is the dot structure manufacturing process synoptic diagram of first embodiment of the invention;
Fig. 4 A～4B is the manufacture method that first embodiment of the invention forms opening;
Fig. 5 A～5D is another manufacture method that first embodiment of the invention forms opening;
Fig. 6 A～6B is the manufacture method that first embodiment of the invention forms the grid and first electrode layer;
Fig. 7 A～7B is the manufacture method that first embodiment of the invention forms source electrode, drain electrode and the second electrode lay;
Fig. 8 is the schematic top plan view of the dot structure of first embodiment of the invention;
Fig. 9 is the dot structure synoptic diagram of second embodiment of the invention;
Figure 10 is the schematic top plan view of the dot structure of second embodiment of the invention.
The main element symbol description:
10: sweep trace 20: data line
100,200,300: dot structure 110,210: substrate
120,220T: thin film transistor (TFT) 120g, 220g: grid
120s, 220s: source electrode 120d, 220d: drain electrode
120i, 220i: gate insulation layer 122,260: protective seam
130,270: pixel electrode 140: storage capacitors
142: lower electrode layer 144: upper electrode layer
210a: silicon nitride layer 210b: patterning photoresist layer
220,250: metal level 220e: first electrode layer
250e: the second electrode lay A: active member district
B: capacitive region C: capacitor
H: opening P: patterned barrier layer
W1, W2, W3: contact hole
Embodiment
For above and other objects of the present invention, feature and advantage can be become apparent, existing especially exemplified by preferred embodiment, and cooperate appended graphicly, be described in detail below:
First embodiment
Fig. 3 A～3H is the dot structure manufacturing process synoptic diagram of first embodiment of the invention.Please refer to Fig. 3 A, one pixel structure process method of the present invention comprises the following steps: at first, and a substrate 210 is provided, and it has an active member district A and a capacitive region B.Then, form a plurality of opening H in the capacitive region B of substrate 210, the radius of this opening H for example is 0.5～3 micron, and its degree of depth for example is 5～10 microns.The usefulness (will be specified in back) of the space that this opening H is reserved for forming in the future capacitor.Yet the method for formation opening H is enumerated two kinds of preferred implementation hereinafter so that illustrate, but and the mode that is not intended to limit to formation opening H.
Fig. 4 A～4B illustrates the manufacture method that forms opening into first embodiment of the invention, and the method mainly comprises the following steps: please refer to Fig. 4 A, at first, forms a patterned barrier layer P on substrate 210.The material of this patterned barrier layer P is a photoresist.Please refer to Fig. 4 B, then, as etch mask substrate 210 is carried out an etching technics with formation opening H with patterned barrier layer P, and this etching technics for example adopts the deep dry etch process with anisotropic.At last, remove patterned barrier layer P, and form structure as shown in Figure 3A.
Darker along with the degree of depth of opening H, and the etching selection ratio of the relative substrate 210 of the material of selected patterned barrier layer P also can be different.Fig. 5 A～5D is another manufacture method that first embodiment of the invention forms opening.Please refer to Fig. 5 A～5D, the method comprises: form a silicon nitride layer 210a (shown in Fig. 5 A) on substrate 210.Then, form a patterning photoresist layer 210b on silicon nitride layer 210a layer (shown in Fig. 5 B).Please refer to Fig. 5 C, then, as etch mask silicon nitride layer 210a layer is carried out etch step, to form patterned barrier layer P with patterning photoresist layer 210b.In other words, the material of the patterned barrier layer P here is silicon nitride.
Please refer to Fig. 5 D, then, as etch mask substrate 210 is carried out etching technics with formation opening H with patterned barrier layer P, and this etching technics for example is to adopt to have the deep dry etch process of anisotropic.Since silicon nitride to the etching selection ratio of substrate 210 with respect to photoresist to the etching selection of substrate 210 recently high.Therefore, can produce the darker opening H of the degree of depth.Then, remove patterned barrier layer P, and the mode that removes patterned barrier layer P for example is to carry out in the mode of wet etching, and forms structure as Fig. 3 A.
After forming opening H, please then refer to Fig. 3 B, in active member district A, form a grid 220g and in capacitive region B, form one first electrode layer 220e, and the first electrode layer 220e is conformally formed in opening H.In fact, the above-mentioned grid 220g and the first electrode layer 220e are to form simultaneously, and its material for example is titanium, aluminium, titanium nitride, copper, chromium, silver or molybdenum, or alloy or the multi-layer metal structure be made up of above-mentioned metal.
In more detail, the method that forms the grid 220g and the first electrode layer 220e comprises the following steps, at first, carry out a depositing operation, to form a metal level 220 (as shown in Figure 6A), wherein depositing operation for example comprises organometallic chemistry vapour deposition process, molecular layer brilliant method of heap of stone or atomic layer chemical vapor deposition method.At last, carry out a photoetching process and an etching technics,, and then form grid 220g and the first electrode layer 220e (shown in Fig. 3 B) with patterned metal layer 220 (shown in Fig. 6 B).
Then, please refer to Fig. 3 C, on substrate 210, form a gate insulation layer 220i, its cover gate 220g and the first electrode layer 220e.Then, please refer to Fig. 3 D, the gate insulation layer 220i in grid 220g top goes up and forms semi-conductor layer 240.
Please refer to Fig. 3 E, then, form an one source pole 220s and a drain electrode 220d on semiconductor layer 240, and form a second electrode lay 250e in capacitive region B, it covers gate insulation layer 220i.And the aforesaid first electrode layer 220e, the second electrode lay 250e and the gate insulation layer 220i that is sandwiched between the two can constitute a capacitor C.What merit attention is, because conformal being formed in the opening H of capacitor C, therefore under the prerequisite of the capacitance that does not influence capacitor C, can reducing capacitor C shared area on substrate 210, and then improve the aperture opening ratio of viewing area.
In one embodiment, above-mentioned source electrode 220s, drain electrode 220d and the second electrode lay 250e are formation simultaneously, and its material for example is titanium, aluminium, titanium nitride, copper, chromium, silver or molybdenum, or alloy or the multi-layer metal structure be made up of above-mentioned metal.Drain in the present embodiment 220d and the second electrode lay 250e links together and for same rete.Certainly, drain electrode 220d also can separate with the second electrode lay 250e, and above-mentioned situation will describe in detail in a second embodiment.
In more detail, the method that forms source electrode 220s, drain electrode 220d and the second electrode lay 250e comprises the following steps, at first, carry out a depositing operation, to form a metal level 250 (shown in Fig. 7 A), wherein depositing operation comprises organometallic chemistry vapour deposition process, molecular layer brilliant method of heap of stone or atomic layer chemical vapor deposition method.Please refer to Fig. 7 B, carry out a photoetching process and an etching technics,, and then form source electrode 220s, drain electrode 220d and the second electrode lay 250e with patterned metal layer 250, so far above-mentioned, just can in active member district A, form a thin film transistor (TFT) 220T.
Please refer to Fig. 3 F, form a protective seam 260 on substrate 210, it covers source electrode 220s, drain electrode 220d and the second electrode lay 250e.What will illustrate in detail here is, owing to have a plurality of opening H on the substrate 210, if will make being covered on the substrate 210 that protective seam 260 can be smooth, the preferable practice is that (spin on glass SOG) forms protective seam 260 by the spin-on glasses mode.Then, in protective seam 260, form a contact window W1, to expose the second electrode lay 250e, as Fig. 3 G.
Please refer to Fig. 3 H, last, on protective seam 260, form a pixel electrode 270, and pixel electrode 270 meetings be electrically connected with the second electrode lay 250e and be electrically connected with drain electrode 220d.So, just finished dot structure 200 of the present invention, its vertical view as shown in Figure 8.Please also refer to Fig. 8 and Fig. 3 H, dot structure 300 of the present invention comprises substrate 210, thin film transistor (TFT) 220T, a capacitor C, a protective seam 260 and a pixel electrode 270.Wherein, substrate 210 has an active member district A and a capacitive region B, and has been formed with a plurality of opening H in capacitive region B.The radius of this opening H for example is 0.5～3 micron, and its degree of depth for example is 5～10 microns.
In addition, thin film transistor (TFT) 220T is disposed among the active member district A, and capacitor C is disposed among the capacitive region B, and is formed in the opening H.In addition, protective seam 260 cover film transistor 220T and capacitor C, and pixel electrode 270 is disposed on the protective seam 260, and pixel electrode 270 can be electrically connected with thin film transistor (TFT) 220T and capacitor C.The dot structure 200 of present embodiment is to drive by sweep trace 10 and data line 20.And, therefore can increase the capacitor stores area because capacitor C of the present invention is conformal being formed in the opening H.Thus, under the prerequisite of the storage capacitors that does not influence capacitor C, can dwindle capacitor C shared area on substrate 210, and then improve the aperture opening ratio of viewing area.
Second embodiment
Fig. 9 is the dot structure synoptic diagram of second embodiment of the invention.Figure 10 is the schematic top plan view of the dot structure of second embodiment of the invention.Please also refer to Fig. 9 and Figure 10; the present embodiment and first embodiment are similar; wherein difference is: the drain electrode 220d in the dot structure 300 of present embodiment is what separate with the second electrode lay 250e; therefore can form contact window W2 and W3 to expose drain electrode 220d and the second electrode lay 250e respectively in protective seam 260, both (drain electrode 220d and the second electrode lay 250e) are electrically connected with it with W3 is interior so that pixel electrode 270 can be inserted contact window W2.
In sum, dot structure of the present invention and preparation method thereof has following advantage at least: because dot structure of the present invention and manufacture method thereof, it can form a plurality of openings earlier on substrate, and forms capacitor to improve the storage capacitors of capacitor in opening.Therefore can dwindle capacitor shared area on substrate under the capacitance situation of capacitor not influencing, and then promote the aperture opening ratio of viewing area.
Though the present invention discloses as above with preferred embodiment; right its is not in order to limit the present invention; any person skilled in the art; without departing from the spirit and scope of the present invention; when can doing a little change and retouching, so protection scope of the present invention is as the criterion when the scope that ask for protection with claims.
Claims (17)
1. one pixel structure process method is characterized in that comprising:
One substrate is provided, and it has an active member district and a capacitive region;
In the described capacitive region of described substrate, form a plurality of openings;
Form a grid and form one first electrode layer in described active member district in described capacitive region, this first electrode layer is conformally formed in described a plurality of openings;
On described substrate, form a gate insulation layer, cover described grid and described first electrode layer;
On the described gate insulation layer of described grid top, form semi-conductor layer;
On described semiconductor layer, form an one source pole and a drain electrode, and in described capacitive region, form a second electrode lay, cover described gate insulation layer;
On described substrate, form a protective seam, cover described source electrode, drain electrode and the second electrode lay; And
On described protective seam, form a pixel electrode, and described pixel electrode can be electrically connected with described drain electrode, and be electrically connected with described the second electrode lay.
2. one pixel structure process method according to claim 1 is characterized in that the method that forms described a plurality of openings comprises:
On described substrate, form a patterned barrier layer;
Described substrate is carried out an etching technics, to form described a plurality of opening; And
Remove described patterned barrier layer.
3. one pixel structure process method according to claim 2 is characterized in that: the material of described patterned barrier layer comprises photoresist.
4. one pixel structure process method according to claim 2 is characterized in that: the material of described patterned barrier layer comprises silicon nitride.
5. one pixel structure process method according to claim 2 is characterized in that: described etching technics comprises dry etching.
6. one pixel structure process method according to claim 4 is characterized in that: the mode that removes described restraining barrier comprises wet etching.
7. one pixel structure process method according to claim 1 is characterized in that: the radius of each opening is 0.5～3 micron.
8. one pixel structure process method according to claim 1 is characterized in that: the degree of depth of each opening is 5～10 microns.
9. one pixel structure process method according to claim 1 is characterized in that: the method that forms described protective seam comprises the spin-on glasses mode.
10. one pixel structure process method according to claim 1 is characterized in that: before forming described pixel electrode on the described protective seam, also comprise forming a contact window earlier in described protective seam, expose described drain electrode and described the second electrode lay.
11. one pixel structure process method according to claim 1 is characterized in that: the described the second electrode lay of formation is to link together with described drain electrode.
12. one pixel structure process method according to claim 11 is characterized in that: before forming described pixel electrode on the described protective seam, also comprise in described protective seam, forming a contact window earlier, expose described the second electrode lay.
13. one pixel structure process method according to claim 1 is characterized in that, the method that forms described grid and described first electrode layer comprises:
Carry out a depositing operation, to form a metal level, wherein said depositing operation comprises organometallic chemistry vapour deposition process, molecular layer brilliant method of heap of stone or atomic layer chemical vapor deposition method; And
Carry out a photoetching process and an etching technics, with the described metal level of patterning.
14. one pixel structure process method according to claim 1 is characterized in that, the method that forms described source electrode, drain electrode and the second electrode lay comprises:
Carry out a depositing operation, to form a metal level, wherein said depositing operation comprises organometallic chemistry vapour deposition process, molecular layer brilliant method of heap of stone or atomic layer chemical vapor deposition method; And
Carry out a photoetching process and an etching technics, with the described metal level of patterning.
15. a dot structure is characterized in that comprising:
One substrate, it has an active member district and a capacitive region, and has been formed with a plurality of openings in described capacitive region;
One thin film transistor (TFT) is disposed in the described active member district;
One capacitor is disposed in the described capacitive region, and is conformally formed in described a plurality of openings;
One protective seam covers described thin film transistor (TFT) and described capacitor; And
One pixel electrode is disposed on the described protective seam, and described pixel electrode can be connected with described thin film transistor (TFT) and capacitor electrode.
16. dot structure according to claim 15 is characterized in that: the radius of each opening is 0.5～3 micron.
17. dot structure according to claim 15 is characterized in that: the degree of depth of each opening is 5～10 microns.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 200510105758 CN1743933A (en) | 2005-09-27 | 2005-09-27 | Pixel structure and its manufacturing method |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 200510105758 CN1743933A (en) | 2005-09-27 | 2005-09-27 | Pixel structure and its manufacturing method |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN1743933A true CN1743933A (en) | 2006-03-08 |
Family
ID=36139363
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN 200510105758 Pending CN1743933A (en) | 2005-09-27 | 2005-09-27 | Pixel structure and its manufacturing method |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN1743933A (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101452176B (en) * | 2007-12-05 | 2012-06-20 | 株式会社半导体能源研究所 | Display device and method for manufacturing the same |
| WO2013017066A1 (en) * | 2011-08-01 | 2013-02-07 | 京东方科技集团股份有限公司 | Array substrate and lcd panel |
| CN106125436A (en) * | 2016-08-31 | 2016-11-16 | 京东方科技集团股份有限公司 | A kind of array base palte, display floater and manufacture method |
-
2005
- 2005-09-27 CN CN 200510105758 patent/CN1743933A/en active Pending
Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101452176B (en) * | 2007-12-05 | 2012-06-20 | 株式会社半导体能源研究所 | Display device and method for manufacturing the same |
| WO2013017066A1 (en) * | 2011-08-01 | 2013-02-07 | 京东方科技集团股份有限公司 | Array substrate and lcd panel |
| US9041889B2 (en) | 2011-08-01 | 2015-05-26 | Boe Technology Group Co., Ltd. | Array substrate and liquid crystal display panel |
| CN106125436A (en) * | 2016-08-31 | 2016-11-16 | 京东方科技集团股份有限公司 | A kind of array base palte, display floater and manufacture method |
| WO2018041081A1 (en) * | 2016-08-31 | 2018-03-08 | 京东方科技集团股份有限公司 | Array substrate, display panel, manufacturing method, and display device |
| CN106125436B (en) * | 2016-08-31 | 2019-09-20 | 京东方科技集团股份有限公司 | A kind of array substrate, display panel and production method |
| US10615181B2 (en) | 2016-08-31 | 2020-04-07 | Boe Technology Group Co., Ltd. | Array substrate, display panel, manufacturing method, and display device |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN1309034C (en) | Method of fabricating bottom-gated polycrystalline silicon thin film transistor | |
| CN1707343A (en) | Liquid crystal display device and fabricating method thereof | |
| CN1928677A (en) | Transflective liquid crystal display device and method of fabricating the same | |
| CN1573445A (en) | Liquid crystal display device and method of fabricating the same | |
| CN1375733A (en) | Liquid crystal display device having bimetallic layer source electrode and drain electrode and its manufacturing method | |
| CN1707342A (en) | Liquid crystal display device and method of fabricating same | |
| CN1773354A (en) | Liquid crystal display device and method of fabricating the same | |
| CN1605918A (en) | Thin film transistor array substrate and method of fabricating the same | |
| CN1551367A (en) | Thin film transistor array substrate and method of fabricating the same | |
| CN101034685A (en) | Method for manufacturing thin film transistor display array with dual-layer metal line | |
| CN1677209A (en) | Liquid crystal display device and method for fabricating the same | |
| CN1901158A (en) | Method of manufacturing thin film transistor substrate | |
| CN1585088A (en) | Producing method for thin-film transistor array baseplate | |
| CN1740882A (en) | Array base plate for liquid crystal display and producing method thereof | |
| CN1288488C (en) | Array substrate of LCD device and it mfg. method | |
| CN100345053C (en) | Thin film transistor substrate using a horizontal electric field and fabricating method thereof | |
| CN101051626A (en) | Semiconductor structure of display device and its producing method and pixel capacitance structure | |
| CN1542508A (en) | Liquid crystal display device and method for manufacturing the same | |
| CN1743933A (en) | Pixel structure and its manufacturing method | |
| CN1652296A (en) | Pixel structure, film transistor and mfg. method thereof | |
| CN1746756A (en) | Array substrate and manufacture method thereof and display panels with this array substrate | |
| CN1905199A (en) | Array substrate having enhanced aperture ratio, method of manufacturing the same and display device | |
| CN1154174C (en) | Manufacture of planar display | |
| CN1606162A (en) | Thin film transistor array substrate and method of manufacturing the same | |
| CN1832149A (en) | Film transistor array substrate and its manufacturing method |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| ASS | Succession or assignment of patent right |
Owner name: YOUDA PHOTOELECTRIC CO., LTD. Free format text: FORMER OWNER: GUANGHUI ELECTRONIC CO., LTD. Effective date: 20071123 |
|
| C41 | Transfer of patent application or patent right or utility model | ||
| TA01 | Transfer of patent application right |
Effective date of registration: 20071123 Address after: Hsinchu city of Taiwan Province Applicant after: AU Optronics Corporation Address before: Taoyuan County of Taiwan Province Applicant before: Guanghui Electronic Co., Ltd. |
|
| C02 | Deemed withdrawal of patent application after publication (patent law 2001) | ||
| WD01 | Invention patent application deemed withdrawn after publication |