CN1734785A - Semiconductor device and method for manufacturing the same - Google Patents
Semiconductor device and method for manufacturing the same Download PDFInfo
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- CN1734785A CN1734785A CN 200510089706 CN200510089706A CN1734785A CN 1734785 A CN1734785 A CN 1734785A CN 200510089706 CN200510089706 CN 200510089706 CN 200510089706 A CN200510089706 A CN 200510089706A CN 1734785 A CN1734785 A CN 1734785A
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Abstract
A semiconductor device including a drain region of a first conductivity type formed on a semiconductor substrate; an element forming region that is provided on the drain region and that has a concave portion reaching the drain region; a gate electrode disposed in the concave portion; a superjunction structure portion that is disposed in the element forming region and that is formed by alternately arranging a drift layer of the first conductivity type penetrated by the concave portion and a resurf layer of a second conductivity type being in contact with the drift layer on the semiconductor substrate; and a base region of the second conductivity type that is disposed on the superjunction structure portion so as to be in contact with the drift layer in the element forming region, that is penetrated by the concave portion, and that faces the gate electrode with the gate insulating film therebetween.
Description
Technical field
The present invention relates to have the semiconductor device and the manufacture method thereof of super junction structure.
Background technology
For forming MOS field-effect transistor (Metal Oxide Semiconductor FieldTransistor; MOS FET mos field effect transistor) semiconductor device attempts improving its voltage endurance capability.Fig. 4 is the graphic profile of semiconductor device in the past that forms MOS FET.
At N
++The top of the semiconductor substrate 51 of type is formed with the semiconductor layer 54 of the retaining layer (P type post layer) 53 of drift (drift) layer (the N type post layer) 52 that comprise the N type and P type.Drift layer 52 and retaining layer 53 alternately are configured on the direction parallel with semiconductor substrate 51, are forming so-called super knot (super juction) type structure.
Semiconductor layer 54 is connected along its thickness direction, forming and have a plurality of grooves 55 that reach to the degree of depth at the interface of semiconductor substrate 51 and semiconductor layer 54.These a plurality of grooves 55 have substantially the madial wall vertical with semiconductor substrate 51 respectively, substantially uniformly-spaced to form parallel to each other.The inwall of groove 55 is covered with by oxide-film 63, and the embedding layer 64 that is made of polysilicon and dielectric etc. is imbedded in its inside.
Drift layer 52 is configured along groove 55.Retaining layer 53 is configured in respectively along between a pair of drift layer 52 of the madial wall of 2 grooves 55 of adjacency.
Above drift layer 52, be formed with N type zone 56.Above retaining layer 53, to be formed with the base 57 of P type with N type zone 56 ways of connecting.57 skin section is formed with the source region 58 of N type in the base.
With dielectric film 59 separate, and be between N type zone 56 and the source region 58 base 57 and near it mode of subtend dispose gate electrode 60.In addition, source electrode 61 is electrically connected with source region 58 and base 57.Be formed with drain electrode 62 at the back side of semiconductor substrate 51 (with the face of the face opposition side that forms gate electrode 60 or source electrode 61).
Such semiconductor device, certain voltage is applied to source electrode 61 at the state that connects with source electrode 61 and drain a side of 62 and external load, by power supply and drain 62 the opposing party and the state between the external load under use.This voltage that applies is given reverse biased for the PN junction that is formed by retaining layer 53 and drift layer 52.
Under this state, have suitable current potential by making gate electrode 60, in the base 57 between N type zone 56 and the source region 58, form raceway groove near interface with dielectric film 59.In addition, will carry out the reverse biased of dividing potential drop with the on state resistance of external load and MOS FET and supply with the PN junction that is formed by retaining layer 53 and drift layer 52, the expansion of the depletion layer of Sheng Chenging is few thus, keeps the path of carrier (electronics) in drift layer 52.
Thus, electric current is from draining 62 through semiconductor substrates 51, drift layer 52, N type zone 56, base 57 flowing to source electrode 61 with near interface dielectric film 59 (raceway groove) and source region 58.Such semiconductor device has so-called planarized structure, and near raceway groove, electric current flows along the direction parallel with semiconductor substrate 51.
Below, when this MOS FET is off-state, gate electrode 60 do not have above-mentioned suitable current potential, describes when not forming raceway groove.In this case, owing to do not flow through electric current among the MOS FET, so supply voltage forms reverse biased same as before and is applied on the PN junction that is formed by drift layer 52 and retaining layer 53.Therefore, depletion layer is expanded rapidly to drift layer 52 and retaining layer 53 from the interface S of drift layer 52 and retaining layer 53, and drift layer 52 and retaining layer 53 be exhausting fully.Thus, drift layer 52 middle and high concentration ground impurities and seek the reduction of on state resistance can have good voltage endurance (for example, 200V) simultaneously in the lump.
In the manufacturing process of such semiconductor device, can form drift layer 52 by internal face implanted dopant to ditch groove (trench) 55.Ditch groove 55 only is used to form drift layer 52, is not utilized effectively.
Such semiconductor device is opened in the 2003-46082 communique the spy and is disclosed.
But the miniaturization of such its element of planar-type semiconductor device is difficult, in addition since for the zone of the formation raceway groove of miniaturization per unit area can not be big, so in fact almost can not reduce on state resistance.
Summary of the invention
The objective of the invention is to, provide a kind of element can miniaturization, can reduce the semiconductor device and the manufacture method thereof of on state resistance simultaneously.
Semiconductor device of the present invention comprises: the drain region of the 1st conductivity type that forms on semiconductor substrate; Be located at this top, drain region, formed the element-forming region that reaches to the recess in above-mentioned drain region; Be configured in the gate electrode in the above-mentioned recess; Gate insulating film between the internal face of this gate electrode and above-mentioned recess; Super junction structure portion, it makes and is configured in that said elements forms in the zone, the retaining layer of drift layer 2nd conductivity type different with above-mentioned the 1st conductivity type when being connected with this drift layer of the 1st conductivity type that connects above-mentioned recess alternate configurations and forming above above-mentioned semiconductor substrate; The base of above-mentioned the 2nd conductivity type, it is in said elements forms the zone, to be configured in above the above-mentioned super junction structure portion with above-mentioned drift layer ways of connecting, to connect above-mentioned recess and by means of above-mentioned gate insulating film and above-mentioned gate electrode subtend; And the source region, it forms, connects above-mentioned recess in said elements forms the zone, above above-mentioned base.
According to the present invention, gate electrode is configured in the inside of recess.When between drain region (drift layer) and source region, applying the voltage of regulation, current potential that gate electrode has regulation, in the base, form raceway groove near interface with dielectric film.Thus, electric current flows through and semiconductor substrate (drain region), drift layer, the conductive path that is connected with the source region with near interface dielectric film (raceway groove) base.Near raceway groove, electric current along the orientation in drift layer, base and source region, be that the depth direction (direction vertical with semiconductor substrate) of recess flows through.
In addition, in the manufacturing process of this semiconductor device, can import the 1st conductive-type impurity ion to the internal face of recess and form drift layer.In the semiconductor device that forms like this, disposing gate electrode at the recess that is used to form drift layer (super junction structure).Thus, can seek the miniaturization of the element (for example, MOS FET) that constitutes by drift layer, base, source region, gate insulating film and gate electrode.
In addition, by making this element miniaturization, the zone of the formation raceway groove of the per unit area of semiconductor substrate is many, can seek the reduction of on state resistance.
On the other hand, this semiconductor device has the super junction structure portion that is formed by drift layer and retaining layer.When gate electrode does not have the current potential of above-mentioned regulation, if when applying the big voltage of reverse biased for the PN junction that forms by drift layer and retaining layer, then depletion layer is from interface (being designated hereinafter simply as " interface ") expansion rapidly to drift layer and guarantor's layer of drift layer and retaining layer, and drift layer and retaining layer be exhausting fully.Thus, this semiconductor device can have high resistance to pressure (80V～300V) for example.That is to say, the impurity concentration of drift layer is increased, can seek the reduction of on state resistance,, resistance to pressure is increased simultaneously by the exhausting fully of drift layer.
The drain region also can be that semiconductor substrate is from body.Gate electrode for example can be by importing impurity by being constituted by the polysilicon of conductionization (low resistanceization).And gate electrode can be made of metal material, also can contain the both sides of polysilicon and metal material.
The inside of recess also can almost completely be full of by gate electrode.In this case, can alleviate semiconductor substrate generation warpage.
Being used to form the degree of depth of the recess of super junction structure, for example can be about 40 μ m.On the other hand, form the base of raceway groove, for example the skin section (for example in the thickness area about the surperficial 1 μ m of distance) at semiconductor layer forms.,, needn't all be full of in the recess as long as establish just passablely owing to gate electrode by gate electrode so it is just passable only to be configured in the interior top of recess with the base subtend.
Semiconductor device of the present invention, also can also comprise: in above-mentioned recess from above-mentioned gate electrode to bottom side the thicker dielectric film of thickness of the packing material of configuration and the above-mentioned gate insulating film of ratio that forms from the zone lining of the bottom side of subtend above-mentioned base and above-mentioned gate electrode portion at the internal face of above-mentioned recess.
According to such formation, owing to packing material and gate electrode are arranged in the internal configurations of recess, so can alleviate semiconductor substrate generation warpage.Preferably almost completely bury by packing material and gate electrode in the inside of recess.In this case, can alleviate semiconductor substrate generation warpage effectively.
Packing material can be made of polysilicon, also can be made of metal material, also can be made of insulant (for example silica), also can be by being selected from constituting more than 2 kinds among polysilicon, metal material and the insulant.Under the situation that packing material is made of polysilicon, in the recess, for example can easily bury by CVD (Chemical Vapor Deposition chemical vapor deposition) method with packing material.
By forming thin gate insulating film, can seek the high speed and the low consumption electrification of device.On the other hand, the dielectric film that has by the bottom that makes recess thickens, in the recess and the resistance to pressure between the semiconductor substrate (and drift layer) can increase.
The manufacture method of semiconductor device of the present invention, be above the drain region of the 1st conductivity type that forms on the semiconductor substrate, the retaining layer of drift layer that makes above-mentioned the 1st conductivity type and 2nd conductivity type different with above-mentioned the 1st conductivity type, alternately configuration and having forms the manufacture method of semiconductor device of the element-forming region of super junction structure portion on above-mentioned semiconductor substrate, it is characterized in that, comprise following operation: the operation that above above-mentioned drain region, forms the semiconductor layer of above-mentioned the 2nd conductivity type; Connect this semiconductor layer, form and to reach to the operation of the recess in above-mentioned drain region; To the above-mentioned semiconductor layer of the internal face that exposes of above-mentioned recess, import above-mentioned the 1st conductive-type impurity and form above-mentioned drift layer, make the zone that is connected with this drift layer of above-mentioned semiconductor layer become the operation of above-mentioned retaining layer along the internal face of above-mentioned recess; Import the impurity of above-mentioned the 2nd conductivity type from the surface of above-mentioned semiconductor layer and form the operation that has towards the base of above-mentioned the 2nd conductivity type of the exposed division of above-mentioned recess internal face in the skin section of above-mentioned semiconductor layer; Skin section to the above-mentioned base of above-mentioned recess edge part imports above-mentioned the 1st conductive-type impurity and is formed on the operation in the source region of above-mentioned the 1st conductivity type that the internal face of above-mentioned recess exposes; On the internal face of above-mentioned recess, form the operation of dielectric film; For in the above-mentioned recess that forms above-mentioned dielectric film, with than the darker mode of the above-mentioned exposed division of above-mentioned base in the operation of in the bottom section of predetermined prescribed depth, packing material being filled; Remove the operation of removing of above-mentioned dielectric film as mask with above-mentioned packing material; On the exposing surface of the internal face of removing the above-mentioned recess that operation exposes by this, form the operation of the gate insulating film thinner in the zone corresponding than above-mentioned dielectric film with the above-mentioned exposed division of above-mentioned base; In above-mentioned recess inside, with across above-mentioned gate insulating film, form should with the operation of the gate electrode of the exposed division subtend of above-mentioned base.
Can make above-mentioned semiconductor device by such manufacture method.
According to the present invention, import the 1st conductive-type impurity and form drift layer to the internal face of the recess that connects semiconductor layer.Remaining areas by drift layer in the semiconductor layer (and base and source region) constitutes retaining layer.In addition, behind the formation drift layer, form gate electrode at this recess.Like this, by this manufacture method, can utilize the recess that is used to form drift layer (super junction structure) fully and form the grid structure.
Form the operation of semiconductor layer, for example also can comprise the operation that forms epitaxial loayer.
Base and source region both can form before forming gate insulating film and gate electrode, also can form after forming gate electrode.That is to say the part that the recess internal face that so-called exposed division towards the recess internal face is included in formation gate insulating film and gate electrode in the base manifests.Equally, expose towards the recess internal face in the source region, is meant to be included in the part that the recess internal face that forms gate insulating film and gate electrode manifests.
The operation that packing material is filled both can be implemented before the operation that forms the base, also can after the operation that forms the base, be implemented.That is to say, also can not form the base as yet when packing material is filled.
Can each self-forming gate insulating film and dielectric film (dielectric film thicker) than the thickness of gate insulating film.In addition, when forming gate insulating film, dielectric film is covered with by packing material.Therefore, can control the formation thickness of dielectric film and the formation thickness of gate insulating film independently.Thus, can make the thickness semiconductor device thicker of dielectric film than the thickness of gate insulating film.
In the operation that forms dielectric film and gate insulating film, can play the mask that the zone of dielectric film is removed in restriction by packing material, when playing the formation zone (remaining area) of restriction dielectric film, the formation zone of playing the restriction gate insulating film.Therefore, in recess, form proper depth, can make dielectric film and gate insulating film be formed on the zone of regulation by making packing material.
Form the operation of above-mentioned dielectric film, also can comprise the internal face thermal oxidation that makes above-mentioned recess and form the operation of above-mentioned dielectric film, form the operation of above-mentioned gate insulating film, also can comprise the internal face thermal oxidation that makes above-mentioned recess and form the operation of above-mentioned gate insulating film.In this case, by condition, for example heating-up temperature or the heating time etc. of control thermal oxidation, can control the thickness of dielectric film or gate insulating film.
Since in recess with relevant with the depth direction of recess, in the bottom section of predesignating the degree of depth, forming packing material than the darker mode of the exposed division of base (part that manifests at the internal face of recess), so after forming the operation of gate insulating film, the top in recess forms and vacancy corresponding to the regional subtend of base.
Form the operation of above-mentioned gate electrode, can be included in the operation that the material that constitutes gate electrode is supplied with in the vacancy in above-mentioned recess after the operation that forms above-mentioned gate insulating film.Thus, form across gate insulating film, with the gate electrode of comprehensive subtend of base.
Packing material for example can be made of polysilicon.In this case, by CVD method etc. can with packing material well (densely) imbed depth-to-width ratio big (for example, with respect to width be about 2 μ m and the degree of depth is about 40 μ m) recess.And gate electrode can be made of metal material, also can contain the both sides of polysilicon and metal material.
Fill the operation of above-mentioned packing material, also can be included in the above-mentioned recess packing material that is full of above-mentioned packing material until the top from the degree of depth of afore mentioned rules and supply with and make above-mentioned packing material carry out the operation of dark etching after operation and this packing material are supplied with operation until the degree of depth of afore mentioned rules.
According to this one-tenth,,, the position of top (the dark etching face) of packing material forms so that can becoming the mode of prescribed depth by controlling dark etched thickness.
When forming gate insulating film, also can above packing material, form dielectric film.Can obtain in this case between gate electrode and packing material, also forming the semiconductor device of dielectric film the gate insulating film between gate electrode and base.
Can easily make the dark etching of packing material under the situation that packing material is made of polysilicon.
Form the operation of above-mentioned base, also can comprise operation from the foreign ion of above-mentioned the 2nd conductivity type to the internal face of above-mentioned recess that inject.
Above-mentioned or other purpose, feature and effect of the present invention can show with reference to the explanation of accompanying drawing by following execution mode.
Description of drawings
Fig. 1 is the graphic profile of structure of the semiconductor device of expression the 1st execution mode of the present invention.
Fig. 2 is the graphic profile of structure of the semiconductor device of expression the 2nd execution mode of the present invention.
Fig. 3 a～Fig. 3 h is the graphic profile of manufacture method that is used for the semiconductor device of key diagram 2.
Fig. 4 is the graphic profile with semiconductor device in the past of super junction structure.
Embodiment
Fig. 1 is the graphic profile of structure of the semiconductor device of expression the 1st execution mode of the present invention.This semiconductor device 1 forms MOS FET and forms on silicon substrate 2.
At the P that forms the drain region
+On the silicon substrate 2 of type, be provided with the element-forming region 3 that has formed MOS FET (element).Pass-through member forms zone 3, forms to reach to a plurality of grooves 4 of the skin section of silicon substrate 2.Each groove 4 has respectively and the vertical substantially madial wall of silicon substrate 2, and the direction vertical with Fig. 1 paper prolongs.That is to say that the length direction of each groove 4 is directions vertical with the paper of Fig. 1, the Width of each groove 4 is parallel with the paper of Fig. 1 and parallel with silicon substrate 2 directions.
The width of groove 4 for example is about 2 μ m, and the degree of depth of groove 4 for example is about 40 μ m.The gap of 2 adjacent grooves 4 (being clipped in the width of the element-forming region 3 between 2 adjacent grooves 4) for example is about 4 μ m～6 μ m.
2 grooves 4 in Fig. 1, have only been represented, but in semiconductor device 1, can form more groove 4 that these grooves 4 are substantially uniformly-spaced to form.
The internal face of each groove 4 is by silica (SiO
2) dielectric film 5 that constitutes is covered with.The inside of each groove 4 is buried by the gate electrode 6 that constitutes by the polysilicon that imports the impurity conduction.
Element-forming region 3 comprises: on silicon substrate 2 with the P of silicon substrate 2 ways of connecting alternate configurations
- Type drift layer 7 and N
-The base 9 of the retaining layer 8 of type, the N type that above drift layer 7 and retaining layer 8, forms and the P that 9 skin section forms in the base
+The source region 10 of type.
Internal face along the Width both sides of each groove 4 is forming drift layer 7.Between a pair of drift layer 7 that forms along the internal face of 2 adjacent grooves 4 respectively, forming retaining layer 8.The formation degree of depth apart from the surface of element-forming region 3 of drift layer 7 and retaining layer 8 is identical substantially.Drift layer 7 and the super junction structure of retaining layer 8 formations portion 20.
Above gate electrode 6 and element-forming region 3, be formed with silicon oxide film 11.On thickness direction, be formed with the contact hole 12 that connects silicon oxide layer 11, in contact hole 12, expose the part in base 9 and source region 10.
Above element-forming region 3 and silicon oxide layer 11, be formed with the electrode (source electrode) 13 that the metal by aluminium (Al) etc. constitutes.Electrode 13 forms in the mode that buries contact hole 12, is electrically connected with base 9 and source region 10.Electrode 13 and gate electrode 6 are by silicon oxide layer 11 electric insulations.
With the face of element-forming region 3 opposition sides of silicon substrate 2 on be formed with electrode (drain electrode) 14.
Under this state,, electric current is flow through between electrode 13 and electrode 14 by the current potential that makes gate electrode 6 have regulation.At this moment, in the base 9 between drift layer 7 and the source region 10, form raceway groove at the near interface with dielectric film 5, semiconductor device 1 is conducting state.The drift layer 7 of base 9 and periphery thereof and the dielectric film 5 between source region 10 and the gate electrode 6 have the function of gate insulating film.
At this moment, will carry out the reverse biased (for example 2V) of dividing potential drop with the on state resistance of external load and MOS FET and supply with the PN junction that is formed by drift layer 7 and retaining layer 8, the expansion of the depletion layer of Sheng Chenging is few thus, the path of residual carrier (electronics) in drift layer 7.In the semiconductor device 1 of conducting state, electric current through in the drift layer 7 not the part of exhausting between electrode 13 and electrode 14, flow through.
Thus, electric current forms through silicon substrates 2 (drain region), drift layer 7, base 9 and near interface dielectric film 5 (raceway groove), source region 10 from electrode 14 and reaches to the current path of electrode 13.Near raceway groove, electric current along the orientation in drift layer 7, base 9 and source region 10, be that the depth direction (direction vertical with silicon substrate 2) of groove 4 flows.
Thus, this semiconductor device 1 can seek to relate to the miniaturization of the element (MOS FET) of the direction parallel with silicon substrate 2.In addition, by making the element miniaturization, the zone of formation raceway groove that can make the per unit area of silicon substrate 2 is increased and is sought the reduction of on state resistance.
On the other hand, when this semiconductor device 1 is off-state, drain electrode 6 do not have the current potential of afore mentioned rules, when not forming raceway groove, owing to do not flow through electric current among the MOS FET, so supply voltage forms reverse biased same as before and is applied on the PN junction that is formed by drift layer 7 and retaining layer 8.
At this moment, near the interface S of drift layer 7 and retaining layer 8, depletion layer is from interface S expansion rapidly to drift layer 7 and retaining layer 8, and drift layer 7 and retaining layer 8 be exhausting fully.Thus, this semiconductor device 1 can have big resistance to pressure (for example, 80V～300V).That is to say that the impurity concentration that makes drift layer 7 increases and can seek the reduction of on state resistance, can also realize high voltage endurance simultaneously.
Fig. 2 is the graphic profile of structure of the semiconductor device of expression the 2nd execution mode of the present invention.In Fig. 2, give identical reference marks and omit its explanation with the part that each several part shown in Figure 1 is corresponding.
This semiconductor device 21 does not form MOS FET above silicon substrate 2.This semiconductor device 21 has the semiconductor device 1 similar structure with Fig. 1, but the bottom side in each groove 22 suitable with the groove 4 of semiconductor device 1 disposes the packing material 23 that for example is made of polysilicon, and disposes the gate electrode 24 that is constituted by the polysilicon of conductionization by by importing impurity in the upper side of each groove 22.
The degree of depth of groove 22 for example is about 40 μ m, and the thickness of base 9 for example is about 1 μ m.That is to say, form in the thickness area of base 9 about the skin section 1 μ m of element-forming region 3.Gate electrode 24 is as long as be set as with base 9 and near drift layer 7 and source region 10 subtends thereof just passable.Therefore, such semiconductor device 21 can be in each groove 22 upper side configuration gate electrode 24, in the zone darker, dispose the structure of packing material 23 than gate electrode 24.
The width of groove 22 is compared with the part of internal configurations packing material 23, and the part of its internal configurations gate electrode 24 is wide a little.
The dielectric film 25 suitable with the dielectric film 5 of semiconductor device 1 also is formed between packing material 23 and the gate electrode 24 except the internal face at groove 22 forms.The inside of groove 22 almost completely is full of by packing material 23, gate electrode 24 and dielectric film 25.Thus, can alleviate silicon substrate 2 warpage takes place.
9 and subtend portion gate electrode 24 be until the lining of the zone of bottom side and form at the internal face of groove 22, from the base for oxide-film 17.The thickness of oxide-film 17 is thicker than the thickness of oxide-film 19.By making the drift layer 7 and the dielectric film 25 between the source region 10 (having part in the oxide-film 19) attenuation of gate electrode 24 and base 9 and periphery thereof, high speed and the low consumption electrification that can seek device as the gate insulating film function.On the other hand, thicken, the resistance to pressure between packing material 23 and silicon substrate 2 and the drift layer 7 is increased by making the dielectric film 25 (oxide-film 17) between packing material 23 and silicon substrate 2 and the drift layer 7.
The gate electrode 24 that contains metal material is with not gate electrode 24 comparisons of metal-containing material (in fact being made of polysilicon), because resistivity is low, so resistance value is low.Therefore, the semiconductor device 21 of the gate electrode 24 by having metal-containing material, owing to can shorten the switching time of the element that forms in the semiconductor device 21, so such semiconductor device 21 high speed motion may.And, this semiconductor device 21, owing to can reduce switch cost, so.Can reduce consumption electric power.
Fig. 3 a～Fig. 3 h is the graphic profile of manufacture method that is used for the semiconductor device 21 of key diagram 2.
At first, be P at conductivity type
+Forming conductivity type on the silicon substrate 2 of type is N
-The epitaxial loayer 15 of type is being formed on the mask 16 that forms opening 16a on the position corresponding with the groove 22 of semiconductor device 1 on the epitaxial loayer 15.Mask 16 for example is made of silica or silicon nitride.
Then,, make epitaxial loayer 15 carry out dry ecthing (for example, reactive ion etching), epitaxial loayer 15 is connected, form a plurality of grooves 22 until the skin section of silicon substrate 2 by means of the opening 16a of mask 16.The depth-to-width ratio of groove 22 is big, and for example the width with respect to groove 22 is about 2 μ m, and the degree of depth of groove 22 is about 40 μ m.
Then, shown in arrow A among Fig. 3 a, squeeze into the foreign ion that the P type is controlled of being used for that (injections) is used to form drift layer 7 in the mode that forms the angle of regulation with (along its length) madial wall perpendicular to the Width of groove 22.Equally, also squeeze into the foreign ion of P type to madial wall relevant with the Width of groove 22, opposition side.The direction of the impurity of squeezing into the P type of this moment is represented with the arrow B among Fig. 3 a.
When epitaxial loayer 15 was squeezed into the p type impurity ion, even with on this iontophoresis silicon substrate 2, owing to imported the impurity of P type on the silicon substrate 2 with high concentration, the impurity concentration of silicon substrate 2 did not change in fact.
Then, make silicon substrate 2 annealing, the skin section of the epitaxial loayer 15 that exposes in the both sides of the Width of each groove 22 forms the 1st injection zone 26 that imports this impurity.This state is shown in Fig. 3 a.
Then, will be heated to the temperature of regulation through the silicon substrate 2 of above operation, on the surface of exposing, be to form oxide-film 17 on the internal face of each groove 22.At this moment, with the thickness of the 1st injection zone 26 complete non-oxidizing mode controlled oxidation films 17.This state is shown in Fig. 3 b.
Then, bury each groove 22, form polysilicon film 18.Above epitaxial loayer 15, also form polysilicon film 18.This operation can be implemented with for example CVD (Chemical Vapor Deposition chemical vapor deposition) method, in this case, as mentioned above, even the depth-to-width ratio of groove 22 is big, also can easily imbed polysilicon film 18 densely in the inside of groove 22.This state is shown in Fig. 3 c.Polysilicon film 18 thereafter also can be by importing the impurity conduction.
Then, make polysilicon film 18 carry out dark etching, remove the polysilicon film 18 on the top in groove 22 outsides and each groove 22.Thus, in each groove 22, relate to the depth direction of groove 22, only in the zone darker, be the state that has polysilicon film 18 than the formation degree of depth of the base in the semiconductor device shown in Figure 2 21 9.That is to say, under this state, top (dark etching face) of polysilicon film 18, in groove 22, be in than the base 9 of the internal face of the groove 22 of semiconductor device shown in Figure 2 21 with the dark prescribed depth of the subtend portion of gate electrode 24.Thereby in groove 22, above polysilicon 18, can guarantee the vacancy.
In addition, under this state, remove the oxide-film 17 (Fig. 3 d represents with two-dot chain line) and the mask 16 of (the exposing) that be arranged in the place more shallow by etching from polysilicon 18 than polysilicon 18.Thus, for the width of groove 22, the top of its groove 22 is than more the deep branch is wide slightly.This state is shown in Fig. 3 d.
Then, make silicon substrate 2 heating, make exposing surface, be the surface heat oxidation of epitaxial loayer 15 of top and groove 22 outsides of madial wall, the polysilicon film 18 on each groove 22 top, form oxide-film 19 through above operation.At this moment, control heating-up temperature and heating time etc., the thickness of oxide-film 19 can form the thickness of the regulation thinner than the thickness of oxide-film 17.The remainder of polysilicon film 18 is packing materials 23.This state is shown in Fig. 3 e.
Then, polysilicon is imbedded the vacancy on each groove 22 top, in this polysilicon, import impurity again, form by the gate electrode 24 of conductionization.This state is shown in Fig. 3 f.
The operation of polysilicon being imbedded the vacancy on groove 22 tops can comprise that also (with reference to Fig. 3 c and Fig. 3 d) is same when for example forming with packing material 23 (polysilicon film 18), to bury each groove 22 inside, after the mode on the surface of covering epitaxial loayer 15 forms polysilicon film, the operation of dark this polysilicon film of etching.
Then, remove the oxide-film 19 that on the surface of epitaxial loayer 15, exposes by etching.The remainder of the remainder of oxide-film 19 and oxide-film 17 constitutes dielectric film 25.
Then, on the surface of epitaxial loayer 15, inject the impurity that is used to control the N type, form the 2nd injection zone 27.This state is shown in Fig. 3 g.
Then, make silicon substrate 2 heating, p type impurity in the 1st injection zone 26 and the N type impurity in the 2nd injection zone 27 are spread in epitaxial loayer 15, form drift layer 7 and base 9 respectively through above operation.Remaining zone of epitaxial loayer 15 (zone that is connected with drift layer) becomes retaining layer 8.Base 9 has towards the exposed division of groove 22 internal faces (part that reveals on the internal face of groove 22) 9a.This state is shown in Fig. 3 h.
At this moment, select heating condition so that the border of base 9 in groove 22 internal faces and drift layer 7 than the depth direction that relates to groove 22, be in oxide-film 19 top shallow of the top of packing material 23.Thus, gate electrode 24 can with the comprehensive subtend from the exposed division 9a of the internal face of groove 22 of base 9.
Then, above base 9, form the diaphragm (not shown) have with source region 10 corresponding opening of semiconductor device 21,, inject the impurity of P type to the skin section of base 9 by means of the opening of this diaphragm.Heat silicon substrate 2 again, make p type impurity 9 diffusions of the skin section of injecting base 9, form source region 10 in the base.Thus, obtain comprising the element-forming region 3 in drift layer 7, retaining layer 8, base 9 and source region 10.
With reference to Fig. 2, through element-forming region 3 sides of the silicon substrate 2 of above operation comprehensively on form silicon oxide film, in addition,, form contact hole 12 by means of this silicon oxide film of the diaphragm with predetermined pattern (not shown) etching.The remainder of silicon oxide layer becomes silicon oxide film 11.
Then, the metal material of regulation is supplied with a side and its opposition side of the formation element-forming region 3 of the silicon substrate 2 that passes through above operation respectively, formed electrode 13,14 respectively.Thus, obtain semiconductor device shown in Figure 2 21.
As mentioned above, this semiconductor device 21 can utilize the groove 22 that is used to form drift layer 7 (super junction structure) fully and form the grid structure.
In above manufacture method, can form oxide-film 17 and oxide-film 19 by different oxidizing condition (for example, the heating-up temperature of silicon substrate 2 and heating time).In addition, when forming oxide-film 19, can be covered with oxide-film 17 with polysilicon film 18.Therefore, can independent controlled oxidation film 17 and the formation thickness of oxide-film 19.
Thus, as shown in Figure 2, for the thickness of dielectric film 25, one of the part of setting between packing material 23 and silicon substrate 2 and the drift layer 7 (oxide-film 17) can be with thicker than the part of setting between gate electrode 24 and the base 9 (oxide-film 19).
In the operation (with reference to Fig. 3 d and Fig. 3 e) that forms oxide-film 17 and oxide-film 19, limit the effect of the mask in the zone of removing oxide-film 17 by polysilicon film 18 performances, when limiting the formation zone (remaining zone) of oxide-film 17, the also effect in the formation zone of performance restriction oxide-film 19.Therefore, by in groove 22, forming polysilicon film 18, just can in the zone of regulation, form oxide-film 17 and oxide-film 19 with the appropriate depth zone.By controlling dark etched thickness, can easily control the formation degree of depth of the polysilicon film 18 in the groove 22.
In addition, in above manufacture method,, can obtain semiconductor device shown in Figure 11 by in the formation of oxide-film 17 with remove the back and form the oxide-film 5 that has with the thickness of degree with oxide-film 19 and replaces formation oxide-film 17.In this case, carry out dark etching, the conduction (low resistanceization) and make the surface cardinal principle flush of this polysilicon film 18 and the epitaxial loayer 15 so that polysilicon film 18 in imbedding groove 22 (4) (with reference to Fig. 3 c) imports impurity can form gate electrode 6.
The explanation of embodiments of the present invention as previously discussed, but the present invention also can otherwise implement.For example, the conduction type of each semiconductor portions of semiconductor device 1,21 also can be opposite, that is to say, in the above-described embodiment, part that also can the P type is the N type, and the part of N type is the P type.
In the manufacture method of semiconductor device shown in Figure 2 21, also can form oxide-film 17 (with reference to Fig. 3 b) back, form that polysilicon film 18 (with reference to Fig. 3 c) is preceding removes oxide-film 17 fully by etching, make the internal face thermal oxidation of each groove 4 once more, form the oxide-film that has with oxide-film 17 condition of equivalent thickness.
The semiconductor device that has formed MOS FET on silicon substrate 2 has been described in the above embodiment, but semiconductor device of the present invention also can be the semiconductor device that has formed IGBT (the integrated grid bipolar transistor of Insulated Gate Bipolar Transistor) on silicon substrate 2.
Have been described in detail for embodiments of the present invention; the concrete example that uses but these only are used for understanding technology contents of the present invention; the present invention is not limited to these concrete examples and explains; only otherwise exceed the various changes of making in the spirit and scope of the present invention, all should be included in protection scope of the present invention.
Claims (5)
1. a semiconductor device is characterized in that, comprising:
The drain region of the 1st conductivity type that on semiconductor substrate, forms;
Be located at top, this drain region, form and reach to the element-forming region of the recess in above-mentioned drain region;
Be configured in the gate electrode in the above-mentioned recess;
Gate insulating film between the internal face of this gate electrode and above-mentioned recess;
Super junction structure portion, it makes and is configured in that said elements forms in the zone, the retaining layer of drift layer 2nd conductivity type different with above-mentioned the 1st conductivity type when being connected with this drift layer of the 1st conductivity type that connects above-mentioned recess alternate configurations and forming above above-mentioned semiconductor substrate;
The base of above-mentioned the 2nd conductivity type, its in said elements forms the zone, be configured in above the above-mentioned super junction structure with above-mentioned drift layer ways of connecting, connect above-mentioned recess, by means of above-mentioned gate insulating film and above-mentioned gate electrode subtend; With
The source region, it forms, connects above-mentioned recess in said elements forms the zone, above above-mentioned base.
2. semiconductor device according to claim 1 is characterized in that, also contains:
The packing material that in above-mentioned recess, disposes from above-mentioned gate electrode to bottom side; With
At the internal face of above-mentioned recess, the thicker dielectric film of thickness of the above-mentioned gate insulating film of ratio that forms from the zone lining of the bottom side of subtend above-mentioned base and above-mentioned gate electrode portion.
3. the manufacture method of a semiconductor device, be above the drain region of the 1st conductivity type that forms on the semiconductor substrate, the retaining layer of drift layer that makes above-mentioned the 1st conductivity type and 2nd conductivity type different with above-mentioned the 1st conductivity type on above-mentioned semiconductor substrate alternately configuration and having formed the manufacture method of semiconductor device of the element-forming region of super junction structure portion, it is characterized in that, comprise following operation:
Above above-mentioned drain region, form the operation of the semiconductor layer of above-mentioned the 2nd conductivity type;
Connect this semiconductor layer, form and to reach to the operation of the recess in above-mentioned drain region;
Import above-mentioned the 1st conductive-type impurity to the above-mentioned semiconductor layer that exposes internal face of above-mentioned recess and form above-mentioned drift layer, make the zone that is connected with this drift layer of above-mentioned semiconductor layer become the operation of above-mentioned retaining layer along the internal face of above-mentioned recess;
From the surface of above-mentioned semiconductor layer, import the impurity of above-mentioned the 2nd conductivity type and, form the operation that has towards the base of above-mentioned the 2nd conductivity type of the exposed division of above-mentioned recess internal face in the skin section of above-mentioned semiconductor layer;
Skin section to the above-mentioned base of above-mentioned recess edge part imports above-mentioned the 1st conductive-type impurity and is formed on the operation in the source region of above-mentioned the 1st conductivity type that the internal face of above-mentioned recess exposes;
On the internal face of above-mentioned recess, form the operation of dielectric film;
For in the above-mentioned recess that forms above-mentioned dielectric film, with than the darker mode of the above-mentioned exposed division of above-mentioned base in the operation of in the bottom section of predetermined prescribed depth, packing material being filled;
Remove the operation of removing of above-mentioned dielectric film as mask with above-mentioned packing material;
In the exposing surface of the internal face of removing the above-mentioned recess that operation exposes by this zone corresponding, form the operation of the gate insulating film thinner than above-mentioned dielectric film with the above-mentioned exposed division of above-mentioned base; With
In the inside of above-mentioned recess, form with across above-mentioned gate insulating film, should with the operation of the gate electrode of the exposed division subtend of above-mentioned base.
4. the manufacture method of semiconductor device according to claim 3 is characterized in that, the operation of filling above-mentioned packing material comprises:
In above-mentioned recess from the degree of depth of afore mentioned rules until above supply with above-mentioned packing material packing material supply with operation and
This packing material makes above-mentioned packing material carry out the operation of dark etching until the degree of depth of afore mentioned rules after supplying with operation.
5. the manufacture method of the described semiconductor device of claim 3 is characterized in that, forms the operation of above-mentioned base, comprises operation from the foreign ion of above-mentioned the 2nd conductivity type to the internal face of above-mentioned recess that inject.
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Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN102347364A (en) * | 2010-07-23 | 2012-02-08 | 英飞凌科技奥地利有限公司 | Semiconductor device with drift regions and compensation regions |
| CN102403354A (en) * | 2010-09-15 | 2012-04-04 | 无锡华润上华半导体有限公司 | CoolMOS device and manufacturing method for same |
| CN102983164A (en) * | 2011-09-07 | 2013-03-20 | 株式会社东芝 | Semiconductor device and method for manufacturing same |
| CN103426912A (en) * | 2012-05-18 | 2013-12-04 | 英飞凌科技奥地利有限公司 | Semiconductor device including superjunction structure and method of manufacturing |
| CN105895529A (en) * | 2015-02-16 | 2016-08-24 | 瑞萨电子株式会社 | Semiconductor device manufacturing method and semiconductor device |
| CN107424928A (en) * | 2016-05-23 | 2017-12-01 | 英飞凌科技股份有限公司 | Power semiconductor with charging balanced design |
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Family Cites Families (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP3291957B2 (en) * | 1995-02-17 | 2002-06-17 | 富士電機株式会社 | Vertical trench MISFET and method of manufacturing the same |
| EP1026749B1 (en) * | 1998-07-23 | 2003-09-17 | Mitsubishi Denki Kabushiki Kaisha | Method of manufacturing a semiconductor device and semiconductor device obtainable thereby |
| JP4924781B2 (en) * | 1999-10-13 | 2012-04-25 | 株式会社豊田中央研究所 | Vertical semiconductor device |
| JP2001210823A (en) * | 2000-01-21 | 2001-08-03 | Denso Corp | Semiconductor device |
| JP4528460B2 (en) * | 2000-06-30 | 2010-08-18 | 株式会社東芝 | Semiconductor element |
| JP4559691B2 (en) * | 2001-05-25 | 2010-10-13 | 株式会社東芝 | Manufacturing method of semiconductor device |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN102347364A (en) * | 2010-07-23 | 2012-02-08 | 英飞凌科技奥地利有限公司 | Semiconductor device with drift regions and compensation regions |
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| CN102983164A (en) * | 2011-09-07 | 2013-03-20 | 株式会社东芝 | Semiconductor device and method for manufacturing same |
| CN103426912A (en) * | 2012-05-18 | 2013-12-04 | 英飞凌科技奥地利有限公司 | Semiconductor device including superjunction structure and method of manufacturing |
| CN103426912B (en) * | 2012-05-18 | 2016-04-27 | 英飞凌科技奥地利有限公司 | Comprise semiconductor device and the manufacture method of super-junction structure |
| CN105895529A (en) * | 2015-02-16 | 2016-08-24 | 瑞萨电子株式会社 | Semiconductor device manufacturing method and semiconductor device |
| CN105895529B (en) * | 2015-02-16 | 2021-10-29 | 瑞萨电子株式会社 | Semiconductor device manufacturing method and semiconductor device |
| CN107424928A (en) * | 2016-05-23 | 2017-12-01 | 英飞凌科技股份有限公司 | Power semiconductor with charging balanced design |
| CN108807184A (en) * | 2018-06-25 | 2018-11-13 | 张帅 | Field-effect transistor with super-junction structures and its manufacturing method |
| CN108807184B (en) * | 2018-06-25 | 2021-01-05 | 济南安海半导体有限公司 | Field effect transistor with super junction structure and manufacturing method thereof |
Also Published As
| Publication number | Publication date |
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| JP2012094920A (en) | 2012-05-17 |
| CN100499163C (en) | 2009-06-10 |
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