CN1728559A - Built self testing unit and method inside D/A converter - Google Patents
Built self testing unit and method inside D/A converter Download PDFInfo
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- CN1728559A CN1728559A CN 200410058641 CN200410058641A CN1728559A CN 1728559 A CN1728559 A CN 1728559A CN 200410058641 CN200410058641 CN 200410058641 CN 200410058641 A CN200410058641 A CN 200410058641A CN 1728559 A CN1728559 A CN 1728559A
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Abstract
D/A signal is differentiated through a differential element in order to obtain difference between pulses of analog signals. Based on a threshold voltage, Schmidt triggering unit converts the analog signals to digital signals. Using a duty cycle picker calculates duty cycle of the digital signal, which is sent to a signature analyzer to calculate degree of non-linearity of differential in order to carry out error analysis. In order to treat D/A signal in high speed, a combined circuit including a pattern test unit, a sample-and-hold circuit and a logic circuit is adopted as front-end circuit of differential element to lower speed of D/A signal.
Description
Technical field
The invention relates to a kind of built-in self-test (Built In Self-Test, BIST) device and method, particularly about a kind of digital-analog convertor (Digital-to-Analog Converter, built-in self-test device and method DAC) of being applied to.
Background technology
Along with the development of highly integrated circuit, more and more Duo circuit is to be integrated in the System on Chip/SoC (SoC).(Analog-to-DigitalConverter ADC) and in conjunction with mixed signal (mixed-signal) circuit of simulation and digital function has been applied to as wireless telecommunications, data conversion system and satellite communication aspect for many digital-analog convertors, analogue-to-digital converters.In recent years, foregoing circuit has developed and the built-in self-test technology, directly carries out the test of self hardware by built-in circuit, to save cost and to shorten the testing time.
Traditionally, the built-in self-test of digital-analog convertor is directly to handle the voltage signal that digital revolving die is intended (DA), but, often must add auxiliary circuit or utilize specific process to be handled, yet the result is still unsatisfactory owing to being difficult for differentiating between analog signal and noise.In addition,, must increase the circuit of an acquisition voltage, and its sampling frequency often is required to be more than the twice of this DA signal frequency, thereby has quite high technical difficulty degree if need to handle the DA signal of high frequency.
Summary of the invention
Main purpose of the present invention provides a kind of built-in self-test device and method of high-speed figure-analog converter, utilize each interpulse error of detection signal and analyze, can reduce the technical difficulty degree of existing built-in self-test, and the foundation of circuit modifications is provided, or the specification (spec.) that is used for circuit detects.
For achieving the above object, the present invention discloses a kind of built-in self-test device of digital-analog convertor, its mainly comprise one first low pass filter (Low Pass Filter, LPF), a differentiation element, one second low pass filter, a schmidt trigger (Schmitt trigger) unit, a duty cycle (duty cycle) acquisition device and a signature analyzer (signature analyzer).This first low pass filter is to be used for analog signal smoothing that a digital-analog convertor is sent.This differentiation element connects the output of this first low pass filter, is used for this analog signal is carried out differential, to obtain each interpulse difference of this analog signal.This second low pass filter connects the output of this differentiation element, is used for the analog signal smoothing behind the differential.This schmidt trigger unit is to be used for the analog signal that this second low pass filter is sent is converted to digital signal according to a critical voltage.This duty cycle acquisition device is the duty cycle that is used to calculate this digital signal.This signature analyzer is to utilize this duty cycle to carry out error analysis.
The implementation method of the built-in self-test device of this digital-analog convertor can reduce and comprise the following step: (1) utilizes this digital-analog convertor that one digital signal is converted to an analog signal; (2) this analog signal is carried out the smoothing first time, to remove noise; (3) will carry out differential through the analog signal of the smoothing first time, to obtain each interpulse difference of this analog signal; (4) this analog signal is carried out the smoothing second time; (5) this analog signal is converted to digital signal according to a critical voltage, wherein the part greater than this critical voltage is converted to high levels " 1 ", is converted to low level " 0 " less than the part of this critical voltage; (6) calculate duty cycle of this digital signal; (7) (differentialnon-linearity DNL), is used to judge the error of this analog signal to utilize this duty cycle computing differential nonlinearity.
As for the high speed D Signal Processing, the front end circuit of above-mentioned differentiation element can utilize one to comprise the combinational circuit replacement of taking a sample and keep (sample-and-hold) circuit and a logical circuit in a test pattern (test pattern) unit,, in order to reduce the speed of DA signal.This test pattern unit is in order to produce a test pattern, and it comprises several the position signals that will deliver to this digital-analog convertor, and wherein this signal is the combination of the identical bits of DA signal, and equals zero between adjacent DA signal.This sampling and holding circuit are to take a sample and keep at the output signal of this digital-analog convertor, use the cumulative and continuous basically output signal of generation and deliver to this differentiation element and handle.This logical circuit is in order to the control signal of this sampling and holding circuit and back-end circuit to be provided.
The implementation method of built-in self-test device that is used to handle the digital-analog convertor of high speed D signal can reduce and comprise the following step: (1) produces a test pattern that comprises several signals, and wherein this signal is the combination of the identical bits of several DA signals to be measured; (2) be an analog signal with this DA conversion of signals; (3) taking a sample at this analog signal and keep, wherein is to take a sample at the pulse of this analog signal, and the peak value of the pulse of this analog signal is then kept; (4) will carry out differential through sampling and the analog signal of keeping, to obtain its each interpulse difference; (5) this analog signal is carried out smoothing; (6) this analog signal is converted to digital signal according to a critical voltage; (7) calculate duty cycle of this digital signal; And (8) utilize this duty cycle to calculate the error of this analog signal.
In brief, the present invention also directly handles the DA signal unlike existing built-in self-test circuit, but utilize differential technology to find out the difference of two adjacent pulses of analog signal, and the amplitude of both difference representatives is converted to duty cycle of digital signal, use the error of analyzing adjacent number, can significantly reduce the complexity and the degree of difficulty of the built-in self-test of digital-analog convertor.
Description of drawings
The present invention will illustrate according to accompanying drawing, wherein:
Fig. 1 is the built-in self-test schematic representation of apparatus of digital-analog convertor of the present invention;
The waveform of signal after differential and smoothing of the built-in self-test device and method of Fig. 2 example digital-analog convertor of the present invention;
Fig. 3 is the conversion of signals schematic diagram of flip-flop element of the built-in self-test device and method of digital-analog convertor of the present invention;
The duty cycle acquisition mode of the built-in self-test device and method of Fig. 4 (a) and 4 (b) examples digital-analog convertor of the present invention;
Fig. 5 is the duty cycle analysis mode schematic diagram of the built-in self-test device and method of digital-analog convertor of the present invention;
Fig. 6 shows a test result of the built-in self-test device and method of digital-analog convertor of the present invention;
Fig. 7 shows the built-in self-test device of another digital-analog convertor of the present invention;
The circuit diagram of the logical circuit in Fig. 8 exemplary plot 7;
Fig. 9 shows the control signal that the logical circuit of the built-in self-test device of digital-analog convertor of the present invention is exported and the relation of clock signal and BIST signal;
Figure 10 shows the control signal that the logical circuit of built-in self-test device when the DA signal of handling four of digital-analog convertor of the present invention exported;
Figure 11 shows the test pattern of the built-in self-test device of digital-analog convertor of the present invention;
Figure 12 shows the output signal of digital-analog convertor of the built-in self-test device of digital-analog convertor of the present invention;
Figure 13 shows the sampling of built-in self-test device of digital-analog convertor of the present invention and the output signal of holding circuit;
Figure 14 shows that the built-in self-test device of digital-analog convertor of the present invention is at the forward and backward signal of its differentiation element.
Element numbers explanation among the figure:
| 10, the built-in self-test device of 70 digital-analog convertors | |
| 101 counters | 102 first multiplexers |
| 103,703 digital-analog convertors | 104 first amplifiers |
| 105 demodulation multiplexers | 107,705 differentiation elements |
| 108 second low pass filters | 109,709 amplifying |
| 11 signals are selected circuit | 110,710 positive amplifiers |
| 111,711 negative amplifiers | 112,712 positive Schmidt triggers |
| 113,713 negative Schmidt triggers | 114,714 second multiplexers |
| 115,715 duty cycle acquisition devices | 116,716 signature analyzers |
| 117 adders | 118 first |
| 12,72 | 13 |
| 14 | |
| 41 | 42 oscillators |
| 43 triggers | 44 |
| 45 | |
| 701 | 702 |
| 704 sampling and | 708 low pass filters |
Embodiment
Fig. 1 shows the built-in self-test device 10 of digital-analog convertor of the present invention, and it is correction and the test that is used for a digital-analog convertor (DAC) 103.The input of this digital-analog convertor 103 connects one first multiplexer 102, is used to the signal of selecting a digital signal or being sent by a counter 101.With 4 be example, the signal that this counter 101 is sent will be in regular turn be " 0000 ", " 0001 " ... " 1111 " get back to " 0000 " more in regular turn.The output of this first multiplexer 102 except connecting this digital-analog convertor 103, one first amplifier 104 in addition in parallel.One demodulation multiplexer (demultiplexer) 105 receives the output signal of this digital-analog convertor 103, the exportable normal analog signal of one output, and another output then is connected to an adder 117, signal output during for test.Another input of this adder 117 connects the output of this first amplifier 104.Utilize this adder 117 to calculate the signal of exporting by this demodulation multiplexer 105 and first amplifier 104.The output of this adder 117 is connected to one first low pass filter 118, utilizes integral action, makes signal smoothingization.The signal of these first low pass filter, 118 outputs carries out differential through a differentiation element 107, is used to analyze the interpulse difference of each signal.This differentiation element 107 can adopt differentiator (differentiator), sampling to keep (sample-and-hold) circuit or switch-capacitor (SwitchedCapacitor, SC) circuit.Afterwards, signal carries out through one second low pass filter 108 delivering to an amplifying unit 109 after the smoothing second time of signal, amplifies to carry out signal.This amplifying unit 109 comprises a positive amplifier 110 and a negative amplifier 111, in order to produce two anti-phase amplifying signals.The output of this positive and negative amplifier 110,111 connects a schmidt trigger unit 12, it is the parallel circuits of a positive Schmidt trigger 112 and negative Schmidt's amplifier 113, in order to signal is divided into high levels " 1 " and low level " 0 " by a default critical voltage, be " 1 " wherein greater than this critical voltage person, less than this critical voltage person is " 0 " then, and with analog signal digital.After selecting, one second multiplexer 114 delivers to a duty cycle acquisition device 115 and a signature analyzer 116 through the signal after the digitlization, to carry out the error analysis of signal.
Signal transfers to circuits before this adder 117 and can reduce a signal and select circuit 11, and it is to be used to proofread and correct or to select and the switching signal path when testing.In other words, this signal selects circuit 11 to comprise this counter 101, first multiplexer 102, digital-analog convertor 103, first amplifier 104 and demodulation multiplexer 105 to be measured, wherein this digital-analog convertor 103 and this demodulation multiplexer 105 constitute a measurement circuit 13, this first amplifier 104 then is a corrector 14, and both are parallel to the output of this first multiplexer 102.Signal the selection through the path be based on that this first multiplexer 102 receives be the test or the indication of proofreading and correct.The function of proofreading and correct is whether be used for the action of measurement circuit normal, and whether the function of test then has abnormal error to produce for the analog signal of test after the digital-analog convertor conversion.
When carrying out correction program, signal is through this first multiplexer 102, first amplifier 104, adder 117, first low pass filter 118, differentiation element 107, second low pass filter 108, positive amplifier 110, positive Schmidt trigger 112, second multiplexer 114, duty cycle acquisition device 115 and signature analyzer 116.This moment, the signal of these demodulation multiplexer 105 input summers 117 was zero.On the other hand, when carrying out test program, signal is then through this first multiplexer 102, digital-analog convertor 103, demodulation multiplexer 105, adder 117, first low pass filter 118, differentiation element 107, second low pass filter 108, amplifying unit 109, schmidt trigger unit 12, second multiplexer 114, duty cycle acquisition device 115 and signature analyzer 116.This moment, the signal of these first amplifier, 104 input summers 117 was zero.The two difference, except the difference of calibrated circuit 12 of signal and measurement circuit 13, because when testing, signal may produce positive and negative two kinds of voltage signals through this differentiation element 107, therefore must utilize positive and negative amplifier 110,111 and positive and negative Schmidt trigger 112,113 in parallel to handle.When carrying out correction program, the signal pulse of exporting through this differentiation element 107 will increase by a unit at every turn, produce so have negative voltage signal.
Fig. 1 all with signal waveform, can learn influence and the effect of each circuit unit to signal waveform in the output of this demodulation multiplexer 105, first low pass filter 118, differentiation element 107, second low pass filter 108 and second multiplexer 114 thus.
The signal that Fig. 2 example one is exported via this second low pass filter 108, its abscissa are the time, and unit is nanosecond (ns), and ordinate is a voltage, and unit is a volt (V).Can find among Fig. 2 that signal produces the pulse that amplitude varies in size after differential and smoothing.
The effect of this schmidt trigger unit 12 of Fig. 3 example, wherein solid line and dotted line represent respectively signal in this schmidt trigger unit 12 forward and backward signal waveforms.When the amplitude of original signal was higher, the part of its high levels " 1 " after 12 digitlizations of schmidt trigger unit just had the bigger duty cycle with broad.The present invention promptly utilizes the correlation properties between this duty cycle and amplitude, transfers analog signal to digital signal, with convenient follow-up data processing and analysis.
Fig. 4 (a) and 4 (b) are the function mode schematic diagram of this duty cycle acquisition device 115, and its difference display application is in the situation of low frequency and high-frequency signal.With reference to Fig. 4 (a), if the signal after these schmidt trigger unit 12 digitlizations belongs to low frequency (for example 5-10ns), at first provide a clock as the right benchmark of time ratio, and utilize an oscillator 42 collocation one counter 41 with calculate this clock during high levels in this signal be in time of low level " 0 ", and clock is positioned at the time that the time subtraction signal of high levels is in low level " 0 ", get final product signal in the time of high levels " 1 ".With reference to Fig. 4 (b), if the signal after these schmidt trigger unit 12 digitlizations belongs to high frequency (for example 0.1-5ns), then can use the technology of delay line (delay line), utilize trigger (flip-flop) 43, buffer) buffer) 44 and one adder (adder) 45 be in the time of middle low level " 0 " with signal calculated.
With reference to Fig. 5, da and db are two adjacent signal pulses before 12 conversions of schmidt trigger unit.Signal db conversion back is during the high levels of a clock, and the time of its low level " 0 " and high levels " 1 " is represented by Wb_0 and Wb_1 respectively.Similarly, it is positioned at the time of high levels " 1 " and low level " 0 " after Wa_1 and the Wa_0 representation signal da conversion.In fact, signal db can be pushed away by previous signal da, and its relational expression is db=da * (Wb_0+ (Wb_1-Wa_1))/Wb_0.Afterwards, but utilize db computing differential non-linear (DNL), its equal db deduct least significant bit (LSB) (least significant bit, LSB), i.e. DNL=db-LSB.DNL is the error between pairing magnitude of voltage of representation signal and LSB.
Table 1 shows that the present invention is applied to an embodiment of 4 figure place analog-to-digital converters, digital " 1 " representative " 0000 ", and digital " 2 " are " 0001 ", analogize in regular turn.Built-in self-test of the present invention is to adopt adjacent number to analyze, so LSB is 1.
Table 1
| Digital | Wx_0 | Wx_1 | db | DNL |
| 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 | 300 298 293 293 292 296 399 242 299 286 243 396 296 295 300 | 340 342 347 347 348 344 241 398 341 354 397 244 344 345 340 | 1 1.006711409 1.023890785 1.023897085 1.02739726 1.013513514 0.751879699 1.239669421 1.003344482 1.048951049 1.234567901 0.757575758 1.013513514 1.016949153 1 | 0 0.006711 0.023891 0.023891 0.027397 0.013514 -0.24812 0.239669 0.003344 0.048951 0.234568 -0.24242 0.013514 0.016949 0 |
Annotate: x is a or b
Fig. 6 is the curve chart of the embodiment of table 1, and the DNL value in digital " 7 " is about-0.2, effectively departs from a LSB, and saying originally in fact is 7, and in fact its value only is about 6.8, relatively, makes its distance with digital " 8 " increase to 1.2.Digital 11,12 similar situation also takes place.It is excessive to judge that thus this number " 7 " reaches the error of " 11 ", must compensate by correction circuit.
Above-mentioned signal selects circuit 11, adder 117 and first low pass filter 118 to be replaced by a circuit, is used to handle DA signal at a high speed.As shown in Figure 7, the built-in self-test device 70 of a digital-analog convertor 703 comprises a test pattern unit 701, a logical circuit 702, a sampling and holding circuit 704, a differentiation element 705, a low pass filter 708, an amplifying unit 709, a schmidt trigger unit 72, a multiplexer 714, a duty cycle acquisition device 715 and a signature analyzer 716.This amplifying unit 709 comprises a positive amplifier 710 and a negative amplifier 711.This schmidt trigger unit 72 comprises a positive Schmidt trigger 712 and a negative Schmidt trigger 713, and wherein this positive Schmidt trigger 712 connects this positive amplifier 710, and should connect this negative amplifier 711 by negative Schmidt trigger 713, and forms parallel circuits.One clock pulse signal CLK transfers to this test pattern unit 701 and this logical circuit 702, and the speed of this CLK signal is identical with the speed of circuit under test, and promptly the speed with the DA signal of importing this digital-analog convertor 703 is identical.When the BIST signal of importing this logical circuit 702 is high levle, be to be used to trigger this device 70 to enter the BIST pattern.
Fig. 8 shows the circuit diagram of these logical circuit 702 difference quadruple rate operations.This logical circuit 702 comprises two flip- flops 81,82 and one and door (AND gate) 83, uses producing control signal 1 and 2.Signal 1 is to transfer to this sampling and 704,2 of holding circuits transfer to this differentiation element 705 and low pass filter 708, in order to control.Therefore, can be by this logical circuit 702 these digital-analog convertors 703 of control and sampling and holding circuit 704 with high speed operation, and after it with low-speed handing.And times speed that high, low speed differs can be reached by adjusting this logical circuit 702.
With reference to Fig. 9, the speed of importing this digital-analog convertor owing to the speed and the DA signal of this CLK signal is identical, so the period T DAC of CLK signal equated with the time of acquisition one DA signal.The BIST conversion of signals is to high levle, and promptly this device 70 enters the BIST pattern.The time that this control signal 1 is positioned at high levle equals TDAC, and the duty cycle of signal 2 then is about 50%.This signal 1 and cycle of 2 are depended on the multiple relation of frequency reducing operation.If high, low speed difference n frequency multiplication, then this signal 1 and cycle of 2 are nTDAC.With reference to Figure 10, high, low speed differs four times for example, and signal 1 and cycle of 2 are 4TDAC.
Figure 11 shows that four that this test pattern (test pattern) unit 701 produced return back to zero (Retum-to-Zero) test pattern, and it comprises four position signal D0, D1, D2, D3, in order to represent the DA digital input signals.D0 represents minimum significantly position (LSB), and D3 then represents maximum significantly position (Most Significant Bit; MSB).For example, the value of the position signal D3 that DA signal " 0001 " is relative, D2, D1, D0 is respectively 0,0,0,1, and relative D3, the D2 of signal " 1111 ", the value of D1, D0 are respectively 1,1,1,1.Collocation CLK signal and 1 is when be high levle, input increment signal " 0001 ", " 0010 " ... the insertion " 0000 " during for low level of " 1111 ", CLK signal and 1, the number of " 0000 " of being inserted are that high, low speed differs multiple and subtracts 1.Therefore the value of the position signal D3 between adjacent DA input signal, D2, D1, D0 is 0, and for example it is 0 between " 0001 " and " 0010 ".In other words, when no DA input signal, D3, D2, D1, D0 signal are to return back to zero.
This signal D3, D2, D1, D0 are input into this digital-analog convertor 703, and the output signal of this digital-analog convertor 703 (DAC output signal) as shown in figure 12.This DAC output signal is to be engaged in when having the DA signal to increase progressively, and then returns back to zero in other period.Therefore, the pulse height of this DAC output signal is progressively to increase, and promptly the next pulse height is higher than previous pulse height.As shown in Figure 12, the pulse frequency of this DAC output signal is 1/4th of this CLK frequency, and promptly the speed of this CLK signal is four times of this DAC output signal.By this, be equal to the speed that reduces after this DA conversion of signals, and applicable to the high speed D Signal Processing.Be that octuple, the speed of this CLK signal are the octuple of the speed of this DAC output signal if the high low speed of design differs, promptly DAC operates under operate as normal speed, and measuring circuit can be operated under low speed.
With reference to Figure 13, the DAC output signal is that input this sampling and holding circuit 704 are with the sampling of carrying out this DAC output signal and the peak value that keeps the pulse of this DAC output signal.Taking a sample or keeping is to decide according to signal 1, when 1 is high levle, takes a sample; Otherwise the value that keeps this DAC output signal.The sampling of Figure 13 and keep phase place with " S " expression sampling period, and keep the period with " H " expression, it corresponds respectively to 1 and is the high and low accurate position period.By this, can produce cumulative and continuous in fact sampling and keep output signal (S/H output signal).
This differentiation element 705, low pass filter 708, amplifying unit 709, schmidt trigger unit 72, multiplexer 714, duty cycle acquisition device 715 and signature analyzer 716 essence are equal to this differentiation element 107, second low pass filter 108, amplifying unit 109, schmidt trigger unit 12, second multiplexer 114, duty cycle acquisition device 115 and signature analyzer 116 respectively.Among Figure 14, a S/H output signal " A " is converted to signal " B " (corresponding to A and B point among Fig. 7 respectively), the difference in signal " B " shows signal " A " between individual pulses after this differentiation element 705 is handled.The transfer process of above-mentioned this differentiation element 705 promptly is equivalent to the conversion that this differentiation element 107 is done.Because of follow-up processing also same or similar described in preceding embodiment, so omit relevant narration at this.
The present invention does not directly handle the DA signal, and utilize this differential technology to find out the difference of two adjacent signals pulses, and the amplitude that can represent this difference is converted to the duty cycle of digital signal, use the error of analyzing adjacent number, can significantly reduce the complexity and the degree of difficulty of the built-in self-test device and method of digital-analog convertor.
Technology contents of the present invention and technical characterstic disclose as above, yet those skilled in the art still may be based on teaching of the present invention and announcement and done all replacement and modifications that does not deviate from spirit of the present invention.Therefore, protection scope of the present invention should be not limited to the content that embodiment discloses, and should comprise various do not deviate from replacement of the present invention and modifications, and is contained by the present patent application claim.
Claims (11)
1. the built-in self-test device of a digital-analog convertor is characterized in that it comprises:
One test pattern unit is connected to a digital-analog convertor to be measured, is used to produce a test pattern that comprises several signals, wherein this test pattern various digital revolving die analog signal that goes out this digital-analog convertor to be measured capable of being combined;
One sampling and holding circuit is in order to take a sample at the output signal of this digital-analog convertor and to keep;
One differentiation element is used for the output signal of this sampling and holding circuit is carried out differential;
One low pass filter is used for the output signal smoothing with this differentiation element;
One schmidt trigger unit is according to a critical voltage and the output signal of this low pass filter is converted to digital signal;
One duty cycle acquisition device, the duty cycle that is used to calculate this digital signal;
One signature analyzer utilizes this duty cycle to carry out error analysis.
2. the built-in self-test device of digital-analog convertor as claimed in claim 1 is characterized in that the value of the position signal between two adjacent digital revolving die analog signals is 0.
3. the built-in self-test device of digital-analog convertor as claimed in claim 1 is characterized in that the multiple of the acquisition frequency of described digital revolving die analog signal for the pulse frequency of the output signal of this digital-analog convertor.
4. the built-in self-test device of digital-analog convertor as claimed in claim 3 is characterized in that described multiple is equal to the figure place of this numeral revolving die analog signal.
5. the built-in self-test device of digital-analog convertor as claimed in claim 1 is characterized in that it comprises a logical circuit in addition, is used to provide the control signal of this sampling and holding circuit.
6. the built-in self-test device of digital-analog convertor as claimed in claim 5 is characterized in that described logical circuit provides the control signal of this differentiation element in addition.
7. the built-in self-test device of digital-analog convertor as claimed in claim 5 is characterized in that described logical circuit comprises two flip-flops and one and door.
8. the built-in self-test method of a digital-analog convertor is characterized in that it comprises the following step:
Produce a test pattern that comprises several signals, this test pattern various digital revolving die analog signal that goes out a digital-analog convertor to be measured capable of being combined;
Should be converted to an analog signal by numeral revolving die analog signal;
Pulse at this analog signal is taken a sample, and the peak value of the pulse of this analog signal is then kept;
To carry out differential through sampling and the analog signal of keeping, to obtain its each interpulse difference;
This analog signal is carried out smoothing;
This analog signal is converted to digital signal according to a critical voltage;
Calculate the duty cycle of this digital signal;
Utilize this duty cycle to calculate the error of this analog signal.
9. the built-in self-test method of digital-analog convertor as claimed in claim 8 is characterized in that the value of the position signal between two adjacent digital revolving die analog signals is 0.
10. the built-in self-test method of digital-analog convertor as claimed in claim 8 is characterized in that the multiple of the acquisition frequency of this numeral revolving die analog signal for the pulse frequency of the output signal of this digital-analog convertor.
11. the built-in self-test method of digital-analog convertor as claimed in claim 10 is characterized in that this multiple is equal to the figure place of this numeral revolving die analog signal.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 200410058641 CN1728559A (en) | 2004-07-26 | 2004-07-26 | Built self testing unit and method inside D/A converter |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 200410058641 CN1728559A (en) | 2004-07-26 | 2004-07-26 | Built self testing unit and method inside D/A converter |
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| CN1728559A true CN1728559A (en) | 2006-02-01 |
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| CN 200410058641 Withdrawn CN1728559A (en) | 2004-07-26 | 2004-07-26 | Built self testing unit and method inside D/A converter |
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101876686A (en) * | 2009-04-28 | 2010-11-03 | Vega格里沙贝两合公司 | Be used to monitor the diagnostic circuit of analog-digital converter circuit |
| CN103959655A (en) * | 2011-12-06 | 2014-07-30 | 三星电子株式会社 | Digital-analog conversion apparatus and method |
| CN112630626A (en) * | 2021-03-05 | 2021-04-09 | 光梓信息科技（上海）有限公司 | On-chip self-test system and method |
-
2004
- 2004-07-26 CN CN 200410058641 patent/CN1728559A/en not_active Withdrawn
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101876686A (en) * | 2009-04-28 | 2010-11-03 | Vega格里沙贝两合公司 | Be used to monitor the diagnostic circuit of analog-digital converter circuit |
| US9054724B2 (en) | 2009-04-28 | 2015-06-09 | Vega Grieshaber Kg | Diagnostic circuit for monitoring an analog-digital converter circuit |
| CN103959655A (en) * | 2011-12-06 | 2014-07-30 | 三星电子株式会社 | Digital-analog conversion apparatus and method |
| US9571117B2 (en) | 2011-12-06 | 2017-02-14 | Samsung Electronics Co., Ltd. | Digital-analog conversion apparatus and method |
| CN103959655B (en) * | 2011-12-06 | 2018-02-13 | 三星电子株式会社 | Digiverter and method |
| CN112630626A (en) * | 2021-03-05 | 2021-04-09 | 光梓信息科技（上海）有限公司 | On-chip self-test system and method |
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