CN1599256A - Built-in self testing device and method of digital analog converter - Google Patents
Built-in self testing device and method of digital analog converter Download PDFInfo
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- CN1599256A CN1599256A CN 03158506 CN03158506A CN1599256A CN 1599256 A CN1599256 A CN 1599256A CN 03158506 CN03158506 CN 03158506 CN 03158506 A CN03158506 A CN 03158506A CN 1599256 A CN1599256 A CN 1599256A
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Abstract
The invention discloses built-in self-detecting device of the digital/analog convertor and the manufacturing method. It mainly differentiates the digital/analog signal with a differential coefficient unit to get the difference between the pulses of analog signal and transforms the analog signal into the digital signal with a Schmidt burst unit according to a critical voltage. Then, it calculates the loading cycle of the digital signal with a load cycle collector and sends it in signature analyzer to calculate the differential coefficient nonlinearity in order to analysis the error.
Description
Technical field
The invention relates to a kind of built-in selftest (BIST) device and method, particularly about a kind of built-in self detector and method that is applied to digital-analog convertor (DAC).
Background technology
Along with the development of highly integrated circuit, more and more Duo circuit is to be integrated in the System on Chip/SoC (SoC).The mixed signal circuit of many digital-analog convertors, analogue-to-digital converters (ADC) and combination simulation and digital function has been applied to as wireless telecommunications, data conversion system and satellite communication aspect.In recent years, foregoing circuit has developed and built-in selftest technology, directly carries out the test of self hardware by built-in circuit, to save cost and to shorten the testing time.
Traditionally, the built-in selftest of digital-analog convertor is directly to handle the voltage signal that digital revolving die is intended (DA), but, often must add auxiliary circuit or utilize specific process to be handled, yet the result is still unsatisfactory owing to being difficult for differentiating between analog signal and noise.In addition,, must increase the circuit of an acquisition voltage, and its sampling frequency often is required to be more than the twice of this DA signal frequency, thereby has quite high technical difficulty degree if need to handle the DA signal of high frequency.
Summary of the invention
Main purpose of the present invention provides a kind of built-in self detector and method of digital-analog convertor, utilize each interpulse error of detection signal and analyze, can reduce the technical difficulty degree of existing built-in selftest, and the foundation of circuit modifications is provided, or the specification that is used for circuit detects.
For achieving the above object, the present invention discloses a kind of built-in self detector of digital-analog convertor, and it mainly comprises one first low pass filter (LPF), a differentiation element, one second low pass filter, a schmidt trigger unit, a duty cycle (duty cycle) acquisition device and signature (signature) analyzer.This first low pass filter is to be used for analog signal smoothing that a digital-analog convertor is sent.This differentiation element connects the output of this first low pass filter, is used for this analog signal is carried out differential, to obtain each interpulse difference of this analog signal.This second low pass filter connects the output of this differentiation element, is used for the analog signal smoothing behind the differential.This schmidt trigger unit is to be used for the analog signal that this second low pass filter is sent is converted to digital signal according to a critical voltage.This duty cycle acquisition device is the duty cycle that is used to calculate this digital signal.This signature analyzer is to utilize this duty cycle to carry out error analysis.
The implementation method of the built-in self detector of this digital-analog convertor can reduce and comprise the following step: (1) utilizes this digital-analog convertor that one digital signal is converted to an analog signal; (2) this analog signal is carried out the smoothing first time, to remove noise; (3) will carry out differential through the analog signal of the smoothing first time, to obtain each interpulse difference of this analog signal; (4) this analog signal is carried out the smoothing second time; (5) this analog signal is converted to digital signal according to a critical voltage, wherein the part greater than this critical voltage is converted to high level " 1 ", is converted to low level " 0 " less than the part of this critical voltage; (6) calculate duty cycle of this digital signal; (7) (differential non-linearity DNL), is used to judge the error of this analog signal to utilize this duty cycle computing differential nonlinearity.
In brief, the present invention also directly handles the DA signal unlike existing built-in self-test circuit, but utilize differential technology to find out the difference of two adjacent pulses of analog signal, and the amplitude of both difference representatives is converted to duty cycle of digital signal, use the error of analyzing adjacent number, can significantly reduce the complexity and the degree of difficulty of the built-in selftest of digital-analog convertor.
Description of drawings
The present invention will illustrate according to accompanying drawing, wherein:
Fig. 1 is the schematic diagram of the built-in self detector of digital-analog convertor of the present invention;
The waveform of signal after differential and smoothing of the built-in self detector of Fig. 2 example digital-analog convertor of the present invention and method;
Fig. 3 is the conversion of signals schematic diagram of the flip-flop element of the built-in self detector of digital-analog convertor of the present invention and method;
The built-in self detector of Fig. 4 (a) and 4 (b) examples digital-analog convertor of the present invention and the duty cycle of method acquisition mode;
Fig. 5 is the built-in self detector of digital-analog convertor of the present invention and the duty cycle analysis mode schematic diagram of method;
Fig. 6 shows the built-in self detector of digital-analog convertor of the present invention and a test result of method.
Embodiment
Fig. 1 shows the built-in self detector 10 of digital-analog convertor of the present invention, and it is correction and the test that is used for a digital-analog convertor (DAC) 103.The input of this digital-analog convertor 103 connects one first multiplexer 102, is used to the signal of selecting a digital signal or being sent by a counter 101.With 4 be example, the signal that this counter 101 is sent will be in regular turn be " 0000 ", " 0001 " ... " 1111 " get back to " 0000 " more in regular turn.The output of this first multiplexer 102 except connecting this digital-analog convertor 103, one first amplifier 104 in addition in parallel.One demodulation multiplexer (demultiplexer) 105 receives the output signal of this digital-analog convertor 103, the exportable normal analog signal of one output, and another output then is connected to an adder 117, signal output during for test.Another input of this adder 117 connects the output of this first amplifier 104.Utilize this adder 117 to calculate the signal of exporting by this demodulation multiplexer 105 and first amplifier 104.The output of this adder 117 is connected to one first low pass filter 118, utilizes integral action, makes signal smoothingization.The signal of these first low pass filter, 118 outputs carries out differential through a differentiation element 107, is used to analyze the interpulse difference of each signal.This differentiation element 107 can adopt differentiator (differentiator), sampling to keep (sample-and-hold) circuit or switch-capacitor (Switched Capacitor, SC) circuit.Afterwards, signal carries out through one second low pass filter 108 delivering to an amplifying unit 109 after the smoothing second time of signal, amplifies to carry out signal.This amplifying unit 109 comprises a positive amplifier 110 and a negative amplifier 111, in order to produce two anti-phase amplifying signals.The output of this positive and negative amplifier 110,111 connects a schmidt trigger unit 12, it is the parallel circuits of a positive Schmidt trigger 112 and negative Schmidt's amplifier 113, in order to signal is divided into high level " 1 " and low level " 0 " by a default critical voltage, be " 1 " wherein greater than this critical voltage person, less than this critical voltage person is " 0 " then, and with analog signal digital.After selecting, one second multiplexer 114 delivers to a duty cycle acquisition device 115 and a signature analyzer 116 through the signal after the digitlization, to carry out the error analysis of signal.
Signal transfers to circuits before this adder 117 and can reduce a signal and select circuit 11, and it is to be used to proofread and correct or to select and the switching signal path when testing.In other words, this signal selects circuit 11 to comprise this counter 101, first multiplexer 102, digital-analog convertor 103, first amplifier 104 and demodulation multiplexer 105 to be measured, wherein this digital-analog convertor 103 and this demodulation multiplexer 105 constitute a measurement circuit 13, this first amplifier 104 then is a corrector 14, and both are parallel to the output of this first multiplexer 102.Signal the selection through the path be based on that this first multiplexer 102 receives be the test or the indication of proofreading and correct.The function of proofreading and correct is whether be used for the action of measurement circuit normal, and whether the function of test then has abnormal error to produce for the analog signal of test after the digital-analog convertor conversion.
When carrying out correction program, signal is through this first multiplexer 102, first amplifier 104, adder 117, first low pass filter 118, differentiation element 107, second low pass filter 108, positive amplifier 110, positive Schmidt trigger 112, second multiplexer 114, duty cycle acquisition device 115 and signature analyzer 116.This moment, the signal of these demodulation multiplexer 105 input summers 117 was zero.On the other hand, when carrying out test program, signal is then through this first multiplexer 102, digital-analog convertor 103, demodulation multiplexer 105, adder 117, first low pass filter 118, differentiation element 107, second low pass filter 108, amplifying unit 109, schmidt trigger unit 12, second multiplexer 114, duty cycle acquisition device 115 and signature analyzer 116.This moment, the signal of these first amplifier, 104 input summers 117 was zero.The two difference, except the difference of calibrated circuit 12 of signal and measurement circuit 13, because when testing, signal may produce positive and negative two kinds of voltage signals through this differentiation element 107, therefore must utilize positive and negative amplifier 110,111 and positive and negative Schmidt trigger 112,113 in parallel to handle.When carrying out correction program, the signal pulse of exporting through this differentiation element 107 will increase by a unit at every turn, produce so have negative voltage signal.
Fig. 1 all with signal waveform, can learn influence and the effect of each circuit unit to signal waveform in the output of this demodulation multiplexer 105, first low pass filter 118, differentiation element 107, second low pass filter 108 and second multiplexer 114 thus.
The signal that Fig. 2 example one is exported via this second low pass filter 108, its abscissa are the time, and unit is nanosecond (ns), and ordinate is a voltage, and unit is a volt (V).Can find among Fig. 2 that signal produces the pulse that amplitude varies in size after differential and smoothing.
The effect of this schmidt trigger unit 12 of Fig. 3 example, wherein solid line and dotted line represent respectively signal in this schmidt trigger unit 12 forward and backward signal waveforms.When the amplitude of original signal was higher, the part of its high level " 1 " after 12 digitlizations of schmidt trigger unit just had the bigger duty cycle with broad.The present invention promptly utilizes the correlation properties between this duty cycle and amplitude, transfers analog signal to digital signal, with convenient follow-up data processing and analysis.
Fig. 4 (a) and 4 (b) are the function mode schematic diagram of this duty cycle acquisition device 115, and its difference display application is in the situation of low frequency and high-frequency signal.With reference to Fig. 4 (a), if the signal after these schmidt trigger unit 12 digitlizations belongs to low frequency (for example 5-10ns), the benchmark of one clock as the time contrast at first is provided, and utilize an oscillator 42 collocation one counter 41 with calculate this clock between high period in this signal be in time of low level " 0 ", and clock is positioned at the time that the time subtraction signal of high level is in low level " 0 ", get final product signal in the time of high level " 1 ".With reference to Fig. 4 (b), if the signal after these schmidt trigger unit 12 digitlizations belongs to high frequency (for example 0.1-5ns), then can use the technology of delay line, utilize trigger 43, buffer 44 and an adder 45 to be in the time of middle low level " 0 " with signal calculated.
With reference to Fig. 5, da and db are two adjacent signal pulses before 12 conversions of schmidt trigger unit.Signal db conversion back is between the high period of a clock, and the time of its low level " 0 " and high level " 1 " is represented by Wb_0 and Wb_1 respectively.Similarly, it is positioned at the time of high level " 1 " and low level " 0 " after Wa_1 and the Wa_0 representation signal da conversion.In fact, signal db can be pushed away by previous signal da, and its relational expression is db=da * (Wb_0+ (Wb_1-Wa_1))/Wb_0.Afterwards, but utilize db computing differential non-linear (DNL), its equal db deduct least significant bit (LSB) (least significant bit, LSB), i.e. DNL=db-LSB.DNL is the error between pairing magnitude of voltage of representation signal and LSB.
Table 1 shows that the present invention is applied to an embodiment of 4 figure place analog-to-digital converters, digital " 1 " representative " 0000 ", and digital " 2 " are " 0001 ", analogize in regular turn.Built-in selftest of the present invention is to adopt adjacent number to analyze, so LSB is 1.
Table 1
Digital Wx_0 Wx_1 db DNL
1 300 340 1 0
2 298 342 1.006711409 0.006711
3 293 347 1.023890785 0.023891
4 293 347 1.023897085 0.023891
5 292 348 1.02739726 0.027397
6 296 344 1.013513514 0.013514
7 399 241 0.751879699 -0.24812
8 242 398 1.239669421 0.239669
9 299 341 1.003344482 0.003344
10 286 354 1.048951049 0.048951
11 243 397 1.234567901 0.234568
12 396 244 0.757575758 -0.24242
13 296 344 1.013513514 0.013514
14 295 345 1.016949153 0.016949
15 300 340 1 0
Annotate: x is a or b
Fig. 6 is the curve chart of the embodiment of table 1, and the DNL value in digital " 7 " is about-0.2, effectively departs from a LSB, and saying originally in fact is 7, and in fact its value only is about 6.8, relatively, makes its distance with digital " 8 " increase to 1.2.Digital 11,12 similar situation also takes place.It is excessive to judge that thus this number " 7 " reaches the error of " 11 ", must compensate by correction circuit.
The present invention does not directly handle the DA signal, and utilize this differential technology to find out the difference of two adjacent signals pulses, and the amplitude that can represent this difference is converted to the duty cycle of digital signal, use the error of analyzing adjacent number, can significantly reduce the built-in self detector of digital-analog convertor and the complexity and the degree of difficulty of method.
Technology contents of the present invention and technical characterstic disclose as above, yet those skilled in the art still may be based on teaching of the present invention and announcement and done all replacement and modifications that does not deviate from spirit of the present invention.Therefore, protection scope of the present invention should be not limited to the content that embodiment discloses, and should comprise various do not deviate from replacement of the present invention and modifications, and is contained by the present patent application claim.
Claims (17)
1. the built-in self detector of a digital-analog convertor comprises:
One first low pass filter is used for the analog signal smoothing that a digital-analog convertor is exported;
One differentiation element is used for the output signal of this first low pass filter is carried out differential;
One second low pass filter is used for the output signal smoothing with this differentiation element;
One schmidt trigger unit is according to a critical voltage and the output signal of this second low pass filter is converted to digital signal;
One duty cycle acquisition device, the duty cycle that is used to calculate this digital signal;
One signature analyzer utilizes this duty cycle to carry out error analysis.
2. the built-in self detector of digital-analog convertor as claimed in claim 1 is characterized in that it comprises in addition:
One signal is selected circuit, and the selection between being used for an input signal proofreaied and correct and test is switched, and it comprises a corrector and a measurement circuit of mutual parallel connection, and this measurement circuit comprises this digital-analog convertor;
One adder, its input connect the output that this signal is selected circuit, and output connects this first low pass filter, is used for the output signal in conjunction with this correction and measurement circuit.
3. the built-in self detector of digital-analog convertor as claimed in claim 2 is characterized in that described signal selection circuit comprises a counter in addition.
4. the built-in self detector of digital-analog convertor as claimed in claim 2 is characterized in that described signal selection circuit comprises a multiplexer in addition, is used to carry out the selection switching of this corrector and measurement circuit.
5. the built-in self detector of digital-analog convertor as claimed in claim 1, it is characterized in that it comprises an amplifying unit in addition, be arranged between this schmidt trigger unit and second low pass filter, be used to amplify the signal that this second low pass filter is sent.
6. the built-in self detector of digital-analog convertor as claimed in claim 5 is characterized in that described amplifying unit is to be composed in parallel by a positive amplifier and a negative amplifier.
7. the built-in self detector of digital-analog convertor as claimed in claim 1 is characterized in that it comprises a multiplexer that is arranged between this schmidt trigger unit and duty cycle acquisition device in addition.
8. the built-in self detector of digital-analog convertor as claimed in claim 1 is characterized in that described schmidt trigger unit is made up of a positive Schmidt trigger and a negative Schmidt trigger of mutual parallel connection.
9. the built-in self detector of digital-analog convertor as claimed in claim 1 is characterized in that described differentiation element is one of to be selected from differentiator, sample-and-hold circuit and the switched-capacitor circuit.
10. the built-in self detector of digital-analog convertor as claimed in claim 1 is characterized in that described duty cycle acquisition device comprises a counter and an oscillator.
11. the built-in self detector of digital-analog convertor as claimed in claim 1 is characterized in that described duty cycle acquisition device comprises several triggers, several buffers and an adder.
12. the built-in selftest method of a digital-analog convertor comprises the following step:
One digital signal is converted to an analog signal;
This analog signal is carried out the smoothing first time, to remove noise;
To carry out differential through the analog signal of the smoothing first time, to obtain each interpulse difference of this analog signal;
This analog signal is carried out the smoothing second time;
This analog signal is converted to digital signal according to a critical voltage;
Calculate the duty cycle of this digital signal;
Utilize this duty cycle to calculate the error of this analog signal.
13. the built-in selftest method of digital-analog convertor as claimed in claim 12 is characterized in that described Error Calculation comprises differential nonlinearity.
14. the built-in selftest method of digital-analog convertor as claimed in claim 12 is characterized in that it comprises a step of amplifying the analog signal of this second time after smoothly in addition.
15. the built-in selftest method of digital-analog convertor as claimed in claim 12 is characterized in that the first time of described analog signal and smoothing for the second time are to utilize a low pass filter to carry out.
16. the built-in selftest method of digital-analog convertor as claimed in claim 12, the differential that it is characterized in that described analog signal are one of to utilize in differentiator, sample-and-hold circuit and the switched-capacitor circuit.
17. the built-in selftest method of digital-analog convertor as claimed in claim 12, the calculating that it is characterized in that the described duty cycle are one of to utilize in counter and the delay circuit.
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN103959655A (en) * | 2011-12-06 | 2014-07-30 | 三星电子株式会社 | Digital-analog conversion apparatus and method |
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103959655A (en) * | 2011-12-06 | 2014-07-30 | 三星电子株式会社 | Digital-analog conversion apparatus and method |
| US9571117B2 (en) | 2011-12-06 | 2017-02-14 | Samsung Electronics Co., Ltd. | Digital-analog conversion apparatus and method |
| CN103959655B (en) * | 2011-12-06 | 2018-02-13 | 三星电子株式会社 | Digiverter and method |
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