CN1722389A - Semiconductor device, method of manufacturing the same, and electro-optical device - Google Patents

Semiconductor device, method of manufacturing the same, and electro-optical device Download PDF

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CN1722389A
CN1722389A CN 200510082537 CN200510082537A CN1722389A CN 1722389 A CN1722389 A CN 1722389A CN 200510082537 CN200510082537 CN 200510082537 CN 200510082537 A CN200510082537 A CN 200510082537A CN 1722389 A CN1722389 A CN 1722389A
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concentration region
resist layer
region
low concentration
semiconductor film
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CN100470736C (en
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世良博
江口司
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Yin's High Tech Co ltd
TCL China Star Optoelectronics Technology Co Ltd
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Seiko Epson Corp
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Abstract

The invention provides a simplifying method for a manufacturing procedure of a semiconductor device which is equipped with an LDD or GOLD structure. The invention relates to a manufacturing method of the semiconductor device which is equipped with: a procedure of forming a thinner film thickness of a resist layer which is corresponding to a source lateral high concentrated region and a leakage lateral high concentrated region on a semiconductor layer than the film thickness of a source lateral low concentrated region, a leakage lateral low concentrated region and a channel region; a procedure of etching the semiconductor layer into a determined shape with the resist layer as a mask and simultaneously injecting impurities into the semiconductor layer to format the source lateral high concentrated region and the leakage lateral high concentrated region.

Description

The manufacture method of semiconductor device, semiconductor device and electro-optical device
Technical field
The present invention relates to the manufacture method and the electro-optical device of semiconductor device, semiconductor device.
Background technology
In electro-optical devices such as liquid-crystal apparatus, organic electroluminescent (EL) device, plasma display, for to a plurality of pixels of each pixel drive, extensively utilize the active array type electro-optical device that on each pixel, is provided with TFT (thin-film transistor) as thin film semiconductor device with rectangular configuration.Above-mentioned TFT generally is as channel region with amorphous silicon or polysilicon.Especially only the multi-crystal TFT made from low temperature process is widely adopted on electro-optical devices such as above-mentioned liquid-crystal apparatus, organic El device owing to electronics or hole have big electric field degree of excursion.
As TFT, the TFT with LDD (Lightly Doped Drain) structure is well-known with the TFT with GOLD (Gate-drain Overlapped LDD) structure.TFT with LDD structure has on the polysilicon layer corresponding with regional exterior lateral area under the gate electrode and forms extrinsic region, forms the structure of the high concentration impurity that will form source region and drain region in its exterior lateral area, and the effect of inhibition cut-off current value is arranged.On the other hand, have the TFT of GOLD structure, have the structure that the zone forms the low concentration impurity region overlapping of above-mentioned LDD structure under the gate electrode end, and the effect that suppresses hot carrier is arranged.
Formation method as TFT with above-mentioned LDD and GOLD structure, disclose with photomask etc. with diffraction grating pattern, formation has the resist layer pattern in the thin zone of thickness from middle body to end, the etching conducting film, formation has the gate electrode in the thin zone of thickness from middle body to end, by with this gate electrode as mask to the semiconductor layer implanted dopant, form the method (for example patent documentation 1) of the TFT with LDD structure.
Patent documentation 1: the spy opens the 2002-151523 communique
Yet, in the formation method of the TFT with above-mentioned patent documentation 1 disclosed LDD and GOLD structure, with above-mentioned resist layer pattern as mask, make the residual-film thickness degree reach 5～30% of initial stage thickness the two end portions dry ecthing of gate electrode, on semiconductor layer, form the low concentration impurity zone as mask with this gate electrode.
But in the formation method of the TFT with above-mentioned LDD and GOLD structure, for the thickness with gate electrode be suppressed to decide thickness, must consider the selection ratio of dry ecthing, thereby have the processing that the makes gate electrode complicated problems that becomes.When this external dry ecthing,, need to solve the problem of restrictions such as the material of selecting to be subjected to constitute gate electrode and etching solution though, find out required selection ratio for considering to select to carry out etching under the situation of ratio for the thickness of control grid electrode as described above.
Summary of the invention
The present invention proposes just in view of the above problems, and its purpose is to provide a kind of method that the manufacturing process of the semiconductor device of LDD or GOLD structure can be simplified.
The present invention, for solving above-mentioned problem, relate to and have the source high concentration region, leak the side high concentration region, the source low concentration region, leak the semiconductor layer of side low concentration region and channel region, with by described semiconductor layer with dielectric film and relative to the manufacture method of semiconductor device of gate electrode, it is characterized in that, comprising: the operation that on substrate, forms semiconductor film; Will be on described semiconductor film the thickness of the resist layer corresponding with described source high concentration region and described leakage side high concentration region, form the thin operation of thickness than the described resist layer of described source low concentration region, described leakage side low concentration region and described channel region correspondence; With described resist layer as mask with described semiconductor film be etched into decided pattern, inject high concentration impurities by the thin part of described resist layer to described semiconductor film simultaneously, form the operation of described source high concentration region and described leakage side high concentration region; Remove described resist layer from described semiconductor film, on described semiconductor film, form the operation of gate insulating film; On position corresponding on the described gate insulating film, form the operation of described gate electrode with described channel region; Inject impurity than described high concentration impurities low concentration as mask to described semiconductor film with described gate electrode, form the operation of described source low concentration region and described leakage side low concentration region.
By the semiconductor device that manufacture method of the present invention is made, be semiconductor device with so-called LDD structure, have the little characteristic of cut-off current value.
In the past, the semiconductor device with so-called LDD structure generally forms by the third photo etching operation.For example, carry out above-mentioned operation when semiconductor layer is etched into the mask of the shape that formalizes in order to form; And then in order to form with gate electrode be etched into carry out above-mentioned operation twice during mask when formalizing shape.
In contrast to this, in the application's invention, after directly forming resist layer on the semiconductor layer, utilize photoetching process to form the source and the thickness that leaks side area with high mercury correspondence of resist layer therewith thinly with formalized shape.Thus, as mask semiconductor layer is etched into the shape that formalized with above-mentioned resist layer, simultaneously can be again with above-mentioned resist layer as mask to above-mentioned semiconductor layer inject decided the impurity of concentration.That is to say, form the resist layer of the shape that formalizes, can be used for simultaneously among two operations such as the etching of semiconductor layer and impurity injection by photo-mask process.Therefore, gate electrode pattern is changed in the shape that formalizes, can form semiconductor device by the Twi-lithography operation with LDD structure.Therefore, compare with existing method and can cut down photo-mask process one time.And can also cut down simultaneously for example resist layer of following after the photo-mask process and operation such as peel off.
And, since with resist layer as the direct implanted dopant on semiconductor layer of mask, so can be not by means of the gate insulating film implanted dopant that on semiconductor layer, forms.So can avoid to provide a kind of high gate insulating film of reliability of guaranteeing insulating properties because of impurity shines the damage that causes gate insulating film.
In addition, in the application's the invention, because form source and leak the side area with high mercury as mask, form source and leak the side low concentration region as mask with above-mentioned gate electrode, so can form all dirt zone in self-adjusting (selfalign) mode with above-mentioned resist layer.
And, with above-mentioned semiconductor layer pattern change into before the shape that formalizes, can be set in source that forms on the semiconductor layer and the position of leaking the side area with high mercury.Therefore, when forming source and leaking the side area with high mercury, needn't carry out the contraposition of mask and semiconductor layer, can on semiconductor layer, form above-mentioned zone with high accuracy by implanted dopant on semiconductor layer.
And form in the operation at the above-mentioned resist layer of the manufacture method of semiconductor device, preferably pass through to use the local different photomask of transmitance during exposure, the thickness of described resist layer that will be corresponding with described source high concentration region and described leakage side high concentration region forms thinner than the thickness of the described resist layer of described source low concentration region, described leakage side low concentration region and described channel region correspondence.
According to this formation, in photo-mask process, can control exposure light intensity through mask or chopper wheel, resist layer is carried out exposure imaging handle.Be that the semi-tone exposure becomes possibility.Thus, the film thickness monitoring Cheng Suoding thickness of resist layer can be formed down.So, can on semiconductor layer, Selective Control form high concentration, low concentration or non-extrinsic region by making the Thickness Variation of above-mentioned resist layer.
And form in the operation at the above-mentioned resist layer of the manufacture method of semiconductor device, preferably the thickness with the resist layer of described source high concentration region and described leakage side high concentration region correspondence forms 50～200 nanometers.
According to this formation, then adopt the high concentration impurities of ion implantation apparatus to shining on the semiconductor layer, can pass through resist layer keeping under the high concentration state.Therefore, can on semiconductor layer, form source region and the drain region that constitutes by high concentration impurities.
In addition, form in the operation, preferably have in the above-mentioned high concentration impurities district of the manufacture method of semiconductor device: with described resist layer as mask with described semiconductor film be etched into decided the operation of pattern; Expose with the described semiconductor film of the part that makes described source high concentration region and described leakage side high concentration region correspondence, inject described high concentration impurities, form the operation of described source high concentration region and described leakage side high concentration region to described semiconductor film.
Under the situation that makes the resist layer film forming on the semiconductor layer, be difficult in and make the even film forming of resist layer on the semiconductor layer.Thus, often can not be on semiconductor layer because the resist layer air spots is smooth even implanted dopant.In contrast to this, according to the present invention because the semiconductor layer that injects high concentration impurities is exposed, so can be on the smooth semiconductor layer that exposes direct implanted dopant.Thereby can be on semiconductor layer even implanted dopant.
The semiconductor device that the present invention relates to, it is the semiconductor device made from above-mentioned manufacture method, wherein said source high concentration region and described leakage side high concentration region form with the same area width from the end of described semiconductor film, the described source high concentration region of described semiconductor film and the thickness of described leakage side high concentration region, preferably the thickness than described source low concentration region, described leakage side low concentration region and described channel region is thin.
According to this formation, then because source and leak the side high concentration region and form with the same area width from the end of described semiconductor layer, so can obtain to have decide the semiconductor device of electrology characteristic.
From the end of above-mentioned semiconductor layer be with the reason that the same area width forms source and leakage side high concentration region, among the present invention after making the resist layer film forming on the semiconductor layer, by this resist layer being implemented the semi-tone exposure of photo-mask process, be formed with the resist layer zone corresponding with the semiconductor regions of implanted dopant.That is to say that the zone that has formed the thin layer resist layer will become the source in the semiconductor layer and leak the side high concentration region.And with this resist layer as mask, above-mentioned semiconductor layer is etched into the shape that formalizes, then implanted dopant on semiconductor layer.Therefore, owing to be before semiconductor layer being etched into institute's shape that formalize, irrelevant with the width of semiconductor layer, promptly need not to carry out contraposition, so can form source and leakage side high concentration region in self-adjusting ground (selfalign).And add man-hour at resist layer, and forming the thin layer resist layer by end with the same area width and form the zone from resist layer, source that can form from semiconductor layer and the end of leaking the semiconductor layer of side high concentration region are controlled in the same area width.
And the reason of the thickness attenuation of source and leakage side high concentration region semiconductor layer is, generally speaking such specific character is arranged, and promptly in case inject high concentration impurities in semiconductor layer, this high concentration impurity is compared etching with non-extrinsic region and will be quickened.And when gate insulating film during film forming, is generally handled implementing fluoric acid (strong acid) on the semiconductor layer in advance on semiconductor layer.Therefore, injected the semiconductor layer of high concentration impurities, compared, because the etching speed of fluoric acid is faster, so other regional thickness attenuation of Film Thickness Ratio of the semiconductor layer of source and leakage side high concentration region with other non-extrinsic regions.Source that the thickness unfertile land of this semiconductor layer forms and leakage side high concentration region can form with same widths from the both ends of semiconductor layer.
The manufacture method of semiconductor device of the present invention, it is the semiconductor layer that has source high concentration region, leakage side high concentration region, source low concentration region, leaks side low concentration region and channel region, with by described semiconductor layer relative with dielectric film to the manufacture method of semiconductor device of gate electrode, it is characterized in that, comprising: the operation that on substrate, forms semiconductor film; Will be on described semiconductor film the thickness of the resist layer corresponding with described source high concentration region and described leakage side high concentration region, form the thinner operation of thickness than the described resist layer of described source low concentration region, described leakage side low concentration region and described channel region correspondence; Thin part by described resist layer is injected high concentration impurities to described semiconductor film, forms the operation of described source high concentration region and described leakage side high concentration region; With described resist layer as mask with described semiconductor film be etched into decided the operation of pattern; Remove described resist layer from described semiconductor film, on described semiconductor film, form the operation of gate insulating film; On position corresponding on the described gate insulating film, form the operation of described gate electrode with described channel region; With with described gate electrode as mask, to the described semiconductor film implantation concentration low concentration impurity lower, form the operation of described source low concentration region and described leakage side low concentration region than described high concentration impurities; In described etching work procedure, to on the described semiconductor film that has formed below the described resist layer of thick thickness, inject the extrinsic region of described high concentration impurities, and the described semiconductor film of the extrinsic region that extends along the raceway groove parallel longitudinal of described channel region is removed.
According to this formation, remove the extrinsic region that extends along the raceway groove parallel longitudinal of channel region at least by etch processes.Like this, can prevent that electric charge from leaking into the drain region from the source region based on above-mentioned extrinsic region.Therefore, by the gate electrode ON/OFF correctly being made semiconductor device open and close.
And the semiconductor device that the present invention relates to, it is the semiconductor device that utilizes the manufacture method manufacturing of above-mentioned semiconductor device, it is characterized in that, the width of wherein said source high concentration region and described leakage side high concentration region is made as below the width of described source low concentration region and described leakage side low concentration region.
According to this formation, can remove the extrinsic region under the resist layer that has formed thick thickness really.Can prevent that like this electric charge from leaking into the drain region from the source region based on above-mentioned extrinsic region.Therefore, by semiconductor device correctly being opened and closed the gate electrode ON/OFF.
And the manufacture method of the semiconductor device that the present invention relates to, it is the semiconductor layer that has source high concentration region, leakage side high concentration region, source low concentration region, leaks side low concentration region and channel region, with by described semiconductor layer relative with dielectric film to the manufacture method of semiconductor device of gate electrode, it is characterized in that, comprising: the operation that on substrate, forms semiconductor film; Will be on described semiconductor film the thickness of the described resist layer corresponding with described source high concentration region, described leakage side high concentration region, described source low concentration region and described leakage side low concentration region, form the thinner operation of thickness than the described resist layer corresponding with described channel region; With described resist layer as mask with described semiconductor film be etched into decided pattern, inject low concentration impurity by the thin part of described resist layer to described semiconductor film simultaneously, form the operation of described source low concentration region and described leakage side low concentration region; Remove described resist layer from described semiconductor film, on described semiconductor film, form the operation of gate insulating film; On position corresponding on the described gate insulating film, form the operation of described gate electrode with described source low concentration region, described leakage side low concentration region and described channel region; With with described gate electrode as mask to the described semiconductor film implantation concentration high concentration impurities higher than described low concentration impurity, form the operation of described source high concentration region and described leakage side high concentration region.
With the semiconductor device that manufacture method of the present invention is made, be semiconductor device with so-called GOLD structure, have hot carrier countermeasure effect excellent characteristic.
According to this formation, after directly forming resist layer on the semiconductor layer, form the source and leakage side low concentration region thickness correspondence or corresponding with low concentration region and area with high mercury of resist layer therewith thinly with formalized shape by photoetching process.Thus, as mask semiconductor layer is etched into the shape that formalized with above-mentioned resist layer, simultaneously can be once more with above-mentioned resist layer as mask to above-mentioned semiconductor layer inject decided the impurity of concentration.That is to say that the resist layer of the shape that formalizes that will form by photo-mask process can be used among the etching and two operations of impurity injection of semiconductor layer simultaneously.Therefore, gate electrode pattern is changed in the shape that formalizes, can form semiconductor device by the Twi-lithography operation with GOLD structure.Therefore, compare with existing method and can cut down photo-mask process one time.And can also cut down simultaneously operation after the photo-mask process, the operation peeled off etc. of resist layer for example.
And form in the operation at the above-mentioned resist layer of the manufacture method of semiconductor device, during exposure, preferably by using the local different photomask of transmitance, the thickness of described resist layer that will be corresponding with described source low concentration region and described leakage side low concentration region forms thinner than the thickness of the described resist layer corresponding with described channel region.
According to this formation, then in photo-mask process, can control luminous intensity through mask or chopper wheel exposure, resist layer is carried out exposure imaging handle.Be that the semi-tone exposure becomes possibility.Thus, the film thickness monitoring of resist layer can be formed under deciding thickness.So, can on semiconductor layer, select control to form high concentration, low concentration or non-extrinsic region by making the Thickness Variation of above-mentioned resist layer.
And form in the operation at the above-mentioned resist layer of the manufacture method of semiconductor device, preferably make the thickness of the resist layer corresponding form 50～200 nanometers with described source low concentration region and described leakage side low concentration region.
According to this formation, adopt the low concentration impurity of ion implantation apparatus to the semiconductor layer irradiation, can pass through resist layer keeping under the low concentration state.Therefore, can on semiconductor layer, form source region and the drain region that constitutes by high concentration impurities.
And form in the operation in the above-mentioned low concentration impurity district of the manufacture method of semiconductor device, preferably have: with described resist layer as mask with described semiconductor film be etched into decided the operation of pattern; With will expose with the resist layer of described source high concentration region, described leakage side high concentration region, described source low concentration region and described leakage side low concentration region counterpart, inject described low concentration impurity to described semiconductor film, form the operation of described source low concentration region and described leakage side low concentration region.
Make resist layer under the situation of film forming on the semiconductor layer, be difficult to make resist layer even film forming on semiconductor layer.Thus, often can not be on semiconductor layer because the resist layer air spots is smooth even implanted dopant.In contrast to this, according to the present invention because the semiconductor layer that has injected low concentration impurity is exposed, so can be on the smooth semiconductor layer that exposes direct implanted dopant.Thereby can be on semiconductor layer even implanted dopant.
And the manufacture method of semiconductor device of the present invention, it is the semiconductor layer that has source high concentration region, leakage side high concentration region, source low concentration region, leaks side low concentration region and channel region, with by described semiconductor layer relative with dielectric film to the manufacture method of semiconductor device of gate electrode, it is characterized in that, comprising: the operation that on substrate, forms semiconductor film; Will be on described semiconductor film the thickness of the resist layer corresponding with described source high concentration region, described leakage side high concentration region, described source low concentration region and described leakage side low concentration region, form the thinner operation of thickness than the described resist layer of described channel region correspondence; Thin part by described resist layer is injected low concentration impurity to described semiconductor film, forms the operation of described source low concentration region and described leakage side low concentration region; With described resist layer as mask with described semiconductor film be etched into decided the operation of pattern; Remove described resist layer from described semiconductor film, on described semiconductor film, form the operation of gate insulating film; On position corresponding on the described gate insulating film, form the operation of described gate electrode with described source low concentration region, described leakage side low concentration region and described channel region; With inject than the high high concentration impurities of described low concentration impurity concentration to described semiconductor film as mask with described gate electrode, form the operation of described source high concentration region and described leakage side high concentration region; In described etching work procedure, to on the described semiconductor film that has formed below the described resist layer of thick thickness, inject the extrinsic region of described low concentration impurity, and the described semiconductor film of the extrinsic region that extends along the raceway groove parallel longitudinal of described channel region is removed.
According to this method, remove the extrinsic region that extends along the raceway groove parallel longitudinal of channel region at least by etch processes.Can prevent that like this electric charge from leaking into the drain region from the source region based on above-mentioned extrinsic region.Therefore, by with the gate electrode ON/OFF, semiconductor device is opened and closed.
And what the present invention relates to is the semiconductor device of being made by the manufacture method of above-mentioned semiconductor device, it is characterized in that, the width of wherein said source high concentration region and described leakage side high concentration region is made as below the width of described source low concentration region and described leakage side low concentration region.
According to this formation, can remove the extrinsic region that has formed under the thick resist layer of thickness really.Can prevent that like this electric charge from leaking into the drain region from the source region based on above-mentioned extrinsic region.Therefore, by the gate electrode ON/OFF correctly being made semiconductor device open and close.
And the present invention relates to a kind of manufacture method of semiconductor device, it is the semiconductor layer that has source high concentration region, leakage side high concentration region, source low concentration region, leaks side low concentration region and channel region, with by described semiconductor layer relative with dielectric film to the manufacture method of semiconductor device of gate electrode, it is characterized in that, comprising: the operation that on substrate, forms semiconductor film; On described semiconductor film, make resist layer form to such an extent that smooth, the two ends of middle body become the operation of conical section; Conical section by resist layer injects high concentration impurities to described semiconductor film, forms the operation of concentration gradient district and described channel region on described semiconductor film; With described resist layer as mask with described semiconductor film be etched into decided the operation of pattern; Remove described resist tunic from described semiconductor film, on described semiconductor film, form the operation of gate insulating film; On the described gate insulating film with described channel region or with a part of corresponding position in described channel region and described concentration gradient zone on form the operation of described gate electrode.
According to this formation and since resist layer form cone-shaped, so along with the end of thickness from semiconductor layer increases to channel region, the impurity of injection has the concentration gradient that is inversely proportional to thickness.That is to say that impurity concentration slowly reduces towards channel region from the end of semiconductor layer.Therefore by adopt above-mentioned pyramidal resist layer to inject an impurity, can on semiconductor layer, form have decide the extrinsic region of concentration gradient, for example source region and drain region high concentration impurity and source region and low concentration impurity zone, drain region.
In the manufacture method of above-mentioned semiconductor device, preferably on same substrate, form: on the described gate insulating film position corresponding with described channel region form described gate electrode semiconductor device and with described channel region and described concentration gradient zone in form the semiconductor device of gate electrode on the corresponding position of at least a portion.
So have in the semiconductor device of LDD and GOLD structure in formation, the mask when adopting pyramidal mask to inject as impurity can form the semiconductor device with LDD and GOLD structure at same substrate by just once injecting.And all self-adjusting ground forms the extrinsic region of the semiconductor device with LDD and GOLD structure.Therefore, can realize the high efficiency of the manufacturing process of semiconductor device.
And in the manufacture method of above-mentioned semiconductor device, preferably form on same substrate:, two ends smooth with middle body are the described resist layer of conical section and the semiconductor device that forms and form thinly described resist layer and the semiconductor device that forms with impurity injection zone thickness.
The employing resist layer corresponding with source and leakage side area with high mercury formed the mask of resist layer as mask with thin layer when formation has the semiconductor device of LDD structure like this, when having the semiconductor device of GOLD structure, formation passes through to adopt pyramidal mask as mask, compare with existing method, the number of times of photo-mask process can be cut down, semiconductor device can be on same substrate, formed with LDD and GOLD structure.Therefore, can realize the high efficiency of the manufacturing process of semiconductor device.
And the present invention relates to a kind of manufacture method of semiconductor device, it is the semiconductor layer that has source high concentration region, leakage side high concentration region, source low concentration region, leaks side low concentration region and channel region, with by described semiconductor layer relative with dielectric film to the manufacture method of semiconductor device of gate electrode, it is characterized in that, comprising: the operation that on substrate, forms semiconductor film; Are flats, becoming the thickness of the end of high concentration injection zone afterwards in the central authorities that become channel region afterwards, thinner than described flat, between the thin described two end portions of the described flat that becomes concentration range afterwards and thickness, form the operation of described resist layer with cone shape; With described resist layer as mask with described semiconductor film be etched into decided the operation of pattern; Inject high concentration impurities by resist layer to described semiconductor film, on described semiconductor film, form the operation of described channel region, described high concentration injection zone and described gradient region; Remove described resist tunic from described semiconductor film, on described semiconductor film, form the operation of gate insulating film; With on the described gate insulating film with described channel region or with a part of correspondence position in described channel region and described concentration gradient zone on form the operation of described gate electrode.
Adopt this formation, because it is cone-shaped that resist layer is formed, so along with thickness increases to channel region from area with high mercury, the impurity of injection has the concentration gradient that is inversely proportional to thickness.That is to say that impurity concentration slowly reduces towards channel region from area with high mercury.Therefore by adopt above-mentioned pyramidal resist layer to inject an impurity, can on semiconductor layer, form have decide the extrinsic region of concentration gradient, for example source region and drain region high concentration impurity and source region and low concentration impurity zone, drain region.
And in the manufacture method of above-mentioned semiconductor device, preferably forming on the same substrate: on described gate insulating film, form on the position corresponding with described channel region described gate electrode semiconductor device and with described channel region and described concentration gradient zone in the semiconductor device of formation gate electrode on the corresponding position of a part.
Form like this when having the semiconductor device of LDD and GOLD structure, the mask when adopting cone-shaped mask to inject as impurity can form the semiconductor device with LDD and GOLD structure at same substrate by just once injecting.And can be all can self-adjusting ground form the extrinsic region of semiconductor device with LDD and GOLD structure.Therefore, can realize the high efficiency of the manufacturing process of semiconductor device.
And in the manufacture method of above-mentioned semiconductor device, preferably form on same substrate: adopt that to make described resist layer form as the central authorities of described channel region considerable part be flat, thickness attenuation ground forms the operation of resist layer in as the end of described high concentration injection zone; And employing forms to such an extent that the described concentration gradient zone between the thin described end of described flat and thickness becomes the described resist layer of cone shape and the semiconductor device that forms; The semiconductor device that forms thin described resist layer with the thickness that adopts the impurity injection zone and form.
The employing resist layer corresponding with source and leakage side area with high mercury formed the mask of resist layer as mask with thin layer when formation has the semiconductor device of LDD structure like this, when having the semiconductor device of GOLD structure, formation passes through to adopt cone-shaped mask as mask, compare with existing method, can cut down the number of times of photo-mask process, can form semiconductor device at same substrate with LDD and GOLD structure.Therefore, can realize the high efficiency of the manufacturing process of semiconductor device.
And the present invention relates to a kind of manufacture method of semiconductor device, it is the semiconductor layer that has source high concentration region, leakage side high concentration region, source low concentration region, leaks side low concentration region and channel region, with by described semiconductor layer relative with dielectric film to the manufacture method of semiconductor device of gate electrode, it is characterized in that, comprising: the operation that on substrate, forms semiconductor film; Form in the zone at first semiconductor device, will be on described semiconductor film the thickness of the described resist layer corresponding with described source area with high mercury and described leakage side area with high mercury, form than the thickness of the described resist layer corresponding with described channel region, described source low concentration region and described leakage side low concentration region more unfertile land form described resist layer operation; Form in the zone at second semiconductor device, the thickness of described resist layer that will be corresponding with described source area with high mercury, described leakage side area with high mercury, described source low concentration region and described leakage side low concentration region, form thinlyyer, and form the operation of described resist layer than the thickness that first semiconductor device forms described resist layer corresponding with described source area with high mercury and described leakage side area with high mercury in the zone with thickening than the thickness of the described resist layer corresponding with described channel region; Form each semiconductor film in zone as described first and second semiconductor devices of mask etching with described resist layer, inject high concentration impurities to described semiconductor film simultaneously, form the zone at described first semiconductor device and form described source area with high mercury and described leakage side area with high mercury, form the operation that the zone forms described source low concentration region, described leakage side low concentration region and described channel region at second semiconductor device; Remove the described resist tunic that forms zone formation respectively at described first and second semiconductor devices from described semiconductor film, on described semiconductor film, form the operation of gate insulating film; Described first semiconductor device forms in the zone, forms the operation of described gate electrode on the described gate insulating film on the position corresponding with described channel region; Described second semiconductor device forms in the zone, on the described gate insulating film with described channel region, source low concentration region with leak the operation that forms described gate electrode on the corresponding position of side low concentration region; Form the described gate electrode in zone as mask with described first and second semiconductor devices respectively, the implantation concentration low concentration impurity lower than described high concentration impurities on described semiconductor film forms the operation that the zone forms described source low concentration region and described leakage side low concentration region at described first semiconductor device; The zone is comprehensive to be covered with resist layer described first semiconductor device being formed, form the described semiconductor film injection high concentration impurities in zone simultaneously to described second semiconductor device, form the operation of described source area with high mercury and described leakage side area with high mercury.
The present invention forms the zone of the zone by high concentration impurities, the zone of passing through low concentration impurity and blocking impurity by resist layer being carried out the semi-tone exposure on resist layer.That is to say,, on resist layer, form the pattern of three kinds of tones by the semi-tone exposure.In the formation of semiconductor device,, compare the number of times that to cut down photo-mask process like this, form LDD and GOLD at same substrate with existing method by adopting aforementioned mask with LDD and GOLD structure.Therefore, can realize the high efficiency of the manufacturing process of semiconductor device.
And the present invention relates to a kind of manufacture method of semiconductor device, it is the semiconductor layer that has source high concentration region, leakage side high concentration region, source low concentration region, leaks side low concentration region and channel region, with by described semiconductor layer relative with dielectric film to the manufacture method of semiconductor device of gate electrode, it is characterized in that, comprising: the operation that on substrate, forms semiconductor film; The thickness of resist layer that will be corresponding with described source zone and territory, described leakage lateral areas on described semiconductor film forms the thinner operation of thickness than the resist layer corresponding with described channel region; With described resist layer as mask with described semiconductor film be etched into decided the operation of pattern; With described resist layer as mask to described semiconductor film implanted dopant, form the operation in described source zone and territory, described leakage lateral areas; Remove described resist layer from described semiconductor film, on described semiconductor film, form the operation of gate insulating film; With the operation that on described gate insulating film, forms described gate electrode.
Can simplify the manufacturing process of semiconductor device with LDD or GOLD structure according to the present invention.
And the present invention relates to a kind of semiconductor device, be to make with the manufacture method of above-mentioned semiconductor device.
According to the present invention because source area with high mercury and leak the side area with high mercury and begin from the end of semiconductor layer to be formed with the same area width, so can access have decide the semiconductor device of electrology characteristic.
The present invention relates to a kind of electro-optical device in addition, is the electro-optical device that possesses above-mentioned semiconductor device.
Can under the situation of cutting down manufacturing process, make and provide electro-optical device according to the present invention.And in the present invention, described electro-optical device is meant, except comprising the variations in refractive index that is made material by electric field, thereby has beyond the device of the effect that the transmitance that makes light changes, and also comprises the general name of the device that can convert electric energy to luminous energy.
Description of drawings
Fig. 1 is the equivalent circuit diagram of the liquid crystal indicator of present embodiment.
Fig. 2 is the vertical view of a pixel of TF array base palte that amplifies the liquid crystal indicator of expression present embodiment.
Fig. 3 is the profile along the A-A ' straight line of liquid-crystal apparatus shown in Figure 2.
Fig. 4 (a)～(c) is the figure of manufacture method of the semiconductor device of first kind of execution mode of expression.
Fig. 5 (a)～(c) is the figure of manufacture method of the semiconductor device of first kind of execution mode of expression.
Fig. 6 (a)～(d) is the figure of manufacture method of the semiconductor device of second kind of execution mode of expression.
Fig. 7 (a)～(c) is the figure of manufacture method of the semiconductor device of the third execution mode of expression.
Fig. 8 (a) and (b) be the figure of manufacture method of the semiconductor device of the 4th kind of execution mode of expression.
Fig. 9 (a) and (b) be the figure of manufacture method of the semiconductor device of the 5th kind of execution mode of expression.
Figure 10 (a) and (b) be the figure of manufacture method of the semiconductor device of the 6th kind of execution mode of expression.
Figure 11 is the figure of manufacture method of the semiconductor device of the 7th kind of execution mode of expression.
Figure 12 (a) and (b) be the figure of manufacture method of the semiconductor device of the 7th kind of execution mode of expression.
Figure 13 (a) and (b) be the figure of manufacture method of the semiconductor device of the 7th kind of execution mode of expression.
Figure 14 (a) and (b) be the figure of manufacture method of the semiconductor device of the 7th kind of execution mode of expression.
Figure 15 (a) and (b) be the figure of manufacture method of the semiconductor device of the 7th kind of execution mode of expression.
Figure 16 (a) and (b) be the figure of manufacture method of the semiconductor device of the 7th kind of execution mode of expression.
Figure 17 (a) and (b) be the figure of manufacture method of the semiconductor device of the 7th kind of execution mode of expression.
Figure 18 (a) and (b) be the figure of manufacture method of the semiconductor device of the 7th kind of execution mode of expression.
Figure 19 (a) and (b) be the figure of manufacture method of the semiconductor device of the 7th kind of execution mode of expression.
Figure 20 is the stereogram of expression electronic instrument one example of the present invention.
Among the figure:
14a, 44,74 ... polycrystal semiconductor film, 16,46,76 ... the photoresist layer, 18,48,78 ... the source area with high mercury, 19,49,79 ... leak the side area with high mercury, 20,50,80 ... channel region, 22,52 ... gate insulating film, 24a, 54,84 ... gate electrode, 26,56,86 ... the source low concentration region, 27,57,87 ... leak the side low concentration region, L ... channel length
Embodiment
[first kind of execution mode]
(structure of electro-optical device)
Below the structure of electro-optical device of the execution mode that explanation the present invention relates to based on Fig. 1～Fig. 3.In the present embodiment, be that example is illustrated with the active array type permeability liquid-crystal apparatus that adopts TFT (thin film semiconductor device) to make switch element.
Fig. 1 be the expression liquid crystal indicator that constitutes present embodiment pixel region, with the equivalent electric circuit of the switch element in a plurality of pixels of rectangular configuration, holding wire etc., Fig. 2 is the amplification plan view of a pixel that expression has formed the tft array substrate of data wire, scan line, pixel electrode etc., Fig. 3 is the profile of liquid crystal indicator structure of expression present embodiment, is along the profile of A-A straight line among Fig. 2.In addition, in Fig. 3, be to represent the light light incident side with the upside of scheming, the downside of figure represents to observe the figure of side (observer's one side).And among each figure, because each layer and various parts are plotted the size that can discern on figure, the engineer's scale of each layer and each parts is different.
The liquid-crystal apparatus of present embodiment, as shown in Figure 1, on a plurality of pixels with rectangular configuration of composing images viewing area, form in advance the switch element TFT (thin film semiconductor device) 90 that pixel electrode 9 and this pixel electrode of control are used respectively, the data wire 6a that supplies with picture signal is electrically connected with the source of this TFT90.Write data wire 6a picture signal S1, S2 ..., Sn, order supply line or adjacent a plurality of data wire 6a are supplied with by group successively according to this.
And in advance scan line 3a is electrically connected with the grid of TFT90, for a plurality of scan line 3a according to institute regularly preface with the line order apply pulse sweep signal G1, G2 ..., Gn.And be electrically connected on the drain region of TFT90 than pixel electrode 9, by only opening TFT90 during certain as switch element, according to institute regularly preface write by picture signal S1, the S2 of data wire 6a supply ..., Sn.
By means of pixel electrode 9 in liquid crystal, write decide level picture signal S1, S2 ..., Sn, be maintained between the common electrode described later in during certain.Liquid crystal changes the orientation of elements collection and order because of applying voltage levvl, thereby modulation light can carry out gray scale (grade) and show.Wherein in order to prevent that maintained picture signal from leaking, can and pixel electrode 9 and common electrode between the additional side by side savings electric capacity 98 of liquid crystal capacitance that forms.
As shown in Figure 3, the liquid-crystal apparatus of present embodiment is to comprise the clamping liquid crystal layer and be relative to the configuration, formed the tft array substrate 100 of TFT90 and pixel electrode 9 and formed the opposite electrode 104 of common electrode 108 and constitute substantially.
The following planar structure that tft array substrate 100 is described according to Fig. 2.
On tft array substrate 100, with rectangular a plurality of rectangular pixel electrodes 9 are set in advance, as shown in Figure 2, are provided with data wire 6a, scan line 3a and electric capacity line 3b along each pixel electrode 9 border in length and breadth.In the present embodiment, formed each pixel electrode and be provided with to such an extent that the zone of data wire 6a, scan line 3a etc. that each pixel electrode 9 is surrounded will form a pixel.
Data wire 6a is electrically connected with source region 18 among the polycrystal semiconductor film 14a that constitutes TFT90 in advance by means of contact hole 92, and pixel electrode 9 is electrically connected with drain region 19 among the polycrystal semiconductor film 14a by means of contact hole 96, source line 6b, contact hole 94 in advance.And channel region 20 is relatively to amplification in the polycrystal semiconductor film 14a for the part of scan line 3a, and the amplification of scan line 3a partly plays a part gate electrode.Below only the part that plays the gate electrode effect among the scan line 3a is called " gate electrode ", 24a represents with symbol.And constitute the polycrystal semiconductor film 14a of TFT90, extend in advance relative with electric capacity line 3b to part, forming with this extension 1f and be bottom electrode, be the savings electric capacity (savings capacity cell) 98 of top electrode with electric capacity line 3B.
Below based on Fig. 3 the cross-section structure of the liquid-crystal apparatus of present embodiment is described.
Tft array substrate 100, the main base main body made from transparent materials such as glass (light-transmitting substrate) 10 reaches the pixel electrode 9, TFT90 and the alignment films 11 that form on its liquid crystal layer 102 side surfaces be that main body constitutes, and substrate 104 main base main body (light-transmitting substrate) 104A that make with transparent materials such as glass are reached the common electrode 108 and the alignment films 110 that form on its liquid crystal layer 102 side surfaces be the main body formation.
Say in detail, in the tft array substrate 100, directly over substrate 10, be formed with the base protective film (buffer film) 12 that constitutes by silicon oxide film etc.And liquid crystal layer 102 side surfaces of base main body 10 are provided with the pixel electrode 9 that is made of indium tin oxide transparent conductivity materials such as (ITO), are provided with the pixel switch TFT90 that switch is controlled each pixel electrode 9 with each pixel electrode position adjacent.
On base protective film 12, forming the polycrystal semiconductor film 14a that constitutes by polysilicon with decided pattern, on this polycrystal semiconductor film 14a, form the gate insulating film of forming by silicon oxide film 22, on this gate insulating film 22, formed scan line 3a.In the present embodiment, the side of gate electrode 24a forms cone-shaped with respect to the surface of gate insulating film 22.And in polycrystal semiconductor film 14a, by gate insulating film 22 relative with gate electrode 24a to the zone, will become the channel region 20 that forms raceway groove under from the effect of electric field of gate electrode 24a.And in polycrystal semiconductor film 14a,, and form drain region 19 at opposite side (diagram right side) in a side (diagram left side) the formation source region 18 of channel region 20.So by the source region 18 of gate electrode 24a, gate insulating film 22, data wire 6a described later, source line 6b, polycrystal semiconductor film 14a, formation pixel switch TFT90 such as channel region 20, drain region 19.
In the present embodiment, pixel switch TFT90 has the LDD structure, and 18 form the relative higher area with high mercury (high concentration source region, high concentration drain region) of impurity concentration respectively with drain region 19 and as the LDD zone (low concentration source region, low concentration drain region) of the relatively low low concentration region of impurity concentration in the source.Below represent source area with high mercury and source low concentration region with symbol 18 and 26 respectively, represent to leak the side area with high mercury and leak the side low concentration region with symbol 19,27.
And on the base main body 10 that has formed scan line 3a (part is gate electrode 24a), be formed with first interlayer dielectric of forming by silicon oxide film etc. 4 in advance, on this interlayer dielectric 4, be formed with data wire 6a and source line 6b.Data wire 6a is electrically connected then by the contact hole 92 of formation on first interlayer dielectric 4 and the source area with high mercury 18 of polycrystal semiconductor film 14a, and source line 6b is electrically connected with the leakage side area with high mercury 19 of polycrystal semiconductor film 14a by the contact hole 94 that forms on first interlayer dielectric 4.
And on first interlayer dielectric 4 that has formed data wire 6a and source line 6b, form second interlayer dielectric of forming by silicon nitride film 5, on second interlayer dielectric 5, be formed with pixel electrode 9.Pixel electrode 9 is electrically connected then with source line 6b by the contact hole 96 that forms on second interlayer dielectric 5.
And the part 1f that extends for leakage side area with high mercury 19 from polycrystal semiconductor film 14a, by means of the dielectric film (dielectric film) integrally formed with gate insulating film 22, the electric capacity line 3b that forms with layer with scan line 3a is as top electrode and subtend is disposing, and extension 1f and electric capacity line 3b form savings electric capacity 98 thus.
And on the outer surface of liquid crystal layer 102 sides of tft array substrate 100, be formed with and make the alignment films 11 that Liquid Crystal Molecules Alignment are used in the liquid crystal layer 102.
On the other hand, in to substrate 104, on liquid crystal layer 102 side surfaces of base main body 104A, be formed with photomask 106, so that the light that prevents to incide in the liquid-crystal apparatus incides in the channel region 20 and low concentration region 26,27 of polycrystal semiconductor film 14a at least.And on the base main body 104A that has formed photomask 106, spread all over its whole surface and form the common electrode 108 that constitutes by ITO etc., the alignment films 110 that molecules align is used in its liquid crystal layer 102 1 sides are formed with control liquid crystal layer 102.
(method of producing thin-film semiconductor)
Fig. 4 (a)～(c) and Fig. 5 (a)～(c) are the profiles of manufacture method of representing to have in the present embodiment n channel-type TFT of LDD structure with process sequence.
At first shown in Fig. 4 (a), prepare to wait light-transmitting substrate such as washed glass as substrate 10 through ultrasonic waves for cleaning.The glass surface temperature is made as under 150～450 ℃ the condition, utilizes plasma CVD method etc. to make the base protective film (buffer film) 12 that is made of silicon oxide layer etc. on all surfaces of substrate 10, film forming is 100～500 nanometer thickness.As the unstrpped gas that this operation adopts, mist, TEOS (tetraethoxy-silicane, the Si (OC of preferred monosilane and nitrous oxide 2H 5) 4) and oxygen, disilane and ammonia etc.
And then shown in Fig. 4 (a), making amorphous semiconductor film 14 film forming on all surfaces of base protective film 12 that is made of amorphous silicon by plasma CVD method is 30～100 nanometer thickness.Preferred disilane and the monosilane of adopting is as unstrpped gas in this operation.Then amorphous semiconductor film 14 is implemented laser annealing and handle, make amorphous semiconductor film 14 polycrystallizations, form the polycrystal semiconductor film 14a that constitutes by polysilicon.
Then shown in Fig. 4 (b), make photoresist layer 16 film forming on above-mentioned polycrystal semiconductor film 14a, utilize photoetching process to be patterned to the shape that formalizes.Wherein in photoetching process, use the semi-tone mask as the exposure of transfer printing on photoresist layer 16 decide pattern mask or chopper wheel.This semi-tone mask has the part with the exposure light blocking of exposure device irradiation, makes exposure light part that sees through fully and the part that exposure light is partly seen through.See through the mask of exposure light or the zone of chopper wheel in part, be provided with the refract light gate pattern that constitutes by slit, can control luminous intensity through exposure light.
When exposure, use above-mentioned semi-tone mask like this, the shape of photoresist layer 16 is formed like this, promptly with the source area with high mercury 18 of polycrystal semiconductor film 14a with leak the thickness in corresponding photoresist layer 16 zone of side area with high mercury 19, thinner than the thickness of the photoresist layer 16 corresponding with channel region 20a.That is to say, the thin part of resist layer is meant, when when polycrystal semiconductor film 14a injects the high concentration impurities ion, irradiated high concentration impurities ion by photoresist layer 16, is injected into the part of the sort of thickness photoresist layer 16 of above-mentioned source area with high mercury 18 and leakage side area with high mercury 19 with the high concentration state.As the thickness of this photoresist layer 16, about for example preferred 50～200 nanometers.
On the other hand, with the source area with high mercury 18 of polycrystal semiconductor film 14a with leak the thickness of the corresponding resist layer of channel region 20 beyond the side area with high mercury 19, when being meant to polycrystal semiconductor film 14a injection high concentration impurities ion, irradiated high concentration impurities ion is by photoresist layer 16 blocking, decide concentration foreign ion can not arrive at the thickness of the degree of polycrystal semiconductor film 14a.As the thickness of this photoresist layer 16, more than for example preferred 200 nanometers.
In addition, described channel region 20a be in the aftermentioned with source low concentration region 26, leak the corresponding zone of side low concentration region 27 and channel region 10.
Then shown in Fig. 4 (c), as mask, the polycrystal semiconductor film 14a that will form in the lower floor of photoresist layer 16 is etched into the shape that formalizes with the photoresist layer 16 that is etched into the above-mentioned shape that formalized.Can suitably adopt the whole bag of tricks such as dry-etching method or wet process as engraving method.
And then shown in Fig. 4 (c), with above-mentioned photoresist layer 16 as mask to polycrystal semiconductor film 14a, for example inject 0.1 * 10 15～about 10 * 10 15/ cm 2The high concentration impurities ion (phosphonium ion) of amount.With regard to the thin zone of above-mentioned photoresist layer 16 thickness, above-mentioned high concentration impurities ion is injected among the polycrystal semiconductor film 14a by photoresist layer 16 with the high concentration state like this.Like this with photoresist layer 16 as mask, can self-adjusting on polycrystal semiconductor film 14a, form source area with high mercury 18 (selfalign) and leak side area with high mercury 19.On the other hand, with regard to above-mentioned photoresist layer 16 thickness thick the zone with regard to because above-mentioned high concentration impurities ion interdicted by photoresist layer 16, so foreign ion can not arrive at polycrystal semiconductor film 14a zone.The zone of concentration of impurities ion that so injection is decided will become the channel region 20a that is made of the polycrystal semiconductor film 14a that does not add impurity.And the preferred etching operation of after foreign ion injects, implementing polycrystal semiconductor film 14a again.
Present embodiment is characterised in that, as mentioned above, directly will be patterned to the above-mentioned shape that formalizes by the photoresist layer 16 of film forming on polycrystal semiconductor film 14a, as mask the high concentration impurities ion is injected polycrystal semiconductor film 14a this point.That is to say, it is characterized in that, do not inject the high concentration impurities ion by means of gate insulating film as before, but before making the gate insulating film film forming, inject high concentration impurities ion this point to polycrystal semiconductor film 14a.Therefore, after semiconductor device formed, the impurity concentration that the gate insulating film of present embodiment 22 is contained was compared with impurity concentration contained in the gate insulating film in the existing method, and the gate insulating film impurities concentration in the existing method is higher.Therefore, if gate insulating film impurities concentration for example is 1 * 10 14/ cm 2, then utilize gate insulating film can inject the foreign ion of high concentration.
Then shown in Fig. 5 (a), to on polycrystal semiconductor film 14a, peel off by the photoresist layer 16 of film forming, after the fluoric acid processing, on all surfaces of the substrate 10 that comprises the polycrystal semiconductor film 14a after peeling off, utilize plasma CVD method, sputtering method etc. to form dielectric film 22.And then on gate insulating film 22 comprehensively formation will become the conduction 24 of gate electrode described later.
Shown in Fig. 5 (b), on all surfaces of above-mentioned conducting film 24, make resist layer 30 film forming then.By photoetching process to above-mentioned resist layer 30 expose, development treatment, be patterned into the shape that formalizes.Wherein above-mentioned resist layer 30 forms, and is narrower than the peak width of the channel region 20a of the Fig. 5 (b) that forms in lower floor, and contraposition and channel region 20a the both ends source described later and the leakage side low concentration region 26,27 that form.
And then shown in Fig. 5 (c), as mask etching conducting film 24, form gate electrode 24a with the resist layer 30 that is patterned to the above-mentioned shape that formalized.
Continue with gate electrode 24a as mask, for example with about 0.1 * 10 then 13～10 * 10 13/ cm 2Doping is injected low concentration impurity ion (phosphonium ion), and the channel region two end portions in polycrystal semiconductor film 14a zone forms the source low concentration region and leaks side low concentration region 26,27.The semiconductor device that like this formation is had so-called LDD structure.
By the semiconductor device with LDD structure of said method manufacturing, source area with high mercury 18 and leak the peak width of side area with high mercury 19 forms to such an extent that have same widths apart from the end of polycrystal semiconductor film 14a.And because of gate insulating film form before the etching speed difference handled of fluoric acid, so can make the source area with high mercury 18 of polycrystal semiconductor film 14a and the thickness of leakage side area with high mercury 19, form thinner than the thickness of source low concentration region 26, leakage side low concentration region 27 and channel region 20.
Just as described above, directly after forming photoresist layer 16 on the semiconductor layer, the thickness that makes the source area with high mercury 18 of this photoresist layer 16 and leak side area with high mercury 19 corresponding positions by photoetching process forms thinly in the present embodiment.Therefore, can as mask polycrystal semiconductor film 14a be etched into the shape that formalized with above-mentioned photoresist layer 16, simultaneously again with above-mentioned resist layer 16 as mask to above-mentioned semiconductor layer inject decided the impurity of concentration.That is to say that the photoresist layer 16 of the shape that formalize that forms by photo-mask process can inject two operations as mask usefulness also at the etching of polycrystal semiconductor film 14a and impurity.Therefore compare with existing method, can reduce photo-mask process one time.And the subsequent handling that can also cut down photo-mask process simultaneously; Stripping process of photoresist layer 16 etc. for example.
And owing to as mask polycrystal semiconductor film 14a is directly carried out the impurity injection with photoresist layer 16, so needn't be by means of the gate insulating film 22 that on polycrystal semiconductor film 14a, forms with regard to the energy implanted dopant.Therefore, can avoid the damage of the gate insulating film 22 that causes because of impurity irradiation, thereby can provide and guarantee gate insulating film 22 insulating properties, that reliability is high.
And because form source area with high mercury 18 and leak side area with high mercury 19 as mask with above-mentioned photoresist layer 16, form source low concentration region 26 and leak side low concentration region 27 as mask with above-mentioned gate electrode 24a then, so all self-adjusting ground (selfalign) forms all dirt zone.
In addition, above-mentioned polycrystal semiconductor film 14a is etched into before the shape that formalizes, can set the source area with high mercury 18 among the polycrystal semiconductor film 14a and leak side area with high mercury 19.Therefore, when polycrystal semiconductor film 14a implanted dopant being formed source area with high mercury 18 and leaking side area with high mercury 19, needn't carry out contraposition to mask and polycrystal semiconductor film 14a, can in polycrystal semiconductor film 14a, form above-mentioned source area with high mercury 18 and leak side area with high mercury 19 with high accuracy.
[second kind of execution mode]
Following with reference to the formation method that has the semiconductor device of GOLD structure in Fig. 6 (a)～(c) explanation present embodiment.
Fig. 6 (a)～(c) is a constructed profile of representing to have in the present embodiment n channel-type TFT manufacture method of GOLD structure with process sequence.Wherein for the explanation of above-mentioned first kind of same operation of execution mode, will omit or simplify in the present embodiment, give prosign for common inscape.
At first shown in Fig. 6 (a), on all surfaces of substrate 10, form base protective film 12, on base protective film 12, make polycrystal semiconductor film 14a film forming.On polycrystal semiconductor film 14a, make photoresist layer 16 film forming then, be patterned to the shape that formalizes.The pattern form of photoresist layer 16 as mentioned above, adopts the semi-tone mask, makes the thickness in polycrystal semiconductor film 14a photoresist layer 16 zone corresponding with source region 18a and drain region 19a in Fig. 6 (a) form thinly.That is to say, injecting on the polycrystal semiconductor film 14a under the situation of low concentration impurity particle, irradiated low concentration impurity particle by photoresist layer 16, forms the photoresist layer 16 of deciding such thickness that the zone is injected into to above-mentioned with the low concentration state.The thickness of this photoresist layer 16 is about for example preferred 50～200 nanometers.
On the other hand, thickness as the photoresist layer 16 corresponding with channel region 20 beyond the source region 18a of polycrystal semiconductor film 14a and the drain region 19a, polycrystal semiconductor film 14a is injected under the situation of low concentration impurity ion, be in the zone of photoresist layer 16, irradiated low concentration impurity ion can be interdicted, make decide concentration foreign ion can not arrive at the thickness of polycrystal semiconductor film 14a.As the thickness of such photoresist layer 16, for example preferably be made as more than 200 nanometers.
Wherein said source region 18a is zone corresponding with source area with high mercury 18 and source low concentration region 27 in the aftermentioned.And described drain region 19a be in the aftermentioned with leak side area with high mercury 19 and leak the corresponding zone of side low concentration region 27.
And then shown in Fig. 6 (a), as mask, the polycrystal semiconductor film 14a that the lower floor of photoresist layer 16 is formed is etched into the shape that formalizes with the photoresist layer 16 that is etched into the above-mentioned shape that formalized.Engraving method can suitably adopt the whole bag of tricks such as dry etching method or wet process.
And preferably inject the etching that polycrystal semiconductor film 14a is implemented in the back at foreign ion.
And then with above-mentioned photoresist layer 16 as mask, to polycrystal semiconductor film 14a, for example with about 0.1 * 10 13～10 * 10 13/ cm 2Amount is injected low concentration impurity ion (phosphonium ion).Shown in Fig. 6 (a), form source region 18a and the drain region 19a that has injected the low concentration impurity ion thus in polycrystal semiconductor film 14a zone.At this moment, be made as photoresist layer 16 thickness thickness portion under the zone of implanting impurity ion not as yet, position, will become channel region 20.Like this with photoresist layer 16 as mask, can self-adjusting (selfalign) on polycrystal semiconductor film 14a zone formation itself be the source region 18a and the drain region 19a in low concentration impurity zone.
To on polycrystal semiconductor film 14a, peel off by the photoresist layer 16 of film forming then.And then shown in Fig. 6 (b), utilize plasma CVD method, sputtering method etc. to form gate insulating film 22 on comprehensively at the substrate 10 that comprises the polycrystal semiconductor film 14a that has peeled off.Then gate insulating film 22 comprehensively on form the conducting film 24 that became gate electrode afterwards.
Then shown in Fig. 6 (b), above-mentioned conducting film 24 comprehensively on make resist layer 30 film forming.And then with photoetching process to above-mentioned resist layer 30 expose, development treatment is patterned to the shape that formalizes.The width of this resist layer 30 shown in Fig. 6 (b), forms greatlyyer than the peak width of the channel region 20 that forms in lower floor, and source region 18a and drain region 19a that the two end portions at channel region 20a is formed are overlapped.
And then shown in Fig. 6 (c), as mask etching conducting film 24, form gate electrode 24a with the resist layer 30 that is patterned to the above-mentioned shape that formalized.
Then shown in Fig. 6 (d), with gate electrode 24a as mask, for example with about 0.1 * 10 15～10 * 10 15/ cm 2Doping is injected high concentration impurities ion (phosphonium ion).Inject the high concentration impurities ion in the polycrystal semiconductor film 14a zone that is covered by gate electrode 24a like this, form source area with high mercury 18 and leak side area with high mercury 19.On the other hand, locational polycrystal semiconductor film 14a zone forms channel region 20 for the blocking foreign ion under the gate electrode 24a that is covered by gate electrode 24a, and forms source low concentration region 26 and leak side low concentration region 27 in its two end portions.Present embodiment is different with above-mentioned first kind of execution mode, and source low concentration region 26 and leakage side low concentration region 27 form overlap condition under gate electrode 24a, promptly form the semiconductor device of so-called GOLD structure.
Just as described above, by adopting the operation that illustrates in above-mentioned second kind of execution mode; Changed the injection order of foreign ion, made source low concentration region 26 and leak side low concentration region 27 on gate electrode 24a, to form overlap condition, can form semiconductor device with GOLD structure.
[the third execution mode]
It is following that explanation forms the formation method that same substrate has the semiconductor device of LDD structure and GOLD structure simultaneously on same substrate with reference to Fig. 7 (a)～(c).Wherein to above-mentioned first or second kind of same operation of execution mode; To omit in the present embodiment or simplified illustration.
Fig. 7 (a)～(c) is the n type channel-type TFT manufacture method profile that has LDD structure and GOLD structure with in the process sequence explanation present embodiment.Wherein the TFT zone with LDD structure shown in the left side among the figure is called LDD and forms the zone, the TFT zone with GOLD structure shown in the right side among the figure is called GOLD forms the zone.
Shown in Fig. 7 (a), at first substrate 40 comprehensively on form base protective film 42.Then be transformed into polycrystal semiconductor film 44, make resist layer film forming on this polycrystal semiconductor film 44 by the non-crystalline semiconductor film is implemented annealing in process.Then as described above, with the semi-tone mask resist layer is patterned to the shape that formalizes.In LDD forms the zone,, shown in Fig. 7 (a), form thinly with source area with high mercury 48 and the thickness that leaks the corresponding resist layer 46 of side area with high mercury 49 as the patterned shape of resist layer 46.As with source area with high mercury 48 with leak the thickness of the corresponding resist layer 46 of side area with high mercury 49, about for example preferred 50～200 nanometers.On the other hand, thickness as the resist layer corresponding 46 with the channel region 50a of polycrystal semiconductor film 44, polycrystal semiconductor film 44 is injected under the situation of high concentration impurities ion, is the thickness of irradiated high concentration impurities ion quilt blocking degree in the zone of resist layer 46.As the thickness of resist layer 46, for example preferably be made as more than 200 nanometers.
Wherein said channel region 50a is with source low concentration region 56 in aftermentioned, leaks the corresponding zone of the low low concentration region 57 of side and channel region 50.
And shown in Fig. 7 (a)～(c), in the GOLD zone, the pattern form of resist layer 76, the thickness in resist layer 76 zones corresponding with source region 78a and drain region 79a forms thinly.Specifically, thicker than the resist layer of using in the above-mentioned LDD zone 46 with the thickness part that thin layer forms, and form thinly than channel region 80.At this moment, the thickness in resist layer 76 zones corresponding with the source region 78a of resist layer 76 and drain region 79a, injecting under the situation of high concentration impurities ion to polycrystal semiconductor film 74, irradiated low concentration impurity ion, forms and is injected into the above-mentioned thickness of deciding the sort of resist layer 76 in zone by resist layer 76 with the low concentration state.That is to say that a part of high concentration impurities ion is interdicted by resist layer 76, arrive at polycrystal semiconductor film 74 after becoming low concentration.
On the other hand, the thickness of the resist layer 76 corresponding with the channel region 80 of polycrystal semiconductor film 74, under the situation of polycrystal semiconductor film 74 being carried out the injection of high concentration impurities ion, irradiated high concentration impurities ion will become by the thickness of blocking degree in resist layer 76 zones.As the thickness of resist layer 76, for example preferably be made as more than 200 nanometers.
Wherein above-mentioned source region 78a is the zone corresponding with source area with high mercury 78 and source low concentration region 86 in aftermentioned.And drain region 79a, in aftermentioned be and leak side area with high mercury 79 and leak the corresponding zone of side low concentration region 87.
And then with the resist layer 46,76 that is patterned into the above-mentioned shape that formalized as mask, the polycrystal semiconductor film 44,74 that will form in the lower floor of resist layer 46,76 is etched into the shape that formalizes respectively.The wherein etching of polycrystal semiconductor film 44,74 is preferably carried out after foreign ion described later injects.
And then shown in Fig. 7 (a), respectively with above-mentioned resist layer 46,76 as mask, to polycrystal semiconductor film 44,74 for example with about 0.1 * 10 15～10 * 10 15/ cm 2Doping is injected high concentration impurities ion (phosphonium ion).Thus, in the LDD zone, on the thin zone of the thickness of above-mentioned resist layer 46, inject high viscosity impurity, on the zone of polycrystal semiconductor film 44, form source area with high mercury 48 (selfalign) and leak side area with high mercury 49 as the mask self-adjusting with above-mentioned resist layer 46.And on the zone of the polycrystal semiconductor film under the resist layer 46 44,,, and form channel region 50a so foreign ion can not inject above-mentioned polycrystal semiconductor film 44 because foreign ion is interdicted by resist layer 46 masks.
In the GOLD zone, about the thin zone of the thickness of above-mentioned resist layer 76, the high concentration impurities ion is injected in the polycrystal semiconductor film 74 because of the thickness of resist layer 76 passes through resist layer 76 with the low concentration state on the other hand.Thus with resist layer 76 as mask, can self-adjusting (selfalign) on polycrystal semiconductor film 74 zones formation itself be the source region 78a and the drain region 79a in low concentration impurity zone.And be made as on the zone of the polycrystal semiconductor film 74 under the resist layer 76, because foreign ion is interdicted by resist layer 76 masks,, foreign ion forms channel region 80 so can not injecting above-mentioned polycrystal semiconductor film 74.
And then shown in Fig. 7 (b), after polycrystal semiconductor film 44,74 was carried out the impurity injection process, the resist layer 44 and 74 that will form on polycrystal semiconductor film 44,74 was peeled off respectively.Then on polycrystal semiconductor film 44,74, form gate insulating film 52, on gate insulating film 52, form conducting film then.Make resist layer film forming on conducting film subsequently, this resist layer is patterned to the shape that formalizes.And the resist layer of the shape that formalized to be patterned to carries out etching as mask to the conducting film that forms in lower floor.In LDD forms the zone, on the position corresponding, form gate electrode 54 after the etching with channel region.And in GOLD forms the zone, with channel region 80 described later and source low concentration region 86 with leak on the corresponding position of side low concentration region 87 and form gate electrode 84.
Then shown in Fig. 7 (b), with gate electrode 54,84 as mask, for example with about 0.1 * 10 13～10 * 10 13/ cm 2Doping is injected high concentration impurities ion (phosphonium ion) to polycrystal semiconductor film 44,74 respectively.
Thus, in forming the zone, LDD can form, at the two end portions formation source low concentration region 56 and the leakage side low concentration region 57 of channel region 50, semiconductor device with LDD structure.In the GOLD zone, though injected low concentration impurity, the source region 78a and the drain region 79a that are injected into impurity are the low concentration impurity zones on the other hand.
And then shown in Fig. 7 (C), in LDD forms the zone, forming resist layer 60 in order to prevent high concentration impurities from injecting, the semiconductor device that will have the LDD structure of above formation covers comprehensively.And then in GOLD forms the zone, with gate electrode 84 as mask, for example with about 0.1 * 10 15～10 * 10 15/ cm 2Doping is injected high concentration impurities ion (phosphonium ion) to polycrystal semiconductor film 74.Thus, itself be the source region 78a in low concentration impurity zone and the zone that drain region 79a is not covered by gate electrode 84, will become the source area with high mercury of forming by high concentration impurities 78 and leak side area with high mercury 79.And under gate electrode 84, source low concentration region 86 and leakage side low concentration region 87 will become overlap condition, form the semiconductor device with GOLD structure.
According to present embodiment, various circuit are carried on the tft array substrate 100 of liquid crystal indicator, can form semiconductor device according to desired function with LDD and GOLD structure.For example, can form the little semiconductor device of dielectric current for TFT with LDD structure as the switch element that can drive pixel electrode, and, then can form the good semiconductor device of hot carrier offside effect with GOLD structure for being formed in the TFT that the pixel peripheral part is provided with drive circuit.
And when the formation of semiconductor device with LDD and GOLD structure, by employing make resist layer that use as mask, corresponding with source region and drain region form very thin mask, compare with existing method, the number of times of photo-mask process can be reduced, and LDD and GOLD can be on same substrate, formed simultaneously.Therefore, can make manufacturing process's high efficiency of semiconductor device.
[the 4th kind of execution mode]
Following with reference to Fig. 8 (a) and 8 (b), with above-mentioned the third execution mode the formation method that forms the semiconductor device with LDD structure and GOLD structure on same substrate simultaneously is described equally.Wherein about with the same operation of above-mentioned first～the third execution mode; To omit in the present embodiment or simplified illustration.
Fig. 8 (a) and 8 (b) are the n type channel-type TFT manufacture method profiles that has LDD structure and GOLD structure with in the process sequence explanation present embodiment.Wherein the TFT zone with LDD structure shown in the right side among Fig. 8 is called LDD and forms the zone, the TFT zone with GOLD structure shown in the left side among the figure is called GOLD forms the zone.
Shown in Fig. 8 (a), at first at comprehensive formation base protective film 42 of substrate 40.Then, resist layer 46 is patterned to the shape that formalizes by annealing in process is transformed into polycrystal semiconductor film 44 with the non-crystalline semiconductor film.In LDD forms the zone, resist layer 46 by semi-tone exposure form have decide the cone-shaped of angle cone, the direction towards channel region 50 thickens the thickness that makes resist layer 46 from the end of polycrystal semiconductor film 44.Say that more specifically above-mentioned pyramidal resist layer 46 forms smoothly at middle body, and forms cone-shaped in the end.
On the other hand, form in the zone too at GOLD, resist layer 76 by the semi-tone exposure form have decide the cone-shaped of angle cone, the direction towards channel region 50 thickens the thickness that makes resist layer 76 from the end of polycrystal semiconductor film 74.
And then with the resist layer 46,76 that is patterned into the above-mentioned shape that formalized as mask, the polycrystal semiconductor film 44,74 that will form in the lower floor of resist layer 46,76 is patterned to the shape that formalizes respectively.The wherein etching of polycrystal semiconductor film 44,74 is preferably carried out after foreign ion described later injects.
Then shown in Fig. 8 (a), with above-mentioned resist layer 46,76 as mask, respectively to polycrystal semiconductor film 44,74, for example with about 0.1 * 10 15～10 * 10 15/ cm 2Doping is injected high concentration impurities ion (phosphonium ion).
By this injection, in the LDD zone, make resist layer 46 form pyramidal zone, the impurity concentration that is injected into along with the thickness of resist layer 46 from the source area with high mercury 48 of polycrystal semiconductor film 44 with leak side area with high mercury 49 and slowly thicken and reduce towards channel region 50.Its result, shown in Fig. 8 (a), on zone under the resist layer 46 that can pass through high concentration impurities, the high concentration impurities ion can be injected polycrystal semiconductor film 44, on the zone of polycrystal semiconductor film 44, form source area with high mercury 48 and leak side area with high mercury 49.On the other hand, on zone under the resist layer 46 that can pass through low concentration impurity, the low concentration impurity ion can be injected polycrystal semiconductor film 44, form source low concentration region 56 and leak side low concentration region 57.Above-mentioned resist layer 46 thickness the thickest zone under, can form channel region 50.
Wherein, above-mentioned polycrystal semiconductor film 44 forms the zone that has concentration gradient from the two end portions of polycrystal semiconductor film 44 towards channel region 50 as described above, has self-adjusting in order to realize with above-mentioned execution mode in the present embodiment, to be boundary with decided impurity concentration, easily polycrystal semiconductor film will be divided into high concentration impurity and the low concentration impurity zone is illustrated.
Equally, in the GOLD zone also shown in Fig. 8 (a), on zone under the resist layer 76 that can pass through high concentration impurities, the high concentration impurities ion can be injected polycrystal semiconductor film 74, on the zone of polycrystal semiconductor film 74, form source area with high mercury 78 and leak side area with high mercury 79.On the other hand, on zone under the resist layer 76 that can pass through low concentration impurity, the low concentration impurity ion can be injected polycrystal semiconductor film 74, form source low concentration region 86 and leak side low concentration region 87.And above-mentioned resist layer 76 thickness the thickest zone under, can form channel region 80.
And then shown in Fig. 8 (b), polycrystal semiconductor film 44,74 carried out the impurity injection process after, respectively the resist layer 46 and 76 that forms on the polycrystal semiconductor film 44,74 is peeled off.Then the substrate 40 that comprises polycrystal semiconductor film 44,74 comprehensively on form gate insulating film 52, on gate insulating film 52, form conducting film then.Make resist layer film forming on conducting film subsequently, this resist layer is patterned to the shape that formalizes.As the patterned shape of this resist layer, in LDD forms the zone, the resist layer patterning must be equated with the peak width of the channel region 50 of above-mentioned polycrystal semiconductor film 44.On the other hand in GOLD forms the zone, shown in Fig. 8 (b), with resist layer patterning in the following manner, even the peak width of source low concentration region 86 that the channel region 80 of above-mentioned polycrystal semiconductor film 74 and two end portions form and leakage side low concentration region 87 equates, perhaps make source low concentration region 86 and leak side low concentration region 87 and overlap.The above-mentioned resist layer of shape formalized then respectively to be patterned to as mask, the conductive film patternization that lower floor is formed.Its result forms gate electrode 54, and form gate electrode 84 in the GOLD structural region in the LDD structural region.
Thus, in the LDD structural region, under gate electrode 54, form channel region 50 in advance, form semiconductor device with LDD structure.On the other hand, the channel region 80 of GOLD structural region under gate electrode 84, make low concentration impurity zone 86,87 overlapping, form semiconductor device with GOLD structure.
In sum, form when having the semiconductor device of LDD and GOLD structure, adopt pyramidal resist layer mask, compare the number of times that can reduce photo-mask process with existing method, and can on same substrate, form LDD and GOLD as mask.Therefore, can make manufacturing process's high efficiency of semiconductor device.
[the 5th kind of execution mode]
Following with reference to Fig. 9 (a) and 9 (b), same with above-mentioned the 4th kind of execution mode, the method that forms the semiconductor device with LDD structure and GOLD structure on same substrate simultaneously is described.Wherein about with above-mentioned the first～four kind of same operation of execution mode; To omit in the present embodiment or simplified illustration.
Fig. 9 (a) and (b) be the n type channel-type TFT manufacture method profile of expression to have LDD structure and GOLD structure in the process sequence explanation present embodiment.Wherein the TFT zone with LDD structure shown in the right side among Fig. 9 is called LDD and forms the zone, the TFT zone with GOLD structure shown in the left side among the figure is called GOLD forms the zone.
Shown in Fig. 9 (a), at first substrate 40 comprehensively on form base protective film 42.Then the non-crystalline semiconductor film is transformed into polycrystal semiconductor film 44, on this polycrystal semiconductor film 44, makes resist layer 46 film forming by annealing in process.Then resist layer 46 is patterned to the shape that formalizes.In LDD formed the zone, resist layer 46 was by semi-tone exposure, and shown in Fig. 9 (a), forming the central authorities suitable with channel region 80 is flats, formed suitable for impurity high concentration injection zone the part of deciding filming in its outside.
On the other hand, form in the zone too at GOLD, resist layer 76 and channel region 80 suitable central authorities are flats, form the conical section suitable in its outside with the impurity concentration gradient region, so its outside formation suitable with impurity high concentration injection zone by the part of deciding filming.
And then with the resist layer 46,76 that is patterned to the above-mentioned shape that formalized as mask, will be patterned to the shape that formalizes respectively at the polycrystal semiconductor film 44,74 that resist layer 46,76 lower floors form.The wherein etching of polycrystal semiconductor film 44,74 is preferably carried out after foreign ion described later injects.
Then shown in Fig. 9 (a), with above-mentioned resist layer 46,76 as mask, respectively to polycrystal semiconductor film 44,74, for example with about 0.1 * 10 15～10 * 10 15/ cm 2Doping is injected high concentration impurities ion (phosphonium ion).
Make resist layer 46 form pyramidal zone in the LDD zone by being infused in, the impurity concentration that is injected into along with the thickness of resist layer 46 from the source area with high mercury 48 of polycrystal semiconductor film 44 with leak side area with high mercury 49 and slowly thicken and reduce towards channel region 50.Thereby form concentration gradient zone with concentration impurity ion gradient.Its result, shown in Fig. 9 (a), on zone under the resist layer 46 that can pass through high concentration impurities, the high concentration impurities ion is injected into polycrystal semiconductor film 44, forms source area with high mercury 48 and leak side area with high mercury 49 on the zone of polycrystal semiconductor film 44.On the other hand, at the positive lower area of the conical section of resist layer 46 that can be by low concentration impurity, the low concentration impurity ion is injected into polycrystal semiconductor film 44, forms source low concentration region 56 and leaks side low concentration region 57.Above-mentioned resist layer 46 thickness the thickest zone under can form channel region 50.
Wherein, above-mentioned polycrystal semiconductor film 44 forms the concentration gradient zone from the area with high mercury of polycrystal semiconductor film 44 towards channel region 50 as described above, has adjustment in order to realize with above-mentioned execution mode in the present embodiment, with decided impurity concentration is boundary, easily polycrystal semiconductor film is divided into the zone explanation of high concentration impurity and low concentration impurity.
Equally, in the GOLD zone, also shown in Fig. 9 (a), regional under the resist layer 76 that can pass through high concentration impurities, the high concentration impurities ion is injected into polycrystal semiconductor film 74, forms source area with high mercury 78 and leaks side area with high mercury 79 in the zone of polycrystal semiconductor film 74.On the other hand, zone under the conical section of the resist layer 76 that can pass through low concentration impurity, the low concentration impurity ion is injected into polycrystal semiconductor film 74, forms source low concentration region 86 and leaks side low concentration region 87.And above-mentioned resist layer 76 thickness the thickest zone under form channel region 80.
Secondly shown in Fig. 9 (b), behind the impurity injection process of polycrystal semiconductor film 44,74, the resist layer 46 and 76 that will form on polycrystal semiconductor film 44,74 is peeled off respectively.Form gate insulating film 52 at the substrate 40 that comprises polycrystal semiconductor film 44,74 on comprehensively then, and then on gate insulating film 52, form conducting film.On conducting film, form resist layer subsequently, this resist layer is patterned to the shape that formalizes.As the patterned shape of this resist layer, form the zone at LDD and resist layer is patterned to the peak width of the channel region 50 of above-mentioned polycrystal semiconductor film 44 equates.Form the zone at GOLD on the other hand, shown in Fig. 9 (b), with resist layer patterning in the following manner, the channel region 80 of above-mentioned polycrystal semiconductor film 74 is equated with the peak width of source low concentration region 86 that forms in two end portions and leakage side low concentration region 87, source low concentration region 86 and leakage side low concentration region 87 are overlapped.The above-mentioned resist layer of shape formalized then respectively to be patterned to as mask, the conductive film patternization that lower floor is formed.Its result forms gate electrode 54, and form gate electrode 84 in the GOLD structural region in the LDD structural region.
In the LDD structural region, under gate electrode 54, form channel region 50 in advance like this, form semiconductor device with LDD structure.On the other hand, in the GOLD structural region, the channel region 80 under gate electrode 84, make low concentration impurity zone 86,87 overlapping, form semiconductor device with GOLD structure.
In sum, form when having the semiconductor device of LDD and GOLD structure, adopt cone-shaped mask, compare the number of times that can reduce photo-mask process, on same substrate, form LDD and GOLD with existing method as mask.Therefore, can make manufacturing process's high efficiency of semiconductor device.
[the 6th kind of execution mode]
Below same with above-mentioned the three～five kind of execution mode, with reference to Figure 10 (a) and 9 (b), the method that is formed on the semiconductor device that has LDD structure and GOLD structure on the same substrate is described.Wherein about with above-mentioned the first～five kind of identical operation of execution mode; To omit in the present embodiment or simplified illustration.
Figure 10 (a) and (b) be the n type channel-type TFT manufacture method profile of expression to have LDD structure and GOLD structure in the process sequence explanation present embodiment.Wherein the TFT zone with LDD structure shown in the right side among Figure 10 is called LDD and forms the zone, the TFT zone with GOLD structure shown in the left side among the figure is called GOLD forms the zone.
Shown in Figure 10 (a), at first form base protective film 42 on comprehensively at substrate 40.Then the non-crystalline semiconductor film is transformed into polycrystal semiconductor film 44, on this polycrystal semiconductor film 44, makes resist layer 46 film forming by annealing in process.Then resist layer 46 is patterned to the shape that formalizes.In LDD formed the zone, resist layer 46 was by semi-tone exposure, made the thickness of the resist layer 46 corresponding with source region 48 and drain region 49 form very thinly.About for example preferred 50～200 nanometers of the thickness of resist layer 46.And the thickness of the resist layer 46 corresponding with the channel region 50a of polycrystal semiconductor film 44, under the situation of carrying out the injection of high concentration impurities ion on polycrystal semiconductor film 44 films, be that the high concentration impurities ion of irradiation can be by the thickness of blocking degree in the zone of resist layer 46.Wherein above-mentioned channel region 50a, be in the aftermentioned with source low concentration region 56, leak the corresponding zone of side low concentration region 57 and channel region 50.
On the other hand, in GOLD formed the zone, resist layer 76 was by semi-tone exposure, formed to have institute and decide the horn-like of angle cone, and resist layer 76 is thickeied towards the thickness of the direction resist layer 76 of channel region 80 from the end of polycrystal semiconductor film 74.
Then with the resist layer 46,76 that is patterned into the above-mentioned shape that formalized as mask, will be patterned to the shape that formalizes at the polycrystal semiconductor film 44,74 that resist layer 46,76 lower floors form respectively.The wherein etching of polycrystal semiconductor film 44,74 is preferably carried out after foreign ion described later injects.
Then shown in Figure 10 (a), with above-mentioned resist layer 46,76 as mask, respectively to polycrystal semiconductor film 44,74, for example with about 0.1 * 10 15～10 * 10 15/ cm 2Doping is injected high concentration impurities ion (phosphonium ion).And in the LDD zone, on the thin zone of the thickness of above-mentioned resist layer 46, inject high concentration impurities.Like this with above-mentioned resist layer 46 as mask, self-adjusting ground (selfalign) forms source area with high mercury 48 and leakage side area with high mercury 49 on polycrystal semiconductor film 44.And on 44 zones of the polycrystal semiconductor film under the resist layer 46,,, and form channel region 50a so foreign ion is not injected into above-mentioned polycrystal semiconductor film 44 because of foreign ion is interdicted by resist layer 34 masks.
On the other hand in the GOLD zone, because it is cone-shaped that resist layer 76 is formed, thus the impurity concentration of being injected along with the thickness of resist layer 76 from the source area with high mercury 78 at polycrystal semiconductor film 74 two ends with leak side area with high mercury 79 and slowly thicken and the concentration gradient that reduces towards channel region 80.Thus shown in Figure 10 (a), zone under the resist layer 76 that can pass through high concentration impurities, the high concentration impurities ion is injected into polycrystal semiconductor film 74, and self-adjusting ground (selfalign) forms source zone 78,79 on the zone of polycrystal semiconductor film 74.On the other hand, zone under the resist layer 76 that can pass through low concentration impurity, the low concentration impurity ion is injected into polycrystal semiconductor film 74, forms source low concentration region 86 and leaks side low concentration region 87.Above-mentioned resist layer 76 thickness the thickest zone under form channel region 80.
Secondly shown in Figure 10 (b), behind the impurity injection process of polycrystal semiconductor film 44,74, the resist layer 46 and 76 that will form on polycrystal semiconductor film 44,74 is peeled off respectively.Form gate insulating film 52 at the substrate 40 that comprises polycrystal semiconductor film 44,74 on comprehensively then, and then on gate insulating film 52, form conducting film.On conducting film, form resist layer subsequently, this resist layer is patterned to the shape that formalizes.Form the zone at LDD, resist layer (diagram is omitted) forms littler than the peak width of the channel region 50a of Figure 10 (a) of lower floor's formation, and contraposition gets the source low concentration region 56 that can form at the both ends of channel region 50a and leaks side low concentration region 57.
Form the zone at GOLD on the other hand, resist layer (diagram is omitted) forms to such an extent that channel region 80 and two end portions thereof source low concentration region 86 that forms and the peak width that leaks side low concentration region 87 at above-mentioned polycrystal semiconductor film 74 are equated.This moment, the peak width of source low concentration region 86 and leakage side low concentration region 87 also can form equally.The above-mentioned resist layer of shape formalized then respectively to be patterned to as mask, the conductive film patternization that lower floor is formed.Thus, in the LDD structural region, form gate electrode 54, and in the GOLD structural region, form gate electrode 84.
Then in LDD forms the zone, with gate electrode as mask, with about 0.1 * 10 13～10 * 10 13/ cm 2Doping is injected low concentration impurity ion (phosphonium ion).To form source low concentration region 56 on self-adjusting ground, the both ends of the channel region 50 of polycrystal semiconductor film 44 (selfalign) like this and leak side low concentration region 57.
As above explanation, in the LDD structural region, under gate electrode 54, form channel region 50 in advance, form semiconductor device with LDD structure.On the other hand, in the GOLD structural region, the channel region 80 under gate electrode 84, make low concentration impurity zone 86,87 overlapping, form semiconductor device with GOLD structure.
According to present embodiment, then when the semiconductor device with LDD structure forms, make the mask of the resist layer very thin formation corresponding with source region and drain region as mask, and when the semiconductor device with GOLD structure forms, adopt cone-shaped mask as mask, compare the number of times that can reduce photo-mask process with existing method, on same substrate, form semiconductor device with LDD and GOLD structure.Thereby can make manufacturing process's high efficiency of semiconductor device.
[the 7th kind of execution mode]
Following with reference to the description of drawings present embodiment.
In the above-mentioned execution mode,, in the thin zone of thickness foreign ion is seen through on polycrystal semiconductor film, to form extrinsic region to resist layer processing, in the thick zone of thickness with foreign ion blocking non-extrinsic region of formation on polycrystal semiconductor film.In this case, the side in the thick zone of the thickness of resist layer under the vertical situation about forming of substrate, forms impurity and sees through zone and the non-border that sees through the zone of impurity.But, because the problem on the exposure device precision often makes the side of resist layer become trumpet-shaped cone face.Therefore, because the thickness attenuation step by step of horn-like cone face as shown in figure 11, makes the original not positive lower area 14b (by the chain-dotted line area surrounded) of the cone face of the resist layer of implanted dopant also be injected into impurity sometimes.Its result, the source region 18,26 and the drain region 19,27 that form in the channel region both sides are all connected by the above-mentioned extrinsic region 14b that forms in the channel region peripheral part, form from the source region 18,26 to the drain region 19,27 path.Thus, 18,26 to the drain region 19,27 from the source region, and electronics leaks with the switch of gate electrode 24a irrelevant, thus exist can not be correctly with the problem of TFT switch.Yet in the present embodiment, removing above-mentioned impurity by the over etching processing addresses the above problem.
The manufacture method that wherein has the semiconductor device of LDD structure, because its basic comprising makes execution mode identical with above-mentioned first kind, so give prosign to common inscape, it describes omission in detail.
Figure 12～Figure 15 is the process chart of the manufacture method of the expression n channel-type TFT that has the LDD structure in the present embodiment.And (a) among Figure 12～Figure 15 is the plane graph of manufacturing process, (b) among Figure 12～Figure 15 be shown in (a) in the manufacturing procedure picture along the profile of B-B' straight line.
At first shown in Figure 12 (b), on glass substrate 10, form the base protective film 12 that constitutes by silicon oxide layer with plasma CVD method comprehensively.Then utilize plasma CVD method to make amorphous film forming film forming on base protective film 12, handling through laser annealing then changes polycrystallization with the amorphous semiconductor film, forms polycrystal semiconductor film 14a on base protective film 12 comprehensively.
Then same with above-mentioned first kind of execution mode, on above-mentioned polycrystal semiconductor film 14a, make photoresist layer 16 film forming, by photoetching treatment photoresist layer 16 is patterned to the shape that formalizes.Photoresist layer 16 forms to such an extent that have a thick zone of thickness that the foreign ion of thin zone of the thickness that sees through the irradiation foreign ion and irradiation is interdicted as mentioned above.This moment, photoresist layer 16 thickness formed to such an extent that make thick regional side, were not injected into for making foreign ion, preferably formed with 90 degree with respect to glass substrate 10.But because the relation on the exposure device precision, shown in Figure 12 (b), the side of photoresist layer 16 often forms with respect to 10 one-tenth pyramidal for example cone face 16a of 80 degree of glass substrate.Wherein in the present embodiment, the zone that the thickness of photoresist layer 16 is thick is decided to be the zone that comprises horn-like cone face 16a.
And then as Figure 13 (a) with (b), the resist layer of the shape that formalized to be patterned to injects the high concentration impurities ion as mask on polycrystal semiconductor film 14a.Therefore in the thin zone of photoresist layer 16 thickness, the foreign ion of high concentration is injected among the polycrystal semiconductor film 14a by photoresist layer 16.On the other hand, in the thick zone of photoresist layer 16 thickness, the high concentration impurities ion photoresist layer 16 thickness thick the zone in interdicted.Wherein in the cone face 16a of photoresist layer 16 side with horn-like formation, shown in Figure 13 (b), because of photoresist layer 16 thickness step by step attenuation the high concentration impurities ion is passed through, on polycrystal semiconductor film 14a, inject the high concentration impurities ion.In Figure 13 (a), oblique line partly represents to inject the zone of high concentration impurities ion, and lattice portion divides expression not inject the regional 14b of high concentration impurities ion originally.Therefore in the present embodiment, as Figure 13 (a) with (b), except that photoresist layer 16 thickness approach under the zone, until being injected into foreign ion till the regional 14b under the photoresist layer 16 horn-like cone face 16a.
And,, polycrystal semiconductor film 14a is carried out etch processes to be etched into the above-mentioned photoresist layer 16 that is shaped as mask as Figure 14 (a) with (b).Can suitably adopt the whole bag of tricks such as dry-etching (RIE) or wet process as engraving method.At first by etch processes, remove under the photoresist layer 16 the polycrystal semiconductor film 14a in (the not zone that is covered by photoresist layer 16) beyond the zone.In addition in the present embodiment, again for regional 14b under the horn-like cone face 16a of photoresist layer 16 is injected into foreign ion, so remove this extrinsic region 14b by etch processes.Therefore, handle carrying out over etching after the etching beyond the zone under the photoresist layer 16 again, shown in Figure 14 (a), remove photoresist layer 16 horn-like cone face 16a under the high concentration impurities ion of regional 14b (among Figure 14 (a) till dotted portion).When over etching is handled, the thickness of photoresist layer 16 thin under in the zone, also from the thickness of photoresist layer 16 thick under the zone begin to carry out etching.Among Figure 14 (a), the thickness of photoresist layer 16 thin under the thickness of live width W1 ' and photoresist layer 16 of polycrystal semiconductor film 14a in zone thick under the live width W2 ' of regional polycrystal semiconductor film 14a compare also and narrow down.Wherein when over etching is handled, by control etch processes speed, can also the thickness that makes photoresist layer 16 thin under the live width W1 ' of polycrystal semiconductor film 14a in zone, the thickness with photoresist layer 16 of becoming thick under the stage termination etch processes that equates of the live width W2' of polycrystal semiconductor film 14a in zone.From above-mentioned as can be known in the present embodiment, in the regional 14b under the horn-like cone face 16a of photoresist layer 16 (form the thick zone of thickness under zone), and the extrinsic region of the polycrystal semiconductor film 14a that extends along the raceway groove parallel longitudinal of channel region, remove by etch processes.
Then, the photoresist layer 16 on the polycrystal semiconductor film 14a is peeled off, on the glass substrate 10 on the polycrystal semiconductor film 14a that comprises after peeling off comprehensive, utilized formation gate insulating films 22 such as plasma CVD method, sputtering method as Figure 15 (a) with (b).And then formation is patterned to gate insulating film 22 the gate electrode 24a of the shape that formalizes.
Use gate electrode 24a as mask then, inject the low concentration impurity ion.Like this shown in Figure 15 (a), on the polycrystal semiconductor film 14a that has removed zone under the gate electrode 24a, form source low concentration region 26 and leak side low concentration region 27, the zone forms channel region 20a under gate electrode 24a simultaneously.Wherein, the thickness of photoresist layer 16 thin under the zone, with source area with high mercury 18 with to leak side area with high mercury 19 corresponding, the thickness of photoresist layer 16 thick under the zone, with source low concentration region 26 and to leak side low concentration region 27 corresponding.
As Figure 15 (a) shown in,, will find this moment in case observe semiconductor device in the plane: source area with high mercury 18 and leak the live width W1 of side area with high mercury 19, compare also with the live width W2 of source low concentration region 26 and leakage side low concentration region 27 and narrow down.Wherein the live width W1 of source area with high mercury 18 and leakage side area with high mercury 19 also can be made as below the live width W2 of source low concentration region 26 and leakage side low concentration region 27.
According to present embodiment, under the horn-like cone face of resist layer in the zone, and, handle and to remove by over etching along the impurity that the channel length L of channel region extends in parallel.Under the situation of removing the above-mentioned extrinsic region that will become the electronics path, can prevent that electronics from leaking to the drain region from the source region like this.Thereby can pass through the correct switching TFT of switch gate electrode.
[variation of the 7th kind of execution mode]
Following with reference to the description of drawings present embodiment.
Present embodiment wherein, only have on the GOLD structure this point different with above-mentioned the 7th kind of execution mode, the basic comprising of the manufacture method of semiconductor device, identical with above-mentioned the 7th kind of execution mode.Therefore will give same-sign for common inscape, and describe in detail and omit.
Figure 16～Figure 19 is the process chart of the manufacture method of the expression n channel-type TFT that has the GLD structure in the present embodiment.And (a) among Figure 16～Figure 19 is the plane graph of manufacturing process, (b) among Figure 16～Figure 19 be shown in (a) in the manufacturing procedure picture along the profile of C-C ' straight line.
At first shown in Figure 16 (b), on glass substrate 10, form base protective film 12 comprehensively, on base protective film 12, make polycrystal semiconductor film 14a film forming with plasma CVD method.On polycrystal semiconductor film 14a, make photoresist layer 16 film forming then, be patterned to the shape that formalizes.Photoresist layer 16 as mentioned above, forms to such an extent that have a thick zone of thickness that the foreign ion of thin zone of the thickness that sees through the irradiation foreign ion and irradiation is interdicted.This moment is in the regional side that photoresist layer 16 thickness form thickly, because the relation on the exposure device precision shown in Figure 16 (b), often forms with respect to 10 one-tenth cone-shaped cone face 16a that for example become 80 degree of glass substrate.
And then as Figure 17 (a) with (b), the resist layer of the shape that formalized to be patterned to injects the high concentration impurities ion as mask on polycrystal semiconductor film 14a.In the thin zone of photoresist layer 16 thickness, the foreign ion of low concentration is injected among the polycrystal semiconductor film 14a like this.And in the thick zone of photoresist layer 16 thickness, the low concentration impurity ion photoresist layer 16 thickness thick the zone in interdicted.Wherein photoresist layer 16 side with horn-like formation cone face 16a in, shown in Figure 17 (b), because of photoresist layer 16 thickness step by step attenuation the low concentration impurity ion is passed through, on polycrystal semiconductor film 14a, inject the low concentration impurity ion.In Figure 17 (a), oblique line partly represents to inject the zone of low concentration impurity ion, and lattice portion divides expression not inject the regional 14b of low concentration impurity ion originally.Therefore in the present embodiment, as Figure 17 (a) with (b), except that photoresist layer 16 thickness approach under the zone, until being injected into foreign ion till the regional 14b under the photoresist layer 16 horn-like cone face 16a.
And,, polycrystal semiconductor film 14a is carried out etch processes to be patterned to the above-mentioned photoresist layer 16 that is shaped as mask as Figure 18 (a) with (b).At first remove the polycrystal semiconductor film 14a beyond the zone under the photoresist layer 16 by etch processes.And then in the present embodiment,, remove this extrinsic region 14b by etch processes for regional 14b under photoresist layer 16 horn-like cone face 16a injects the low concentration impurity ion.Therefore in the present embodiment, handle carrying out over etching after the etching beyond the zone under the photoresist layer 16 again, shown in Figure 18 (b), remove photoresist layer 16 horn-like cone face 16a under the low concentration impurity ion of regional 14b (among Figure 18 (a) until dotted portion).When over etching is handled, photoresist layer 16 thickness thin under in the zone, also from photoresist layer 16 thickness thick under the zone begin to carry out etching.Among Figure 18 (a), photoresist layer 16 thickness thin under live width W1 ' and photoresist layer 16 thickness of polycrystal semiconductor film 14a in zone thick under the live width W2 ' of regional polycrystal semiconductor film 14a compare also and narrow down.From above-mentioned as can be known in the present embodiment, will be under photoresist layer 16 horn-like cone face 16a in the regional 14b (form the thick zone of thickness under zone), and the extrinsic region of the polycrystal semiconductor film 14a that extends along the raceway groove parallel longitudinal of channel region, remove by etch processes.
The photoresist layer 16 of polycrystal semiconductor film 14a being gone up film forming is peeled off then.Then as Figure 19 (a) with (b), utilize formation gate insulating film 22 on the glass substrate 10 on the polycrystal semiconductor film 14a that comprises after peeling off comprehensive such as plasma CVD method, sputtering method.And then on gate insulating film 22, form gate electrode 24a.This moment, gate electrode 24a formed with the two ends of gate electrode 24a and the region overlapping that has injected low concentration impurity on above-mentioned polycrystal semiconductor film 14a.
Use gate electrode 24a as mask then, inject the high concentration impurities ion to polycrystal semiconductor film 14a.Shown in Figure 19 (a), on the polycrystal semiconductor film 14a that is not covered, inject the high concentration impurities particle like this, form source area with high mercury 18 and leak side area with high mercury 19 by gate electrode 24a.On the other hand, on the throne installing to forming channel region 20a on the polycrystal semiconductor film 14a zone under the gate electrode 24a that is covered by gate electrode 24a forms source low concentration region 26 and leaks side low concentration region 27 in its both sides.As Figure 19 (a) shown in, will find this moment in case observe semiconductor device in the plane: source area with high mercury 18 and leak the live width W1 of side area with high mercury 19, compare also with the live width W2 of source low concentration region 26 and leakage side low concentration region 27 and narrow down.
According to present embodiment, can produce the effect same with above-mentioned execution mode.That is to say, under the horn-like cone face of resist layer in the zone, and, can handle by over etching and remove along the low concentration impurity that the channel length L of channel region extends in parallel.Under the situation of removing the above-mentioned extrinsic region that becomes the electronics path, can prevent that electronics from leaking to the drain region from the source region like this.Thereby can pass through the correct switching TFT of switch gate electrode.
[electronic instrument]
Below be example with the electronic instrument of the liquid crystal indicator that has above-mentioned execution mode of the present invention
Be illustrated.
Figure 20 is the shaft side figure of expression lcd television set 1200 examples.Among Figure 20, symbol 1202 expression television set main bodys, symbol 1203 expression loud speakers, the display part that above-mentioned display unit has been adopted in symbol 1201 expressions.Wherein above-mentioned liquid crystal indicator 1, thereby can be used for above-mentioned lcd television set various electronic instruments in addition.For example can be used for projecting apparatus, PC (PC) and engineering work station (EWS), beep-pager, word processor, view-finder type or single transoid video camera, electronic ID card, electronic computer, automobile navigation apparatus, the POS terminal corresponding, have the electronic instruments such as device of touch-screen with multimedia.
Technical scope of the present invention is not limited to above-mentioned execution mode, comprising the various changes of making in originally not by the scope of main points of the present invention.
For example, in the above-described embodiment, be so that decide the corresponding resist layer in zone thickness form than the thin resist layer of other regional thickness as mask, polycrystal semiconductor film is carried out the injection of foreign ion.In contrast to this, also preferably make the resist layer that forms thinly with the above-mentioned thickness of deciding the corresponding resist layer in zone, by exposing (overexposure etc.) again and peeling off, make with after above-mentioned resist layer forms thin regional corresponding polycrystal semiconductor film and exposes, impurity is directly injected polycrystal semiconductor film.Can make impurity evenly inject polycrystal semiconductor film like this.Wherein in this case, inject,, preferably carry out the injection of foreign ion in the case so can set the accelerating voltage of impurity injection device etc. lower than above-mentioned execution mode because directly carry out impurity to polycrystal semiconductor film.
Though and the present invention adopts liquid crystal indicator to be elaborated,, also can be used for the light emitting-type organic EL display or make the linearity shaven head, tape deck etc. of light source with organic EL about the semiconductor device part of substrate 10 sides.

Claims (23)

1, a kind of manufacture method of semiconductor device, it is the semiconductor layer that has source high concentration region, leakage side high concentration region, source low concentration region, leaks side low concentration region and channel region, with by described semiconductor layer relative with dielectric film to the manufacture method of semiconductor device of gate electrode
It is characterized in that, comprising:
On substrate, form the operation of semiconductor film;
Will be on described semiconductor film the thickness of the resist tunic corresponding with described source high concentration region and described leakage side high concentration region, form the thin operation of thickness than the described resist tunic of described source low concentration region, described leakage side low concentration region and described channel region correspondence;
With described resist layer as mask, with described semiconductor film be etched into decide pattern, inject high concentration impurities by the thin part of described resist layer to described semiconductor film simultaneously, form the operation of described source high concentration region and described leakage side high concentration region;
Remove described resist layer from described semiconductor film, on described semiconductor film, form the operation of gate insulating film;
On position corresponding on the described gate insulating film, form the operation of described gate electrode with described channel region;
As mask, inject the low concentration impurity lower with described gate electrode, form the operation of described source low concentration region and described leakage side low concentration region than described high concentration impurities to described semiconductor film.
2, the manufacture method of semiconductor device according to claim 1, it is characterized in that, form in the operation at described resist layer, during exposure, by using the local different photomask of transmitance, the thickness of described resist layer that will be corresponding with described source high concentration region and described leakage side high concentration region forms thinner than the thickness of the described resist layer of described source low concentration region, described leakage side low concentration region and described channel region correspondence.
3, the manufacture method of semiconductor device according to claim 1 and 2 is characterized in that, forms in the operation at resist layer, and the thickness of resist layer that will be corresponding with described source high concentration region and described leakage side high concentration region forms 50～200 nanometers.
4, according to the manufacture method of the semiconductor device described in any one of claim 1～3, it is characterized in that, wherein form in the operation and comprise in described high concentration impurities district:
With described resist layer as mask with described semiconductor film be etched into decided the operation of pattern; With
The semiconductor film of the part of described source high concentration region and described leakage side high concentration region correspondence is exposed, inject described high concentration impurities, form the operation of described source high concentration region and described leakage side high concentration region to described semiconductor film.
5, a kind of semiconductor device, it is the semiconductor device that utilizes the manufacture method of the semiconductor device described in any one of described claim 1～4 to make, it is characterized in that, wherein said source high concentration region and described leakage side high concentration region form with the same area width from the end of described semiconductor film, the described source high concentration region of described semiconductor film and the thickness of described leakage side high concentration region are thinner than the thickness of described source low concentration region, described leakage side low concentration region and described channel region.
6, a kind of manufacture method of semiconductor device, it is the semiconductor layer that has source high concentration region, leakage side high concentration region, source low concentration region, leaks side low concentration region and channel region, with by described semiconductor layer relative with dielectric film to the manufacture method of semiconductor device of gate electrode
It is characterized in that, comprising:
On substrate, form the operation of semiconductor film;
Will be on described semiconductor film the thickness of the resist layer corresponding with described source high concentration region and described leakage side high concentration region, form the thin operation of thickness than the described resist layer of described source low concentration region, described leakage side low concentration region and described channel region correspondence;
Thin part by described resist layer is injected high concentration impurities to described semiconductor film, forms the operation of described source high concentration region and described leakage side high concentration region;
With described resist layer as mask with described semiconductor film be etched into decided the operation of pattern;
Remove described resist layer from described semiconductor film, on described semiconductor film, form the operation of gate insulating film;
On position corresponding on the described gate insulating film, form the operation of described gate electrode with described channel region; With
As mask, inject the low concentration impurity lower with described gate electrode, form the operation of described source low concentration region and described leakage side low concentration region than described high concentration impurities to described semiconductor film;
In described etching work procedure, to on the described semiconductor film that has formed below the described resist layer of thick thickness, inject the extrinsic region of described high concentration impurities, and the described semiconductor film of the extrinsic region that extends along the raceway groove parallel longitudinal of described channel region is removed.
7, a kind of semiconductor device, it is the semiconductor device of making by the manufacture method of the described semiconductor device of claim 6, it is characterized in that, the width of wherein said source high concentration region and described leakage side high concentration region is made as below the width of described source low concentration region and described leakage side low concentration region.
8, a kind of manufacture method of semiconductor device, it is the semiconductor layer that has source high concentration region, leakage side high concentration region, source low concentration region, leaks side low concentration region and channel region, with by described semiconductor layer relative with dielectric film to the manufacture method of semiconductor device of gate electrode
It is characterized in that, comprising:
On substrate, form the operation of semiconductor film;
Will be on described semiconductor film the thickness of the described resist layer corresponding with described source high concentration region, described leakage side high concentration region, described source low concentration region and described leakage side low concentration region, form the thin operation of thickness than the described resist layer corresponding with described channel region;
With described resist layer as mask with described semiconductor film be etched into decided pattern, inject low concentration impurity by the thin part of described resist layer to described semiconductor film simultaneously, form the operation of described source low concentration region and described leakage side low concentration region;
Remove described resist layer from described semiconductor film, on described semiconductor film, form the operation of gate insulating film;
On position corresponding on the described gate insulating film, form the operation of described gate electrode with described source low concentration region, described leakage side low concentration region and described channel region; With
As mask, inject the high concentration impurities higher with described gate electrode, form the operation of described source high concentration region and described leakage side high concentration region than described low concentration impurity to described semiconductor film.
9, the manufacture method of semiconductor device according to claim 8, it is characterized in that, form in the operation at described resist layer, during exposure, by using the local different photomask of transmitance, the thickness of described resist layer that will be corresponding with described source low concentration region and described leakage side low concentration region forms thinner than the thickness of the described resist layer corresponding with described channel region.
10, according to Claim 8 or the manufacture method of 9 described semiconductor devices, it is characterized in that, form in the operation at described resist layer, the thickness of resist layer that will be corresponding with described source low concentration region and described leakage side low concentration region forms 50～200 nanometers.
11, according to Claim 8 the manufacture method of any one described semiconductor device～10,
It is characterized in that, wherein in described low concentration impurity district formation operation, comprise:
With described resist layer as mask with described semiconductor film be etched into decided the operation of pattern; With
The resist layer of part that will be corresponding with described source high concentration region, described leakage side high concentration region, described source low concentration region and described leakage side low concentration region exposes, inject described low concentration impurity to described semiconductor film, form the operation of described source low concentration region and described leakage side low concentration region.
12, a kind of manufacture method of semiconductor device, it is the semiconductor layer that has source high concentration region, leakage side high concentration region, source low concentration region, leaks side low concentration region and channel region, with by described semiconductor layer relative with dielectric film to the manufacture method of semiconductor device of gate electrode
It is characterized in that, comprising:
On substrate, form the operation of semiconductor film;
Will be on described semiconductor film the thickness of the resist layer corresponding with described source high concentration region, described leakage side high concentration region, described source low concentration region and described leakage side low concentration region, form the thin operation of thickness than the described resist layer of described channel region correspondence;
Thin part by described resist layer is injected low concentration impurity to described semiconductor film, forms the operation of described source low concentration region and described leakage side low concentration region;
With described resist layer as mask with described semiconductor film be etched into decided the operation of pattern;
Remove described resist layer from described semiconductor film, on described semiconductor film, form the operation of gate insulating film;
On position corresponding on the described gate insulating film, form the operation of described gate electrode with described source low concentration region, described leakage side low concentration region and described channel region; With
As mask, inject the high concentration impurities higher with described gate electrode, form the operation of described source high concentration region and described leakage side high concentration region than described low concentration impurity to described semiconductor film;
In described etching work procedure, will in the described semiconductor film below having formed the described resist layer of thick thickness, inject the extrinsic region of described low concentration impurity and the described semiconductor film of the extrinsic region that extends along the raceway groove parallel longitudinal of described channel region is removed.
13, a kind of semiconductor device, it is the semiconductor device of making by the manufacture method of the described semiconductor device of claim 12, it is characterized in that, the width of wherein said source high concentration region and described leakage side high concentration region is made as below the width of described source low concentration region and described leakage side low concentration region.
14, a kind of manufacture method of semiconductor device, it is the semiconductor layer that has source high concentration region, leakage side high concentration region, source low concentration region, leaks side low concentration region and channel region, with by described semiconductor layer relative with dielectric film to the manufacture method of semiconductor device of gate electrode
It is characterized in that, comprising:
On substrate, form the operation of described semiconductor film;
On described semiconductor film, make resist layer form to such an extent that smooth, the two ends of middle body become the operation of conical section;
Conical section by described resist layer injects high concentration impurities to described semiconductor film, forms the operation of concentration gradient district and described channel region on described semiconductor film;
With described resist layer as mask with described semiconductor film be etched into decided the operation of pattern;
Remove described resist layer from described semiconductor film, on described semiconductor film, form the operation of gate insulating film;
On the described gate insulating film with described channel region or with a part of corresponding position in described channel region and described concentration gradient zone on form the operation of described gate electrode.
15, the manufacture method of semiconductor device according to claim 14, it is characterized in that, forming on the same substrate: the semiconductor device that forms described gate electrode on the described gate insulating film position corresponding with described channel region and with the corresponding position of at least a portion in described channel region and described concentration gradient zone on form the semiconductor device of gate electrode.
16, the manufacture method of semiconductor device according to claim 14, it is characterized in that, on same substrate, form: the described resist layer of, two ends cone smooth and the semiconductor device that forms and form thinly described resist layer and the semiconductor device that forms with the thickness of impurity injection zone with middle body.
17, a kind of manufacture method of semiconductor device, it is the semiconductor layer that has source high concentration region, leakage side high concentration region, source low concentration region, leaks side low concentration region and channel region, with by described semiconductor layer relative with dielectric film to the manufacture method of semiconductor device of gate electrode
It is characterized in that, comprising:
On substrate, form the operation of described semiconductor film;
Make on described semiconductor film that resist layer forms that middle body is smooth, Film Thickness Ratio described flat in end is thin, between described flat and described two end portions that thickness approaches, become the operation of cone shape;
With described resist layer as mask with described semiconductor film be etched into decided the operation of pattern; Inject high concentration impurities by described resist layer to described semiconductor film, on described semiconductor film, form the operation in described channel region, described high concentration injection zone and described concentration gradient zone;
Remove described resist tunic from described semiconductor film, on described semiconductor film, form the operation of gate insulating film;
On the described gate insulating film with described channel region or with a part of corresponding position in described channel region and described concentration gradient zone on form the operation of described gate electrode.
18, the manufacture method of semiconductor device according to claim 17, it is characterized in that, forming on the same substrate: the semiconductor device that forms described gate electrode on the position corresponding on the described gate insulating film with described channel region and with the corresponding position of the part in described channel region and described concentration gradient zone on the semiconductor device of formation gate electrode.
19, the manufacture method of semiconductor device according to claim 17, it is characterized in that, on same substrate, form: adopt make described resist layer form be equivalent to described channel region part central authorities be flat, and thickness attenuation ground forms the operation of described resist layer in as the end of described high concentration injection zone; And employing forms to such an extent that the described concentration gradient zone between the thin described end of described flat and thickness becomes the described resist layer of cone shape and the semiconductor device that forms; The semiconductor device that forms thinly described resist layer with the thickness that adopts the impurity injection zone and form.
20, a kind of manufacture method of semiconductor device, it is the semiconductor layer that has source high concentration region, leakage side high concentration region, source low concentration region, leaks side low concentration region and channel region, with by described semiconductor layer relative with dielectric film to the manufacture method of semiconductor device of gate electrode
It is characterized in that, comprising:
On substrate, form the operation of semiconductor film;
Form in the zone at described first semiconductor device, will be on described semiconductor film the thickness of the described resist layer corresponding with described source area with high mercury and described leakage side area with high mercury, form the operation of the formation described resist layer thinner than the thickness of the described resist layer corresponding with described channel region, described source low concentration region and described leakage side low concentration region;
Form in the zone at described second semiconductor device, the thickness of described resist layer that will be corresponding with described source area with high mercury, described leakage side area with high mercury, described source low concentration region and described leakage side low concentration region, form thinlyyer, and form the operation of the described resist layer of formation that the thickness of the described resist layer corresponding with described source area with high mercury and described leakage side area with high mercury in the zone thickens than described first semiconductor device than the thickness of the described resist layer corresponding with described channel region;
Form each described semiconductor film in zone as described first and second semiconductor devices of mask etching with described resist layer, inject high concentration impurities to described semiconductor film simultaneously, form the zone at described first semiconductor device and form described source area with high mercury and described leakage side area with high mercury, form the operation that the zone forms described source low concentration region, described leakage side low concentration region and described channel region at described second semiconductor device;
Remove the described resist layer that forms zone formation respectively at described first and second semiconductor devices from described semiconductor film, on described semiconductor film, form the operation of gate insulating film;
Form in the zone at described first semiconductor device, on position corresponding on the described gate insulating film, form the operation of described gate electrode with described channel region;
Form in the zone at described second semiconductor device, on position corresponding on the described gate insulating film, form the operation of described gate electrode with described channel region, source low concentration region and leakage side low concentration region;
Form zone described gate electrode separately as mask with described first and second semiconductor devices, the implantation concentration low concentration impurity lower than described high concentration impurities on described semiconductor film forms the operation that the zone forms described source low concentration region and described leakage side low concentration region at described first semiconductor device; With
With resist layer described first semiconductor device is formed the zone covers comprehensively, form in the regional described semiconductor film to described second semiconductor device simultaneously and inject high concentration impurities, form the operation of described source area with high mercury and described leakage side area with high mercury.
21, a kind of manufacture method of semiconductor device, it is the semiconductor layer that has source high concentration region, leakage side high concentration region, source low concentration region, leaks side low concentration region and channel region, with by described semiconductor layer relative with dielectric film to the manufacture method of semiconductor device of gate electrode
It is characterized in that, comprising:
On substrate, form the operation of semiconductor film;
The thickness of will be on described semiconductor film corresponding with described source zone and territory, described leakage lateral areas resist layer forms the thin operation of thickness than the described resist layer corresponding with described channel region;
With described resist layer as mask with described semiconductor film be etched into decided the operation of pattern;
With described resist layer as mask to described semiconductor film implanted dopant, form the operation in described source zone and territory, described leakage lateral areas;
Remove described resist layer from described semiconductor film, on described semiconductor film, form the operation of gate insulating film; With
On described gate insulating film, form the operation of described gate electrode.
22, a kind of semiconductor device is that the manufacture method of semiconductor device according to claim 21 is made.
23, a kind of electro-optical device is characterized in that, wherein possesses the described semiconductor device of claim 22.
CNB2005100825378A 2004-07-12 2005-07-07 Semiconductor device, method of manufacturing the same, and electro-optical device Active CN100470736C (en)

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Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102088030B (en) * 2009-12-04 2012-10-10 无锡华润上华半导体有限公司 Laterally double-diffused metal oxide semiconductor field effect transistor and manufacturing method thereof
CN102881571A (en) * 2012-09-28 2013-01-16 京东方科技集团股份有限公司 Active layer ion implantation method and active layer ion implantation method for thin-film transistor
WO2015014070A1 (en) * 2013-07-31 2015-02-05 京东方科技集团股份有限公司 Array substrate and manufacturing method therefor, and display device

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102088030B (en) * 2009-12-04 2012-10-10 无锡华润上华半导体有限公司 Laterally double-diffused metal oxide semiconductor field effect transistor and manufacturing method thereof
CN102881571A (en) * 2012-09-28 2013-01-16 京东方科技集团股份有限公司 Active layer ion implantation method and active layer ion implantation method for thin-film transistor
US9230811B2 (en) 2012-09-28 2016-01-05 Boe Technology Group Co., Ltd. Active layer ion implantation method and active layer ion implantation method for thin-film transistor
WO2015014070A1 (en) * 2013-07-31 2015-02-05 京东方科技集团股份有限公司 Array substrate and manufacturing method therefor, and display device
US9496294B2 (en) 2013-07-31 2016-11-15 Boe Technology Group Co., Ltd. Array substrate, manufacturing method and display device

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