CN1722122A - Bus structure and its data transmitting method - Google Patents
Bus structure and its data transmitting method Download PDFInfo
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- CN1722122A CN1722122A CN 200410069670 CN200410069670A CN1722122A CN 1722122 A CN1722122 A CN 1722122A CN 200410069670 CN200410069670 CN 200410069670 CN 200410069670 A CN200410069670 A CN 200410069670A CN 1722122 A CN1722122 A CN 1722122A
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Abstract
The invention relates to a bus structure and data transmitting method, which is used in signal transmitting environment of information system's each function component. It uses at least one wire to transmit data and/ or address and / or control signal by serial transmitting mode between two function components. The bus system will execute the changing movement of parallel signal and serial signal (that is to say the movement of changing parallel signal to serial signal, and changing serial signal to parallel signal).
Description
Technical field
The invention relates to a kind of signal transmission technology, particularly about bus structure and data transmission method thereof, be applied in the signal delivery context between contained each functional module of infosystem, between any two functional modules, with one or more lead at least with serial transmission mode Data transmission, address and control signal; When these bus structure are carried out the data transmission method flow process, be used for carrying out switching motion each other,, then need to decide according to actual conditions as for the sequencing of this switching motion at parallel signal and serial signal.
Background technology
For infosystem (as computing machine), its each functional module that assembles is (as each contained unit of infosystem, element, assembly, device) between, with signal being sent to somewhere another when place by infosystem inside, the connecting path of process promptly be called bus, with regard to prior art, bus is one group of parallel wire, its each unit of link information system, be the communication path between the unit, carry data is sent to another unit by a unit, and these unit comprise each processor in the system, each internal memory, input-output system and peripheral unit.
Bus can make the system synergistic working of a complexity, bus comprises local bus and system bus, local (local) bus connects an internal memory and I/O device to a specific processor, makes the frequency range between processor and internal memory be able to effective utilization, so relevant with the structure of processor.System (global) bus then connects limited processor, serves as the examination foundation with the maximum efficiency between subsystem, and a system bus often has harmony messages or transmission method, makes between the contained different processor of internal system and is able to mutual swap data.
For the personal information system, bus can roughly be divided into three types in title and design: 1. data bus (Data Bus): data bus is used for connection processing device (CPU), the electronics path of other hardware unit on internal memory and the motherboard, it is one group of parallel lead, the number of data line then has influence on the transmission speed of data between hardware, generally speaking, data bus can be 8 leads, once transmit 8 bits, or be 16 leads, once transmit 16 bits, because processor development of technology, the quantity that the contained chip of processor once can receive and transmit data also increases thereupon, at this moment, will be provided with impact damper between processor and internal memory or processor and I/O device comes control data to flow to and flow.2. address bus (Address Bus): address bus is one group of data line similar to data bus, is used for transmitting memory address.3. control bus (Control Bus): transmit control signal, real internal memory or the I/O device directly controlled of control bus.
Among the existing personal information system, no matter data bus, address bus or control bus are one group of wire type, for example, are 8 or 16; And the control signal transmission mode of the address date transmission mode of the data transfer mode of data bus, address bus or control bus is the parallel data transmission.Because the processor development of technology, converge the transmission situation of the data between other hardware unit, address, control signal on whole processor and the motherboard so often need add upper bumper; Yet, along with functional processor increases, under the situation that number of pins can not infinitely increase, should how pin be done best utilization, all be the problem that is worth thinking.Moreover with regard to some angle, serial data transmission can reach quite high message transmission rate, for example, can reach more than the per second 1.5G position.
So, consider as a kind of new thinking angle how, could be between any two contained functional modules of infosystem, and need not to add upper bumper on processor and internal memory, the motherboard when data between other hardware unit, address, control signal transmission, whether the parallel transmission of data bus, address bus or control bus is necessary, and when the functional processor increase, and under the not enough situation of using of pin, whether can reduce the number of pins of data bus, address bus and the control bus of processor, be existing bus structure problems to be solved.
Summary of the invention
For overcoming the shortcoming of above-mentioned prior art, fundamental purpose of the present invention is to provide a kind of bus structure and data transmission method thereof, be applied in the signal delivery context between each functional module such as the contained unit of infosystem, element, assembly, device, between any two contained functional modules of infosystem, with one or more lead at least with serial transmission mode Data transmission, address and/or control signal.
Another purpose of the present invention is to provide a kind of bus structure and data transmission method thereof, bus structure of the present invention are when carrying out the data transmission method flow process, execution is converted to the action of serial signal and the action that serial signal is converted to parallel signal with parallel signal, as for the sequencing of these two actions or only need carry out single action the time, then decide according to the actual requirements.
A further object of the present invention is to provide a kind of bus structure and data transmission method thereof, and it can reduce the number of pins of data bus, address bus and the control bus of processor.
According to above-described purpose, the invention provides a kind of bus structure and data transmission method thereof of novelty.Bus structure of the present invention comprise at least parallel/serial conversion module and serial modular converter.
This data transmission method comprises following program: will be at least parallel signal on one or more the lead be converted to serial signal, and this serial signal is exported.
This data transmission method also can comprise following program: parallel/serial signal modular converter will come from parallel signal on the lead at least one or more and convert serial signal to and export.
This data transmission method also can comprise following program: parallel/serial signal modular converter will come from least one parallel signal with upper conductor and convert serial signal and output to, and at this, this serial signal exports the serial signal conversion module to.
This data transmission method can comprise following program again: parallel data signal and parallel address conversion of signals that parallel/serial signal modular converter will import at least on one or more the lead are serial data signal and serial address signal, and this serial data signal and this serial address signal are exported.
This data transmission method also can comprise following program: parallel data signal and parallel control conversion of signals that parallel/serial signal modular converter will import at least on one or more the lead are serial data signal and serial control signal, and this serial data signal and this serial control signal are exported.
These bus structure comprise: parallel/the serial signal modular converter, should comprise parallel signal input end and serial signal output terminal by parallel/serial signal modular converter, this parallel signal input end comes from least one with the parallel signal on the upper conductor with input, should parallel/serial signal modular converter convert the parallel signal of input to serial signal, and the serial signal after will change via this serial signal output terminal is exported.
Bus structure are when carrying out the data transmission method flow process, be used to carry out switching motion that parallel signal is converted to serial signal and serial signal is converted to parallel signal, as for the sequencing of this switching motion or only need carry out single action the time, then decide according to the actual requirements.When bus structure are converted to serial signal with parallel signal, parallel signal on parallel/the data at least one or more, address or control signal wire that the serial conversion module will import converts serial signal to and also exports, otherwise single one data that then will import or the serial signal on address or the control signal wire convert parallel signal and output to.
As for contained parallel/serial conversion module and the serial modular converter of bus structure of the present invention, can be when infosystem be made in which, also or with the form of additional circuit combine with infosystem unit, element, assembly, device.
Description of drawings
Fig. 1 is a system block diagrams, the square module map of basic organizational structure of display application bus-structured system of the present invention;
Fig. 2 is a workflow diagram, and the bus structure of display application in Fig. 1 are to carry out the process program of bus method;
Fig. 3 is a workflow diagram, and the bus structure of display application in Fig. 1 are to carry out another process program of bus method;
Fig. 4 is a workflow diagram, and the bus structure of display application in Fig. 1 are to carry out a flow process program again of bus method;
Fig. 5 is a workflow diagram, and the bus structure of display application in Fig. 1 are to carry out a flow process program again of bus method;
Fig. 6 is a workflow diagram, and the bus structure of display application in Fig. 1 are to carry out a flow process program again of bus method;
Fig. 7 is a workflow diagram, and the bus structure of display application in Fig. 1 are to carry out a flow process program again of bus method;
Fig. 8 is a calcspar, the basic structure of the embodiment of the bus-structured parallel/serial signal modular converter in the key diagram 1;
Fig. 9 is a calcspar, the basic structure of the embodiment of the bus-structured serial signal conversion module in the key diagram 1;
Figure 10 is a calcspar, the basic structure of the digital circuit in the key diagram 9;
Figure 11 is a synoptic diagram, and the cycle of the CLK1 to CLK7 among Figure 10 is described;
Figure 12 is a calcspar, the basic structure of another embodiment of the bus-structured parallel/serial signal modular converter in the key diagram 1;
Figure 13 is a synoptic diagram, and the variation situation of CKL, loaded in parallel PL signal, each wave form varies situation of exporting of JK flip-flop are described;
Figure 14 is a calcspar, the basic structure of another embodiment of the bus-structured serial signal conversion module in the key diagram 1;
Figure 15 is a synoptic diagram, and the sequential in the serial signal conversion module among Figure 14 is described;
Figure 16 is a calcspar, the basic structure of the another embodiment of the bus-structured parallel/serial signal modular converter in the key diagram 1;
Figure 17 is a calcspar, and the basic structure of the digital circuit among Figure 16 is described;
Figure 18 is a synoptic diagram, the structure calcspar of display application bus-structured embodiment of the present invention;
Figure 19 is a workflow diagram, and the bus structure of display application in Figure 18 are to carry out the process program of bus method;
Figure 20 is a synoptic diagram, the structure calcspar of display application bus-structured another embodiment of the present invention; And
Figure 21 is a workflow diagram, and the bus structure of display application in Figure 20 are to carry out the process program of bus method.
Embodiment
Embodiment
Below be conjunction with figs., describe the embodiment of bus structure of the present invention and data transmission method thereof in detail.
Fig. 1 is a system block diagrams, the block schematic diagram of display application bus-structured infosystem of the present invention elementary organization.As shown in Figure 1, bus structure 1 comprise parallel/serial signal modular converter 2, and serial signal conversion module 3.Parallel/serial signal modular converter 2 comprises parallel signal input end 21 and serial signal output terminal 22.3 of serial signal conversion module comprise serial signal input end 31 and parallel signal output terminal 32.Can directly be connected with parallel signal output terminal 32 via parallel signal input end 21 between parallel/serial signal modular converter 2 and the serial signal conversion module 3, and/or directly be connected with serial signal input end 31 via serial signal output terminal 22; And/or do connection with one or more lead at least, at this, this lead is data line, address wire and/or control signal wire.
When bus structure 1 are converted to serial signal with parallel signal, be will be at least parallel signal on one or more data, address or the control signal wire be input to parallel signal input end 21, parallel/serial signal modular converter 2 converts the parallel signal of input to serial signal, and the output of the serial signal after will changing via serial signal output terminal 22, the serial signal of this output can send infosystem (figure is mark not) to via data line, address wire or a control signal wire, or sends serial signal input end 31 to; At this, the parallel input signal on the data more than at least one, address or the control signal wire of parallel/serial signal modular converter 2 can be by infosystem, or by the parallel signal output terminal 32 of serial signal conversion module 3.
When bus structure 1 are converted to parallel signal with serial signal, the serial signal input end 31 of serial signal conversion module 3 will be imported a serial signal on data, address or the control signal wire, serial signal conversion module 3 converts the serial signal of input to parallel signal, and the output of the parallel signal after will changing via parallel signal output terminal 32, the parallel signal of this output can send infosystem to or send the parallel signal input end 21 of parallel/serial signal modular converter 2 to via the data more than at least one, address or control signal wire; At this, the serial input signals on single data, address or the control signal wire of serial signal conversion module 3 can be by the infosystem unit, or by the serial signal output terminal 22 of parallel/serial signal modular converter 2.
As for parallel/serial conversion module 2 and/or serial modular converter 3 of bus structure 1, can be when the contained functional module of infosystem be made in which, or combine with infosystem with the form of additional circuit.These functional modules can be, for example, and central processor CPU, microprocessor MCU, e-book card controller, display controller, display surface (all figure mark).
Fig. 2 is a workflow diagram, and the bus structure of display application in Fig. 1 are with the program of the method for carrying out data transmission.At this, bus structure 1 are that parallel signal is converted to serial signal.As shown in Figure 2, in step 11, the parallel signal input end 21 of parallel/serial signal modular converter 2 will be imported at least the parallel signal on one or more data, address or the control signal wire, parallel/serial signal modular converter 2 converts the parallel signal of input to serial signal, at this, parallel input signal on data more than at least one, address or the control signal wire of parallel/serial signal modular converter 2 can be by the contained functional module of infosystem, or by the parallel signal output terminal 32 of serial signal conversion module 3, and proceed to step 12.
In step 12, the serial signal after the serial signal output terminal 22 output conversions of parallel/serial signal modular converter 2, and send infosystem to via at least one data, address or control signal wire.
Fig. 3 is a workflow diagram, and the bus structure 1 of display application in Fig. 1 are to carry out another flow process of data transmission method.At this, bus structure 1 are used for parallel signal is converted to serial signal.As shown in Figure 3, in step 41, make the parallel signal input end 21 input parallel signal on one or more data, address or the control signal wire at least, parallel/serial signal modular converter 2 converts the parallel signal of input to serial signal, at this, parallel input signal on data more than at least one, address or the control signal wire of parallel/serial signal modular converter 2 can be by contained each functional module of infosystem, or by the parallel signal output terminal 32 of serial signal conversion module 3, subsequently and proceed to step 42.
In step 42, from the serial signal that the serial signal output terminal 22 of parallel/serial signal modular converter 2 is exported after changing, the serial signal of this output can send the serial signal input end 31 of serial signal conversion module 3 via data, address or a control signal wire to.
Fig. 4 is a workflow diagram, and the bus structure 1 of display application in Fig. 1 are to carry out a flow process program again of data transmission method.At this, bus structure 1 are used for serial signal is converted to parallel signal.As shown in the figure, in step 51, the serial signal input end 31 of serial signal conversion module 3 will be imported the serial signal on single data, address or the control signal wire, serial signal conversion module 3 converts the serial signal of input to parallel signal, at this, serial input signals on data, address or the control signal wire of serial signal conversion module 3 can be by the functional module of infosystem, or by the serial signal output terminal 22 of parallel/serial signal modular converter 2, and enter step 52.
In step 52, parallel signal output after will changing from the parallel signal output terminal 32 of serial signal conversion module 3, the parallel signal of this output can send the contained functional module of infosystem to via the data more than at least one, address or control signal wire.
Fig. 5 is a workflow diagram, and the bus structure 1 of display application in Fig. 1 are carried out the another program of data transmission method.At this, bus structure 1 are used for serial signal is converted to parallel signal.As shown in the figure, in step 61, the serial signal input end 31 of serial signal conversion module 3 will be imported the serial signal on single data, address or the control signal wire, serial signal conversion module 3 converts the serial signal of input to parallel signal, at this, serial input signals on single data, address or the control signal wire of serial signal conversion module 3 can be by the contained functional module of infosystem, or by the serial signal output terminal 22 of parallel/serial signal modular converter 2, and enter step 62.
In step 62, parallel signal output after will changing from the parallel signal output terminal 32 of serial signal conversion module 3, the parallel signal of this output can send the parallel signal input end 21 of parallel/serial signal modular converter 2 via the data more than at least one or address or control signal wire to.
Fig. 6 is a workflow diagram, and the bus structure of display application in Fig. 1 are to carry out a flow process program again of bus method.At this, bus structure 1 are carried out action that parallel signal is converted to serial signal and serial signal is converted to parallel signal.
As shown in Figure 6, at first, in step 71, the parallel signal input end 21 of parallel/serial signal modular converter 2 will be imported at least the parallel signal on one or more data, address or the control signal wire, parallel/serial signal modular converter 2 converts the parallel signal of input to serial signal, and the output of the serial signal after will changing via serial signal output terminal 22, the serial signal of this output can send the serial signal input end 31 of serial signal conversion module 3 via data, address or a control signal wire to; At this, the data more than at least one or the parallel input signal on address or the control signal wire of parallel/serial signal modular converter 2 can be by the contained functional modules of infosystem, or, and enter step 72 by the parallel signal output terminal 32 of serial signal conversion module 3.
In step 72, the serial signal input end 31 of serial signal conversion module 3 will be imported single data, serial signal on address or the control signal wire, this serial signal is from the serial signal output terminal 22 of parallel/serial signal modular converter 2, serial signal conversion module 3 converts the serial signal of input to parallel signal, and the output of the parallel signal after will changing via parallel signal output terminal 32, the parallel signal of this output can be via the data more than at least one, address or control signal wire and send each contained functional module of infosystem to, or send the parallel signal input end 21 of parallel/serial signal modular converter 2 to.
Fig. 7 is a workflow diagram, and the bus structure 1 of display application in Fig. 1 are to carry out a flow process program again of bus method.At this, bus structure 1 will be carried out action that serial signal and parallel signal are changed mutually.
As shown in Figure 7, at first in step 81, the serial signal input end 31 of serial signal conversion module 3, with the serial signal on the single data of input or address or the control signal wire, serial signal conversion module 3 converts the serial signal of input to parallel signal, and the output of the parallel signal after will changing via parallel signal output terminal 32, the parallel signal of this output can send the parallel signal input end 21 of parallel/serial signal modular converter 2 via the data more than at least one, address or control signal wire to; At this, the single data or the serial input signals on address or the control signal wire of serial signal conversion module 3 can be by each contained functional modules of infosystem, or by the serial signal output terminal 22 of parallel/serial signal modular converter 2, and enter step 82.
In step 82, the parallel signal input end 21 of parallel/serial signal modular converter 2 will be imported the data of one or more at least, parallel signal on address or the control signal wire, this parallel signal comes from the parallel signal output terminal 32 of serial signal conversion module 3, parallel/serial signal modular converter 2 converts the parallel signal of input to serial signal, and the output of the serial signal after will changing via serial signal output terminal 22, the serial signal of this output can be via data, address or control signal wire and send each contained functional module of infosystem to, or send the serial signal input end 31 of serial signal conversion module 3 to.
Fig. 8 is calcspar (block diagram), the basic structure of the parallel/serial signal modular converter embodiment of the bus structure 1 in the key diagram 1.At this, input signal 44 is the data mode of 8bit, and these 8bit data can be parallel data, parallel address or parallel control signal.As shown in the figure, parallel/serial signal modular converter 2 can be the type of multiplexer 4 and locking data circuit 5, this multiplexer 4 is 8 to 1 MUX type, the parallel signal input end 21 of parallel/serial signal modular converter 2 is made up of the data input pin 5F0-5F7 of locking data circuit 5, and the output terminal 5Z0-5Z7 of locking data circuit 5 then distinguishes one by one the corresponding connection of data input pin 4D0-4D7 with multiplexer 4; The serial signal output terminal 22 of parallel/serial signal modular converter 2 then is made of the output terminal 4Z of multiplexer 4, at this, multiplexer 4 still has 3 to select control line end 4C1-4C3, the control input signals of control line 4C1-4C3 will determine which the input data among the input end 4D0-4D7 to export via output terminal 4Z, locking data circuit 5 can be brought in the action that data/sense data is read in execution in decision via R/W, when locking data circuit 5 with data D0-D7 after its input end 5F0-5F7 input, can carry out the function of locking data, and the data of its output terminal 5Z0-5Z7 are locked as D0-D7 respectively, the output terminal 5Z0-5Z7 of locking data circuit 5 is then corresponding one by one respectively to be connected with the data input pin 4D0-4D7 of multiplexer 4, at this, as shown in Figure 8, be T0 the cycle length of the work period CLKA of locking data circuit 5, and be (T0/8) cycle length of the work period CLKB of multiplexer 4, just, be 8 times of cycle length of CLKB the cycle length of CLKA.
Because the data of parallel signal or address or control signal are the type of 8bit, this input signal 44 (parallel data or parallel address date) is made of D0-D7 for the data type of 8bit, so the input end 4D0-4D7 of multiplexer 4 incites somebody to action the D0-D7 of corresponding one by one input 8bit data respectively, as shown in Figure 8, at this, the 8bit data of input are data, address or control signal.This multiplexer 4 is when work, (these data can be data with the input data of input end 4D0-4D7, address or control signal) export from output terminal 4Z in order, via the control input signals of selecting control line 4C1-4C3, for example, the control input signals of input is [111], and multiplexer 4 is exported data D7 earlier via output terminal 4Z, then, for example, the control input signals of input is [110], and multiplexer 4 is exported data D6 again via output terminal 4Z, follow again, for example, the control input signals of input is [101], and multiplexer 4 is exported data D5 again via output terminal 4Z, and the rest may be inferred, at last, for example, the control input signals of input is [000], and multiplexer 4 is exported data D0 at last via output terminal 4Z, via output terminal 4Z, to export serial data 55, as shown in Figure 8, at this, the cycle of serial data 55 is T0, and serial data 55 is made up of data D0-D7.At this, though the parallel data of discussing is 8bit,, also can in like manner analogize for the data of 4bit, 16bit, 32bit or 64bit, do not repeat them here.
Fig. 9 is a calcspar, the basic structure of the embodiment of the bus-structured serial signal conversion module in the key diagram 1.At this, input signal 66 is the serial data of 8bit, at this, input signal 66 only is discussed is made of the E0-E7 signal, and this serial data can be serial data or serial address or serial control signal.As shown in Figure 9, serial signal conversion module 3 is by separating multiplexer 6 and digital circuit 7 constitutes, this separates multiplexer 6 and is the DeMUX form of 1x8, the work period of separating multiplexer 6 is CLKC, and the serial signal input end 31 of serial signal conversion module 3 is made of the data input pin 6D that separates multiplexer 6; The parallel signal output terminal 32 of serial signal conversion module 3 then is made of the output terminal 7Y0-7Y7 of digital circuit 7, at this, separating multiplexer 6 has 3 to select line end 6C1 to 6C3, the input signal of selection wire 6C1-6C3 will determine that the input data of input end 6D will be via the output of which output terminal among the output terminal 6Z0-6Z7 that separates multiplexer 6, and the output terminal 6Z0-6Z7 that separates multiplexer 6 will distinguish one by one the corresponding connection of input end 7X0-7X7 with digital circuit 7.
Because serial input signals 66 is a serial data, this serial input signals 66 (serial data or serial address or serial control signal) is made of the E0-E7 signal, will import data E0-E7 output in regular turn respectively one to one so separate the output terminal 6Z0-6Z7 of multiplexer 6; The cycle of serial input signals 66 is T3, and be (T3/8) cycle length of separating the work period CLKC of multiplexer 6; The input service cycle that digital circuit 7 is had is respectively CLK1 to CLK7, but no matter is CLK1 or CLK2-CLK7, and be T4 its cycle length, and T4=T3, and just, be 8 times of cycle length of CLKC the cycle length of CLK1-CLK7.
At this, can run into a problem, be that data E0-E7 is when output terminal 6Z0-6Z7 exports, be not to be synchronous output, and for separating multiplexer 6, also output synchronously of each output terminal 6Z0-6Z7, so, must the data E0-E7 that output terminal 6Z0-6Z7 is occurred be done synchronization process with digital circuit 7, digital circuit 7 as shown in figure 10.
Figure 10 is a calcspar, the basic structure of the digital circuit in the key diagram 9.As shown in figure 10, this digital circuit 7 can be made of D flip-flop D1-D28, the input end 7X0-7X7 of digital circuit 7 will be one by one corresponding to the output terminal 6Z0-6Z7 that separates multiplexer 6 and do connection.No matter the cycle of CLK1 to CLK7 but is CLK1 or CLK2-CLK7 then as shown in Figure 11, and be T4 its cycle length, and T4=T3, and just, be 8 times of CLKC cycle length the cycle length of CLK1-CLK7.Effect via the D flip-flop in the digital circuit 7, after data E0 is input to the input end 7X0 of digital circuit 7 via the output terminal 6Z0 that separates multiplexer 6, will be via D flip-flop D1 (the input CLK of D1 be CLK1), D flip-flop D2 (the input CLK of D2 is CLK2), D flip-flop D3 (the input CLK of D3 is CLK3), D flip-flop D4 (the input CLK of D4 is CLK4), D flip-flop D5 (the input CLK of D5 is CLK5), the effect of D flip-flop D6 (the input CLK of D6 is CLK6) and D flip-flop D7 (the input CLK of D7 is CLK7), wherein, the input D of D1 is 7X0, the input of D2 then is the output of D1, the input of D3 then is the output of D2, the input of D3 then is the output of D2, the input of D4 then is the output of D3, the input of D5 then is the output of D4, the input of D6 then is the output of D5, the input of D7 then is the output of D6, and D7 is output as the output terminal 7Y0 of digital circuit 7; Acting as of D1 to D7 flip-flop postpones the E0 signal.But according to the principle of work of the E1 to E6 of class release in like manner signal, so do not repeat them here at D8 to D28.For the E7 signal, owing to be last signal, so need not delay circuit.The output signal of the output terminal 7Y0 to 7Y7 of digital circuit 7 is the parallel output signal of the parallel signal output terminal 32 of serial signal conversion module 3.
Figure 12 is a calcspar, the basic structure of another embodiment of bus-structured walking abreast/serial signal modular converter in the key diagram 1.As shown in figure 12, input signal 55 is the data mode of parallel signal 4bit, and these 4bit data can be parallel data or parallel address or parallel control signal.As shown in figure 12, parallel/serial signal modular converter 2 can be combined by JK flip-flop A, B, C, D, NAND lock g1 to g8 and reverse brake S1-S4.The parallel signal input end 21 of parallel/serial signal modular converter 2 is made up of the input g51 of input g31, the NAND lock g5 of the g11 input of NAND lock g1, NAND lock g3 and the input g71 of NAND lock g7.The work clock of JK flip-flop A, B, C, D is same CLK.Figure 13 is, the wave form varies situation of the output QC of the output QA of the variation situation of CKL, loaded in parallel PL signal, JK flip-flop A, the output QB of JK flip-flop B, JK flip-flop C and the output QD of JK flip-flop D.
The output Q end of JK flip-flop D is the J input end of JK flip-flop C, and the output Q backward end of JK flip-flop D is the K input end of JK flip-flop C; The output Q end of JK flip-flop C is the J input end of JK flip-flop B, and the output Q backward end of JK flip-flop C is the K input end of JK flip-flop B; The output Q end of JK flip-flop B is the J input end of JK flip-flop A, and the output Q backward end of JK flip-flop B is the K input end of JK flip-flop A; The output Q end of JK flip-flop A is the serial signal output terminal 22 of parallel/serial signal modular converter 2.Offset buffer will be eliminated when the removing line CL input pulse " 1 → 0 " of each JK flip-flop A, B, C, D; The output of offset buffer will be predetermined to be 1 when preplaced line PR (PRESET) input pulse " 1 → 0 " of each JK flip-flop A, B, C, D.
When loaded in parallel PL signal is " 0 ", because loaded in parallel PL signal is the input end of NAND lock g1 to g8, so the output valve of g1-g8 is " 1 "; After loaded in parallel PL signal is by " 0 → 1 ", and input signal 55 is parallel signal [1010], then because PL=" 1 " and g11=" 1 ", g31=" 0 ", g51=" 1 ", g71=" 0 ", then the output of g1, g4, g6, g7 is all served as reasons " 1 → 0 ", and the output of g2, g3, g5, g8 then still is maintained " 1 "; Because the output of g1, g7 is by " 1 → 0 ", institute be so that JK flip-flop A, D will carry out deliberate action, and the output Q value of JK flip-flop A, D all is made as " 1 "; Because the output of g4, g6 is by " 1 → 0 ", institute removes action so that JK flip-flop B, C will carry out, and the output Q value of JK flip-flop B, C is made as " 0 ", so that the output QA=" 1 " of JK flip-flop A, the output QB=" 0 " of JK flip-flop B, the output QA=" 0 " of JK flip-flop C, the output QA=" 1 " of JK flip-flop D.
Then, when loaded in parallel PL=" 0 ", make deliberate action and remove action and can't carry out, and this moment, JK flip-flop A, B, C, D will begin to carry out the function of offset buffer along with " 1 → 0 " among the CLK of input.In the output of the 1st clock week after date JK flip-flop A by " 1 → 0 ", then in the output of the 2nd all after date JK flip-flop A by " 0 → 0 ", at the 3rd clock week after date, the output of JK flip-flop A is by " 0 → 1 ", finished output " 1 " via the QA output terminal of JK flip-flop A, " 0 ", " 0 ", the action of " 1 " serial signal.
Figure 14 is a calcspar, is used for the basic structure of another embodiment of key diagram 1 bus-structured serial signal conversion module.At this, input signal 77 is the 4bit serial data, and this serial data type can be serial data or serial address or serial control signal.As shown in figure 14, serial signal conversion module 3 can be made up of D flip-flop A1, A2, A3, A4 and AND lock h1 to h4.The serial signal input end 31 of serial signal conversion module 3 is the input end DA1 of D flip-flop A1, and parallel signal output terminal 32 is made up of the output terminal DZ0-DZ3 of lock h1 to h4, the output terminal DA1Q of D flip-flop A1 is that input and the DA1Q of h1 is connected with the input end DA2 of D flip-flop A2, the output terminal DA2Q of D flip-flop A2 is that input and the DA2Q of h2 is connected with the input end DA3 of D flip-flop A3, the output terminal DA3Q of D flip-flop A3 is that input and the DA3Q of h3 is connected with the input end DA4 of D flip-flop A4, and the output terminal DA4Q of D flip-flop A4 is h4 one input.The work clock of D flip-flop A1, A2, A3, A4 is same CLK9.
Need 4 clock pulses to be loaded in the buffer (D flip-flop A1, A2, A3, A4) with serial input signals 77 with 4bit, after the 4th pulse, in store effective 4 bit data of buffer, when exporting this 4 bit data, reading enable line RE needs in high-end trim, AND lock h1 to h4 makes the data that are stored in offset buffer utilize once all output of four parallel output terminal DZ0, DZ1, DZ2, DZ3, and just the signal data of the DA1Q-DA4Q of D flip-flop A1-A4 output terminal shows in DZ0-DZ3 output at one time.Needed four extra clock pulses are exported in serial not to be needed at this, and certainly, recycle still will exist.
Figure 15 is the sequential chart in the serial signal conversion module among Figure 14.As shown in figure 15, input signal 77 is the serial data of 4bit, at this, input signal 77 is " 1 ", " 0 ", " 0 ", " 1 ", after the clock of first CLK9 pulse, the output signal of the output terminal DA1Q of D flip-flop A1 is " 1 ", because the output terminal DA1Q of D flip-flop A1 does with the input end DA2 of D flip-flop A2 and is connected, so this signal " 1 " is as the input of the input end DA2 of D flip-flop A2.Then, after the clock pulse of the 2nd CLK9, the output signal " 1 → 0 " of the output terminal DA1Q of D flip-flop A1 is because the output terminal DA1Q of D flip-flop A1 is connected with the input end DA2 of D flip-flop A2, so this signal " 0 " is treated as the input of the input end DA2 of D flip-flop A2; And when the clock pulse of the 2nd CLK9, because the signal of the input end DA2 of D flip-flop A2 is " 1 ", so after the clock pulse of the 2nd CLK9, the signal of the output terminal DA2Q of D flip-flop A2 is " 1 "; Because the output terminal DA2Q of D flip-flop A2 is connected with the input end DA3 of D flip-flop A3, so this signal " 1 " is as the input of the input end DA3 of D flip-flop A3.In like manner the rest may be inferred, can draw after the clock pulse of the 4th CLK9, the signal of the output terminal DA1Q of D flip-flop A1 is that the signal of the output terminal DA2Q of " 1 ", D flip-flop A2 is " 1 " for the signal of the output terminal DA3Q of " 0 ", D flip-flop A3 for the signal of the output terminal DA4Q of " 0 " and D flip-flop A4, at this, D flip-flop A1-A4 act as offset buffer.
When after the clock pulse of the 4th CLK9, the signal of the output terminal DA1Q of D flip-flop A1 is " 1 ", the signal of the output terminal DA2Q of D flip-flop A2 is " 0 ", the signal of the output terminal DA3Q of D flip-flop A3 is " 0 ", this moment is after reading pulse of enable line RE input, with the output terminal DZ0-DZ3 of while at h1-h4, in DZ0 output signal " 1 ", in DZ1 output signal " 0 ", in DZ2 output signal " 0 " and in DZ3 output signal " 1 ", just, the output signal data at the DA1Q-DA4Q of D flip-flop A1-A4 output terminal shows in DZ0-DZ3 output at one time.
Figure 16 is a calcspar, the basic structure of the another embodiment of the bus-structured parallel/serial signal modular converter in the key diagram 1.At this, input signal 88 is the data type of 8bit, and this 8bit data type can be parallel data or parallel address or parallel control signal.As shown in figure 16, parallel/serial signal modular converter 2 can be combined by multiplexer 8 and digital circuit 9, this multiplexer 8 is 8 to 1 MUX type, the parallel signal input end 21 of parallel/serial signal modular converter 2 is made up of the data input pin 9D0-9D7 of digital circuit 9, and the output terminal 9D0Q-9D7Q of digital circuit 9 then distinguishes one by one the corresponding connection of data input pin 8D0-8D7 with multiplexer 8; The serial signal output terminal 22 of parallel/serial signal modular converter 2 then is made of the output terminal 8Z of multiplexer 8, at this, multiplexer 8 still has 3 to select control line end 8C1-8C3, the control input signals of control line 8C1-8C3 will determine which the input data among the input end 8D0-8D7 to export via output terminal 8Z, since the output terminal 9D0Q-9D7Q of digital circuit 9 respectively one by one with the corresponding connection of data input pin 8D0-8D7 of multiplexer 8, the output terminal 9D0Q-9D7Q of digital circuit 9 is input to data F0-F7 the data input pin 8D0-8D7 of multiplexer 8 respectively one by one.To in Figure 18, do explanation about digital circuit 9.
At this, as shown in figure 16, be T5 the cycle length of the work period CLKE of digital circuit 9, and be (T5/8) cycle length of the work period CLKF of multiplexer 8, and just, be 8 times of cycle length of CLKF the cycle length of CLKE.Because the data of parallel signal or address or control signal are the 8bit type, this input signal 88 (parallel data or parallel address or parallel control signal) is the data type of 8bit, constitute by F0-F7, so the input end 8D0-8D7 of multiplexer 8 incites somebody to action the F0-F7 of corresponding one by one input 8bit data respectively, as shown in figure 16, at this, the 8bit data of input are data or address or control signal.This multiplexer 8 is when work, input data with input end 8D0-8D7, these input data can be data or address or control signal, in order in output terminal 8Z output, via the control input signals of selecting control line 8C1-8C3, for example, the control input signals of input is [111], and multiplexer 8 is exported data F7 earlier via output terminal 8Z, then, for example, the control input signals of input is [110], and multiplexer 8 is exported data F6 again via output terminal 8Z, follow again, for example, the control input signals of input is [101], and multiplexer 8 is exported data F5 again via output terminal 8Z, and the rest may be inferred, at last, for example, the control input signals of input is [000], and multiplexer 8 is exported data F0 at last via output terminal 8Z, via output terminal 8Z, to export serial data 99, as shown in figure 16, at this, the cycle of serial data 99 is T5, and serial data 99 is made up of data F0-F7.
Figure 17 is a calcspar, and the basic structure of the digital circuit among Figure 16 is described.As shown in figure 17, this digital circuit 9 can be made of D flip-flop D91-D97, and D flip-flop D91-D97 has input end 9D0-9D7 and output terminal 9D0Q-9D7Q respectively.The parallel signal input end 21 of parallel/serial signal modular converter 2 is made up of the data input pin 9D0-9D7 of digital circuit 9; The output terminal 9D0Q-9D7Q of digital circuit 9 will distinguish one by one the corresponding connection of input end 8D0-8D7 with multiplexer 8.
The work clock pulse of D flip-flop D91-D97 is CLKE, and the work clock pulse of multiplexer 8 is CLKF.Be T5 the cycle length of the work period CLKE of digital circuit 9, and be (T5/8) cycle length of the work period CLKF of multiplexer 8, and just, be 8 times of cycle length of CLKF the cycle length of CLKE.When data F0-F7 is input to D flip-flop D91-D97 by input end D90-D97 respectively, and the clock pulse of CLKE by " 0 → 1 " after, D flip-flop D91-D97 becomes the data F0-F7 of input output signal and is presented in output terminal 9D0Q-9D7Q respectively respectively, the time that data F0-F7 is temporarily stored on the output terminal 9D0Q-9D7Q is a CLKE clock period T 5, just, in cycle length, the output signal on the output terminal 9D0Q-9D7Q of flip-flop D91-D97 can not done any change and keep ortho states at a CLKE clock pulse T5; The characteristic that output signal on this output terminal 9D0Q-9D7Q can not change in time T 5, persist on the output terminal D90Q-D97Q of D flip-flop D91-D97 as interior data F0-F7 in time T 5, and at this moment in the period T 5, data F0-F7 can offer multiplexer 8 and use.Because T5 cycle length of CLKE is 8 times of cycle length of CLKF, so in one-period time T 5, multiplexer 8 can be carried out 8 work periods, just, multiplexer 8 will be worked 8 times, and this 8 task is done 8 output respectively in regular turn with the output terminal 8Z that makes data F7 to F0 from multiplexer 8 respectively.
Figure 18 is a synoptic diagram, the structure calcspar of display application bus-structured embodiment of the present invention.As shown in Figure 18, bus structure 1 will be applied between central processing unit 25 and the e-book card controller 26.
Parallel/parallel signal the input end 21 of serial signal modular converter 2 of bus structure 1 is done with the address output interface 251 of central processing unit 25 and is connected, to receive the parallel address signal 2511 from the address output interface 251 of central processing unit 25; The parallel signal output terminal 32 of serial signal conversion module 3 will be connected with the address input interface 261 of e-book card controller 26, parallel signal 2513 be sent to the address input interface 261 of e-book card controller 26 via parallel signal output terminal 32.
Parallel/parallel signal the input end 21 of serial signal modular converter 2 comes from input the parallel address signal 2511 of the address output interface 251 of central processing unit 25, parallel/serial signal modular converter 2 will convert parallel address signal 2511 to serial signal 2512, and 2512 outputs of the serial signal after will changing via serial signal output terminal 22, the serial signal 2512 of this output can send the serial signal input end 31 of serial signal conversion module 3 via an address wire 200 to.
The serial signal input end 31 of serial signal conversion module 3 will receive from the serial signal 2512 on the single address wire 200, serial signal conversion module 3 converts the serial signal 2512 of input to parallel signal 2513, and 2513 outputs of the parallel signal after will changing via parallel signal output terminal 32, the parallel signal 2513 of this output can send the address input interface 261 of e-book card controller 26 via the address wire more than at least one 300 to.
Another of bus structure 1 be parallel/and the parallel signal input end 21 of serial signal modular converter 2 is connected with the data output interface 252 of central processing unit 25, with the data-signal 2514 of reception from the parallel data of the data output interface 252 of central processing unit 25; The parallel signal output terminal 32 of another serial signal conversion module 3 will be connected with the data-signal input interface 262 of e-book card controller 26, parallel signal 2516 be sent to the data-signal input interface 262 of e-book card controller 26 via parallel signal output terminal 32.
The parallel signal input end 21 of parallel/serial signal modular converter 2 will be imported the parallel data signal 2514 from the data output interface 252 of central processing unit 25, parallel/serial signal modular converter 2 will convert parallel data signal 2514 to serial signal 2515, and 2515 outputs of the serial signal after will changing via serial signal output terminal 22, the serial signal 2515 of this output can send the serial signal input end 31 of serial signal conversion module 3 via a data line 400 to.
The serial signal input end 31 of serial signal conversion module 3 comes from serial signal 2515 on the single data line 400 with reception, serial signal conversion module 3 converts the serial signal 2515 of input to parallel signal 2516, and 2516 outputs of the parallel signal after will changing via parallel signal output terminal 32, the parallel signal 2516 of this output can send the data-signal input interface 262 of e-book card controller 26 via the data line more than at least one 500 to.
The enforcement of parallel/serial conversion module 2 can be implemented by the circuit of choosing as shown in Fig. 8 or Figure 12 or Figure 16; And the enforcement of serial modular converter 3 can be implemented via the circuit of choosing as shown in Fig. 9 or Figure 14.
At this, the parallel/serial conversion module 2 of bus structure 1 and serial modular converter 3 combine with central processing unit 25 and e-book card controller 26 with the form of additional circuit; But, parallel/serial conversion the module 2 of bus structure 1 can be therein built-in when central processing unit 25 is made, and serial modular converter 3 also can be therein built-in when e-book card controller 26 is made, about the built-in situation of this kind, since with parallel/serial conversion module 2 and serial modular converter 3 be additional circuit form in like manner, so do not repeat them here discussion.
Figure 19 is a workflow diagram, and the bus structure of display application in Figure 18 are to carry out the process program of bus method.As shown in figure 19, at first in step 201, parallel/parallel signal the input end 21 of serial signal modular converter 2 comes from input the parallel address signal 2511 of the address output interface 251 of central processing unit 25, parallel/serial signal modular converter 2 will carry out parallel address signal 2511 is converted to the action of serial signal 2512, and 2512 outputs of the serial signal after will changing via serial signal output terminal 22, the serial signal 2512 of this output can send the serial signal input end 31 of serial signal conversion module 3 via an address wire 200 to; Another parallel/parallel signal input end 21 of serial signal modular converter 2 comes from input the parallel data signal 2514 of the data output interface 253 of central processing unit 25, parallel/serial signal modular converter 2 will convert parallel data signal 2514 to serial signal 2515, and 2515 outputs of the serial signal after will changing via serial signal output terminal 22, the serial signal 2515 of this output can send the serial signal input end 31 of another serial signal conversion module 3 via a data line 400 to, and enters step 202.
In step 202, the serial signal input end 31 of serial signal conversion module 3 will receive from the serial signal 2512 on the single address wire 200, serial signal conversion module 3 converts the serial signal 2512 of input to parallel signal 2513, and 2513 outputs of the parallel signal after will changing via parallel signal output terminal 32, the parallel signal 2513 of this output can send the address input interface 261 of e-book card controller 26 via the address wire more than at least one 300 to; The serial signal input end 31 of serial signal conversion module 3 will receive from the serial signal 2515 on the single data line 400, serial signal conversion module 3 converts the serial signal 2515 of input to parallel signal 2516, and 2516 outputs of the parallel signal after will changing via parallel signal output terminal 32, the parallel signal 2516 of this output can send the data-signal input interface 262 of e-book card controller 26 via the data line more than at least one 500 to.
Figure 20 is a synoptic diagram, the structure calcspar of display application bus-structured another embodiment of the present invention.As shown in figure 20, bus structure 1 will be applied between display controller 27 and the display panel 28.
Parallel/parallel signal the input end 21 of serial signal modular converter 2 of bus structure 1 is connected with the control signal output interface 271 of display controller 27, to receive the parallel control signal 2517 from the control signal output interface 271 of display controller 27; The parallel signal output terminal 32 of serial signal conversion module 3 will be connected with the control signal input interface 281 of display panel 28, parallel signal 2519 be sent to the control signal input interface 281 of display panel 28 via parallel signal output terminal 32.
The parallel signal input end 21 of parallel/serial signal modular converter 2 will be imported the parallel control signal 2517 from the control signal output interface 271 of display controller 27, parallel/serial signal modular converter 2 will carry out parallel control signal 2517 is converted to the action of serial signal 2518, and 2518 outputs of the serial signal after will changing via serial signal output terminal 22, the serial signal 2518 of this output can send the serial signal input end 31 of serial signal conversion module 3 via a control signal wire 600 to.
The serial signal input end 31 of serial signal conversion module 3 will receive from the serial signal 2518 on the single control signal wire 600, serial signal conversion module 3 converts the serial signal 2518 of input to parallel signal 2519, and 2519 outputs of the parallel signal after will changing via parallel signal output terminal 32, the parallel signal 2519 of this output can send the control signal input interface 281 of display panel 28 via the control signal wire more than at least one 700 to.
Another of bus structure 1 be parallel/and the parallel signal input end 21 of serial signal modular converter 2 is connected with the data output interface 273 of display controller 27, with the data-signal 2611 of reception from the parallel data of the data output interface 273 of display controller 27; The parallel signal output terminal 32 of another serial signal conversion module 3 will be connected with the data-signal input interface 282 of display panel 28, parallel signal 2613 be sent to the data-signal input interface 282 of display panel 28 via parallel signal output terminal 32.
The parallel signal input end 21 of parallel/serial signal modular converter 2 will be imported the parallel data signal 2611 from the data output interface 273 of display controller 27, parallel/serial signal modular converter 2 will carry out parallel data signal 2611 is converted to the action of serial signal 2612, and 2612 outputs of the serial signal after will changing via serial signal output terminal 22, the serial signal 2612 of this output can send the serial signal input end 31 of serial signal conversion module 3 via a data line 800 to.
The serial signal input end 31 of serial signal conversion module 3 will receive from the serial signal 2612 on the single data line 800, serial signal conversion module 3 converts the serial signal 2612 of input to parallel signal 2613, and 2613 outputs of the parallel signal after will changing via parallel signal output terminal 32, the parallel signal 2613 of this output can send the data-signal input interface 282 of display panel 28 via the data line more than at least one 900 to.
The enforcement of parallel/serial conversion module 2 can be implemented via the circuit of choosing as shown in Fig. 8 or Figure 12 or Figure 16; And the enforcement of serial modular converter 3 can be implemented via the circuit of choosing as shown in Fig. 9 or Figure 14.
At this, the parallel/serial conversion module 2 of bus structure 1 and serial modular converter 3 are done with display controller 27 and display panel 28 with the form of additional circuit and are combined; But, parallel/serial conversion the module 2 of bus structure 1 can be therein built-in when display controller 27 is made, and serial modular converter 3 also can be therein built-in during fabrication at display panel 28, about the built-in situation of this kind, since with parallel/serial conversion module 2 and serial modular converter 3 be additional circuit form in like manner, so do not repeat them here discussion.
Figure 21 is a workflow diagram, and the bus structure of display application in Figure 20 are to carry out the process program of bus method.As shown in Figure 21, at first in step 401, parallel/parallel signal the input end 21 of serial signal modular converter 2 comes from input the parallel control signal 2517 of the control signal output interface 271 of display controller 27, parallel/serial signal modular converter 2 will carry out parallel control signal 2517 is converted to the action of serial signal 2518, and 2518 outputs of the serial signal after will changing via serial signal output terminal 22, the serial signal 2518 of this output can send the serial signal input end 31 of serial signal conversion module 3 via a control signal wire 600 to; The parallel signal input end 21 of parallel/serial signal modular converter 2 will be imported the parallel data signal 2611 from the data output interface 273 of display controller 27, parallel/serial signal modular converter 2 will carry out parallel data signal 2611 is converted to the action of serial signal 2612, and 2612 outputs of the serial signal after will changing via serial signal output terminal 22, the serial signal 2612 of this output can send the serial signal input end 31 of serial signal conversion module 3 via a data line 800 to, and enters step 402.
In step 402, the serial signal input end 31 of serial signal conversion module 3 will receive from the serial signal 2518 on the single control signal wire 600, serial signal conversion module 3 converts the serial signal 2518 of input to parallel signal 2519, and 2519 outputs of the parallel signal after will changing via parallel signal output terminal 32, the parallel signal 2519 of this output can send the control signal input interface 281 of display panel 28 via the control signal wire more than at least one 700 to; Another serial signal input end 31 of serial signal conversion module 3 will receive from the serial signal 2612 on the single data line 800, serial signal conversion module 3 converts the serial signal 2612 of input to parallel signal 2613, and 2613 outputs of the parallel signal after will changing via parallel signal output terminal 32, the parallel signal 2613 of this output can send the data-signal input interface 282 of display panel 28 via the data line more than at least one 900 to.
Comprehensive above embodiment, we can obtain bus structure of the present invention and data transmission method thereof, it is applied in the signal delivery context between infosystem unit, element, assembly, the device, between any two infosystem unit, element, assembly, device, come Data transmission and/or address and/or control signal with the serial transmission mode with one or more lead at least; These bus structure are when carrying out the bus method flow process, with carrying out parallel signal is converted to the action of serial signal and the action that serial signal is converted to parallel signal, as for sequencing of these two actions or only need carry out single action the time, then decide according to the actual requirements.The advantage of bus structure of the present invention and method is as follows:
1. bus structure and data transmission method thereof are provided, it is applied in the signal delivery context between infosystem unit, element, assembly, the device, between any two infosystem unit, element, assembly, device, come Data transmission and/or address and/or control signal with one or more lead at least with the serial transmission mode, carry out the transmission of data or address in the serial transmission mode.
2. can reduce the number of pins of the data bus and the address bus of processor.
Claims (20)
1. the data transmission method of a bus is applied in the signal delivery context between infosystem unit, element, assembly, the device, it is characterized in that this data transmission method comprises following program:
At least the parallel signal on one or more the lead is converted to serial signal, and this serial signal is exported.
2. data transmission method as claimed in claim 1 is characterized in that, this data transmission method also comprises following program:
Serial signal on the lead is converted to parallel signal, and with this parallel signal output.
3. the data transmission method of a bus is applied in the signal delivery context between infosystem unit, element, assembly, the device, it is characterized in that this data transmission method comprises following program:
Parallel/serial signal modular converter will come from parallel signal on the lead at least one or more and convert serial signal to and export.
4. data transmission method as claimed in claim 3 is characterized in that this data transmission method also comprises following program;
The serial signal of parallel/serial signal modular converter output that the serial signal conversion module will come from is converted to parallel signal and output.
5. the data transmission method of a bus is applied in the signal delivery context between infosystem unit, element, assembly, the device, it is characterized in that this data transmission method comprises following program:
Parallel/serial signal modular converter will come from least one parallel signal with upper conductor and convert serial signal and output to, and at this, this serial signal exports the serial signal conversion module to.
6. data transmission method as claimed in claim 5 is characterized in that, this data transmission method also comprises following program:
The serial signal of parallel/serial signal modular converter output that the serial signal conversion module will come from converts parallel signal and output to.
7. as claim 1 or 2 or 3 or 4 or 5 or 6 described data transmission methods, it is characterized in that the lead in this method more than at least one is for transmitting the data line of data.
8. as claim 1 or 2 or 3 or 4 or 5 or 6 described data transmission methods, it is characterized in that the lead in this method more than at least one is the address wire of transfer address.
9. as claim 1 or 2 or 3 or 4 or 5 or 6 described data transmission methods, it is characterized in that the lead in this method more than at least one is for transmitting the control line of control signal.
10. the data transmission method of a bus is applied in the signal delivery context between infosystem unit, element, assembly, the device, it is characterized in that this data transmission method comprises following program:
Parallel data signal and parallel address conversion of signals that parallel/serial signal modular converter will import at least on one or more the lead are serial data signal and serial address signal, and this serial data signal and this serial address signal are exported.
11. data transmission method as claimed in claim 10 is characterized in that, this serial data signal and this serial address signal export the serial signal conversion module to, and this method also comprises following program:
The serial data signal of the serial signal conversion module will come from parallel/serial signal modular converter and this serial address conversion of signals become parallel data signal and parallel address signal and output.
12. the data transmission method of a bus is applied in the signal delivery context between infosystem unit, element, assembly, the device, it is characterized in that this data transmission method comprises following program:
Parallel data signal and parallel control conversion of signals that parallel/serial signal modular converter will import at least on one or more the lead are serial data signal and serial control signal, and this serial data signal and this serial control signal are exported.
13. data transmission method as claimed in claim 12 is characterized in that, this serial data signal and this serial control signal export the serial signal conversion module to, and this method also comprises following program:
The serial data signal of the serial signal conversion module will come from parallel/serial signal modular converter and this serial control signal convert parallel data signal and parallel control signal and output to.
14., it is characterized in that this parallel/serial signal modular converter is made up of digital circuit and multiplexer as claim 3 or 5 or 10 or 12 described data transmission methods, wherein, this digital circuit is made up of at least more than one flip-flop.
15. as claim 3 or 5 or 10 or 12 described data transmission methods, it is characterized in that, should form by digital circuit by parallel/serial signal modular converter, wherein, this digital circuit is made up of at least more than one flip-flop, at least more than one NAND lock and at least more than one reverser.
16., it is characterized in that this parallel/serial signal modular converter is made up of data interlock circuit and multiplexer as claim 3 or 5 or 10 or 12 described data transmission methods.
17., it is characterized in that this serial signal conversion module is by digital circuit and separate multiplexer and form as claim 4 or 6 or 11 or 13 described data transmission methods, wherein, this digital circuit is made up of at least more than one flip-flop.
18. as claim 4 or 6 or 11 or 13 described data transmission methods, it is characterized in that, the serial signal conversion module is made up of digital circuit, and wherein, this digital circuit is made up of at least more than one flip-flop and at least more than one AND lock.
19. bus structure are applied in the signal delivery context between infosystem unit, element, assembly, the device, it is characterized in that these bus structure comprise:
Parallel/the serial signal modular converter, should comprise parallel signal input end and serial signal output terminal by parallel/serial signal modular converter, this parallel signal input end comes from least one with the parallel signal on the upper conductor with input, should parallel/serial signal modular converter convert the parallel signal of input to serial signal, and the serial signal after will change via this serial signal output terminal is exported.
20. bus structure as claimed in claim 19 is characterized in that, these bus structure also comprise:
The serial signal conversion module, this serial signal conversion module comprises serial signal input end and parallel signal output terminal, this serial signal input end comes from serial signal on the single lead with input, this serial signal conversion module converts the serial signal of input to parallel signal, and the parallel signal after will change via this parallel signal output terminal is exported.
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| CN 200410069670 CN1722122A (en) | 2004-07-14 | 2004-07-14 | Bus structure and its data transmitting method |
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| CN 200410069670 CN1722122A (en) | 2004-07-14 | 2004-07-14 | Bus structure and its data transmitting method |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102033846A (en) * | 2010-11-25 | 2011-04-27 | 青岛海信信芯科技有限公司 | Communication interface conversion method and system, serial controller and television |
| CN102254002A (en) * | 2011-07-15 | 2011-11-23 | 苏州天准精密技术有限公司 | Data output format self-adaptive control method of measuring apparatus |
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2004
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102033846A (en) * | 2010-11-25 | 2011-04-27 | 青岛海信信芯科技有限公司 | Communication interface conversion method and system, serial controller and television |
| CN102033846B (en) * | 2010-11-25 | 2012-12-05 | 青岛海信信芯科技有限公司 | Communication interface conversion method and system, serial controller and television |
| CN102254002A (en) * | 2011-07-15 | 2011-11-23 | 苏州天准精密技术有限公司 | Data output format self-adaptive control method of measuring apparatus |
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