CN1719593A - Measurability and safety design method for information safety IC - Google Patents
Measurability and safety design method for information safety IC Download PDFInfo
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- CN1719593A CN1719593A CN 200410009319 CN200410009319A CN1719593A CN 1719593 A CN1719593 A CN 1719593A CN 200410009319 CN200410009319 CN 200410009319 CN 200410009319 A CN200410009319 A CN 200410009319A CN 1719593 A CN1719593 A CN 1719593A
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Abstract
This invention provides a method for increasing the testability and safety of information safety IC, which connects testing points needing to be observed to the detection points tested by probes by links in which, these detection points and links do not change the original logic and increase the testability of the IC, at the same time, since an attacker does not understand the circuit structure and can't analyze the concrete meaning of signals, an automatic placement wiring tool is applied to connect the observation points and detection points to form a redundant design to said IC and sets an obstacle to the reverse project of the attacker so as to increase its safety.
Description
Technical field
The invention belongs to the integrated circuit (IC) design technical field, particularly relate to the measurability and the safety Design of the integrated circuit of information security field.
Background technology
Along with developing rapidly of computer technology, the communication technology and microelectric technique, information becomes the enormous motivation that promotes social development.It has important status in non-civil areas such as the politics of country, military affairs, diplomacy, simultaneously with finance, commercial, the economic dispatch civil area is also closely related.In order to protect the safety of key message, adopting cryptographic technique is a kind of common and effective method.For speed up processing and raising fail safe, use specific information safety integrated circuit to realize that specific cryptographic algorithm is a kind of otherwise effective technique.
In very lagre scale integrated circuit (VLSIC); in order to help to carry out the analysis and the test of product; usually Testability Design support (as scan chain etc.) can be added,, when circuit breaks down, the reason of searching fault can be analyzed like this so that can the internal node of circuit be conducted interviews.The basic thought of Testability Design is controllability and the observability that improves circuit, so that the response of excitation and observation circuit is provided for circuit, but concerning the information security integrated circuit, because the method for testing that can read internal signal and state may be used to the working condition of analysis circuit inside, thereby bring the problem of fail safe aspect, therefore can not adopt.In fact, in the design of information security integrated circuit, should guarantee that the intermediate object program before entire process is finished all is inaccessible to external world, in order to avoid the assailant utilizes these information that the processing procedure of algorithm is analyzed, therefore in the information security integrated circuit, exist certain contradiction between testability and the fail safe.Present designing technique is not seen as yet to this way to solve the problem.
Summary of the invention
The present invention has overcome the testability of above-mentioned information security integrated circuit and the contradiction of fail safe, a kind of measurability and safety Design method of information security integrated circuit are provided, both can realize the testability of integrated circuit, and make the assailant be difficult to obtain concrete circuit information again.
Technology contents of the present invention: a kind of measurability of information security integrated circuit and safety Design method, its step comprises:
1, as required, determine point of observation and the design and the corresponding circuit sensing point of point of observation of test;
2, adopt automatic placement and routing's instrument to realize being connected of point of observation and sensing point;
3, when test, utilize probe and circuit sensing point to detect the relevant information of information security integrated circuit.
The line of buffer circuits driving from the sensing point to the point of observation is set.
For convenience of design process, sensing point can be arranged in the pressure point unit, as the signaling point of pressure point unit.
Technique effect of the present invention: in the physical layout of information security integrated circuit, the point of observation that needs are tested is connected on the sensing point that can survey with probe by line, realized the testability of circuit, initiate line and pressure point do not change original logic, therefore do not influence the controllability of circuit; The assailant is under the uncomprehending situation to circuit structure, the concrete implication that is difficult to analytic signal, these initiate lines are redundant lines to the circuit logic function in the domain of circuit, use the reverse engineering method to attack to the assailant and are provided with obstacle.Between the testability of information security integrated circuit and fail safe, obtained compromise preferably by this method, also very little to other Effect on Performance such as area of chip, speed, power consumptions.
Description of drawings
Below in conjunction with accompanying drawing, the present invention is made detailed description.
Fig. 1 is the measurability of information security integrated circuit of the present invention and the schematic diagram of safety Design.
Embodiment
In the test of integrated circuit, can survey signal on the integrated circuit (IC) chip by probe, prerequisite is that sensing point 1 size of these signals is enough big, can be sought and visited by probe, and sensing point 1 is exposed to outside the passivation layer of integrated circuit processing.Therefore sensing point 1 should adopt the top-level metallic design of integrated circuit processing technology, and designs enough sizes so that check by probe.
The signal that needs to observe can be selected according to actual needs.Corresponding relation between point of observation 1 and the test point 3 is determined when carrying out circuit design, the structure of this corresponding relation and circuit itself has confidential relation, and only when carrying out test analysis, just can use, therefore being security information, is bigger in the difficulty of not knowing this corresponding relation of analysis under the situation of circuit structure.
The node that needs are observed, in order to guarantee can not cause mistake because of the effect of probe, can isolate by buffer circuits 2, guarantee that sensing point 1 can obtain the driving from point of observation 3, and do not have reverse signal transmission, thereby avoided influence to raw observation point.
In order further to increase redundancy and the chaotic effect that signal link 5 brings in these points of observation, anti-attack ability with intensifier circuit, in layout design, use automatic placement and routing's instrument to carry out the design of circuit, finish the arrangement of various unit and line in the circuit by it.For guarantee can by automatic placement and routing's instrument setting be connected these sensing points 1, can be together, and as the signaling point that needs in the pressure point unit 4 to connect pressure point unit 4 designs of they and circuit.Redundant line in these circuit increases difficulty can for the reverse engineering analysis of domain.Because the automated tool design is inconsistent with the mode that artificial design is adopted, therefore when carrying out the reverse engineering analysis, can further increase the difficulty of analyzing, thus the fail safe of raising circuit.
If in the time of need knowing the logical value of point of observation in the circuit, only need to get final product by the situation of the corresponding sensing point of pin check.
The present invention does not change the design cycle of circuit and the instrument of use in circuit design, and utilizes these instruments to increase the difficulty that reverse engineering is analyzed.This method can not change the function of circuit, does not increase extra control signal, and is to the speed and the almost not influence of power consumption of integrated circuit, little to the influence of area yet.Aspects such as cost, fail safe, complexity effective relatively is adapted at the information security integrated circuit and particularly adopts in the design of the circuit of algorithm secrecy.
Claims (3)
1, a kind of measurability of information security integrated circuit and safety Design method, its step comprises:
(1) as required, determine point of observation and the design and the corresponding circuit sensing point of point of observation of test;
(2) adopt automatic placement and routing's instrument to realize being connected of point of observation and sensing point;
(3) when test, utilize probe and circuit sensing point to detect the relevant information of information security integrated circuit.
2, the measurability of information security integrated circuit as claimed in claim 1 and safety Design method is characterized in that: the line of buffer circuits driving from the sensing point to the point of observation is set.
3, the measurability of information security integrated circuit as claimed in claim 1 or 2 and safety Design method is characterized in that: sensing point is arranged in the pressure point unit, as the signaling point of pressure point unit.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB2004100093197A CN100370597C (en) | 2004-07-09 | 2004-07-09 | Measurability and safety design method for information safety IC |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB2004100093197A CN100370597C (en) | 2004-07-09 | 2004-07-09 | Measurability and safety design method for information safety IC |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN1719593A true CN1719593A (en) | 2006-01-11 |
| CN100370597C CN100370597C (en) | 2008-02-20 |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CNB2004100093197A Expired - Fee Related CN100370597C (en) | 2004-07-09 | 2004-07-09 | Measurability and safety design method for information safety IC |
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| CN (1) | CN100370597C (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101916317A (en) * | 2010-08-23 | 2010-12-15 | 清华大学 | Grid-free model based wiring method of integrated circuit from module to module |
| CN113156843A (en) * | 2021-01-25 | 2021-07-23 | 济南明湖建筑节能技术开发有限公司 | Water supply system collector and remote control system |
Family Cites Families (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5783846A (en) * | 1995-09-22 | 1998-07-21 | Hughes Electronics Corporation | Digital circuit with transistor geometry and channel stops providing camouflage against reverse engineering |
| US5861652A (en) * | 1996-03-28 | 1999-01-19 | Symbios, Inc. | Method and apparatus for protecting functions imbedded within an integrated circuit from reverse engineering |
| US5920112A (en) * | 1998-04-07 | 1999-07-06 | Micro Networks Corporation | Circuit including a corral for containing a protective coating, and method of making same |
| US6137173A (en) * | 1998-06-30 | 2000-10-24 | Intel Corporation | Preventing backside analysis of an integrated circuit |
| US20020096744A1 (en) * | 2001-01-24 | 2002-07-25 | Hrl Laboratories, Llc | Integrated circuits protected against reverse engineering and method for fabricating the same using etched passivation openings in integrated circuits |
| US6897535B2 (en) * | 2002-05-14 | 2005-05-24 | Hrl Laboratories, Llc | Integrated circuit with reverse engineering protection |
-
2004
- 2004-07-09 CN CNB2004100093197A patent/CN100370597C/en not_active Expired - Fee Related
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101916317A (en) * | 2010-08-23 | 2010-12-15 | 清华大学 | Grid-free model based wiring method of integrated circuit from module to module |
| CN101916317B (en) * | 2010-08-23 | 2012-05-23 | 清华大学 | Grid-free model based wiring method of integrated circuit from module to module |
| CN113156843A (en) * | 2021-01-25 | 2021-07-23 | 济南明湖建筑节能技术开发有限公司 | Water supply system collector and remote control system |
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| Publication number | Publication date |
|---|---|
| CN100370597C (en) | 2008-02-20 |
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Granted publication date: 20080220 Termination date: 20100709 |