CN1713292A

CN1713292A - Adjustment and adjuster for sampling clock phase and synchronizing signal forescasting time sequence

Info

Publication number: CN1713292A
Application number: CN 200410059798
Authority: CN
Inventors: 颜光裕
Original assignee: Realtek Semiconductor Corp
Current assignee: Realtek Semiconductor Corp
Priority date: 2004-06-23
Filing date: 2004-06-23
Publication date: 2005-12-28
Anticipated expiration: 2024-06-23
Also published as: CN100411046C

Abstract

A device for regulating phase of sampling clock consists of sampling module for generating multiple sampling data, comparing module for comparing these sampling data to preset synchronous mode to generate a comparing result and carrying out above comparing action again to generate another comparing result after interval of preset time as well as regulating module for counting up comparing results and regulating phase of sampling clock according to counted up result.

Description

Adjust the method and the device thereof of sampling clock phase place and synchronizing signal prediction sequential

Technical field

The present invention relates to a kind of method and device thereof of handling optical disc reading signal, relate to a kind of relatively sampled data and synchronous mode synchronously and predict the synchronizing signal of optical disc reading signal and method and the device thereof of adjusting the sampling phase of optical disc reading signal.

Background technology

In communication system, the transmission end is in order to align each frame (frame), usually add that a synchronous mode (synchronization pattern) transmits signal, and receiving end is when received signal, then utilize and obtain (acquisition) or the modes such as (tracking) of tracking is sought this synchronous mode, again the data after this synchronous mode are deciphered processing.With digital universal disc (Digital Versatile Disc, DVD) be example, the employed synchronous mode of DVD is that continuous 14 logical values are 1 signal, and DVD player is when decoding DVD signal, then constantly be that 1 synchronous mode compares with DVD signal and 14 continuous logic values, to find out the synchronous mode that is comprised in the DVD signal, again the frame signal after the synchronous mode is deciphered processing.

In communication system, receiving end utilizes sampling clock to come sampled analog signals, utilize signal level (level) that sampled signal is converted to digital signal to carry out digital signal processing again, yet, signal jitter (jitter) can cause sampling clock to come sampled analog signals according to desirable sequential, thereby cause the sampling value of sampled signal to depart from ideal value, even also the bit error rate of communication system (bit error rate) improves.With the dvd system is example, and it is that 1 signal comes as synchronous mode that dvd system uses continuous 14 logical values, and the utilization and operation limited length (run-length limited, RLL) sign indicating number carries out modulating-coding.When signal jitter is ordered about sampling clock not in sequential accurately (that is the phase place of sampling clock produces skew) when taking a sample, sampled signal thereby be judged as wrong signal level, thereby influence the synchronizing signal of optical disc reading signal or influence the demodulation process of optical disc reading signal, even may cause optical disc reading signal can't successfully finish demodulation.

Summary of the invention

Therefore, the present invention provides and a kind ofly adjusts the method and the device thereof of the prediction sequential of the phase place of sampling clock and synchronizing signal via optical disc reading signal, to address the above problem.

According to embodiments of the invention, it is to disclose a kind of sync signal detection apparatus that is used for light memory device, and it includes: sampling module is used to use sampling clock sampling optical disc reading signal to produce a plurality of sampled datas; Comparison module is electrically connected on this sampling module, is used for these sampled datas of comparison and predetermined synchronous mode, produces comparative result, and at the fixed time at interval after, carry out above-mentioned comparison again, produce another comparative result; And an adjusting module, be electrically connected on this comparison module, in order to add up these above-mentioned comparative results, adjust the phase place of this sampling clock again according to statistics.

In addition, according to embodiments of the invention, it discloses a kind of sychronizing signal detecting method that is used for light memory device in addition, and it includes: use the sampling clock optical disc reading signal of taking a sample to produce a plurality of sampled datas; Relatively these sampled datas and a predetermined synchronous mode produce a comparative result, and behind a predetermined time interval, carry out above-mentioned comparison again, produce another comparative result; And add up these above-mentioned comparative results, and adjust the sequential of this synchronizing signal of output according to the result of statistics.

Description of drawings

Fig. 1 is applied to the synoptic diagram of a CD-ROM drive for sampling phase adjusting gear of the present invention and sync signal detection apparatus.

Fig. 2 is the sampling phase adjusting gear shown in Figure 1 and the operational flowchart of sync signal detection apparatus.

Fig. 3 is sampling clock shown in Figure 1, the sequential chart that stores clock and synchronizing signal.

Fig. 4 is the function block schematic diagram of comparison module shown in Figure 1.

Fig. 5 is the synoptic diagram of storage element shown in Figure 1.

Fig. 6 is the register shown in Figure 5 and the synoptic diagram of corresponding calculated value.

Fig. 7 is the synoptic diagram of the average computation value that adjusting module produced in the sampling phase adjusting gear shown in Figure 1.

The reference numeral explanation:

10 CD-ROM drives

12 analog filters

14 limiters

16 asymmetry compensation modules

18 phaselocked loops

20 sampling phase adjusting gears

22 delay cells

22 sampling modules

26 rearmounted processing modules

30 sync signal detection apparatus

32 comparison modules

26 storage elements

36,38 adjusting modules

40,46 delay cells

42 totalizers

44 subtracters

50,52,54,56,58 registers

Embodiment

Please refer to Fig. 1, Fig. 1 is applied to the synoptic diagram of a CD-ROM drive 10 for sampling phase adjusting gear 20 of the present invention and sync signal detection apparatus 30.CD-ROM drive 10 is imported an input signal Si n (for example EFM data that read by a CD) by the outside, analog filter 12 can carry out Filtering Processing to produce a filtering signal S to input signal Si n, and limiter 14 is converted to a corresponding clipped signal S ' according to a clipping lever (slice level) with filtering signal S.In addition, asymmetry compensation module 16 is to be connected to limiter 14 to form a feedback, be used for the direct current offset (DC offset) of clipped signal S ' is removed, that is the clipping lever of recoverable limiter 14 reaches the purpose that reduces direct current offset, and phaselocked loop 18 then produces a corresponding sampling clock CLK according to clipped signal S '.Sampling phase adjusting gear 20 is used to adjust the sampling phase of sampling clock CLK sampling clipped signal S ', and it includes a delay cell 22, a sampling module 24 and an adjusting module 38.Sync signal detection apparatus 30 is used to detect the synchronizing signal among the input signal Si n, and it includes a comparison module 32, a storage element 34 and an adjusting module 36.In the present embodiment, sampling module 24 utilizes sampling clock CLK ' to take a sample clipped signal S ' to produce sampled data D, handles (post-processing) module 26 by postposition again and carries out the postposition processing.

Please refer to Fig. 2, Fig. 2 is the sampling phase adjusting gear 20 shown in Figure 1 and the operational flowchart of sync signal detection apparatus 30.Details are as follows in the running of adjustment sampling phase device 20 and sync signal detection apparatus 30:

Step 100: sampling module 24 is constantly taken a sample to produce a plurality of sampled data D in regular turn to clipped signal S ' according to sampling clock CLK ';

Step 102: comparison module 32 with a plurality of sampled data D and a synchronous mode comparison to produce one first synchronizing signal;

Step 104: comparison module 32 is predicted the sequential of next second synchronizing signal according to this first synchronizing signal;

Step 106: before the sequential of second synchronizing signal, comparison module 32 uses corresponding a plurality of relatively a plurality of sampled datas and this synchronous modes of period to compare to produce a plurality of calculated value V;

Step 108: storage element 34 stores clock CLKsv according to one and stores these a plurality of calculated value V;

Step 110: adjusting module 36 is predicted the sequential of next the 3rd synchronizing signal SYNC according to storage element 34 stored calculated value V; And

Step 112: adjusting module 36 utilizes storage element 34 stored calculated value V to drive delay cell 22, to adjust the sampling phase of sampling clock CLK ' sampling clipped signal S '.

Please refer to Fig. 3, Fig. 3 is sampling clock CLK ' shown in Figure 1, the sequential chart that stores clock CLKsv and synchronizing signal SYNC.Comparison module 32 relatively produces a synchronous signal SYNC1 with sampled data D and known synchronous mode, and predicts the sequential of next synchronizing signal SYNC2 according to synchronizing signal SYNC1.Most preferred embodiment of the present invention is to be example with dvd system (that is CD-ROM drive 10 is DVD drive), so, synchronizing signal be spaced apart 1488 clock period, therefore, the sequential of synchronizing signal SYNC1 ought to be the sequential of synchronizing signal SYNC2 after adding clock period of 1488 sampling clock CLK.In the present embodiment, two clock period of comparison module 32 before synchronizing signal SYNC2 rise, begin sampled data D and this synchronous mode are compared, and triggering (trigger) stores clock CLKsv, storage element 34 then stores the calculated value V that comparison module 32 relatively produces according to storing clock CLKsv, be comparison module 32 relatively before and after the scheduled timing of synchronizing signal SYNC2 between two clock period a plurality of sampled data D of (five clock period altogether) and be stored among the storage element 34 producing five calculated value V respectively.Present embodiment is to obtain desired calculated value according to the relevance of sampled data and predetermined synchronous mode (correlation), that is this calculated value is the similarity of representing between sampled data and the predetermined synchronous mode, after its operation is specified in.

Please refer to Fig. 4, Fig. 4 is the function block schematic diagram of comparison module 32 shown in Figure 1.Comparison module 32 includes delay cell (delay unit) 40a, 40b, 40c, the 40d of a plurality of sequence serial connections, a totalizer 42, one subtracters 44, and a delay cell 46.In the present embodiment, input signal Si n one meets the signal of DVD specification, so comparison module 32 synchronous mode that uses the delay cell 40 of 14 serial connections relatively to have 14 continuous logic values " 1 ".Therefore, the function of comparison module 32 is with the synchronous mode of 14 continuous logic values " 1 " and does relevance (correlation) computing to calculate association numerical value (that is calculated value V), so in fact comparison module 32 can be provided with the delay cell of 14 serial connections, yet, not influencing under the technology of the present invention exposure, only show 4

delay cell

40a, 40b, 40c, 40d among Fig. 4.A plurality of sampled data D import comparison module 32 in regular turn, suppose that

delay cell

40a, 40b, 40c, 40d, 46 initial values that kept are " 0 ", therefore as a sampled data D ₁During input delay unit 40a, delay cell 40a can keep sampled data D ₁, in addition, the output data A of totalizer 42 is sampled data D ₁, and the output data C of subtracter 44 also is sampled data D ₁As next sampled data D ₂During input delay unit 40a, delay cell 40a can be earlier with original sampled data D ₁Be passed to next delay cell 40b, just note down sampled data D then ₂, that is

delay cell

40a, 40b keep sampled data D respectively at this moment ₁, D ₂, in addition, because delay cell 46 is noted down sampled data D at present ₁, so the output data A of totalizer 42 is sampled data D ₁With sampled data D ₂Summation, and the output data C of subtracter 44 also is sampled data D ₁With sampled data D ₂Summation, so delay cell 46 just can be upgraded its storage values and write down sampled data D ₁With sampled data D ₂Summation.So, as 14 sampled data D ₁-D ₁₄Behind the input comparison module 32, delay cell 40a shown in Figure 4,40b, 40c, 40d just can note down sampled data D respectively ₁₄, D ₁₃, D ₂, D ₁, and delay cell 46 can record sampled data D ₁-D ₁₄Summation.As next sampled data D ₁₅During input comparison module 32, the output data A of totalizer is sampled data D ₁-D ₁₅Summation, and delay cell 40d can be with its sampled data D originally ₁Output (that is output data B) is so the output data C of subtracter 44 just becomes sampled data D ₂-D ₁₅Summation, and the storage values of updating delay unit 46 (that is calculated value V) further note that delay cell 40a shown in Figure 4,40b, 40c, 40d note down sampled data D respectively ₁₅, D ₁₄, D ₃, D ₂So for every continuous 14 sampled datas, comparison module 32 just can calculate the calculated value V to comparison period that should 14 sampled datas.

Please refer to Fig. 5, Fig. 5 is the synoptic diagram of storage element 34 shown in Figure 1.Storage element 34 includes a plurality of

registers

50,52,54,56,58, it is to store clock CLKsv according to one to store comparison module 32 five five calculated value V that relatively period produced in regular turn respectively, and wherein the register 54 pairing relatively zero-times of period are 50,52,54,56,58 corresponding respectively a plurality of relatively mediants (median value) of the zero-time of period of register.Please also refer to Fig. 6 and Fig. 5, Fig. 6 is the

register

50,52,54,56,58 shown in Figure 5 and the synoptic diagram of calculated value.For convenience of explanation, the transverse axis of Fig. 6 is with code R _-2, R _-1, R ₀, R ₁, R ₂Represent register 50,52,54,56,58 respectively, and the calculated value V (that is the alleged association value of the present invention) that the longitudinal axis is a

register

50,52,54,56,58 to be write down.For instance, under desirable operating environment, during the cycle, the calculated value that comparison module 32 is calculated is 12, and is stored in the register 50 at the first two sampling clock of scheduled timing of synchronizing signal SYNC2; During the cycle, the calculated value that comparison module 32 is calculated is 13, and is stored in the register 52 at the last sampling clock of scheduled timing of synchronizing signal SYNC2; When the scheduled timing of synchronizing signal SYNC2, the calculated value that comparison module 32 is calculated is 14, and be stored in the register 54, in like manner, because calculated value has symmetry, comparison module 32 after the sequential of synchronizing signal SYNC2 a sampling clock cycle and two sampling clock cycles the calculated value that calculates respectively be respectively 13 and 12, and be stored in respectively in register 56 and the register 58.

Present embodiment, adjusting module 36 are sequential of utilizing the calculated value V be stored in

register

50,52,54,56,58 to predict and proofread and correct next synchronizing signal SYNC3.If in the time of can correctly estimating the sequential of synchronizing signal SYNC2 according to synchronizing signal SYNC1, then in

register

50,52,54,56,58, register 54 can be noted down a maximal value; If the stored maximal value of storage element 34 is not among register 54 time, can utilize the side-play amount between pairing register of this maximal value and the register 54, learn the timing off-set amount (offset) of present synchronizing signal SYNC2, and the sequential of estimating of further proofreading and correct next synchronizing signal SYNC3.For instance, suppose that maximal value is to be stored among the register 52, mean when using synchronizing signal SYNC1 to predict the sequential of synchronizing signal SYNC2, the sequential of estimating of synchronizing signal SYNC2 is that the actual sequential that is later than synchronizing signal SYNC2 reaches a sampling clock cycle, therefore when using the estimating sequential and predict the sequential of synchronizing signal SYNC3 of synchronizing signal SYNC2, must do sth. in advance a sampling clock cycle and decide the sequential of estimating of synchronizing signal SYNC3, that is producing 1487 sampling clocks after the sequential during cycle estimating of synchronizing signal SYNC2, the triggered time of next sampling clock point is the sequential of synchronizing signal SYNC3.If maximal value is to be stored among the register 58, promptly mean when using synchronizing signal SYNC1 to predict the sequential of synchronizing signal SYNC2, the sequential of estimating of synchronizing signal SYNC2 is that actual sequential early than synchronizing signal SYNC2 reaches two sampling clock cycles, therefore when using the estimating sequential and predict the sequential of synchronizing signal SYNC3 of synchronizing signal SYNC2, must prolong two sampling clock cycles decides the sequential of estimating of synchronizing signal SYNC3, that is, produce 1490 sampling clocks after the sequential during cycle estimating of synchronizing signal SYNC2, the triggered time of next sampling clock point is the sequential of synchronizing signal SYNC3.By that analogy, adjusting module 28 just can utilize five the relatively calculated values that calculate of period of estimating before and after the sequential of a synchronous signal, proofreaies and correct the sequential of estimating of next synchronizing signal.

In the present embodiment, adjusting module 38 also is to utilize the calculated value V that is stored in

register

50,52,54,56,58 to drive delay cell 22 to adjust the sampling phase of sampling clock CLK ' when taking a sample clipped signal S '.See also Fig. 7, Fig. 7 is the synoptic diagram of the average computation value that adjusting module 38 is produced in the sampling phase adjusting gear 20 shown in Figure 1.The transverse axis representative is used for noting down the register RV of average computation value _-2, RV _-1, RV ₀, RV ₁, RV ₂, and the longitudinal axis is represented the average computation value.Register RV in the adjusting module 38 _-2, RV _-1, RV ₀, RV ₁, RV ₂Be the

register

50,52,54,56,58 in the corresponding storage element 34 of difference, and each register RV _-2, RV _-1, RV ₀, RV ₁, RV ₂Be the mean value that is used for noting down a plurality of calculated value V that

corresponding register

50,52,54,56,58 exported, in other words, adjusting module 36 can constantly calculate up-to-date mean value to upgrade mean value originally at the calculated value V that is received one by one.Under ideal state, that is sampling clock CLK ' is not when having clock skew (jitter), register RV _-2, RV _-1, RV ₀, RV ₁, RV ₂Respectively the record average computation value V ₁, V ₂, V ₃, V ₄, V ₅The family curve CV that meeting is corresponding shown in Figure 7, that is be symmetrical in central register RV ₀Two registers (RV for example _-1With RV ₁Or RV _-2With RV ₂) ought to have identical average computation value.Yet, when sampling clock CLK ' takes a sample ahead of time because of the clock skew influence, register RV _-1Stored average computation value is between 12 and 13 (mark A as shown in Figure 6) just, and register RV ₁Stored average computation value then can be between 13 and 14 (mark C as shown in Figure 6), therefore, and as register RV ₁The average computation value greater than register RV _-1The average computation value time, adjusting module 36 just drives delay cell 22 so that sampling clock CLK ' postpones the sampling optical disc reading signal; On the other hand, when postponing sampling because of clock skew influence as sampling clock CLK ', register RV then _-1Stored average computation value just can be between 13 and 14 (mark B as shown in Figure 6), and register RV ₁Stored average computation value is between 12 and 13 (mark D as shown in Figure 6) then, therefore, and as register RV _-1The average computation value greater than register RV ₁The average computation value time, adjusting module 36 just drives delay cell 22 so that sampling clock CLK ' takes a sample ahead of time optical disc reading signal.At last, the clock signal clk after sampling module 24 utilization is proofreaied and correct ' sampling clipped signal S ' to be to produce sampled data, goes the sample data to carry out postposition processing (as demodulation or digital signal processing) by 26 pairs of rearmounted processing modules again.

As mentioned above, adjusting module 36 is to utilize

register

50,52,54,56,58 stored calculated maximum to adjust the sequential of estimating of next synchronizing signal.Because calculated value has symmetry, can also use the stored calculated value of register of symmetry to judge, promptly in the ideal case, the register (register 52 and register 56) of symmetry ought to have identical calculated value, and when calculated maximum is stored in register 56, register 52 stored calculated values are 12, therefore utilize register 56 stored calculated values to deduct register 52 stored calculated values and obtain one greater than zero off-set value, be used for representing estimating sequential and should postponing again backward of synchronizing signal SYNC2 to meet its actual sequential, so when the sequential of next synchronizing signal SYNC3 of prediction, must come ahead of time or postpone the sequential of estimating of script according to off-set value.In addition, can also use the stored calculated value of register of symmetry to judge whether the sampling phase of optical disc reading signal produces deviation, and further drive the phase place that delay cell 22 is adjusted sampling clock CLK '.

Method and device thereof that the present invention detects synchronizing signal utilize the comparative result of sampled data and synchronous mode to adjust the sequential of next prediction synchronizing signal, therefore do not need relatively more all sampled datas to find out synchronizing signal, only need promptly can utilize off-set value to adjust the sequential of next prediction synchronizing signal in sequential more several clock period of front and back of the synchronizing signal of predicting.Therefore, under the situation of CD damage, the present invention detects the method and the device thereof of synchronizing signal also can find out correct synchronizing signal fast near estimating next synchronizing signal, thereby can reduce power consumption.In addition, method and device thereof that the present invention adjusts sampling phase utilize the comparative result of sampled data and synchronous mode to adjust the phase place of sampling clock, to reduce the bit error rate that signal jitter was caused.

The above only is preferred embodiment of the present invention, and all equalizations of being done according to the present patent application claim change and modify, and all should belong to the covering scope of patent of the present invention.

Claims

1. sychronizing signal detecting method that is used for light memory device, it includes:

Use the sampling clock optical disc reading signal of taking a sample to produce a plurality of sampled datas;

Relatively these sampled datas and a predetermined synchronous mode produce a comparative result, and behind a predetermined time interval, carry out above-mentioned comparison again, produce another comparative result; And

Add up these above-mentioned comparative results, and adjust the phase place of this sampling clock according to statistics.

2. the method for claim 1, wherein, should predetermined synchronous mode be to include continuous 14 positions with a logical value, this predetermined time interval is to 1488-n cycle that should the data sampling clock, and this method be this predetermined clock at interval the back continuously m sampling clock all carry out this comparison, wherein m, n are a positive integer.

3. the method for claim 1, wherein, this comparison is to these sampled datas and should carries out the relevance computing by predetermined synchronous mode, wherein, should comprise a plurality of synchrodatas by predetermined synchronous mode, and this comparison module is that continuous a plurality of sampled datas and these synchrodatas that should be scheduled in the synchronous mode are compared, and calculates these serial sampling data number identical with the value of corresponding these synchrodatas and come as this comparative result.

4. the method for claim 1, wherein this method is to be used as this comparative result according to comparing these serial sampling data maximum persons of number identical with the value of corresponding these synchrodatas.

5. the method for claim 1, wherein this light memory device is a digital versatile disc.

6. sync signal detection apparatus that is used for light memory device, it includes:

One sampling module is used to use the sampling clock optical disc reading signal of taking a sample to produce a plurality of sampled datas;

One comparison module is electrically connected on this sampling module, is used for these sampled datas of comparison and a predetermined synchronous mode, produces a comparative result, and behind a predetermined time interval, carries out above-mentioned comparison again, produces another comparative result; And

One adjusting module is electrically connected on this comparison module, in order to add up these above-mentioned comparative results, produces one and adjusts signal, in order to adjust the phase place of this sampling clock.

7. sync signal detection apparatus as claimed in claim 6, its, should be scheduled to synchronous mode is the logical value that comprises continuous 14 positions " 1 ", this predetermined time interval is to 1488-n cycle that should the data sampling clock, and this comparison module be this predetermined clock at interval the back continuously m sampling clock all carry out this comparison, wherein m, n are a positive integer.

8. sync signal detection apparatus as claimed in claim 6, wherein, this comparison module is to these sampled datas and should carries out the relevance computing by predetermined synchronous mode, should comprise a plurality of synchrodatas by predetermined synchronous mode, this comparison module is that continuous a plurality of sampled datas are compared the identical number of value of calculating these serial sampling data and corresponding these synchrodatas with these synchrodatas that should be scheduled in the synchronous mode, and this adjusting module is to come as this comparative result according to the maximum persons of number that relatively these serial sampling data are identical with the value of corresponding these synchrodatas.

9. sync signal detection apparatus as claimed in claim 6, wherein, this device more comprises:

One storage element is in order to store this comparative result; And

One delay cell is coupled to this adjusting module and this sampling module, in order to adjust the phase place of this sampling clock according to this adjustment signal, exports adjusted sampling clock again to this sampling module.

10. sync signal detection apparatus as claimed in claim 6, wherein, this light memory device is a digital versatile disc.