CN1707595A - Source driver, source driver array, driving circuit with the array and display - Google Patents
Source driver, source driver array, driving circuit with the array and display Download PDFInfo
- Publication number
- CN1707595A CN1707595A CN 200410042968 CN200410042968A CN1707595A CN 1707595 A CN1707595 A CN 1707595A CN 200410042968 CN200410042968 CN 200410042968 CN 200410042968 A CN200410042968 A CN 200410042968A CN 1707595 A CN1707595 A CN 1707595A
- Authority
- CN
- China
- Prior art keywords
- signal
- display
- data
- source driver
- source
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 230000001360 synchronised effect Effects 0.000 claims description 41
- 239000010409 thin film Substances 0.000 claims description 33
- 238000006243 chemical reaction Methods 0.000 claims description 12
- 229910021417 amorphous silicon Inorganic materials 0.000 claims description 8
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 7
- 239000004973 liquid crystal related substance Substances 0.000 claims description 7
- 229910052710 silicon Inorganic materials 0.000 claims description 7
- 239000010703 silicon Substances 0.000 claims description 7
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 4
- 229920005591 polysilicon Polymers 0.000 claims description 4
- 238000001514 detection method Methods 0.000 claims 2
- 230000001960 triggered effect Effects 0.000 claims 2
- 238000010586 diagram Methods 0.000 description 13
- 101000869896 Homo sapiens Death-inducer obliterator 1 Proteins 0.000 description 10
- 101001053773 Homo sapiens Type I iodothyronine deiodinase Proteins 0.000 description 10
- 102100024063 Type I iodothyronine deiodinase Human genes 0.000 description 10
- 238000013461 design Methods 0.000 description 10
- 238000005070 sampling Methods 0.000 description 6
- 238000012546 transfer Methods 0.000 description 6
- 101001053754 Homo sapiens Type II iodothyronine deiodinase Proteins 0.000 description 4
- 102100024060 Type II iodothyronine deiodinase Human genes 0.000 description 4
- 230000008901 benefit Effects 0.000 description 4
- 230000000694 effects Effects 0.000 description 4
- 239000010408 film Substances 0.000 description 4
- 230000004913 activation Effects 0.000 description 3
- 150000001875 compounds Chemical class 0.000 description 3
- 239000013078 crystal Substances 0.000 description 3
- 230000002950 deficient Effects 0.000 description 3
- 238000005516 engineering process Methods 0.000 description 3
- 230000000750 progressive effect Effects 0.000 description 3
- 230000008859 change Effects 0.000 description 2
- 230000006872 improvement Effects 0.000 description 2
- 239000011159 matrix material Substances 0.000 description 2
- 238000000034 method Methods 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- NHDHVHZZCFYRSB-UHFFFAOYSA-N pyriproxyfen Chemical compound C=1C=CC=NC=1OC(C)COC(C=C1)=CC=C1OC1=CC=CC=C1 NHDHVHZZCFYRSB-UHFFFAOYSA-N 0.000 description 2
- 230000009286 beneficial effect Effects 0.000 description 1
- 238000010276 construction Methods 0.000 description 1
- 238000011161 development Methods 0.000 description 1
- 238000006073 displacement reaction Methods 0.000 description 1
- 239000007788 liquid Substances 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 230000005855 radiation Effects 0.000 description 1
- 238000011160 research Methods 0.000 description 1
- 238000004088 simulation Methods 0.000 description 1
Images
Landscapes
- Control Of Indicators Other Than Cathode Ray Tubes (AREA)
- Liquid Crystal Display Device Control (AREA)
Abstract
The invention relates to a source driver, an array formed by the source driver, a driving circuit with the array and a display, belonging to an improved device of a starting pulse signal. The driving circuit is suitable for driving a display panel of a display, and comprises: the source driver array comprises a plurality of source drivers, the time schedule controller is connected with each source driver and provides display time sequence data for each source driver, each source driver receives a corresponding position code signal, the position code signal corresponding to each source driver is determined according to the driving sequence of the source drivers in the source driver array and is used as a data distribution control signal of a display data signal in the display time sequence data according to the position code signal so as to be transmitted to the display panel. The invention can improve the problem that the highest operation frequency of the traditional flat panel display driver is limited by the starting pulse signal, and can save the cost increased by the traditional framework for increasing the operation frequency.
Description
Technical field
The present invention relates to a kind of display and driving circuit thereof, particularly relate to a kind of source electrode driver, source electrode driver array, driving circuit and display with this array.
Background technology
LCD (Liquid Crystal Display, hereinafter to be referred as LCD) have a characteristic of in light weight, thin thickness, little, the low radiation of volume and power saving, these characteristics make it can save usage space in office or family, and reduce and watch the sense of fatigue that human eye is caused for a long time.Therefore, in all flat-panel screens, LCD has the characteristics of comprehensive replacement conventional cathode ray tube (CRT) most.And more and more higher resolution demand means that the display data amount of each picture (Frame) increases thereupon, and therefore, the operating frequency of plane display driver also increases.
Seeing also shown in Figure 1ly, is a kind of existing traditional active thin film transistor (TFT) (Active MatrixThin Film Transistor, AMTFT) block schematic diagram of LCD 100.And in this LCD 100, the source electrode driver array that comprises a LCD panel of thin-film transistor 101, formed by plurality of sources driver (Source Driver) (array is array, below all be called array) 102, gate pole driver array 103, the Voltage Supply Device 104 and time schedule controller 105 formed by a plurality of gate pole drivers (Gate Driver).This time schedule controller 105 offers the source electrode driver in the source electrode driver array 102, and the operation of the gate pole driver in the gate pole driver array 103 clock pulse CLK (clock signal as shown).And simultaneously, time schedule controller 105 is also sent a vertical synchronizing signal and is given gate pole driver array 103, and sends a horizontal-drive signal in addition to source electrode driver array 102 and gate pole driver array 103.For convenience of description, be called source control signal and gate control signal for the control signal of source electrode driver array 102 and gate pole driver array 103 in the drawings.And desire to be presented at the display data of LCD panel of thin-film transistor 101, then can be introduced into time schedule controller 105 after, deliver to source electrode driver array 102 by time schedule controller 105 again.And after the source electrode drivers in the source electrode driver array 102 obtain display data, (numerical digit is numeral to the horizontal signal that provided of matching timing controller 105 through numerical digit again, below all be called numerical digit) (analogy is simulation to analogy, below all be called analogy) conversion after, export a gray scale voltage to transistor LCD display panel 101, with display frame.
Seeing also shown in Figure 2ly, is in a kind of tradition active (Active Matrix) Thin Film Transistor-LCD, a kind of time schedule controller 210 and a kind of source electrode driver array 220 annexation structural representation each other.This source electrode driver array 220 comprise n source electrode driver (as shown 2201～220n).And time schedule controller 210 is connected with each source electrode driver 2201～220n, and provides as shown in the figure a start pulse (Start Pulse) signal DIO1, an operation clock signal CLK, a display data signal DATA and a horizontal bolt lock signal LD to give each source electrode driver (2201～220n) respectively.Operation clock signal CLK, display data signal DATA and horizontal bolt lock signal LD are at same bus (BUS, bus is bus-bar, below all is called bus), and each source electrode driver (2201～220n) all are connected to this bus with received signal.Initial pulse signals DIO1 then is the connected mode of point-to-point (Point to Point), and CLK carries out bolt-lock (Latch) by the operation clock signal, with the control signal of distributing in proper order as data signal DATA.When line buffer (Line Buffer) data bolt-lock has been expired (Data Latch Full), then can send start pulse (Start Pulse) signal DIO2, use with supply next stage source electrode driver.The mode of utilizing this data to be connected in series reaches the expansion of display frame.
Seeing also shown in Figure 3ly, is the block schematic diagram of the source electrode driver of the active Thin Film Transistor-LCD of a kind of tradition.This source electrode driver 300, include a shift registor (ShiftRegister) 310, a sampling working storage (Sample Register) 320 is connected to a data bolt-lock unit 330, and keeps working storage (Hold Register) 340, rank shift units (LevelShift) 350, a numerical digit class specific revolution position (Digital-to-Analog Converter, DAC) unit 360 and an output buffer 370.And this numerical digit class specific revolution bit location 360 is connected to a Gamma device for generating voltage (Gamma Voltage Generator) 380.
This shift registor (Shift Register) 310 receives start pulse (StartPulse) the signal DIO1 of an outside input.And the control signal that adopts this initial pulse signals of bolt-lock (Latch) DIO1 to distribute in proper order as data.Display data signal DATA then is sent to sampling working storage 320 via data bolt-lock unit 330 and data bus (Data Bus).And be sent to and keep working storage 340.And this keeps working storage 340 and receives horizontal bolt lock signal (Latch Signal, represent with LD), and after adjusting rank, display data voltage of signals position, be sent to unit, numerical digit class specific revolution position (DAC) 360 through displacement (Level Shift) unit, rank, position 350.And Gamma device for generating voltage 380 receives an outside Gamma voltage, and is sent to unit, numerical digit class specific revolution position (DAC) 360 according to this, and as the reference that is adjusted into anaiog signal.And the adjustment display data signal after then will adjusting is sent to the panel of Thin Film Transistor-LCD via output buffer 370.
Yet the bottleneck of this mode is the progressive error of initial pulse signals DIO1 with the operation clock signal CLK of receiving end, often causes initial pulse signals bolt-lock mistake, thereby the highest operating frequency of restriction, has only about 100MHz with present technology.
Seeing also shown in Figure 4ly, is a kind of sequential chart of source electrode driver of traditional active Thin Film Transistor-LCD.As shown in the figure, when time T 1, source electrode driver receives horizontal bolt lock signal (LD).Then when time T 2, receive the input of initial pulse signals DIO1, and carry out bolt-lock (Latch), with the control signal of distributing in proper order as data according to operation clock pulse CLK.Expired (Data Latch Full) when line buffer (LjneBuffer) data bolt-lock, can send initial pulse signals DIO2 output and use, as time T 3 for the next stage source electrode driver.The framework of this one-level serial connection one-level is until the complete bolt-lock of horizontal display data finishes.At this moment, time schedule controller is sent horizontal bolt lock signal LD, and line buffer (Line Buffer) data after numerical digit to analogy is changed, is exported the panel of a gray scale voltage to Thin Film Transistor-LCD.
This shows, above-mentioned existing source electrode driver, source electrode driver array and display with this array structure with use, obviously still have inconvenience and defective, and demand urgently further being improved.In order to address the above problem, relevant manufacturer there's no one who doesn't or isn't seeks solution painstakingly, but do not see always that for a long time suitable design finished by development, and common product does not have appropriate structure to address the above problem, this obviously is the problem that the anxious desire of relevant dealer solves.
Because above-mentioned existing source electrode driver, source electrode driver array and have the defective that this array display exists, the inventor is based on being engaged in this type of product design manufacturing abundant for many years practical experience and professional knowledge, and the utilization of cooperation scientific principle, actively studied innovation, source electrode driver, source electrode driver array, the driving circuit with this array and display in the hope of founding a kind of new structure make it have more practicality.Through constantly research, design, and after studying sample and improvement repeatedly, create the present invention who has practical value finally.
Summary of the invention
The objective of the invention is to, overcome existing source electrode driver, the source electrode driver array, and the defective that exists of the display with this array, and provide a kind of source electrode driver of new structure, the source electrode driver array, driving circuit and display with this array, it is the improved device that belongs to initial pulse signals, technical matters to be solved is to make its highest operating frequency that can improve traditional plane display driver be subject to the problem of initial pulse signals, and can save conventional architectures in order to improve the cost that operating frequency increases, as dual-bus structure (Two Bus Architecture), thereby be suitable for practicality more.
The object of the invention to solve the technical problems is to adopt following technical scheme to realize.A kind of driving circuit according to the present invention's proposition, be applicable to a display panel that drives a display, it comprises: time schedule controller and one source pole drive array, wherein this source electrode driver array comprises the plurality of sources driver, this source electrode driver of this time schedule controller and each is connected, and provide a display timing generator data to each this source electrode driver, and each this source electrode driver receives a pairing position code signal, this position code signal corresponding to each this source electrode driver is to decide according to the driving order of those source electrode drivers in this source drive array, and according to this position code signal, distribute the signal of control as the data of the display data signal in this display timing generator data, use being sent to this display panel.
The object of the invention to solve the technical problems also can be applied to the following technical measures to achieve further.
Aforesaid driving circuit, wherein said display timing generator data comprise operation clock signal, a horizontal bolt lock signal and this display data signal.
Aforesaid driving circuit, wherein said operation clock signal, display data signal and horizontal bolt lock signal are a kind of differential voltage signal (Differential Voltage Signal).
Aforesaid driving circuit, wherein said operation clock signal, display data signal and horizontal bolt lock signal are a kind of transistor-transistor logic (Transistor-Transistor Logic, TTL) voltage signal.
Aforesaid driving circuit, wherein said position code signal have most bits, and the bit number of this position code signal is to decide according to the quantity of those source electrode drivers.
Aforesaid driving circuit, the bit number of wherein said position code signal more than or equal to the quantity of those source electrode drivers with bit number that binary representation was had.
Aforesaid driving circuit, wherein each this source electrode driver comprises that a start pulse produces circuit, in order to receive and, to produce an initial pulse signals, distribute the signal of control as the data of this display data signal in this display timing generator data according to this position code signal.
Aforesaid driving circuit, wherein said start pulse produces circuit and more receives this display timing generator data, to produce this initial pulse signals.
Aforesaid driving circuit, when wherein distributing the signal of control as the data of the display data signal in this display timing generator data for this position code signal that this source electrode driver received in this source electrode driver array, be to produce one source pole driver coding (POS) signal, receive the foundation of this display data signal in this display timing generator data to start with.
Aforesaid driving circuit, wherein said source electrode driver coding (POS) signal is for the x in this source electrode driver array this source electrode driver, the value of source electrode driver coding (POS) signal then is (x-1) * k, and count down to the value of this source electrode driver coding (POS) signal via counting assembly control after, begin to receive this display data signal in this display timing generator data, and k is the data number that is defined as the required bolt-lock of those source electrode drivers (Latch).
Aforesaid driving circuit, wherein after a horizontal data bolt-lock of this display data signal in this display timing generator data finishes, this moment, this time schedule controller can will be sent a horizontal bolt lock signal, this horizontal data was outputed to this display panel of this display to the analogy conversion through numerical digit.
The object of the invention to solve the technical problems also adopts following technical scheme to realize.A kind of source electrode driver array according to the present invention's proposition, be applicable to a display panel that drives a display, this source electrode driver array comprises the plurality of sources driver, each this source electrode driver is electrically connected to time schedule controller, in order to receive a display timing generator data, and each this source electrode driver receives a pairing position code signal, this position code signal corresponding to each this source electrode driver is to decide according to the driving order of those source electrode drivers in this source drive array, and according to this position code signal, distribute the signal of control as the data of the display data signal in this display timing generator data, use being sent to this display panel.
The object of the invention to solve the technical problems also can be applied to the following technical measures to achieve further.
Aforesaid source electrode driver array, wherein said display timing generator data comprise operation clock signal, a horizontal bolt lock signal and this display data signal.
Aforesaid source electrode driver array, wherein said operation clock signal, this display data signal and this horizontal bolt lock signal are a kind of differential voltage signal (Differential Voltage Signal).
Aforesaid source electrode driver array, wherein said operation clock signal, display data signal and horizontal bolt lock signal are a kind of transistor-transistor logic (Transistor-Transistor Logic, TTL) voltage signal.
Aforesaid source electrode driver array, wherein said position code signal have most bits, and the bit number of this position code signal is to decide according to the quantity of those source electrode drivers.
Aforesaid source electrode driver array, the bit number of wherein said position code signal more than or equal to the quantity of those source electrode drivers with bit number that binary representation was had.
Aforesaid source electrode driver array, wherein each this source electrode driver comprises that a start pulse produces circuit, in order to receive and, to produce an initial pulse signals, distribute the signal of control as the data of this display data signal in this display timing generator data according to this position code signal.
Aforesaid source electrode driver array, wherein said start pulse produces circuit and more receives this display timing generator data, to produce this initial pulse signals.
Aforesaid source electrode driver array, when wherein distributing the signal of control as the data of the display data signal in this display timing generator data for this position code signal that this source electrode driver received in this source electrode driver array, be to produce one source pole driver coding (POS) signal, receive the foundation of this display data signal in this display timing generator data to start with.
Aforesaid source electrode driver array, wherein said source electrode driver coding (POS) signal is for the x in this source electrode driver array this source electrode driver, the value of source electrode driver coding (POS) signal then is (x-1) * k, and after the value via this source electrode driver coding (POS) signal of counting assembly control counting, begin to receive this display data signal in this display timing generator data, and k is the data number that is defined as the required bolt-lock of those source electrode drivers (Latch).
Aforesaid source electrode driver array, wherein after a horizontal data bolt-lock of this display data signal in this display timing generator data finishes, this moment, this time schedule controller can will be sent a horizontal bolt lock signal, this horizontal data was outputed to this display panel of display to the analogy conversion through numerical digit.
The object of the invention to solve the technical problems also adopts following technical scheme to realize.A kind of source electrode driver according to the present invention's proposition, be applicable to a display panel that drives a display, this source electrode driver is in order to receive the display timing generator data by time schedule controller provided, this source electrode driver comprises that a start pulse produces circuit, in order to receive a position code signal, and, produce an initial pulse signals according to this position code signal, distribute the signal of control as the data of the display data signal in this display timing generator data.
The object of the invention to solve the technical problems also can be applied to the following technical measures to achieve further.
Aforesaid source electrode driver, when wherein distributing the signal of control as the data of the display data signal in this display timing generator data for this position code signal that this source electrode driver received, be to produce one source pole driver coding (POS) signal, receive the foundation of this display data signal in this display timing generator data to start with.
Aforesaid source electrode driver, wherein said source electrode driver coding (POS) signal is being to belong to for x in the one source pole drive array for this source electrode driver, the value of this source electrode driver coding (POS) signal then is (x-1) * k, and after the value via this source electrode driver coding (POS) signal of counting assembly control counting, begin to receive this display data signal in this display timing generator data, and k is the data number that is defined as the required bolt-lock of those source electrode drivers (Latch).
Aforesaid source electrode driver, the data number of the required bolt-lock of wherein said source electrode driver (Latch) are the quantity of a plurality of output channels that this source electrode driver has.
Aforesaid source electrode driver, wherein after a horizontal data bolt-lock of this display data signal in this display timing generator data finishes, this moment, this time schedule controller can will be sent a horizontal bolt lock signal, this horizontal data was outputed to this display panel of this display to the analogy conversion through numerical digit.
Aforesaid source electrode driver, wherein said start pulse produces circuit and comprises: one opens beginning sign indicating number circuit for detecting, in order to receive this display timing generator data by this time schedule controller transmitted, and whether a horizontal bolt lock signal of detecting in this display timing generator data occurs, after detecting this horizontal bolt lock signal, whether this display data signal of detecting this display timing generator data again the beginning sign indicating number occurs opening and produces an activation signal according to this; One synchronous counter, be electrically connected to this and open beginning sign indicating number circuit for detecting, in order to receive this enable signal and this horizontal bolt lock signal and an operation clock signal, wherein this horizontal bolt lock signal is removed this synchronous counter to be 0, then to begin counting according to this enable signal; One decoding circuit in order to receiving this position code signal, and produces one source pole driver coding (POS) signal according to this; An and digital comparator, be electrically connected to this synchronous counter and this decoding circuit, in order to the count value in this source electrode driver coding (POS) signal relatively and this synchronous counter, if then begin to receive this display data signal in this display timing generator data when equal.
Aforesaid source electrode driver, wherein said digital comparator is relatively after the count value in this source electrode driver coding (POS) signal and this synchronous counter, uses so that this source electrode driver begins to receive this display data signal in this display timing generator data if then export a start pulse (Start Pulse) signal when equating.
Aforesaid source electrode driver, wherein said synchronous counter are the counter that a positive edge triggers, when this enable signal is counted when a logic low potential transfers a logic high potential to.
Aforesaid source electrode driver, wherein said synchronous counter are the counter that a negative edge triggers, when this enable signal is counted when a logic high potential transfers a logic low potential to.
The object of the invention to solve the technical problems also realizes by the following technical solutions.A kind of display according to the present invention's proposition, have a display panel and a kind of driving circuit, wherein this driving circuit comprises time schedule controller and one source pole drive array, wherein this source electrode driver array comprises the plurality of sources driver, this source electrode driver of this time schedule controller and each is connected, and provide a display timing generator data to each this source electrode driver, and each this source electrode driver receives a pairing position code signal, this position code signal corresponding to each this source electrode driver is to decide according to the driving order of those source electrode drivers in this source drive array, and according to this position code signal, distribute the signal of control as the data of the display data signal in this display timing generator data, use being sent to this display panel.
The object of the invention to solve the technical problems also can be applied to the following technical measures to achieve further.
Aforesaid display, wherein said display timing generator data comprise operation clock signal, a horizontal bolt lock signal and this display data signal.
Aforesaid display, wherein said operation clock signal, this display data signal and this horizontal bolt lock signal can be differential voltage signal (Differential Voltage Signal).
Aforesaid display, wherein said operation clock signal, this display data signal and this horizontal bolt lock signal are a kind of TTL (Transistor-Transistor Logic, TTL) voltage signal.
Aforesaid display, wherein said position code signal have most bits, and wherein the bit number of this position code signal is to decide according to the quantity of those source electrode drivers.
Aforesaid display, the bit number of wherein said position code signal more than or equal to the quantity of those source electrode drivers with bit number that binary representation was had.
Aforesaid display, wherein each this source electrode driver comprises that a start pulse produces circuit, in order to receive and, to produce an initial pulse signals, distribute the signal of control as the data of this display data signal in this display timing generator data according to this position code signal.
Aforesaid display, wherein said start pulse produces circuit and more receives this display timing generator data, to produce this initial pulse signals.
Aforesaid display, when wherein distributing the signal of control as the data of the display data signal in this display timing generator data for this position code signal that this source electrode driver received in this source electrode driver array, be to produce one source pole driver coding (POS) signal, receive the foundation of this display data signal in this display timing generator data to start with.
Aforesaid display, wherein said source electrode driver coding (POS) signal is for the x in this source electrode driver array this source electrode driver, the value of source electrode driver coding (POS) signal then is (x-1) * k, and after the value via this source electrode driver coding (POS) signal of counting assembly control counting, begin to receive this display data signal in this display timing generator data, and k is the data number that is defined as the required bolt-lock of those source electrode drivers (Latch).
Aforesaid display, wherein after a horizontal data bolt-lock of this display data signal in this display timing generator data finishes, this moment, this time schedule controller can will be sent a horizontal bolt lock signal, this horizontal data was outputed to this display panel of this display to the analogy conversion through numerical digit.
Aforesaid display, wherein this display is an active drive display.
Aforesaid display, wherein this display is an amorphous silicon film transistor (AmorphousSilicon Thin Film Transistor) LCD.
Aforesaid display, wherein this display is a low temperature compound crystal silicon thin film transistor (TFT) (LowTemperature Polysilicon Thin Film Transistor) LCD.
Aforesaid display, wherein this display is a LcoS (Liquid Crystal on Silicon) display driver.
Aforesaid display, wherein this display is an organic light emitting diode display driver (OLED).
The present invention compared with prior art has tangible advantage and beneficial effect.By above technical scheme as can be known, in order to reach aforementioned goal of the invention, major technique of the present invention thes contents are as follows:
The invention provides a kind of source electrode driver, be applicable to a display panel that drives a display.This source electrode driver is in order to receive the display timing generator data by time schedule controller provided.This source electrode driver comprises that a start pulse produces circuit, in order to receiving a position code signal, and according to the position code signal, produces an initial pulse signals, distributes the signal of control as the data of the display data signal in the display timing generator data.
Above-mentioned source electrode driver, in one embodiment, when distributing the signal of control as the data of the display data signal in the display timing generator data for the position code signal that source electrode driver received, be to produce one source pole driver coding (POS) signal, receive the foundation of the display data signal in the display timing generator data to start with.
Above-mentioned source electrode driver, in one embodiment, this source electrode driver coding (POS) signal is being to belong to for x in the one source pole drive array for source electrode driver, the value of source electrode driver coding (POS) signal then is (x-1) * k, and after the value via counting assembly control counting source driver coding (POS) signal, begin to receive the display data signal in the display timing generator data, and k is the data number that is defined as the required bolt-lock of source electrode driver (Latch).And the data number of the required bolt-lock of this source electrode driver (Latch) is the quantity of a plurality of output channels that source electrode driver has.
Above-mentioned source electrode driver, in one embodiment, after a horizontal data bolt-lock of the display data signal in the display timing generator data finishes, this moment, time schedule controller can will be sent a horizontal bolt lock signal, horizontal data was outputed to the display panel of display to the analogy conversion through numerical digit.
Above-mentioned source electrode driver, in one embodiment, its start pulse produces circuit and comprises and open a beginning sign indicating number circuit for detecting, a synchronous counter, a decoding circuit and a digital comparator.This opens beginning sign indicating number circuit for detecting in order to receive the display timing generator data by time schedule controller transmitted, and whether the horizontal bolt lock signal in the detecting display timing generator data occurs, after detecting the horizontal bolt lock signal, whether this display data signal of detecting the display timing generator data again the beginning sign indicating number occurs opening and produces an activation signal according to this.This synchronous counter is electrically connected to and opens a beginning sign indicating number circuit for detecting, and in order to receive enable signal and horizontal bolt lock signal and an operation clock signal, wherein the horizontal bolt lock signal is removed this synchronous counter to be 0, then to begin to count according to enable signal.And this decoding circuit is in order to the receiving position coded signal, and produces one source pole driver coding (POS) signal according to this.And digital comparator is electrically connected to synchronous counter and decoding circuit, in order to the count value in reference source driver coding (POS) signal and the synchronous counter, if then begin to receive display data signal in the display timing generator data when equal.
The invention provides a kind of source electrode driver array, be applicable to a display panel that drives a display.This source electrode driver array comprises the plurality of sources driver, and each source electrode driver is electrically connected to time schedule controller, in order to receive a display timing generator data.Each source electrode driver receives a pairing position code signal, is to decide according to the driving order of the source electrode driver in the source drive array corresponding to the position code signal of each source electrode driver.According to this position code signal, distribute the signal of control as the data of the display data signal in the display timing generator data, use being sent to display panel.
The invention provides a kind of driving circuit, be applicable to a display panel that drives a display, comprise time schedule controller and one source pole drive array.The source electrode driver array comprises the plurality of sources driver.This time schedule controller is connected with each source electrode driver, and provides a display timing generator data to each source electrode driver.Each source electrode driver receives a pairing position code signal, position code signal corresponding to each source electrode driver is to decide according to the driving order of the source electrode driver in the source drive array, and according to the position code signal, distribute the signal of control as the data of the display data signal in the display timing generator data, use being sent to display panel.
In the above-mentioned source electrode driver array, wherein each source electrode driver comprises that a start pulse produces circuit, in order to receive and, to produce an initial pulse signals, distribute the signal of control as the data of the display data signal in the display timing generator data according to the position code signal.
The invention provides a kind of display, have a display panel and a kind of driving circuit, wherein driving circuit comprises time schedule controller and one source pole drive array.This source electrode driver array comprises the plurality of sources driver.This time schedule controller is connected with each source electrode driver, and provide a display timing generator data to each source electrode driver, and each source electrode driver receives a pairing position code signal, position code signal corresponding to each source electrode driver is to decide according to the driving order of the source electrode driver in the source drive array, and according to the position code signal, distribute the signal of control as the data of the display data signal in the display timing generator data, use being sent to display panel.
Above-mentioned display is to be an active drive display.And in one embodiment, this display can be an amorphous silicon film transistor (Amorphous Silicon Thin Film Transistor) LCD, a low temperature compound crystal silicon thin film transistor (TFT) (Low Temperature Polysilicon ThinFilm Transistor) LCD, a LcoS (Liquid Crystal on Silicon) display driver or an organic light emitting diode display driver (OLED).
By technique scheme, the present invention has following advantage at least: the source electrode driver of special construction of the present invention, source electrode driver array, the driving circuit with this array and display, it is the improved device that belongs to initial pulse signals, it can improve the problem that the highest operating frequency that has traditional plane display driver now is subject to initial pulse signals, and can save conventional architectures in order to improve the cost that operating frequency increases, as dual-bus structure (Two Bus Architecture).
In sum, source electrode driver of the present invention, source electrode driver array, driving circuit and display with this array, have above-mentioned many advantages and practical value, and in like product, do not see have similar structural design to publish or use and really genus innovation, no matter it all has bigger improvement on product structure or function, have technically than much progress, and produced handy and practical effect, thereby be suitable for practicality more, and have the extensive value of industry, really be a new and innovative, progressive, practical new design.
Above-mentioned explanation only is the general introduction of technical solution of the present invention, for can clearer understanding technological means of the present invention, and can be implemented according to the content of instructions, and for above-mentioned and other purposes, feature and advantage of the present invention can be become apparent, preferred embodiment cited below particularly, and cooperate appended graphicly, be described in detail below.
Description of drawings
Fig. 1 is a kind of block schematic diagram of traditional active thin film transistor (TFT) (AMTFT) LCD.
Fig. 2 is in the active Thin Film Transistor-LCD of a kind of tradition, time schedule controller and source electrode driver array annexation synoptic diagram each other.
Fig. 3 is the block schematic diagram of the source electrode driver of the active Thin Film Transistor-LCD of a kind of tradition.
Fig. 4 is a kind of sequential chart of source electrode driver of traditional active Thin Film Transistor-LCD.
Fig. 5 is the time schedule controller and the source electrode driver array annexation synoptic diagram each other of a kind of active Thin Film Transistor-LCD of a preferred embodiment of the present invention.
Fig. 6 is a kind of active Thin Film Transistor-LCD (AMTFTLCD) of one embodiment of the invention, comprises time schedule controller and one source pole drive array and a panel of LCD.
Fig. 7 is the circuit box synoptic diagram that the interior start pulse of the source electrode driver of a preferred embodiment of the present invention produces circuit.
Fig. 8 is the signal timing diagram that the start pulse among Fig. 7 produces circuit.
100: active Thin Film Transistor-LCD 102: source electrode driver array
101: LCD panel of thin-film transistor 103: the gate pole driver array
104: Voltage Supply Device 105: time schedule controller
210: sequence controller 220: the source electrode driver array
2201～220n: source electrode driver DIO1, DIO2: initial pulse signals
CLK: operation clock signal DATA: display data signal
LD: horizontal bolt lock signal 300: source electrode driver
310: shift registor (Shift Register) 330: data bolt-lock unit
320: sampling working storage (Sample Register) 360: unit, numerical digit class specific revolution position (DAC)
340: keep working storage (Hold Register) 370: output buffer
350: position rank shift units (Level Shift) 380:Gamma device for generating voltage
510: time schedule controller 520: the source electrode driver array
5201～520n: source electrode driver 530: panel of LCD
600: active Thin Film Transistor-LCD (AMTFT LCD)
610: shift registor (Shift Register) 630: data bolt-lock unit
620: sampling working storage (Sample Register) 670: output buffer
640: keep working storage (Hold Register) 690: start pulse produces circuit
650: position rank shift units (Level Shift) 700: start pulse produces circuit
660: unit, numerical digit class specific revolution position (DAC) 710: open beginning sign indicating number circuit for detecting
680:Gamma device for generating voltage (Gamma Voltage Generator)
DIO: start pulse (Start Pulse) signal 720: synchronous counter
730: digital comparator 740: decoding circuit
Embodiment
Reach technological means and the effect that predetermined goal of the invention is taked for further setting forth the present invention, below in conjunction with accompanying drawing and preferred embodiment, to source electrode driver, source electrode driver array, driving circuit and its embodiment of display, structure, feature and the effect thereof that foundation the present invention proposes with this array, describe in detail as after.
For convenience of description, following LCD (LCD) is with active Thin Film Transistor-LCD (Active Matrix Thin Film Transistor LCD, AMTFT LCD) explanation, yet haveing the knack of this skill person all knows, the invention relates to a kind of driving circuit of display, therefore, be applicable to the display of any kind, comprise amorphous silicon film transistor (Amorphous Silicon Thin FilmTransistor) LCD, low temperature compound crystal silicon thin film transistor (TFT) (Low Tempera turePolysilicon Thin Film Transistor) LCD, LcoS (Liquid Crystalon Silicon) display driver, with organic light emitting diode display driver (OLED) or the like, all belong to category of the present invention.
Seeing also shown in Figure 5ly, is the time schedule controller 510 and source electrode driver array 520 annexation synoptic diagram each other of a kind of LCD (LiquidCrystal Display is hereinafter to be referred as LCD) of a preferred embodiment of the present invention.This source electrode driver array 520 comprise n source electrode driver (as shown 5201～520n).And time schedule controller 510 is connected with each source electrode driver 5201～520n, and provides a display data signal DATA that as shown in the figure an operation clock signal CLK, for example has the P bit and a horizontal bolt lock signal LD to each source electrode driver (5201～520n) respectively.Operation clock signal CLK, display data signal DATA and horizontal bolt lock signal LD are at same bus (BUS), and each source electrode driver (5201～520n) all are connected to this bus with received signal.And in one embodiment, these operation clock signals CLK, display data signal DATA and horizontal bolt lock signal LD can be a kind of differential voltage signal (Differential Voltage Signal), or a kind of transistor-transistor logic (Transistor-Transistor Logic, TTL) voltage signal.And each source electrode driver (as shown 5201～520n) most output channels are arranged all, to export panel of LCD to.
Present embodiment and conventional architectures difference shown in Figure 3 are, this time schedule controller 510 only send operation clock signal CLK, display data signal DATA and horizontal bolt lock signal LD give each source electrode driver (5201～520n), still but do not send so-called start pulse (Start Pulse) signal DIO1.And each source electrode driver (5201～520n) need not send start pulse (Start Pulse) signal DIO2 yet uses so that the next stage source electrode driver to be provided.In addition, present embodiment and conventional architectures difference shown in Figure 3 comprise that more having increased by one has for example position code signal P input of m bit.
The bit number of this position code signal P is source electrode driver (5201～520n) the quantity and deciding according to required definition.In the present embodiment, because need n source electrode driver, therefore, the bit number of position code signal P must be greater than can be with the number of binary representation n.And each source electrode driver (5201～520n) the position code signal P that received are according in the source electrode driver array 520, and designed source electrode driver drives and puts in order and decide, and are defined by these m bits.Source electrode driver 5201 as shown, the position code signal P that it received, then for decade represent 0, and source electrode driver 5202, the position code signal P that it received, then for decade represent 1, analogize on the right side by a left side according to the arrangement that source electrode driver drives, so source electrode driver 520n, the position code signal P that it received, then n-1 for representing with decade.Yet above-mentioned position code signal P design only is one embodiment of the invention.
In other design, can (5201～520n) set putting in order be adjusted position code signal P according to the source electrode driver of the source electrode driver array 520 that will drive.This feature is the source electrode driver array that known one-level is followed one-level, and by the source electrode driver of upper level transmit next stage source electrode driver one start pulse DIO the effect that can not reach.And set the putting in order that present embodiment is mentioned, for example, can be at n source electrode driver in the source electrode driver array 520, drive to put in order earlier and be the source electrode driver of odd number, then drive the source electrode driver of even number again, this designs according to an embodiment of the invention, is feasible design.
Seeing also shown in Figure 6ly, is a kind of active Thin Film Transistor-LCD (AMTFT LCD) 600 of one embodiment of the invention, comprises time schedule controller 510 and an one source pole drive array 520 and a panel of LCD 530.This source electrode driver array 520 comprise n source electrode driver (as shown 5201～520n).For describing the source electrode driver of one embodiment of the invention in detail, at this only at the circuit block diagram explanation of the source electrode driver 5201 of diagram source electrode driver array 520, yet other source electrode driver (as shown 5202～520n) all have identical framework.
This source electrode driver 5201, comprise a shift registor (Shift Register) 610, sampling working storage (Sample Register) 620 be connected to a data bolt-lock unit 630, keep working storage (Hold Register) 640, rank shift units (Level Shift) 650, one numerical digit class specific revolution position (Digital-to-Analog Corverter, DAC) unit 660, an output buffer 670, produce circuit 690 with a start pulse.And this numerical digit class specific revolution bit location 660 is connected to a Gamma device for generating voltage (Gamma Voltage Generator) 680.
This shift registor (Shift Register) 610 receives start pulses and produces start pulse (Start Pulse) the signal DIO that circuit 690 are produced, the control signal of distributing in proper order as data in order to this initial pulse signals of bolt-lock (Latch) DIO1.Display data signal DATA then is sent to sampling working storage 620 via data bolt-lock unit 630 and data bus (Data Bus), and is sent to storage working storage 640.And this keeps working storage 640 and receives horizontal bolt lock signal (Latch Signal represents with LD), and after adjusting rank, display data voltage of signals position through rank, position shift unit 650, is sent to unit, numerical digit class specific revolution position (DAC) 660.And Gamma device for generating voltage 680 receives an outside Gamma voltage, and is sent to unit, numerical digit class specific revolution position (DAC) 660 according to this, and as the reference that is adjusted into anaiog signal.And the adjustment display data signal after then will adjusting is sent to the panel 530 of Thin Film Transistor-LCD via output buffer 670.
Seeing also shown in Figure 7ly, is the circuit box synoptic diagram that start pulse in the source electrode driver of a preferred embodiment of the present invention produces circuit.This start pulse produces circuit 700, for example comprises opening beginning sign indicating number circuit for detecting 710, a synchronous counter 720, a digital comparator 730 and a decoding circuit 740.Wherein open beginning sign indicating number circuit for detecting 710 in order to receive operation clock signal CLK, display data signal DATA and the horizontal bolt lock signal LD that is transmitted by time schedule controller 510.Then produce an activation signal (Enable Signal, " EN " as shown in the figure), and be sent to coupled synchronous counter 720, begin counting for synchronous counter 720 according to these signals.And this synchronous counter 720 also receives horizontal bolt lock signal LD and operation clock signal CLK.
The operational example that opens beginning sign indicating number circuit for detecting 710 and synchronous counter 720 as, at Qi Shishi, after opening a beginning sign indicating number circuit for detecting 710 and receiving horizontal bolt lock signal LD, begin to detect display data signal DATA and beginning sign indicating number (S_code) whether occurs opening, and this LD signal is 0 with synchronous counter 720 removings simultaneously also.When open beginning sign indicating number circuit for detecting 710 detect display data signal DATA open beginning sign indicating number (S_code) after, open a beginning sign indicating number circuit for detecting 710 and promptly produce enable signal EN according to this and begin counting for synchronous counter 720.In one embodiment, this synchronous counter 720 can be a positive edge and triggers, and certainly, the personage who has the knack of this skill also understands can change a negative edge triggering into.The count results CNT of this synchronous counter 720 then is sent to digital comparator 730.
And decoding circuit 740 receives one and has multidigit unit, the position code signal P of m bit for example, and produce one source pole driver coding (POS) signal according to this, and pass to digital comparator 730.Because the source electrode driver array has most source electrode drivers, source electrode driver array 520 for example shown in Figure 6, have n source electrode driver 5201～520n, therefore, this position code signal P decides in the position of source electrode driver array according to each source electrode driver.For example, first source electrode driver in the source electrode driver array, its defined position code signal P then for represent with decade 0.According to putting in order that source electrode driver drives, the position code signal P that defines each source electrode driver respectively and received.Certainly, as previously mentioned, can adjust position code signal P value according to set putting in order among the other again embodiment.
With first source electrode driver, and defined position code signal P 0 is the example explanation.When receiving position code signal P when being 0, can transfer source driver coding (POS) signal 0 to digital comparator 730.Then, when the count results CNT of synchronous counter 720 is 0, sends start pulse (Start Pulse) signal DIO and give shift registor.And for example for second source electrode driver, and defined position code signal P is 1, therefore, source electrode driver coding (POS) signal is k.When the count results CNT of synchronous counter 720 is k, sends start pulse (Start Pulse) signal DIO and give shift registor.The rest may be inferred, and when for x source electrode driver, and defined position code signal P is x, and therefore, source electrode driver coding (POS) signal is x*k, and just x multiply by k.When the count results CNT of synchronous counter 720 is x*k, sends start pulse (Start Pulse) signal DIO and give shift registor.And k is defined herein as the data number of the required bolt-lock of each source electrode driver (Latch), the output channel number that just each source electrode driver had.After a complete bolt-lock of horizontal data finished, this moment, time schedule controller 510 was sent horizontal bolt lock signal LD, and for example the data of a line buffer (Line Buffer) to the analogy conversion, is exported a gray scale voltage to panel of LCD through numerical digit.
Seeing also shown in Figure 8ly, is the signal timing diagram that start pulse produces circuit among Fig. 7, below cooperates Fig. 7 to describe.At Qi Shishi, open beginning sign indicating number circuit for detecting 710 and when time T 0, receive horizontal bolt lock signal LD, promptly begin to detect display data signal DATA and beginning sign indicating number (S_code) whether occurs opening, and this LD signal is 0 with synchronous counter 720 removings simultaneously also.The dissimilar display of design consideration that this opens beginning sign indicating number (S_code) has different settings, and all after dates of several clock signals can send after horizontal bolt lock signal LD begins usually.
When this open beginning sign indicating number circuit for detecting 710 detect display data signal DATA open beginning sign indicating number (S_code) time, time T 1 as shown, open a beginning sign indicating number circuit for detecting 710 and promptly produce enable signal EN according to this and begin counting for synchronous counter 720, enable signal EN as shown transfers logic high potential to from logic low potential.In this embodiment, this synchronous counter 720 is that a positive edge triggers, certainly, if being a negative edge, triggers by this synchronous counter 720, then can with enable signal EN detect display data signal DATA open beginning sign indicating number (S_code) after, transfer logic low potential to from logic high potential, to trigger this synchronous counter 720.
The count results CNT of synchronous counter 720 then is sent to digital comparator 730.With first source electrode driver, and defined position code signal P 0 is the example explanation.Because position code signal P is 0, therefore can arrive digital comparator 730 by transfer source driver coding (POS) signal 0.Then, when the count results CNT of synchronous counter 720 is 0, sends start pulse (Start Pulse) signal DIO (1) and give shift registor.And for example for second source electrode driver, and defined position code signal P is 1, therefore, source electrode driver coding (POS) signal is k.When the count results CNT of synchronous counter 720 was k, just time T 2 was as shown sent the shift registor that start pulse (StartPulse) signal DIO (2) gives second source electrode driver.And when time T 3, send the shift registor that start pulse (Start Pulse) signal DIO (3) gives the 3rd source electrode driver.The rest may be inferred, and when for x source electrode driver, and defined position code signal P is x, and therefore, source electrode driver coding (POS) signal is (x-1) * k, and just x multiply by k.When the count results CNT of synchronous counter 720 is (x-1) * k, sends start pulse (Start Pulse) signal DIO and give shift registor.And k is defined herein as the data number of the required bolt-lock of each source electrode driver (Latch), the output channel number that just each source electrode driver had.After a complete bolt-lock of horizontal data finished, this moment, time schedule controller 510 was sent horizontal bolt lock signal LD, and for example the data of a line buffer (Line Buffer) to the analogy conversion, is exported a gray scale voltage to panel of LCD through numerical digit.
Flat display driving circuit of the present invention, the highest operating frequency that can improve existing flat-panel screens driving circuit is subject to the shortcoming of the progressive error of start pulse (Start Pulse) input signal and clock signal, and possesses following characteristics at least.At first, flat display driving circuit of the present invention is compared to traditional driving circuit, and it is higher to have a higher operating frequency.In addition, driving circuit of the present invention does not need the input of start pulse (Start Pulse) signal DIO1.Replacing, is to need according to data bolt-lock order, given each each source electrode driver certain location coded signal P.Therefore, can provide a kind of structure-improved of initial pulse signals, be subject to the problem of initial pulse signals, and can save conventional architectures in order to improve the cost that operating frequency increases with the highest operating frequency that improves the conventional planar display driver.
The above, it only is preferred embodiment of the present invention, be not that the present invention is done any pro forma restriction, though the present invention discloses as above with preferred embodiment, yet be not in order to limit the present invention, any those skilled in the art, in not breaking away from the technical solution of the present invention scope, when the structure that can utilize above-mentioned announcement and technology contents are made a little change or be modified to the equivalent embodiment of equivalent variations, but every content that does not break away from technical solution of the present invention, according to technical spirit of the present invention to any simple modification that above embodiment did, equivalent variations and modification all still belong in the scope of technical solution of the present invention.
Claims (47)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB2004100429687A CN100373443C (en) | 2004-06-04 | 2004-06-04 | Source driver, source driver array, driving circuit with source driver array and display |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB2004100429687A CN100373443C (en) | 2004-06-04 | 2004-06-04 | Source driver, source driver array, driving circuit with source driver array and display |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN1707595A true CN1707595A (en) | 2005-12-14 |
| CN100373443C CN100373443C (en) | 2008-03-05 |
Family
ID=35581472
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CNB2004100429687A Expired - Fee Related CN100373443C (en) | 2004-06-04 | 2004-06-04 | Source driver, source driver array, driving circuit with source driver array and display |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN100373443C (en) |
Cited By (20)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN100369105C (en) * | 2006-07-05 | 2008-02-13 | 友达光电股份有限公司 | Time schedule controller for controlling pixel quasi-position multitask display panel |
| CN100411003C (en) * | 2005-12-31 | 2008-08-13 | 义隆电子股份有限公司 | Source electrode driving mode of liquid crystal display |
| CN101527126B (en) * | 2008-03-07 | 2011-07-27 | 环旭电子股份有限公司 | Image regulating system and regulating method |
| CN102243836A (en) * | 2010-05-10 | 2011-11-16 | 三星电子株式会社 | Display panel data driver and display apparatus including same |
| CN101114429B (en) * | 2006-07-28 | 2012-01-18 | 奇美电子股份有限公司 | Flat panel display and image driving method thereof |
| CN102419962A (en) * | 2006-08-31 | 2012-04-18 | 株式会社半导体能源研究所 | Liquid crystal display device |
| CN101339727B (en) * | 2007-07-06 | 2012-07-04 | 瑞萨电子株式会社 | Display controller and method of controlling the same |
| CN102542976A (en) * | 2011-11-11 | 2012-07-04 | 友达光电股份有限公司 | Method for triggering source driver and display |
| CN102592566A (en) * | 2011-12-09 | 2012-07-18 | 友达光电股份有限公司 | Data driving device, corresponding operation method and corresponding display |
| CN101751890B (en) * | 2008-12-15 | 2012-10-10 | 乐金显示有限公司 | Liquid crystal display and method of driving the same |
| CN101751886B (en) * | 2008-12-15 | 2012-11-07 | 乐金显示有限公司 | Liquid crystal display and driving method thereof |
| CN102881246A (en) * | 2011-07-14 | 2013-01-16 | 乐金显示有限公司 | Flat panel display and driving circuit thereof |
| CN102930808A (en) * | 2011-08-08 | 2013-02-13 | 联咏科技股份有限公司 | Display panel driving device, operation method thereof and source driver thereof |
| CN103377609A (en) * | 2012-04-20 | 2013-10-30 | 刘鸿达 | Display control system and electronic device |
| CN105096906A (en) * | 2014-05-20 | 2015-11-25 | 联咏科技股份有限公司 | Visual signal transmission system |
| CN108694897A (en) * | 2017-06-09 | 2018-10-23 | 京东方科技集团股份有限公司 | Drive control method, component and display device |
| WO2018223919A1 (en) * | 2017-06-09 | 2018-12-13 | 京东方科技集团股份有限公司 | Configuration information setting method, assembly and display apparatus |
| WO2018223912A1 (en) * | 2017-06-09 | 2018-12-13 | 京东方科技集团股份有限公司 | Register value transmission method and transmitter, display device, and computer-readable storage medium |
| CN112530337A (en) * | 2019-09-18 | 2021-03-19 | 矽创电子股份有限公司 | Video data display device |
| TWI834265B (en) * | 2022-08-29 | 2024-03-01 | 大陸商集創北方（珠海）科技有限公司 | Self-testable column driver circuits, display devices and information processing devices |
Family Cites Families (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR0161918B1 (en) * | 1995-07-04 | 1999-03-20 | 구자홍 | Data driver of liquid crystal device |
| GB9706943D0 (en) * | 1997-04-04 | 1997-05-21 | Sharp Kk | Active matrix device circuits |
| JP3770360B2 (en) * | 1998-03-18 | 2006-04-26 | シャープ株式会社 | Liquid crystal display device, control circuit thereof, and liquid crystal display panel driving method |
| JP3691318B2 (en) * | 1999-09-30 | 2005-09-07 | シャープ株式会社 | Semiconductor device for driving display drive device, display drive device, and liquid crystal module using the same |
| JP3409768B2 (en) * | 2000-02-14 | 2003-05-26 | Ｎｅｃエレクトロニクス株式会社 | Display device circuit |
| CN100433100C (en) * | 2000-12-06 | 2008-11-12 | 索尼公司 | Timing generating circuit for display and display having the same |
| JP2002311880A (en) * | 2001-04-10 | 2002-10-25 | Nec Corp | Picture display device |
| JP4904641B2 (en) * | 2001-07-13 | 2012-03-28 | 日本電気株式会社 | LCD display control circuit |
-
2004
- 2004-06-04 CN CNB2004100429687A patent/CN100373443C/en not_active Expired - Fee Related
Cited By (39)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN100411003C (en) * | 2005-12-31 | 2008-08-13 | 义隆电子股份有限公司 | Source electrode driving mode of liquid crystal display |
| CN100369105C (en) * | 2006-07-05 | 2008-02-13 | 友达光电股份有限公司 | Time schedule controller for controlling pixel quasi-position multitask display panel |
| CN101114429B (en) * | 2006-07-28 | 2012-01-18 | 奇美电子股份有限公司 | Flat panel display and image driving method thereof |
| US11971638B2 (en) | 2006-08-31 | 2024-04-30 | Semiconductor Energy Laboratory Co., Ltd. | Liquid crystal display device |
| CN102419962B (en) * | 2006-08-31 | 2014-12-24 | 株式会社半导体能源研究所 | Liquid crystal display device |
| CN102419962A (en) * | 2006-08-31 | 2012-04-18 | 株式会社半导体能源研究所 | Liquid crystal display device |
| US11194203B2 (en) | 2006-08-31 | 2021-12-07 | Semiconductor Energy Laboratory Co., Ltd. | Liquid crystal display device |
| US10606140B2 (en) | 2006-08-31 | 2020-03-31 | Semiconductor Energy Laboratory Co., Ltd. | Liquid crystal display device |
| US10401699B2 (en) | 2006-08-31 | 2019-09-03 | Semiconductor Energy Laboratory Co., Ltd. | Liquid crystal display device |
| US10088725B2 (en) | 2006-08-31 | 2018-10-02 | Semiconductor Energy Laboratory Co., Ltd. | Liquid crystal display device |
| US9684215B2 (en) | 2006-08-31 | 2017-06-20 | Semiconductor Energy Laboratory Co., Ltd. | Liquid crystal display device |
| US9184183B2 (en) | 2006-08-31 | 2015-11-10 | Semiconductor Energy Laboratory Co., Ltd. | Liquid crystal display device |
| US8643586B2 (en) | 2006-08-31 | 2014-02-04 | Semiconductor Energy Laboratory Co., Ltd. | Liquid crystal display device |
| CN101339727B (en) * | 2007-07-06 | 2012-07-04 | 瑞萨电子株式会社 | Display controller and method of controlling the same |
| CN101527126B (en) * | 2008-03-07 | 2011-07-27 | 环旭电子股份有限公司 | Image regulating system and regulating method |
| CN101751890B (en) * | 2008-12-15 | 2012-10-10 | 乐金显示有限公司 | Liquid crystal display and method of driving the same |
| CN101751886B (en) * | 2008-12-15 | 2012-11-07 | 乐金显示有限公司 | Liquid crystal display and driving method thereof |
| CN102243836A (en) * | 2010-05-10 | 2011-11-16 | 三星电子株式会社 | Display panel data driver and display apparatus including same |
| US9111509B2 (en) | 2011-07-14 | 2015-08-18 | Lg Display Co., Ltd. | Display apparatus that generates black image signal in synchronization with the driver IC whose internal clock has the highest frequency when image/timing signals are not received |
| CN102881246B (en) * | 2011-07-14 | 2016-04-06 | 乐金显示有限公司 | Flat-panel monitor and driving circuit thereof |
| CN102881246A (en) * | 2011-07-14 | 2013-01-16 | 乐金显示有限公司 | Flat panel display and driving circuit thereof |
| CN102930808A (en) * | 2011-08-08 | 2013-02-13 | 联咏科技股份有限公司 | Display panel driving device, operation method thereof and source driver thereof |
| CN102542976A (en) * | 2011-11-11 | 2012-07-04 | 友达光电股份有限公司 | Method for triggering source driver and display |
| CN102592566A (en) * | 2011-12-09 | 2012-07-18 | 友达光电股份有限公司 | Data driving device, corresponding operation method and corresponding display |
| CN102592566B (en) * | 2011-12-09 | 2014-07-09 | 友达光电股份有限公司 | Data driving device, corresponding operation method and corresponding display |
| CN103377609A (en) * | 2012-04-20 | 2013-10-30 | 刘鸿达 | Display control system and electronic device |
| CN105096906A (en) * | 2014-05-20 | 2015-11-25 | 联咏科技股份有限公司 | Visual signal transmission system |
| WO2018223926A1 (en) * | 2017-06-09 | 2018-12-13 | 京东方科技集团股份有限公司 | Drive control method, assembly and display apparatus |
| CN109036328A (en) * | 2017-06-09 | 2018-12-18 | 京东方科技集团股份有限公司 | Register value transmission method and component, display device |
| CN109036300A (en) * | 2017-06-09 | 2018-12-18 | 京东方科技集团股份有限公司 | Configuration information setting method, component and display device |
| WO2018223912A1 (en) * | 2017-06-09 | 2018-12-13 | 京东方科技集团股份有限公司 | Register value transmission method and transmitter, display device, and computer-readable storage medium |
| US11062634B2 (en) | 2017-06-09 | 2021-07-13 | Beijing Boe Display Technology Co., Ltd. | Drive control method, assembly and display device |
| CN109036328B (en) * | 2017-06-09 | 2021-09-03 | 京东方科技集团股份有限公司 | Register value transmission method and assembly and display device |
| WO2018223919A1 (en) * | 2017-06-09 | 2018-12-13 | 京东方科技集团股份有限公司 | Configuration information setting method, assembly and display apparatus |
| US11250809B2 (en) | 2017-06-09 | 2022-02-15 | Beijing Boe Display Technology Co., Ltd. | Configuration information setting method and component, and display device |
| US11302281B2 (en) | 2017-06-09 | 2022-04-12 | Beijing Boe Display Technology Co., Ltd. | Register value transmission method and transmitter, display device and computer readable storage medium |
| CN108694897A (en) * | 2017-06-09 | 2018-10-23 | 京东方科技集团股份有限公司 | Drive control method, component and display device |
| CN112530337A (en) * | 2019-09-18 | 2021-03-19 | 矽创电子股份有限公司 | Video data display device |
| TWI834265B (en) * | 2022-08-29 | 2024-03-01 | 大陸商集創北方（珠海）科技有限公司 | Self-testable column driver circuits, display devices and information processing devices |
Also Published As
| Publication number | Publication date |
|---|---|
| CN100373443C (en) | 2008-03-05 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN1707595A (en) | Source driver, source driver array, driving circuit with the array and display | |
| CN1282025C (en) | Field sequence driving liquid crystal display device capable of increasing bright and suppressing non-eveness and its driving method | |
| CN1845235A (en) | Improvement of Inverted Drive LCD | |
| CN1305019C (en) | Display driver and photoelectric apparatus | |
| CN1514426A (en) | image display device | |
| CN1287350C (en) | Image display device and image display method, and image display programme | |
| CN1447302A (en) | Indicator and its drive method | |
| CN1684132A (en) | Light-emitting display, driving method thereof, and light-emitting display panel | |
| CN101075417A (en) | Displaying apparatus using data line driving circuit and data line driving method | |
| CN1624737A (en) | Display device, its driving circuit and its driving method | |
| CN1766972A (en) | Scan driver, light emitting display using same, and driving method thereof | |
| CN1815545A (en) | Gate driver, display device having the same and method of driving the same | |
| CN1581256A (en) | Signal conversion circuit and displaying device | |
| CN1694143A (en) | Column driver and flat panel display with same | |
| CN1940645A (en) | Apparatus and method for transmission data, apparatus and method for driving image display device using the same | |
| CN1758322A (en) | Display element drive unit, display device including the same, and display element drive method | |
| CN1776801A (en) | Driver chip for a display device and display device having the same | |
| CN1306464C (en) | Planel display | |
| CN1819005A (en) | Display and related driving method | |
| CN101055702A (en) | Display device and its capacitive load driving circuit | |
| CN101075399A (en) | Method and device for low power consumption source driver | |
| CN1658268A (en) | Timing controller and method for reducing liquid crystal display operating current | |
| CN1766979A (en) | Apparatus and method for driving display panel to reduce power consumption of gray scale voltage generator | |
| CN1595479A (en) | Display driver and electro-optical device | |
| CN1904983A (en) | Driving apparatus and display device including the same and method of driving the same |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| C17 | Cessation of patent right | ||
| CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20080305 Termination date: 20130604 |