CN1697088A - Dynamic shift register - Google Patents
Dynamic shift register Download PDFInfo
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- CN1697088A CN1697088A CN 200410027227 CN200410027227A CN1697088A CN 1697088 A CN1697088 A CN 1697088A CN 200410027227 CN200410027227 CN 200410027227 CN 200410027227 A CN200410027227 A CN 200410027227A CN 1697088 A CN1697088 A CN 1697088A
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Abstract
A register of dynamic displacement consists of the first unit including a logic signal input end and the first external controllable transmission gate as well as the second unit including the second controllable transmission gate and a logic signal output end. It is featured as setting the first holding circuit connected to output end of the first transmission gate on the first unit and setting the second holding circuit connected to output end of the second transmission gate on the second unit.
Description
[technical field]
The invention relates to a kind of shift register, particularly a kind of dynamic shift register.
[background technology]
Current thin film transistor liquid crystal display (TFT-LCD) (TFT-LCD) becomes the standard output device of various digital products gradually, and it need design suitable driving circuit to guarantee its steady operation.
Usually, liquid crystal display drive circuit can be divided into two parts, i.e. source electrode drive circuit and gate driver circuit.Source electrode drive circuit is used to control the GTG of each pixel cell of TFT-LCD, and gate driver circuit then is used to control the scanning of each pixel cell.Two kinds of driving circuits are all used shift register as core circuit.
Bit shift register is can the delay data signal and preserve the circuit of binary data signal, and it generally is made of the multi-level pmultistage circuit that connects successively.
At the bit shift register duration of work, any time, each of bit shift register grade circuit all can be preserved a binary bit data, and this Bit data is distinguished the high voltage or the low-voltage of output node in corresponding each grade circuit, and its holding time is the one-period of clock pulse signal.This clock pulse signal drives each grade circuit simultaneously, makes the output terminal of each grade circuit periodically export this bit data to the next stage circuit that links to each other when each clock period finishes.Under the clock pulse signal continuous drive, this bit data is each grade circuit by bit shift register successively, promptly from the input end of the first order circuit output terminal of one-level circuit to the end.In each clock period, the input end of each grade circuit receives a new bit data, and the output terminal of this grade circuit displacement is simultaneously also exported a bit data of itself preserving and arrived the next stage circuit.
Shift register can be divided into two kinds of static shift register and dynamic shift registers usually, and static shift register allows to apply logical signal at any time usually, and the output of generation data immediately result.Dynamic shift register allows to apply the logical signal synchronous with clock signal usually, and the logical signal that output and clock signal are synchronous, though static shift register is having more superiority aspect the data of preservation, realize the required transistor of static shift register than realizing that the required transistor of dynamic shift register is many.
With reference to figure 1, it is a kind of typical dynamic shift register, this dynamic shift register 100 comprises the first module 11 and second unit 12, first module 11 comprises that a logic signal input end 101, first transmission gate 111 and first phase inverter, 121, the second unit 12 comprise second transmission gate 112, second phase inverter 122 and logical signal output terminal 105.This first transmission gate 111 comprises that an input end, an output terminal, a P type isolated-gate FET (P-type Insulated Gate Field Effect Transistor) the 181 and the one N type isolated-gate FET (N-type Insulated Gate Field Effect Transistor) 171, the second transmission gates 112 comprise an input end, an output terminal, the 2nd P type isolated-gate FET 182 and the 2nd N type isolated-gate FET 172.
This logic signal input end 101 is connected to the input end of this first transmission gate 111, the output terminal of this first transmission gate 111 is connected to the input end of this first phase inverter 121, the output terminal of this first phase inverter 121 is connected to the input end of this second transmission gate 112, the output terminal of this second transmission gate 112 is connected to the input end of this second phase inverter 122, and the output terminal of this second phase inverter 122 is connected to logical signal output terminal 105.In this first transmission gate 111, the drain electrode of the source electrode of this P type isolated-gate FET 181 and this N type isolated-gate FET 171 all is connected to the input end of this first transmission gate 111, the source electrode of the drain electrode of this P type isolated-gate FET 181 and this N type isolated-gate FET 171 all is connected to the output terminal of this first transmission gate 111, in this second transmission gate 112, the input end of this second transmission gate 112 is all received in the drain electrode of the source electrode of this P type isolated-gate FET 182 and this N type isolated-gate FET 172, and the source electrode of the drain electrode of this P type isolated-gate FET 182 and this N type isolated-gate FET 172 is all received the output terminal of this second transmission gate 112.
The complementary clock signal XCLK that clock signal clk and it is provided is behind the grid of the grid of this first transmission gate 111 and this second transmission gate 112, this P type isolated-gate FET 181 and this N type isolated-gate FET 171 allow the logical signal of this logic signal input end 101 to be transferred to the output terminal of this first transmission gate 111 from the input end of this first transmission gate 111, this logical signal appears at the input end of second transmission gate 112 after by first phase inverter 121 then, simultaneously, this P type isolated-gate FET 182 and this N type isolated-gate FET 172 allow these logical signals to be transferred to the output terminal of second transmission gate 112 from the input end of second transmission gate 112, then by this second phase inverter 122 to this logical signal output terminal 105.
After each cycle internal clock signal CLK and its complementary clock signal XCLK stop, first transmission gate 111 is closed, the voltage of the output terminal of first transmission gate 111 is the attitude of floating, this voltage only depends on this P type isolated-gate FET 181 in this first phase inverter 121 and this first transmission gate 111 and the high impedance of this N type isolated-gate FET 171 keeping, so this voltage is subjected to the influence of other ghost effect easily.Equally, after each cycle internal clock stopped, this second transmission gate 112 was closed, and the voltage of the output terminal of this second transmission gate 112 is the attitude of floating, and this voltage also is subjected to the influence of other ghost effect easily.More stable for drive signal preservation in the TFT-LCD driving circuit, need provide a kind of each cycle clock to stop the back logical signal and preserve more stable dynamic shift register.
[summary of the invention]
The object of the present invention is to provide a kind of each cycle clock to stop the back data and preserve more stable dynamic shift register.
The technical scheme of technical solution problem of the present invention is: a kind of dynamic shift register, comprise first module and Unit second, first module comprises first transmission gate of a logic signal input end and external controllable system, this first transmission gate comprises an input end and an output terminal, Unit second comprises second transmission gate and the logical signal output terminal of external controllable system, this second transmission gate comprises an input end and an output terminal, this logic signal input end is connected to the input end of first transmission gate, the output terminal of this first transmission gate is connected with the input end of this second transmission gate, the output terminal of this second transmission gate is connected to this logical signal output terminal, it is characterized in that this first module further comprises one first holding circuit, this first holding circuit is connected to the output terminal of first transmission gate, this Unit second further comprises one second holding circuit, and this second holding circuit is connected to the output terminal of second transmission gate.
Compared to prior art, dynamic shift register of the present invention is after adopting holding unit, after each cycle internal clock stops, logical signal in this dynamic shift register can both be continued to keep by this holding circuit, therefore after dynamic shift register of the present invention realized that each cycle internal clock stops, data were preserved stable purpose.
In addition, series connection one transmission gate can reduce the power consumption that this dynamic shift register keeps logical signal in first holding unit and second holding unit.
[description of drawings]
Fig. 1 is the circuit diagram of prior art dynamic shift register.
Fig. 2 is the first embodiment circuit diagram of dynamic shift register of the present invention.
Fig. 3 A, Fig. 3 B and Fig. 3 C are the working timing figures of dynamic shift register shown in Figure 2.
Fig. 4 is the second embodiment circuit diagram of dynamic shift register of the present invention.
Fig. 5 A, Fig. 5 B and Fig. 5 C are the working timing figures of dynamic shift register shown in Figure 4.
[embodiment]
Please refer to Fig. 2, it is the circuit diagram of dynamic shift register first embodiment of the present invention, this dynamic shift register 200 comprises the first module 21 and second unit 22, first module 21 comprises first transmission gate 211 of a logic signal input end 201, external controllable system and second transmission gate 212, second holding circuit 232 and the logical signal output terminal 205 that first holding circuit, 231, the second unit 22 comprise an external controllable system.This first transmission gate 211 comprises an input end, an output terminal, a P type isolated-gate FET 281 and a N type isolated-gate FET N type isolated-gate FET 271, this second transmission gate 212 comprises an input end, an output terminal, the 2nd P type isolated-gate FET 282 and the 2nd N type isolated-gate FET 272, this first holding circuit 231 comprises first phase inverter 221 and second phase inverter 222, and this second holding circuit 232 comprises the 3rd phase inverter 223 and the 4th phase inverter 224.
This logic signal input end 201 is connected to the input end of this first transmission gate 211, the output terminal of this first transmission gate 211 is connected to the input end of this second transmission gate 212, the output terminal of this second transmission gate 212 is connected to this logic signal input end 205, this first holding circuit 231 is connected to the output terminal of this first transmission gate 211, and this second holding circuit 232 is connected to the output terminal of this second transmission gate 212.
In this first transmission gate 211, the drain electrode of the source electrode of the one P type isolated-gate FET 281 and this N type isolated-gate FET 271 all is connected to the input end of this first transmission gate 211, and the source electrode of the drain electrode of a P type isolated-gate FET 281 and this N type isolated-gate FET 271 all is connected to the output terminal of this first transmission gate 211.In this second transmission gate 212, the input end of this second transmission gate 212 is all received in the drain electrode of the source electrode of the 2nd P type isolated-gate FET 282 and the 2nd N type isolated-gate FET 272, and the source electrode of the drain electrode of the 2nd P type isolated-gate FET 282 and the 2nd N type isolated-gate FET 272 is all received the output terminal of this second transmission gate 212.In this first holding circuit 231, the output terminal of this first phase inverter 221 is connected to the input end of this second phase inverter 222, and the output terminal of the input end of this first phase inverter 221 and this second phase inverter 222 all is connected to the output terminal of this first transmission gate 211.In this second holding circuit 232, the output terminal of the 3rd phase inverter 223 is connected to this input end of 224, and the input end of the 3rd phase inverter 223 and this output terminal of 224 all are connected to the output terminal of this second transmission gate 212.
The complementary clock signal XCLK that clock signal clk and it is provided is behind the grid of the grid of this first transmission gate 211 and second transmission gate 212, first transmission gate 211 and second transmission gate 212 are all opened, therefore this first transmission gate 211 allows the output terminal of the logical signal of logic signal input end 201 by these first transmission gate, 211 these first transmission gates 211 of arrival, and this first holding circuit 231 that is connected with the output terminal of this first transmission gate 211 can keep the logical signal of the output terminal of this first transmission gate 211 constantly.Simultaneously, this second transmission gate 212 allows this logical signal to arrive the output terminal of this second transmission gate 212 by these second transmission gate, 212 backs, second holding circuit 232 that is connected with the output terminal of this second transmission gate 212 can keep the logical signal of the output terminal of this this second transmission gate 212 constantly, and this logical signal offers logical signal output terminal 205 then.
Please refer to Fig. 3 A, Fig. 3 B and Fig. 3 C, is the working timing figure of dynamic shift register of the present invention 200 shown in Figure 2.Among Fig. 3 A, " CLOCK " provides the clock signal to the grid of the grid of first transmission gate 211 and second transmission gate 212, and " D " is the logical signal of logic signal input end 201 among Fig. 3 B, and " Q " is the logical signal of logical signal output terminal 205 among Fig. 3 C.
T
nConstantly, logical signal D is a high voltage, and logical signal Q is a low-voltage, T
nWhen the rising edge of clock signal C LOCK arrives constantly, first transmission gate 211 and second transmission gate 212 are opened, logical signal D offers logical signal output terminal 205 by first transmission gate 211 and second transmission gate 212, so logical signal Q changes high voltage into and keeps this high voltage from low-voltage.T
N+1Constantly, logical signal D is a low-voltage, and logical signal Q is a high voltage, T
N+1When the rising edge of clock signal C LOCK arrives constantly, first transmission gate 211 and second transmission gate 212 are opened, logical signal D offers logical signal output terminal 205 by first transmission gate 211 and second transmission gate 212, so logical signal Q changes low-voltage into and keeps this low-voltage from high voltage.T
N+2Constantly, logical signal D is a high voltage, and logical signal Q is a low-voltage, T
N+2When the rising edge of clock signal C LOCK arrives constantly, first transmission gate 211 and second transmission gate 212 are opened, logical signal D offers logical signal output terminal 205 by first transmission gate 211 and second transmission gate 212, so logical signal Q changes high voltage into and keeps this high voltage from low-voltage.T
N+3Constantly, logical signal D is a low-voltage, and logical signal Q is a high voltage, T
N+3When the rising edge of clock signal C LOCK arrives constantly, first transmission gate 211 and second transmission gate 212 are opened, logical signal D offers logical signal output terminal 205 by first transmission gate 211 and second transmission gate 212, so logical signal Q changes low-voltage into and keeps this low-voltage from high voltage.Compare with prior art, after dynamic shift register 200 of the present invention adopts holding unit, after each cycle internal clock stops, logical signal in this dynamic shift register 200 can both be continued to keep, after dynamic shift register 200 therefore of the present invention realized that each cycle internal clock stops, data were preserved stable purpose.
Because after each cycle internal clock stops, the logical signal in this dynamic shift register 200 is continued to keep, but should continue to keep action to increase the power consumption of this dynamic shift register 200.
At the too high problem of power consumption, the present invention's transmission gate of connecting respectively in first holding unit and second holding unit, this two transmission gate can reduce the power consumption that this dynamic shift register 200 keeps logical signals.
Please refer to Fig. 4, it is the circuit diagram of dynamic shift register second embodiment of the present invention, this dynamic shift register 400 comprises the first module 41 and second unit 42, first module 41 comprises first transmission gate 411 of a logic signal input end 401, an external controllable system and second transmission gate 412, second holding circuit 432 and the logical signal output terminal 405 that one first holding circuit, 431, the second unit 42 comprise an external controllable system.This first transmission gate 411 comprises an input end, an output terminal, a P type isolated-gate FET 481 and a N type isolated-gate FET 471, this second transmission gate 412 comprises an input end, an output terminal, the 2nd P type isolated-gate FET 482 and the 2nd N type isolated-gate FET 472, this first holding circuit 431 comprises first phase inverter 421, second phase inverter 422 and the 3rd transmission gate 413, and this second holding circuit 432 comprises the 3rd phase inverter 423, the 4th phase inverter 424 and the 4th transmission gate 414.The 3rd transmission gate 413 comprises that an input end, an output terminal, the 3rd P type isolated-gate FET 483 and the 3rd N type isolated-gate FET 473, the four transmission gates 414 comprise an input end, an output terminal, the 4th P type isolated-gate FET 484 and the 4th N type isolated-gate FET 474.
This logic signal input end 401 is connected to the input end of this first transmission gate 411, the output terminal of this first transmission gate 411 is connected to the input end of this second transmission gate 412, this first holding circuit 431 is connected to the output terminal of this first transmission gate 411, this second holding circuit 432 is connected to the output terminal of this second transmission gate 412, and this logical signal output terminal 405 is connected to second holding circuit 432.
In this first transmission gate 411, the drain electrode of the source electrode of the one P type isolated-gate FET 481 and a N type isolated-gate FET 471 all is connected to the input end of this first transmission gate 411, and the source electrode of the drain electrode of a P type isolated-gate FET 481 and a N type isolated-gate FET 471 all is connected to the output terminal of this first transmission gate 411.
In this second transmission gate 412, input end is all received in the drain electrode of the source electrode of the 2nd P type isolated-gate FET 482 and the 2nd N type isolated-gate FET 472, and the source electrode of the drain electrode of the 2nd P type isolated-gate FET 482 and the 2nd N type isolated-gate FET 472 is all received output terminal.
In this first holding circuit 431, this first phase inverter 421, second phase inverter 422 and the 3rd transmission gate 413 are connected successively, promptly the output terminal of this first phase inverter 421 is connected to the input end of this second phase inverter 422, the output terminal of this second phase inverter 422 is connected to the input end of the 3rd transmission gate 413, and the output terminal of the input end of this first phase inverter 421 and the 3rd transmission gate 413 all is connected to the output terminal of this first transmission gate 411.
In this second holding circuit 432, the 3rd phase inverter 423, the 4th phase inverter 424 and the 4th transmission gate 414 are connected successively, promptly the output terminal of the 3rd phase inverter 423 is connected to the input end of the 4th phase inverter 424, the output terminal of the 4th phase inverter 424 is connected to the input end of the 4th transmission gate 414, and the output terminal of the input end of the 3rd phase inverter 423 and the 4th transmission gate 414 all is connected to the output terminal of this second transmission gate 412.This logical signal output terminal 405 is connected to the output terminal of the 4th phase inverter 424.
In the 3rd transmission gate 413, the drain electrode of the source electrode of the 3rd P type isolated-gate FET 483 and the 3rd N type isolated-gate FET 473 all is connected to the input end of the 3rd transmission gate 413, and the source electrode of the drain electrode of the 3rd P type isolated-gate FET 483 and the 3rd N type isolated-gate FET 473 all is connected to the output terminal of the 3rd transmission gate 413.
In the 4th transmission gate 414, input end is all received in the drain electrode of the source electrode of the 4th P type isolated-gate FET 484 and the 4th N type isolated-gate FET 474, and the source electrode of the drain electrode of the 4th P type isolated-gate FET 484 and the 4th N type isolated-gate FET 474 is all received output terminal.
During work, provide clock signal clk and its complementary clock signal XCLK in the grid of this first transmission gate 411, the grid of second transmission gate 412, behind the grid of the grid of the 3rd transmission gate 413 and the 4th transmission gate 414, this first transmission gate 411, second transmission gate 412, the 3rd transmission gate 413 and the 4th transmission gate 414 are all opened, this first holding circuit 431 and second holding circuit 432 keep the logical signal of these second transmission gate, 412 output terminals after a period of time, this first transmission gate 411 and second transmission gate 412 allow the output terminal of the logical signal of this logic signal input end 401 by this first transmission gate 411 and second transmission gate, 412 these second transmission gates 412 of arrival simultaneously, and logical signal offers logical signal output terminal 405 by the output terminal of the 4th phase inverter 424 in this second holding circuit 432 then.
Please refer to Fig. 5 A, Fig. 5 B and Fig. 5 C, is the working timing figure of dynamic shift register of the present invention 400 shown in Figure 4.Among Fig. 5 A, " CLOCK " provides the clock signal to this first transmission gate 411, second transmission gate 412, the 3rd transmission gate 413 and the 4th transmission gate 414, " D " is the logical signal of logic signal input end 401 among Fig. 5 B, and " Q " is the pulse signal of logical signal output terminal 405 among Fig. 5 C.
T
nConstantly, logical signal D is a high voltage, logical signal Q low-voltage, T
nWhen the rising edge of clock signal C LOCK arrives constantly, this first transmission gate 411, second transmission gate 412, the 3rd transmission gate 413, the 4th transmission gate 414 is all opened, because of the 3rd transmission gate 413 and 414 unlatchings of the 4th transmission gate, 432 pairs of these second transmission gate, 412 output terminals discharges of this first holding circuit 431 and second holding circuit, simultaneously, because of this first transmission gate 411 and 412 unlatchings of second transmission gate, logical signal D charges to these second transmission gate, 412 output terminals by this first transmission gate 411 and second transmission gate, 412 backs, the low-voltage of these second transmission gate, 412 output terminals changes high voltage into after decline a period of time as a result, this voltage changes by offering logical signal output terminal 405 after the 3rd phase inverter 423 and 424 delays of the 4th phase inverter then, changes high voltage so the low-voltage of logical signal Q descends into after a period of time.T
N+1Constantly, logical signal D is a low-voltage, and logical signal Q is a high voltage, T
N+1When the rising edge of clock signal C LOCK arrives constantly, this first transmission gate 411, second transmission gate 412, the 3rd transmission gate 413 and the 4th transmission gate 414 are all opened, because of the 3rd transmission gate 413 and 414 unlatchings of the 4th transmission gate, 432 pairs of these second transmission gate, 412 output terminals chargings of this first holding circuit 431 and second holding circuit, simultaneously, because of this first transmission gate 411 and 412 unlatchings of second transmission gate, logical signal D is by this first transmission gate 411 and 412 pairs of these second transmission gate, 412 output terminals discharges of this second transmission gate, the high voltage of these second transmission gate, 412 output terminals changes low-voltage into after rising a period of time as a result, this this voltage changes by offering logical signal output terminal 405 after the 3rd phase inverter 423 and 424 delays of the 4th phase inverter then, changes low-voltage so the high voltage of logical signal Q rises into after a period of time.T
N+2Constantly, logical signal D is a high voltage, logical signal Q low-voltage, T
N+2When the rising edge of clock signal C LOCK arrives constantly, this first transmission gate 411, second transmission gate 412, the 3rd transmission gate 413, the 4th transmission gate 414 is all opened, because of the 3rd transmission gate 413 and 414 unlatchings of the 4th transmission gate, 432 pairs of these second transmission gate, 412 output terminals discharges of this first holding circuit 431 and second holding circuit, simultaneously, because of this first transmission gate 411 and 412 unlatchings of second transmission gate, logical signal D charges to these second transmission gate, 412 output terminals by this first transmission gate 411 and second transmission gate, 412 backs, the low-voltage of these second transmission gate, 412 output terminals changes high voltage into after decline a period of time as a result, this voltage changes by offering logical signal output terminal 405 after the 3rd phase inverter 423 and 424 delays of the 4th phase inverter then, changes high voltage so the low-voltage of logical signal Q descends into after a period of time.T
N+3Constantly, logical signal D is a low-voltage, and logical signal Q is a high voltage, T
N+3When the rising edge of clock signal C LOCK arrives constantly, this first transmission gate 411, second transmission gate 412, the 3rd transmission gate 413 and the 4th transmission gate 414 are all opened, because of the 3rd transmission gate 413 and 414 unlatchings of the 4th transmission gate, 432 pairs of these second transmission gate, 412 output terminals chargings of this first holding circuit 431 and second holding circuit, simultaneously, because of this first transmission gate 411 and 412 unlatchings of second transmission gate, logical signal D is by this first transmission gate 411 and 412 pairs of these second transmission gate, 412 output terminals discharges of second transmission gate, the high voltage of these second transmission gate, 412 output terminals changes low-voltage into after rising a period of time as a result, this voltage changes by offering logical signal output terminal 405 after the 3rd phase inverter 423 and 424 delays of the 4th phase inverter then, changes low-voltage so the high voltage of logical signal Q rises into after a period of time.
By analyzing as can be known: first holding circuit 431 and second holding circuit 432 are connected respectively behind the 3rd transmission gate 413 and the 4th transmission gate 414 in the dynamic shift register 400 of second embodiment of the invention, only when arriving, implements rising edge clock to keep action, keep the logical signal in this dynamic shift register, therefore can reduce the power consumption that this dynamic shift register keeps logical signal, and this logical signal output terminal 405 is connected to the output terminal of the 4th phase inverter 424, exports after the logical signal of these second transmission gate, 412 output terminals can be delayed a period of time.Clearly, this dynamic shift register 400 can be realized the basic function of common dynamic shift register.Promptly according to clock signal displacement memory data signal and outputting data signals.
Claims (7)
1. a dynamic shift register comprises:
First module, this first module comprise first transmission gate of a logic signal input end and an external controllable system, and this first transmission gate comprises an input end and an output terminal, and this logic signal input end is connected with this first transmission gate input end;
Unit second, this Unit second comprises second transmission gate and a logical signal output terminal of an external controllable system, this second transmission gate comprises an input end and an output terminal, the input end of this second transmission gate is connected to the output terminal of this first transmission gate, and the output terminal of this second transmission gate is connected to this logical signal output terminal;
It is characterized in that: this first module further comprises one first holding circuit, this first holding circuit is connected to the output terminal of first transmission gate, this Unit second further comprises one second holding circuit, and this second holding circuit is connected to the output terminal of second transmission gate.
2. dynamic shift register as claimed in claim 1, it is characterized in that: this first holding circuit comprises first phase inverter and second phase inverter, the input end of this second phase inverter is connected to the output terminal of this first phase inverter, and the output terminal of the input end of this first phase inverter and this second phase inverter all is connected to the output terminal of this first module; This second holding circuit comprises the 3rd phase inverter and the 4th phase inverter, and the input end of the 4th phase inverter is connected to the output terminal of the 3rd phase inverter, and the output terminal of the input end of the 3rd phase inverter and the 4th phase inverter all is connected to the output terminal of this Unit second.
3. dynamic shift register as claimed in claim 1 is characterized in that: this first transmission gate and this second transmission gate all comprise isolated-gate FET.
4. dynamic shift register as claimed in claim 1 is characterized in that: this dynamic shift register further comprises an external circuit, is used to control the on off state of first transmission gate and second transmission gate.
5. dynamic shift register as claimed in claim 1, it is characterized in that: this first holding circuit comprises first phase inverter, second phase inverter and the 3rd transmission gate, the 3rd transmission gate comprises an input end and an output terminal, the output terminal of this first phase inverter is connected to the input end of this second phase inverter, the output terminal of this second phase inverter is connected to the input end of the 3rd transmission gate, and the input end of the output terminal of the 3rd transmission gate and this first phase inverter all is connected to the output terminal of this first transmission gate; This second holding circuit comprises the 3rd phase inverter, the 4th phase inverter and the 4th transmission gate, the 4th transmission gate comprises an input end and an output terminal, the output terminal of the 3rd phase inverter is connected to the input end of the 4th phase inverter, the output terminal of the 4th phase inverter is connected to the input end of the 4th transmission gate, and the input end of the output terminal of the 4th transmission gate and the 3rd phase inverter all is connected to the output terminal of this second transmission gate.
6. dynamic shift register as claimed in claim 5 is characterized in that: this dynamic shift register comprises that further an external circuit is used to control the on off state of first transmission gate, second transmission gate, the 3rd transmission gate and the 4th transmission gate.
7. dynamic shift register as claimed in claim 5 is characterized in that: this logical signal output terminal is connected to the output terminal of the 4th phase inverter.
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| Application Number | Priority Date | Filing Date | Title |
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| CN 200410027227 CN1697088A (en) | 2004-05-10 | 2004-05-10 | Dynamic shift register |
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| Application Number | Priority Date | Filing Date | Title |
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| CN 200410027227 CN1697088A (en) | 2004-05-10 | 2004-05-10 | Dynamic shift register |
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| CN1697088A true CN1697088A (en) | 2005-11-16 |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103366661A (en) * | 2012-03-30 | 2013-10-23 | 群康科技(深圳)有限公司 | An image display system and a bidirectional shift register circuit |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103366661A (en) * | 2012-03-30 | 2013-10-23 | 群康科技(深圳)有限公司 | An image display system and a bidirectional shift register circuit |
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