CN1687902A - Embedded real-time simulation platform - Google Patents
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- CN1687902A CN1687902A CN 200510025331 CN200510025331A CN1687902A CN 1687902 A CN1687902 A CN 1687902A CN 200510025331 CN200510025331 CN 200510025331 CN 200510025331 A CN200510025331 A CN 200510025331A CN 1687902 A CN1687902 A CN 1687902A
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Abstract
The invention is an embedded real-time simulation platform, comprising: two processors, i.e. microprocessor and DSP; keyboard universal I/O port connected with the microprocessor; flash memory, second extended interface, latch and optical coupling circuit, all connected with the microprocessor through PLD and bus buffer; LAN controller and third extended interface both connected with the microprocessor through PLD and serial peripheral interface bus; serial EEPROM and first extended interface both connected with the microprocessor through PLD and internal IC bus; external interface of the serial interface, static memory as data space and static memory as program space, all connected with the DSP. The invention provides a flexible simulation platform with multiple equipment interfaces, high simulating and calculating accuracy, and good realtimeness of signal input.
Description
Technical field
The present invention relates to a kind of emulation platform, relate in particular to a kind of embedded real-time simulation platform.
Background technology
Formerly in the technology, emulation platform has remote terminal able to programme (Programmable RemoteTerminal), programmable logic controller (PLC) (Programmable Logic Controller), industrial computer to add multiple modes such as data capture card.The emulation of watercraft engine room and propulsion system is the real-time emulation systems of one and half material objects at ring, wherein existing virtual propulsion system promptly operate in the mathematical model on the simulation computer, real console panel platform, physical display device are arranged again, are a kind of canonical systems that integrates real-time control and high-speed computation function.The Subsystem in Marine Engine Simulator of shipping simulation centre early development success adopts industrial computer to add the mode of data capture card, with industrial computer as simulation computer, constitute the core of whole simulation system, finish input and output by data collecting card, carry out exchanges data with the external world, and also all directly bear by industrial computer to the processing of data with to the control of input and output.When the model more complicated of simulation object, because the processor of industrial computer is the general purpose personal computer processor, it is low to special-purpose digital signal processor (DSP) chip of digital signal processing efficiency.Because complicated realistic model computing is more time-consuming, to having relatively high expectations of processor digital signal processing capability, and the general processor processing power of industrial computer is limited, and emulation application is subjected to installing the restriction of this class non-real time operating system of superincumbent form (Windows) again, the degree of accuracy of emulation and real-time are difficult to obtain satisfactory to both parties, can only exchange approximate real-time for by the way of sacrificing simulation accuracy usually.Like this, want to improve the degree of accuracy and the real-time of cabin and propulsion system emulation, strengthen the degree true to nature of emulation, must abandon original is original technical scheme of core with the industrial computer, and then adopts effective more at a high speed emulation platform.
Summary of the invention
The purpose of this invention is to provide a kind of problem that overcomes in the above-mentioned technology formerly, can strengthen emulation precision and real-time, improve the embedded real-time simulation platform of emulator performance.
To achieve the above object, emulation platform provided by the invention, it comprises processor, the keyboard that is connected with processor, debugging interface and programmable logic device (PLD), the bus buffer device that is connected with programmable logic device (PLD) by parallel bus, the display controller and the display that are connected with the bus buffer device, analog to digital converter and digital to analog converter by the serial peripheral interface bus is connected with programmable logic device (PLD) drive amplifying circuit with pre-filtering amplifying circuit and the analog quantity that analog to digital converter is connected with digital to analog converter respectively; Wherein processor is the dual core processor that comprises microcontroller and digital signal processor; Comprise the keyboard that is connected with microcontroller, universal input/output interface, the static memory that is connected with microcontroller by programmable logic device (PLD) and bus buffer device, flash memories, the 2nd expansion interface and the latch that is connected with photoelectric coupled circuit, the controller local area network's controller that has controller local area network's interface and the 3rd expansion interface that are connected with microcontroller by programmable logic device (PLD) and serial peripheral interface bus, the serial Electrically Erasable Read Only Memory and the 1st expansion interface that are connected with microcontroller by programmable logic device (PLD) and internal integrate circuit bus; The serial port that links to each other with digital signal processor draws interface, data space static memory and program space static memory outward respectively.
As above-mentioned structure of the present invention, serial peripheral interface (SPI) bus is drawn from programmable logic device (PLD) (CPLD), on bus, be connected to multichannel modulus (AD) converter and digital-to-analogue (DA) converter, and controller local area network's (Controller Area Network is called for short CAN) bus controller.The simulating signal of outside input is earlier through entering modulus (AD) converter behind the pre-filtering amplification appliance, by modulus (AD) converter its simulating signal is transformed to digital signal, be input to the interior microcontroller (ARM) of processor by serial peripheral interface (SPI) bus, handle for processor; Signal from processor output outputs to digital-to-analogue (DA) converter by microcontroller (ARM) by spi bus, and digital-to-analogue (DA) converter becomes simulating signal to digital signal, outputs to ambient systems through the analog quantity driving amplifier again; The CAN bus controller that is connected on the spi bus communicates in the CAN mode by the system that the CAN interface can link to each other with the CAN bus and other is connected on the CAN bus.
Internal integrated circuit (the I that draws from programmable logic device (PLD) (CPLD)
2C) bus is connected with serial Electrically Erasable Read Only Memory (E
2PROM) and the 1st expansion interface.
Draw parallel bus from programmable logic device (PLD) (CPLD) and comprise outer address bus (serial peripheral interface (SPI) bus), external data bus (internal integrated circuit (I
2C) bus) reach relevant external control bus (parallel bus).These parallel buss cushion through bus buffer at first that (address bus and control bus are by the unidirectional bus impact damper, data bus is by the bidirectional bus impact damper), improving load-carrying ability, and then link to each other with static memory (SRAM), flash memories (FLASH) and the synchronous dynamic random access memory (SDRAM) of the outside expansion of microcontroller (ARM).Wherein, be provided with wire jumper on the address wire of SRAM and FLASH, the map addresses space of SRAM and FLASH can be exchanged, when satisfying debugging with independent operating to the different requirements of low address space storer character.Display also is connected on the parallel bus by display controller, as the output demonstration of system.In addition, parallel bus also is connected with latch, and latch is connected with photoelectric coupled circuit.Latch is divided into two groups according to the difference of data transfer direction, and one group is used for input, and another group is used for output, to realize the multi-path digital amount input and output of application system.Parallel bus provides expansion interface equally, uses for hardware expanding.
Digital signal processor (DSP) outside has been expanded corresponding to program space static memory and data space static memory and serial port and has been drawn interface (being also referred to as multichannel buffer serial port (McBSP)) outward, and this interface can be drawn out on the expansion interface for expansion.
As above-mentioned structure, we can say the dedicated emulated platform that The present invention be directed to the distributing emulation system exploitation.It has following characteristics:
● the present invention is owing to comprise the processor of microcontroller (ARM) and digital signal processor (DSP) double-core, mode interaction data by shared drive between two processor cores is so the simulation calculation precision height of emulation platform of the present invention, signal input and output real-time are good.When general model was carried out real-time simulation, its simulation step length can reach the microsecond level;
● the present invention has passed through programmable logic device (PLD) (CPLD) at the microcontroller (ARM) of processor and the interface of peripherals, make device address to shine upon flexibly like this, interface sequence is easy to coupling, interface logic is convenient to be provided with, can satisfy the interface needs of distinct device, very flexible;
● emulation platform of the present invention has comprised processor, storer, IO interface, it is a complete computer system, simultaneously it provides the expansion and the interface of system bus and various communication buss again, so but its not only independent operating but also can form bigger system synergistic working with other system;
● contain the corresponding interface of controller local area network (CAN) bus on the emulation platform of the present invention, can be directly link to each other with controller local area network (CAN) bus, carry out the CAN bus mode and communicate by letter with the various device on being connected the CAN bus, for the distributed emulation mode based on fieldbus provides support;
● emulation platform of the present invention itself just has keyboard and the directly on-the-spot display that shows that is easy to execute-in-place, is convenient to on-site supervision and debugging;
● emulation platform of the present invention provides sufficient volatile memory, and (FLASH E2PROM) and volatile memory (RAM), can satisfy different simulation run needs.Both can allow program directly in nonvolatile memory FLASH, move, can be kept at program and data in the nonvolatile memory again.And when operation, be loaded in the volatile memory, with the speed of faster procedure operation and the dynamic change in the realization program run;
● emulation platform of the present invention provides the plurality of devices interface, and the equipment that can connect corresponding interface procedure is used for the expansion of function and system, makes system can finish complicated more work;
● the chip integration that emulation platform of the present invention adopted is all very high, has adopted 3.3V low-voltage integrated package as far as possible, and power consumption is all smaller; Hardware using 8 layer printed circuit boards, and taked to reduce accordingly the mode that electrical measurement disturbs and connected up, make that the hardware volume of system is less, good reliability.
Description of drawings
Fig. 1 is the structural representation of emulation platform of the present invention.
Fig. 2 is the structural representation that emulation platform of the present invention is used for the marine main engine real-time emulation system.
Fig. 3 is the process flow diagram that is embedded in the operation control system in the interior microcontroller (ARM) of processor in the emulation platform of the present invention in Fig. 2 example.
Fig. 4 is the process flow diagram that is embedded in the operation control system in the digital signal processor in the emulation platform of the present invention (DSP) in Fig. 2 example.
Embodiment
Below in conjunction with accompanying drawing concrete structure of the present invention is further described.
Fig. 1 is the structural representation of emulation platform of the present invention.As shown in Figure 1, emulation platform of the present invention comprises: processor 5, the keyboard 1 that is connected with processor 5, debugging interface 2 and programmable logic device (PLD) (CPLD) 12, by the bus buffer device 14 that parallel bus 13 is connected with programmable logic device (PLD) (CPLD) 12, display controller 11 that is connected with bus buffer device 14 and display 10.Modulus (AD) converter 20 and digital-to-analogue (DA) converter 22 that are connected with programmable logic device (PLD) (CPLD) 12 by serial peripheral interface (SPI) bus 19, pre-filtering amplifying circuit 21 and the analog quantity driving amplifier 23 that is connected with digital-to-analogue (DA) converter 22 with modulus (AD) converter 20 respectively; Processor 5 comprises the double-core of microcontroller (ARM) 5-1 and digital signal processor (DSP) 5-2; Comprise the keyboard universal input/output interface (KBGPIO) 27 that is connected with microcontroller (ARM) 5-1, the static memory (SRAM), flash memories (FLASH) the 15, the 2nd expansion interface 16 and the latch 17 that is connected with photoelectric coupled circuit 18 that are connected with microcontroller (ARM) 5-1 by programmable logic device (PLD) (CPLD) 12 and bus buffer device 14; The controller local area network that has controller local area network's interface 26 (CAN) controller 25 and the 3rd expansion interface 24 that are connected with microcontroller (ARM) 5-1 by programmable logic device (PLD) (CPLD) 12 and serial peripheral interface (SPI) bus 19; By programmable logic device (PLD) (CPLD) 12 and internal integrated circuit (I
2C) the serial Electrically Erasable Read Only Memory 7 and the 1st expansion interface 8 that are connected with microcontroller (ARM) 5-1 of bus 9; Interface 6, data space static memory (SRAM) 4 and program space static memory (SRAM) 3 are drawn in the serial that links to each other with digital signal processor (DSP) 5-2 outward respectively.
The described processor 5 that comprises microcontroller (ARM) 5-1 and digital signal processor (DSP) 5-2 is selected for use and is contained the TMS320VC5470 process chip that ARM adds the double-core of DSP in the present embodiment.In this chip, ARM (MCU) is 32 RISC (Reduced Instruction Set Computing, i.e. reduced instruction set computer) microcontrollers (this microcontroller is acknowledged as the advanced person's of the world today microcontroller).Its function aspect supervision control, communication interface is very perfect, is to examine as primary processor.Be responsible for task management, IO interface, to the control and the operation embedded OS of external unit; The digital signal processor that wherein comprises (DSP) 5-2 is very powerful to the ability of various digital signals or data processing, be as processor from processor core.Only be responsible for the fast data calculation process.The ARM+DSP double-core is combined, and the complementation of making the most of the advantage can obtain higher performance.Communicate by the inner two visit RAM---API (Application Programming Interface, i.e. application programming interface)---that share between two processor cores.
In the present embodiment, the microcontroller (ARM) among the described dual core processor chip TMS320VC5470 can link to each other with 3 * 8 keyboard by the keyboard universal input/output interface (KBGPIO) that it provided, and can support the keyboard of 24 hardware button.All the other KBGPIO that provide and no multiplexing GPIO (part universal input/output interface) all are drawn out to GPIO/KBGPIO expansion interface, the hardware expanding on the supporting platform.For the outer address bus of microcontroller (ARM), external data bus, relevant control bus, serial peripheral interface (SPI) bus and internal integrated circuit (I
2C) after bus is drawn by this processor chips pin, at first link to each other with programmable logic device (PLD) (CPLD), through programmable logic device (PLD) (CPLD) signal is carried out the transform decoding (signal packets that will come from microprocessor, through after suitable the logical conversion combination or sequential conversion, from CPLD output) after, be divided into 3 parts: serial peripheral interface (SPI) bus 19 parts, internal integrated circuit (I
2C) bus 9 parts and parallel bus 13 (outer address bus, external data bus and relevant external control bus) part.
Described program space static memory (SRAM) 3 and the data space static memory (SRAM) 4 that is connected in digital signal processor (DSP) nuclear 5-2 is respectively 64K program SRAM and 64K data SRAM.
In the present embodiment, display and display controller adopt LCD and LCD controller.
Fig. 2 is the structural representation that emulation platform of the present invention is used for the marine main engine real-time emulation system.Emulation platform of the present invention can be used in the emulation of marine propuision system and other large scale systems.Shown in Figure 2 is the example that a kind of Ship Propeling real-time emulation system is used emulation platform of the present invention.System mainly comprises the industrial computer 01 that is inserted with CAN card 02 and data collecting card 03 on the mainboard, emulation platform 06 of the present invention and CAN bus 05.In order to satisfy teaching and need of practice, the physical environment of half material object has been added by system, comprises the thruster and the propeller system 07 of real ship control handwheel platform, Displaying Meter and warning device 04 and simulating electric machine simulation, or the like.Wherein, emulation platform of the present invention is connected between industrial computer 01 and the motor propeller system 07, constitutes the core of whole simulation system as simulation computer.In order to mathematical model that obtains in real time accurate marine main engine system and the input and output of finishing some live signals, the simulating electric machine system operation of control bottom.The host computer of its analogue system is industrial computer (PC), communicates by letter with emulation platform of the present invention by the CAN card, sends control information and simulation parameter, receives simulation result and demonstration.
The ARM of dual core processor of the present invention (ARM nuclear-microcontroller) is a primary processor, is the control center of total system.Placing the bottom of the software of ARM inside to run on embedded OS μ C/OS-II (title of a kind of embedded real-time operating system that American (Jean J.Labrosse) provides), is the driver and the application software of equipment on this operating system.In addition for making in this system electric energy start operation, and software code is loaded into reads and write convenient and move among the RAM faster.Also have bootstrap loader to be responsible for powering up the back in the software and from the FLASH of ARM outside, program is loaded among the RAM, finish the boot-loader of total system.The task program of ARM is that the control program of whole simulation (mainly comprises starting emulation, suspends emulation, stops the control of these states of emulation and pass to the realistic model input quantity, obtain the output quantity of realistic model) and communication control program (comprise by the upper industrial computer on CAN bus communication device and the CAN bus network and the program of other devices communicatings, obtain console panel station information that upper industrial computer collects by data collecting card or send simulation result information to upper industrial computer.Also have, directly accept the control or the parameter information of the external input device keyboard input of native system, send the program of display message etc. to the LCD of native system).Because the last operation of ARM has real-time kernel μ C/OS-II, so the program of all these ARM all is the form realization with embedded real-time operating system μ C/OS-II task, finishes synchronous mutual exclusion and message transmission by the message mailbox and the semaphore that call μ C/OS-II between task.
Fig. 3 is the flow process that Fig. 2 embodiment is embedded in the operating system in the ARM.Running program mainly is made of 3 tasks (process) and used message mailbox and the semaphore of intertask communication.These three tasks are respectively the tasks 001 that is used for carrying out with the external world data input and output (being meant the data on the CAN bus and the transmitting-receiving of control information here), Simulation Control task 002 is to reentry emulation output result's the task 003 of DSP of the input value of DSP input emulation.These three tasks have different priority for operating system scheduling, and wherein 002 priority is the highest, and 003 take second place, 001 priority is minimum.
As shown in Figure 3, task 001 is at first carried out 1-1 step transceive data or control information on the CAN bus, then the 1-2 step judges whether it is legal data or control information, if just carry out the 1-3 step, the message mailbox of calling μ C/OS-II operating system sends function OSMboxPost () and sends the information that receives to message mailbox 007, otherwise skips the 1-3 step.The message call mailbox sends function OSMboxPost () can make μ C/OS-II kernel carry out the switching of task, and this moment, task 002 was just at message call mailbox receiver function OSMboxPend ().2-1 goes on foot the information in the mailbox 007 that waits for the arrival of news, because the priority of task 002 is the highest, so task 002 obtains carrying out immediately, task 001 then enters dormant state.Next task 002 carries out the 2-2 step, the value of representing a global variable Sim_Ctrl of simulation status according to the message alteration that receives from message mailbox 007, and relevant data is saved in the emulation input buffering formation, the priority of task 003 is set to time high priority again, jumps to the 2-1 step then and continues to wait for new message.At this moment, task 001 does not also continue to carry out, thereby does not have new message, so task 002 enters the suspended state that waits for the arrival of news, kernel carries out task scheduling again, and the task 003 of inferior high priority is entered running status.Task 003 is at first carried out the 3-1 step, detect the value of global variable Sim_Ctrl (being the variable name of a global variable of definition), see whether Sim_Ctrl is beginning (START), if not then calling system delay function OSTimeDly () (delay function that μ C/OS-II provides) time-delay, carry out task and switch operation task 001; If then carry out the 3-2 step, producing emulation input data puts emulation input buffering formation into or uses the data that deposit emulation input buffering formation in that obtain from the outside, carry out the 3-3 step again, the OSSemPend () function of calling system is waited for 0 the binary signal amount 004 that is initialized as.Because semaphore 004 is 0 now, so task 003 enters the suspended state of wait-semaphore, the task that enters is switched operation task 001.Calculate according to simulation algorithm after the data in the DSP reception emulation input buffering formation, after finishing simulation result is put into the output buffering to row, and send interruption to the ARM side, ARM has no progeny in receiving, carry out break in service, break in service is called OSSemPost () system function with binary signal amount 004 release signal 005, and this makes task 003 enter ready state.When interruption is withdrawed from, kernel carries out task and switches, allow task 003 be continued downward operation, carry out the 3-4 step, from output buffer queue, read output valve, call OSMboxPost () and in message mailbox 6, send the gained result, and carry out 3-5 step, calling system delay function OSTimeDly () time-delay, task turns back to it again and begins the place then, continue to carry out new one and take turns input and output, the time-delay of task 003 can cause that task switches to task 001.Task 001 is carried out the 1-3 step, carry out 1-4 step time-delay in the back that initiates a message to message mailbox 007, the message of the mailbox 006 that waits for the arrival of news is when task 003 is sent to message mailbox 006, task 001 runs to this and just carries out the 1-5 step, and this message (simulation result) is sent on the CAN bus.
Fig. 4 is the flow process that is embedded in the operating system in the DSP.Running program in the DSP mainly is the running program of Real-Time Model, and the running program of this model mainly is to obtain input quantity from ARM, through resolving, draws the output quantity of model and passes it back ARM.Some two visit RAM (API) that share by ARM and DSP between two parts program carry out exchanges data.Carry out data communication by what share at the sheet storer between two processor cores, speed is very fast, and this has guaranteed the real-time of emulation on hardware.Open up two sections spaces in the API storer, one section is the input buffering formation, and another section is an output buffer queue.The input value (formation can not be sky, otherwise model is not just imported) from ARM is preserved in the input buffering formation, and output buffer queue is preserved the model output valve that DSP calculates in real time, and two formations realize with the array form.
Running program at first carried out for the 10th step, was the inlet-beginning of program, next carried out the 20th step initialization, entered the maim body part then.It at first is the value of the 30th step judging the variable of controlling models state, if variate-value represents not move emulation, then continue to judge the variation of waiting for artificial variable, if variate-value represents to carry out emulation at this, then carried out for the 40th step, enter in the running status of realistic model inquiry and wait for variable run.Enable timer cycle this moment and interrupt, after each interrupted arriving, interrupt service routine carried out for the 100th step, and an indexed variable run is changed to 1, and master routine inquiry run is 0 o'clock, continues inquiry and waits for; When run was interrupted service routine and becomes 1, after interrupting returning, beginning was to following operation; Carried out for the 50th step, from the input buffering formation, read input value; Carried out for the 60th step then, call real-time simulation mathematics model function, calculate the output valve that model is carved at this moment; And carried out for the 70th step, put it into output buffer queue and send to simulating electric machine control system; Carried out for the 80th step again, send interruption to ARM, notice ARM, DSP output is finished; And then carried out for the 90th step, run is put 0 again, jumped to for the 30th step.From embodiment, demonstrate fully and use emulation platform of the present invention as superiority recited above.
Claims (2)
1. embedded real-time simulation platform, it comprises processor, the keyboard that is connected with processor, debugging interface and programmable logic device (PLD), the bus buffer device that is connected with programmable logic device (PLD) by parallel bus, the display controller and the display that are connected with the bus buffer device, the analog to digital converter and the digital to analog converter that are connected with programmable logic device (PLD) by the serial peripheral interface bus, pre-filtering amplifier and the analog quantity driving amplifier that is connected with digital to analog converter with analog to digital converter respectively; It is characterized in that processor comprises microcontroller and digital signal processor; Also comprise the keyboard universal input/output interface that is connected with microcontroller, the static memory, flash memories, the 2nd expansion interface and the latch that is connected with photoelectric coupled circuit that are connected with microcontroller by programmable logic device (PLD) and bus buffer device; The controller local area network's controller that has controller local area network's interface and the 3rd expansion interface that are connected with microcontroller by programmable logic device (PLD) and serial peripheral interface bus; The serial Electrically Erasable Read Only Memory and the 1st expansion interface that are connected with microcontroller by programmable logic device (PLD) and internal integrate circuit bus; The serial port that links to each other with digital signal processor draws interface, data space static memory and program space static memory outward respectively.
2. embedded real-time simulation platform according to claim 1 is characterized in that the described processor that comprises microcontroller and digital signal processor is the process chip that contains microcontroller and digital signal processor double-core.
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| CN100410887C (en) * | 2006-09-18 | 2008-08-13 | 中国航天时代电子公司第七七一研究所 | Structuring method of distributed type simulated testing system series based on signal classification |
| CN100419705C (en) * | 2006-11-29 | 2008-09-17 | 中国人民解放军理工大学 | Configurable universal synchronous and asynchronous communication debugging device and bugging method thereof |
| CN100524221C (en) * | 2007-12-28 | 2009-08-05 | 中国科学院计算技术研究所 | Parallel simulator and method |
| CN101453371B (en) * | 2008-06-26 | 2010-10-27 | 北京科技大学 | Simulation method and apparatus thereof for network embedded system |
| CN101593151B (en) * | 2008-05-29 | 2011-12-14 | 帝斯贝思数字信号处理和控制工程有限公司 | Method and simulator for real-time calculation of the state variables of a process model |
| CN101154183B (en) * | 2006-09-29 | 2011-12-28 | 上海海尔集成电路有限公司 | Microcontroller built-in type on-line simulation debugging system |
| CN101442324B (en) * | 2008-12-23 | 2012-07-18 | 电子科技大学 | Monitoring and controlling processor based on wireless network low-power level signal and processing method |
| CN103744342A (en) * | 2014-01-22 | 2014-04-23 | 大连理工计算机控制工程有限公司 | PAC (programmable automatic controller) real-time control system based on dual-core processor |
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| CN101154183B (en) * | 2006-09-29 | 2011-12-28 | 上海海尔集成电路有限公司 | Microcontroller built-in type on-line simulation debugging system |
| CN100419705C (en) * | 2006-11-29 | 2008-09-17 | 中国人民解放军理工大学 | Configurable universal synchronous and asynchronous communication debugging device and bugging method thereof |
| CN100524221C (en) * | 2007-12-28 | 2009-08-05 | 中国科学院计算技术研究所 | Parallel simulator and method |
| CN101593151B (en) * | 2008-05-29 | 2011-12-14 | 帝斯贝思数字信号处理和控制工程有限公司 | Method and simulator for real-time calculation of the state variables of a process model |
| CN101453371B (en) * | 2008-06-26 | 2010-10-27 | 北京科技大学 | Simulation method and apparatus thereof for network embedded system |
| CN101442324B (en) * | 2008-12-23 | 2012-07-18 | 电子科技大学 | Monitoring and controlling processor based on wireless network low-power level signal and processing method |
| CN103744342A (en) * | 2014-01-22 | 2014-04-23 | 大连理工计算机控制工程有限公司 | PAC (programmable automatic controller) real-time control system based on dual-core processor |
| CN104834504A (en) * | 2015-04-28 | 2015-08-12 | 江苏宏云技术有限公司 | SOC dual-core structure based on master-slave cooperative work of MCU and DSP and working method thereof |
| CN111158950A (en) * | 2019-11-28 | 2020-05-15 | 中国航空工业集团公司西安航空计算技术研究所 | Positioning system and method for abnormal reset of embedded computer system |
| CN112131741A (en) * | 2020-09-22 | 2020-12-25 | 西安电子科技大学 | Real-time double-kernel single-machine semi-physical simulation architecture and simulation method |
| CN112131741B (en) * | 2020-09-22 | 2024-01-30 | 西安电子科技大学 | Real-time dual-kernel single-machine semi-physical simulation architecture and simulation method |
| CN115006681A (en) * | 2022-06-05 | 2022-09-06 | 上海中医药大学 | Flashing light stimulation nerve regulation and control device capable of flexibly regulating parameters |
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