CN1687896A - Method and apparatus for generating random number - Google Patents
Method and apparatus for generating random number Download PDFInfo
- Publication number
- CN1687896A CN1687896A CN 200510073000 CN200510073000A CN1687896A CN 1687896 A CN1687896 A CN 1687896A CN 200510073000 CN200510073000 CN 200510073000 CN 200510073000 A CN200510073000 A CN 200510073000A CN 1687896 A CN1687896 A CN 1687896A
- Authority
- CN
- China
- Prior art keywords
- bit
- temporary storage
- storage location
- shift register
- bit temporary
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Images
Landscapes
- Logic Circuits (AREA)
- Compression, Expansion, Code Conversion, And Decoders (AREA)
Abstract
The invention provides a random number generating method and device, according to a Boolean function set, designing the feedback control of a N-bit linear feedback shift register to make the N-bit linear feedback shift register able to generate a bit group corresponding to the Boolean function after each clock pulse, where the function stands for the accumulated bit groups outputted by the N-bit linear feedback shift register after the Mth clock pulse, and the Boolean function is a relational expression generated by using the 0th clock pulse as a reference; and using the bit group corresponding to the Boolean function as the feedback input to the N-bit linear feedback shift register, so as to generate the next bit group corresponding to the Boolean function after the next clock pulse.
Description
Technical field
The present invention relates to a kind of random-number generating method and device, particularly a kind of Boolean function of exporting via the prediction linear feedback shift register, arrange in pairs or groups simple logic gate and related operation are to shorten random number method and the device of operation time.
Background technology
In the field of present circuit design, (Liner Feedback ShiftRegister LFSR) is a kind of be used for producing quasi random number style (Pseudo Random PatternGeneration, circuit design PRPG) to linear feedback shift register.In general, the most basic linear feedback shift register is mainly shift register (Shift Register SR) has exclusive-OR gate (exclusive-OR) path of serial connection, with the bit of output as the random number result in its output terminal feedback.Usually, n bit linear feedback shift register the most basic is after through 1 time clock (clock), can produce the random number result of a bit, after through n time clock, can produce the random number result of n bit, and the linear feedback shift register of a n bit can produce 2 at most
nThe random number result of-1 bit.
Please refer to Fig. 1, Fig. 1 is the synoptic diagram of 16 bit linear feedback shift registers commonly used.In Fig. 1,16 bit linear feedback shift registers 100 include 16 bit shift register 110 and exclusive-OR gate 120,130.Wherein, the 0th～15th bit temporary storage location can be accepted a[0 respectively in 16 bit shift register 100]～a[15] bit input.And every through after the time clock, the a[0 in the 0th～15th bit temporary storage location]～a[15] bit then respectively to position of left dislocation.With the a[0 in the 0th bit temporary storage location] bit is example, after a time clock, a[0] bit promptly is displaced to the 1st bit temporary storage location by the 0th bit temporary storage location, again through after the time clock, a[0] bit promptly is displaced to the 2nd bit temporary storage location by the 1st bit temporary storage location ... by that analogy.
And this 16 bit linear feedback shift register 100 is for the design of random number output, then be to take and to be temporarily stored in the bit output of the 5th, the 10th and the 15th bit temporary storage location, and the bit that will be temporarily stored in the 15th and the 10th bit temporary storage location is after exclusive-OR gate 120 is made xor, export after exclusive-OR gate 130 is made xor with the bit that is temporarily stored in the 5th bit temporary storage location again, and with this as the bit 140 that feeds back to the 0th bit temporary storage location and output.Therefore, this 16 bit linear feedback shift register 100 every through after the time clock be an exportable bit 140 as the random number result, and bit 140 also feed back to simultaneously the 0th bit temporary storage location with the bit 140 that produces next time clock as the random number result.Yet, driving along with the high speed circuit development, linear feedback shift register only produces a bit and has not applied required as the random number result after each time clock, therefore, producing a plurality of bits after each time clock then is designed out as random number result's linear feedback shift register.
Please refer to Fig. 2, Fig. 2 is the synoptic diagram of another linear feedback shift register commonly used.In Fig. 2, this linear feedback shift register 200 with 16 bit linear feedback shift registers, 210, the 20 bit linear feedback shift registers 220 of parallel connection, collocation full adder 230 to produce dibit 240,245 simultaneously as the random number result.Wherein, the random number bit 240 that this linear feedback shift register 200 is produced is to see through 16 bit linear feedback shift registers 210, and 20 bits 215,225 of after each time clock, producing respectively of bit linear feedback shift register 220, as the input of full adder 230 input end A, B.Therefore, after each time clock, full adder 230A input end A, B receive bit 215 and 225 respectively, in order to producing and (sum) bit 240 and carry (carry) bit 245, and carry-out bit 245 is also fed back the input as the previous stage carry input carryin of full adder 230 simultaneously.Therefore, the full adder 230 of this linear feedback shift register 200 can produce after each time clock and bit 240 and carry-out bit 245, with as the random number result.In like manner, if will be after each time clock, produce for example be 8 bits or 16 bits as random number as a result the time, must parallel connection more the polyteny feedback shift register could realize.But, more under the situation of polyteny feedback shift register, certainly will pay more costs in parallel connection.
In view of this, the present invention proposes a kind of random-number generating method and device, can needn't pay under the too many condition of cost, produces a plurality of bits after each time clock, with as a plurality of random number results.
Summary of the invention
An object of the present invention is to provide a kind of random-number generating method, comprise: the FEEDBACK CONTROL that designs a N bit linear feedback shift register according to a Boolean function group, so that this N bit linear feedback shift register is after each time clock, can produce the pairing bit group of this Boolean function, wherein this function represents this N bit linear feedback shift register in the bit group of accumulating output after M time clock, and this Boolean function is the relational expression that benchmark was produced with the 0th time clock; And with this bit group corresponding to this Boolean function that this N bit linear feedback shift register is exported, import as the feedback of this N bit linear feedback shift register, after next time clock, to produce next bit group corresponding to this Boolean function.
According to above-mentioned purpose, this random-number generating method, also comprise: if this N bit linear feedback shift register is one 16 bit linear shift registers, and when this 16 bit linear shift register has one the 0th～1 the 15th bit temporary storage location, then this 16 bit linear shift register is after 1 time clock, and this Boolean function group is predicted to be:
A. the bit of bit the 15th bit temporary storage location of bit the 10th bit temporary storage location of the 15th bit temporary storage location.
According to above-mentioned purpose, this random-number generating method, wherein this 16 bit linear shift register is after 2 time clock, and this Boolean function group is predicted to be in regular turn:
A. the bit of bit the 5th bit temporary storage location of bit the 10th bit temporary storage location of the 15th bit temporary storage location; And
B. the bit of bit the 4th bit temporary storage location of bit the 9th bit temporary storage location of the 14th bit temporary storage location.
According to above-mentioned purpose, this random-number generating method, wherein this 16 bit linear shift register is after 3 time clock, and this Boolean function group is predicted to be in regular turn:
A. the bit of bit the 5th bit temporary storage location of bit the 10th bit temporary storage location of the 15th bit temporary storage location;
B. the bit of bit the 4th bit temporary storage location of bit the 9th bit temporary storage location of the 14th bit temporary storage location; And
C. the bit of bit the 3rd bit temporary storage location of bit the 8th bit temporary storage location of the 13rd bit temporary storage location.
According to above-mentioned purpose, this random-number generating method, wherein this 16 bit linear shift register is after 4 time clock, and this Boolean function group is predicted to be in regular turn:
A. the bit of bit the 5th bit temporary storage location of bit the 10th bit temporary storage location of the 15th bit temporary storage location;
B. the bit of bit the 4th bit temporary storage location of bit the 9th bit temporary storage location of the 14th bit temporary storage location;
C. the bit of bit the 3rd bit temporary storage location of bit the 8th bit temporary storage location of the 13rd bit temporary storage location; And
D. the bit of bit the 2nd bit temporary storage location of bit the 7th bit temporary storage location of the 12nd bit temporary storage location.
According to above-mentioned purpose, this random-number generating method, wherein this 16 bit linear shift register is after 5 time clock, and this Boolean function group is predicted to be in regular turn:
A. the bit of bit the 5th bit temporary storage location of bit the 10th bit temporary storage location of the 15th bit temporary storage location;
B. the bit of bit the 4th bit temporary storage location of bit the 9th bit temporary storage location of the 14th bit temporary storage location;
C. the bit of bit the 3rd bit temporary storage location of bit the 8th bit temporary storage location of the 13rd bit temporary storage location;
D. the bit of bit the 2nd bit temporary storage location of bit the 7th bit temporary storage location of the 12nd bit temporary storage location; And
E. the bit of bit the 1st bit temporary storage location of bit the 6th bit temporary storage location of the 11st bit temporary storage location.
According to above-mentioned purpose, this random-number generating method, wherein these 16 bit linear shift registers are after 6 time clock, and this Boolean function group is predicted to be in regular turn:
A. the bit of bit the 5th bit temporary storage location of bit the 10th bit temporary storage location of the 15th bit temporary storage location;
B. the bit of bit the 4th bit temporary storage location of bit the 9th bit temporary storage location of the 14th bit temporary storage location;
C. the bit of bit the 3rd bit temporary storage location of bit the 8th bit temporary storage location of the 13rd bit temporary storage location;
D. the bit of bit the 2nd bit temporary storage location of bit the 7th bit temporary storage location of the 12nd bit temporary storage location;
E. the bit of bit the 1st bit temporary storage location of bit the 6th bit temporary storage location of the 11st bit temporary storage location: and
F. the bit of bit the 0th bit temporary storage location of bit the 5th bit temporary storage location of the 10th bit temporary storage location.
According to above-mentioned purpose, this random-number generating method, wherein this 16 bit linear shift register is after 7 time clock, and this Boolean function group is predicted to be in regular turn:
A. the bit of bit the 5th bit temporary storage location of bit the 10th bit temporary storage location of the 15th bit temporary storage location;
B. the bit of bit the 4th bit temporary storage location of bit the 9th bit temporary storage location of the 14th bit temporary storage location;
C. the bit of bit the 3rd bit temporary storage location of bit the 8th bit temporary storage location of the 13rd bit temporary storage location;
D. the bit of bit the 2nd bit temporary storage location of bit the 7th bit temporary storage location of the 12nd bit temporary storage location;
E. the bit of bit the 1st bit temporary storage location of bit the 6th bit temporary storage location of the 11st bit temporary storage location;
F. the bit of bit the 0th bit temporary storage location of bit the 5th bit temporary storage location of the 10th bit temporary storage location; And
G. the bit of bit the 4th bit temporary storage location of the 9th bit temporary storage location (bit of bit the 5th bit temporary storage location of bit the 10th bit temporary storage location of the 15th bit temporary storage location).
According to above-mentioned purpose, this random-number generating method, wherein these 16 bit linear shift registers are after 8 time clock, and this Boolean function group is predicted to be in regular turn:
A. the bit of bit the 5th bit temporary storage location of bit the 10th bit temporary storage location of the 15th bit temporary storage location;
B. the bit of bit the 4th bit temporary storage location of bit the 9th bit temporary storage location of the 14th bit temporary storage location;
C. the bit of bit the 3rd bit temporary storage location of bit the 8th bit temporary storage location of the 13rd bit temporary storage location;
D. the bit of bit the 2nd bit temporary storage location of bit the 7th bit temporary storage location of the 12nd bit temporary storage location;
E. the bit of bit the 1st bit temporary storage location of bit the 6th bit temporary storage location of the 11st bit temporary storage location;
F. the bit of bit the 0th bit temporary storage location of bit the 5th bit temporary storage location of the 10th bit temporary storage location;
G. the bit of bit the 4th bit temporary storage location of the 9th bit temporary storage location (bit of bit the 5th bit temporary storage location of bit the 10th bit temporary storage location of the 15th bit temporary storage location); And
H. the bit of bit the 3rd bit temporary storage location of the 8th bit temporary storage location (bit of bit the 4th bit temporary storage location of bit the 9th bit temporary storage location of the 14th bit temporary storage location).
According to above-mentioned purpose, this random-number generating method, wherein this 16 bit linear shift register is after 8 time clock, and this method also comprises:
8 positions of bit displacement that this 16 bit linear shift register is kept in; And
This 16 bit linear shift register is imported as the feedback of this 16 bit linear feedback shift register with 8 bits of output.
Another object of the present invention provides a kind of random number generating apparatus, comprising: a shift register has a plurality of bit temporary storage location; And a plurality of logic gates, be arranged on the feedback path of these bit temporary storage location outputs, wherein, this shift register only sees through these logic gates exporting a plurality of output bits, and these output bits are simultaneously as a plurality of feedback input bits of this shift register.
According to above-mentioned purpose, this random number generating apparatus, wherein this shift register is one 16 bit shift register, and has one the 0th～the 15th bit temporary storage location.
According to above-mentioned purpose, this random number generating apparatus, wherein these logic gates are one the 1st～1 the 8th exclusive-OR gate.
According to above-mentioned purpose, this random number generating apparatus, wherein the 1st exclusive-OR gate receives the 15th, the 10th, the output of the 5th bit temporary storage location, the 2nd exclusive-OR gate receives the 14th, the 9th, the output of the 4th bit temporary storage location, the 3rd exclusive-OR gate receives the 13rd, the 8th, the output of the 3rd bit temporary storage location, the 4th exclusive-OR gate receives the 12nd, the 7th, the output of the 2nd bit temporary storage location, the 5th exclusive-OR gate receives the 11st, the 6th, the output of the 1st bit temporary storage location, the 6th exclusive-OR gate receives the 10th, the 5th, the output of the 0th bit temporary storage location, the 7th exclusive-OR gate receives the 9th, the output of the 4th bit temporary storage location and this exclusive-OR gate 510, the 8th exclusive-OR gate receives the 8th, the output of the 3rd bit temporary storage location and this exclusive-OR gate 520, and the output of the 1st～the 8th exclusive-OR gate is also imported as the feedback of the 7th～the 0th bit temporary storage location respectively.
Comprehensively above-mentioned, the present invention proposes a kind of random-number generating method and device, under the situation that only increases some logic gates, can produce a plurality of bits after each time clock, with as a plurality of random number results.
Description of drawings
Wherein, description of reference numerals is as follows:
Fig. 1 is the synoptic diagram of 16 bit linear feedback shift registers commonly used;
Fig. 2 is the synoptic diagram of another linear feedback shift register commonly used;
Fig. 3 is the process flow diagram of the random-number generating method of preferred embodiment of the present invention;
Fig. 4 A, 4B are the synoptic diagram of Figure 116 bit linear feedback shift register temporary bit of its bit temporary storage location after each time clock of process; And
Fig. 5 redesigns the circuit diagram of its feedback path with the Boolean function group of its accumulative total output byte representative after 8 time clock for Figure 116 bit linear feedback shift register.
The number in the figure explanation:
100,200,210,220: linear feedback shift register
110: shift register
120,130: exclusive-OR gate
215,225: bit
230: full adder
240: and bit
245: carry-out bit
301～303: step
510～580: exclusive-OR gate
Embodiment
Please refer to Fig. 3, Fig. 3 is the process flow diagram of the random-number generating method of preferred embodiment of the present invention.At first, the N bit linear feedback shift register of a bit is only only exported in prediction originally after each time clock, predict that it is after the individual time clock of process M (for example N/2), the Boolean function of this N bit linear feedback shift register accumulation output byte representative, wherein, its bit temporary storage location bit of N bit linear feedback shift register is when the 0th time clock and the relational expression between the bit group for this reason for this Boolean function, and this is a step 301.
Then, redesign the FEEDBACK CONTROL of this N bit linear feedback shift register according to the Boolean function of prediction.That is to say that the FEEDBACK CONTROL layout of this N bit linear feedback shift register is used the logical value of this Boolean function representative instead and constructed, this is a step 302.Therefore, the N bit linear feedback shift register of this redesign, its output bit is the bit of above-mentioned bit group bit number.
At last, promptly with the output bit of this N bit linear feedback shift register that redesigns as FEEDBACK CONTROL, to produce the output bit of above-mentioned bit group bit number after next time clock, this is a step 303.
The 16 bit linear feedback shift registers 100 that exemplary graph 1 is commonly used are example, and please also refer to Fig. 4 A, 4B and be described further.Fig. 4 A, 4B are Figure 116 bit linear feedback shift register 100, through its bit temporary storage location after each time clock the synoptic diagram of temporary bit.In at the beginning, when just time clock was 0, its temporary bit of 16 bit linear feedback shift registers, 100 its 0th～15 bit temporary storage location was respectively a[0]～a[15].After 1 time clock, 16 bit linear feedback shift registers 100 will be temporarily stored in the bit a[5 of the 5th, the 10th and the 15th bit temporary storage location respectively], bit a[10] and bit a[15] output, and bit a[5], bit a[10] and bit a[15] after exclusive-OR gate 120,130 computings, obtain:
A[15] a[10] a[5] and bit output.Therefore, after 1 time clock, 16 bit linear feedback shift registers 100 output a[15] a[10] a[5] and bit, as the random number result and feed back to the 0th bit temporary storage location, and the bit of being kept in the 0th～15 bit temporary storage location of 16 bit linear feedback shift registers 100 will be to position of left dislocation.Therefore, after 1 time clock, the bit that 16 bit linear feedback shift registers, 100 its 0th～15 bit temporary storage location are kept in will be respectively a[15] a[10] a[5], a[0]～a[14].In like manner, after through 2,3～8 time clock, the bit that 16 bit linear feedback shift registers, 100 its 0th～15 bit temporary storage location are kept in will be as shown in Fig. 4 A, the 4B.
In addition, when doping this 16 bit linear feedback shift register 100 bit that its 0th～15 bit temporary storage location is kept in after through 8 time clock, can learn simultaneously that also this 16 bit linear feedback shift register 100 is after through 8 time clock, add up the bit group of output will be for this reason 16 bit linear feedback shift registers 100 after through 8 time clock, the bit that its 7th～0 bit temporary storage location is kept in:
a[15]a[10]a[5]
a[14]a[9]a[4]
a[13]a[8]a[3]
a[12]a[7]a[2]
a[11]a[6]a[1]
a[10]a[5]a[0]
a[9]a[4](a[15]a[10]a[5])
a[8]a[3](a[14]a[9]a[4])
And above-mentioned these bits are with the expression of Boolean function performance, are this 16 bit linear feedback shift register 100 during with respect to the 0th time clock in fact, its bit temporary storage location temporary bit of institute and the relational expression between the bit group totally.
Also therefore, according to notion of the present invention, when doping 16 bit linear feedback shift registers 100 and after 8 time clock, add up to export the Boolean function group of bit group representative, as if the feedback path that redesigns 16 bit linear feedback shift registers 100 according to this Boolean function group, this 16 bit linear feedback shift register 100 can produce the bit group that needs add up output originally after 8 time clock after through 1 time clock.
Please continue with reference to figure 5, Fig. 5 be Figure 116 bit linear feedback shift register 100 with after 8 time clock, the Boolean function group that its accumulative total is exported bit group representative redesigns the circuit diagram of its feedback path.In Fig. 5, the shift register 110 in the 16 bit linear feedback shift registers 100 will design its feedback path according to aforementioned Boolean function group.By aforementioned Boolean function group as can be known, only need the 0th of shift register 110～the 15th bit temporary storage location all is provided with output, and the output of the 0th～the 15th bit temporary storage location then couples exclusive-OR gate 510～580 in parallel according to aforementioned Boolean function group.Wherein, exclusive-OR gate 510 receives the 15th, the 10th, the output of the 5th bit temporary storage location, exclusive-OR gate 520 receives the 14th, the 9th, the output of the 4th bit temporary storage location, exclusive-OR gate 530 receives the 13rd, the 8th, the output of the 3rd bit temporary storage location, exclusive-OR gate 540 receives the 12nd, the 7th, the output of the 2nd bit temporary storage location, exclusive-OR gate 550 receives the 11st, the 6th, the output of the 1st bit temporary storage location, exclusive-OR gate 560 receives the 10th, the 5th, the output of the 0th bit temporary storage location, exclusive-OR gate 570 receives the 9th, the output of the 4th bit temporary storage location and exclusive-OR gate 510, exclusive-OR gate 580 receives the 8th, the output of the 3rd bit temporary storage location and exclusive-OR gate 520.And wherein, the output of exclusive-OR gate 510～580 is also imported as the feedback of the 7th～the 0th bit temporary storage location respectively.Therefore, setting by above feedback path, input bit in shift register 110 its 0th～the 15th bit temporary storage location is respectively a[0]～a[15] situation under and after next time clock, shift register 110 can once be exported the byte of 8 bits as the random number result, and the bit a[0 that shift register 110 its 0th～the 7th bit temporary storage location are temporary originally]～a[7] move to the 8th～the 15th bit temporary storage location, the 0th～the 7th bit temporary storage location then receives 8 bits respectively as the feedback input.
Significantly, compare with shift register 100 commonly used, the shift register 110 of preferred embodiment of the present invention only utilizes the operation time of a time clock, and can produce needs just producible random number result of 8 time clock originally.Similarly, for the N bit shift register, can be based on the spirit of preferred embodiment of the present invention, after doping originally the Boolean function that M time clock can produce, design a shift register according to the Boolean function of being predicted subsequently, so the operation time that it only needs a time clock, can produce the N bit random number that shift register commonly used needs M time clock to produce.The people who is familiar with the technology of the present invention field can be changed according to preferred embodiment spirit of the present invention, for example according to the actual requirements or the specification modification of changing M value etc., yet all should be contained in the claim of the present invention based on equivalent modifications or variation that spirit of the present invention is carried out.
Comprehensively above-mentioned, the present invention proposes a kind of random-number generating method and device, originally once export a bit its output after a plurality of time clock of linear feedback shift register by prediction as the random number result, and feedback path according to the predictive designs linear feedback shift register, with every after a time clock, can export a plurality of bits simultaneously with as the random number result.And, because the present invention once exports many bits with the notion of prediction output, therefore, on the feedback path of linear feedback shift register used in the present invention only with a little logic gate as layout component.Therefore, the present invention can be under the situation that feedback path layout cost is saved most, once exports many bits with as the random number result.
Foregoing only is preferred embodiment of the present invention, can not limit the scope of the invention with it.Promptly, will not lose main idea of the present invention place, also not break away from the spirit and scope of the present invention, therefore all should be considered as further enforcement situation of the present invention as long as the equalization of making according to claim of the present invention changes and modification.
Claims (10)
1. random-number generating method comprises:
Design the FEEDBACK CONTROL of a N bit linear feedback shift register according to a Boolean function group, so that this N bit linear feedback shift register is after each time clock, can produce the pairing bit group of this Boolean function, wherein this function represents this N bit linear feedback shift register in the bit group of accumulating output after M time clock, and this Boolean function is the relational expression that benchmark was produced with the 0th time clock; And
With this bit group that this N bit linear feedback shift register is exported, import as the feedback of this N bit linear feedback shift register, after next time clock, to produce next bit group corresponding to this Boolean function corresponding to this Boolean function.
2. random-number generating method as claimed in claim 1 also comprises:
If this N bit linear feedback shift register is one 16 bit linear shift registers, and when this 16 bit linear shift register has one the 0th～1 the 15th bit temporary storage location, then this 16 bit linear shift register is after 1 time clock, and this Boolean function group is predicted to be:
A. the bit of bit the 15th bit temporary storage location of bit the 10th bit temporary storage location of the 15th bit temporary storage location.
3. random-number generating method as claimed in claim 1, wherein this 16 bit linear shift register is after 2 time clock, and this Boolean function group is predicted to be in regular turn:
A. the bit of bit the 5th bit temporary storage location of bit the 10th bit temporary storage location of the 15th bit temporary storage location; And
B. the bit of bit the 4th bit temporary storage location of bit the 9th bit temporary storage location of the 14th bit temporary storage location.
4. random-number generating method as claimed in claim 1, wherein this 16 bit linear shift register is after 3 time clock, and this Boolean function group is predicted to be in regular turn:
A. the bit of bit the 5th bit temporary storage location of bit the 10th bit temporary storage location of the 15th bit temporary storage location;
B. the bit of bit the 4th bit temporary storage location of bit the 9th bit temporary storage location of the 14th bit temporary storage location; And
C. the bit of bit the 3rd bit temporary storage location of bit the 8th bit temporary storage location of the 13rd bit temporary storage location.
5. random-number generating method as claimed in claim 1, wherein this 16 bit linear shift register is after 4 time clock, and this Boolean function group is predicted to be in regular turn:
A. the bit of bit the 5th bit temporary storage location of bit the 10th bit temporary storage location of the 15th bit temporary storage location;
B. the bit of bit the 4th bit temporary storage location of bit the 9th bit temporary storage location of the 14th bit temporary storage location;
C. the bit of bit the 3rd bit temporary storage location of bit the 8th bit temporary storage location of the 13rd bit temporary storage location; And
D. the bit of bit the 2nd bit temporary storage location of bit the 7th bit temporary storage location of the 12nd bit temporary storage location.
6. random-number generating method as claimed in claim 1, wherein this 16 bit linear shift register is after 5 time clock, and this Boolean function group is predicted to be in regular turn:
A. the bit of bit the 5th bit temporary storage location of bit the 10th bit temporary storage location of the 15th bit temporary storage location;
B. the bit of bit the 4th bit temporary storage location of bit the 9th bit temporary storage location of the 14th bit temporary storage location;
C. the bit of bit the 3rd bit temporary storage location of bit the 8th bit temporary storage location of the 13rd bit temporary storage location;
D. the bit of bit the 2nd bit temporary storage location of bit the 7th bit temporary storage location of the 12nd bit temporary storage location; And
E. the bit of bit the 1st bit temporary storage location of bit the 6th bit temporary storage location of the 11st bit temporary storage location.
7. random-number generating method as claimed in claim 1, wherein these 16 bit linear shift registers are after 6 time clock, and this Boolean function group is predicted to be in regular turn:
A. the bit of bit the 5th bit temporary storage location of bit the 10th bit temporary storage location of the 15th bit temporary storage location;
B. the bit of bit the 4th bit temporary storage location of bit the 9th bit temporary storage location of the 14th bit temporary storage location;
C. the bit of bit the 3rd bit temporary storage location of bit the 8th bit temporary storage location of the 13rd bit temporary storage location;
D. the bit of bit the 2nd bit temporary storage location of bit the 7th bit temporary storage location of the 12nd bit temporary storage location;
E. the bit of bit the 1st bit temporary storage location of bit the 6th bit temporary storage location of the 11st bit temporary storage location: and
F. the bit of bit the 0th bit temporary storage location of bit the 5th bit temporary storage location of the 10th bit temporary storage location.
8. random-number generating method as claimed in claim 1, wherein this 16 bit linear shift register is after 7 time clock, and this Boolean function group is predicted to be in regular turn:
A. the bit of bit the 5th bit temporary storage location of bit the 10th bit temporary storage location of the 15th bit temporary storage location;
B. the bit of bit the 4th bit temporary storage location of bit the 9th bit temporary storage location of the 14th bit temporary storage location;
C. the bit of bit the 3rd bit temporary storage location of bit the 8th bit temporary storage location of the 13rd bit temporary storage location;
D. the bit of bit the 2nd bit temporary storage location of bit the 7th bit temporary storage location of the 12nd bit temporary storage location;
E. the bit of bit the 1st bit temporary storage location of bit the 6th bit temporary storage location of the 11st bit temporary storage location;
F. the bit of bit the 0th bit temporary storage location of bit the 5th bit temporary storage location of the 10th bit temporary storage location; And
G. the bit of bit the 4th bit temporary storage location of the 9th bit temporary storage location (bit of bit the 5th bit temporary storage location of bit the 10th bit temporary storage location of the 15th bit temporary storage location).
9. random-number generating method as claimed in claim 1, wherein these 16 bit linear shift registers are after 8 time clock, and this Boolean function group is predicted to be in regular turn:
A. the bit of bit the 5th bit temporary storage location of bit the 10th bit temporary storage location of the 15th bit temporary storage location;
B. the bit of bit the 4th bit temporary storage location of bit the 9th bit temporary storage location of the 14th bit temporary storage location;
C. the bit of bit the 3rd bit temporary storage location of bit the 8th bit temporary storage location of the 13rd bit temporary storage location;
D. the bit of bit the 2nd bit temporary storage location of bit the 7th bit temporary storage location of the 12nd bit temporary storage location;
E. the bit of bit the 1st bit temporary storage location of bit the 6th bit temporary storage location of the 11st bit temporary storage location;
F. the bit of bit the 0th bit temporary storage location of bit the 5th bit temporary storage location of the 10th bit temporary storage location;
G. the bit of bit the 4th bit temporary storage location of the 9th bit temporary storage location (bit of bit the 5th bit temporary storage location of bit the 10th bit temporary storage location of the 15th bit temporary storage location); And
H. the bit of bit the 3rd bit temporary storage location of the 8th bit temporary storage location (bit of bit the 4th bit temporary storage location of bit the 9th bit temporary storage location of the 14th bit temporary storage location).
10. random-number generating method as claimed in claim 1, wherein this 16 bit linear shift register is after 8 time clock, and this method also comprises:
8 positions of bit displacement that this 16 bit linear shift register is kept in; And
This 16 bit linear shift register is imported as the feedback of this 16 bit linear feedback shift register with 8 bits of output.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 200510073000 CN1687896A (en) | 2005-05-25 | 2005-05-25 | Method and apparatus for generating random number |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 200510073000 CN1687896A (en) | 2005-05-25 | 2005-05-25 | Method and apparatus for generating random number |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN1687896A true CN1687896A (en) | 2005-10-26 |
Family
ID=35305937
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN 200510073000 Pending CN1687896A (en) | 2005-05-25 | 2005-05-25 | Method and apparatus for generating random number |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN1687896A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101127575B (en) * | 2007-09-12 | 2010-09-01 | 中兴通讯股份有限公司 | An equably distributed random number generator and its generation method |
| CN105739946A (en) * | 2014-12-08 | 2016-07-06 | 展讯通信（上海）有限公司 | Random digit generation method and device |
-
2005
- 2005-05-25 CN CN 200510073000 patent/CN1687896A/en active Pending
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101127575B (en) * | 2007-09-12 | 2010-09-01 | 中兴通讯股份有限公司 | An equably distributed random number generator and its generation method |
| CN105739946A (en) * | 2014-12-08 | 2016-07-06 | 展讯通信（上海）有限公司 | Random digit generation method and device |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN1186759C (en) | Driving circuit and method for organic electroluminescent device | |
| CN1503938A (en) | Multiplication logic circuit | |
| CN1430331A (en) | Computing circuit | |
| CN1252566A (en) | Method and device for access control of direct memory | |
| CN1821951A (en) | Arithmetic unit | |
| CN1858999A (en) | Pseudo-random sequence generating device | |
| CN101053158A (en) | Reconfigurable semiconductor integrated circuit and its processing allocation method | |
| CN1687896A (en) | Method and apparatus for generating random number | |
| CN1949221A (en) | Method and system of storing element and method and system of searching element | |
| CN1226105A (en) | Improvement of activation speed of signal wiring line in semiconductor integrated circuit | |
| CN1700281A (en) | Switching control circuit for data driver of display device and method thereof | |
| CN1520041A (en) | Converter for converting thermometer code and its method | |
| CN1914847A (en) | Apparatus and method for generating random number using digital logic | |
| CN1379409A (en) | Semiconductor storage device | |
| CN1661919A (en) | Operation mode setting circuit | |
| CN1862968A (en) | Integrated circuit design utilizing array of functionally interchangeable dynamic logic cells | |
| CN100338876C (en) | Circuit arrangement | |
| CN1870131A (en) | Character string retrieving circuit and character string retrieving method | |
| CN1809806A (en) | Improved reduction calculations | |
| CN1809001A (en) | Method of testing transmission performance of HSDPA channel | |
| CN1383285A (en) | Cyclic redundancy check method for parallel data | |
| CN1841258A (en) | Clock frequency eliminator and clock frequency eliminating method | |
| CN1152361C (en) | Signal processing device | |
| CN1543600A (en) | Power raising circuit | |
| CN1776906A (en) | Configuration system of chip identifying code and con figuration method |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C02 | Deemed withdrawal of patent application after publication (patent law 2001) | ||
| WD01 | Invention patent application deemed withdrawn after publication |