CN1682214A

CN1682214A - Matrix operation device

Info

Publication number: CN1682214A
Application number: CN03821223.4A
Authority: CN
Inventors: 中胜义; 北川惠一
Original assignee: Matsushita Electric Industrial Co Ltd
Current assignee: Panasonic Holdings Corp
Priority date: 2003-03-07
Filing date: 2003-03-07
Publication date: 2005-10-12
Also published as: WO2004079585A1

Abstract

A matrix operator can calculate simultaneous functions including upward or downward triangular array by forward or backward substitution with a small device with less electric energy consumption. It consists of nine sum-product units and a linear operating unit to carry out fixed linear calculation concerned. The linear operating unit solves function N while the sum-product units process the next function.

Description

Matrix operating device

Technical field

The present invention relates to a kind ofly can be used to the matrix operating device of separating of obtaining the simultaneous linear equation formula, this simultaneous linear equation formula is to comprise upper triangular matrix or the form performance of triangle battle array down.

Background technology

When using robot calculator to carry out numerical evaluation (matrix operation), adopt sometimes by symmetric matrix being carried out Qiao Laisiji and decompose the form of the product that becomes upper triangular matrix and following triangle battle array, and replace or afterwards obtain in regular turn the method for separating of simultaneous linear equation formula with forward direction to replacement.

This matrix operation can be carried out by the multicomputer system 1000 that possesses a plurality of processors (DSP1002,1004) as shown in figure 12.For example open the record that has in the 2000-339296 communique for the matrix operation of using a plurality of processors the spy.

Use a plurality of processors to carry out between processor, to convey a message in the method for matrix operation, thereby the delay handled takes place.

In addition, because this method is essentially the computing of being undertaken by software, so restricted on the high speed.

In addition, unit scale is easy to maximize.Therefore, on the transfer tables such as portable phone that strict demand is arranged on miniaturization, lightweight or the low consumption electrification, be difficult to load above-mentioned multicomputer system.

Summary of the invention

The objective of the invention is to the obvious raising of realization matrix arithmetic unit processing power, and the miniaturization of implement device and low consumption electrification.

Matrix operating device of the present invention is a kind of circular form arithmetic processing circuit of being made up of hardware, and this device is replaced with forward direction or separating of simultaneous linear equation formula obtained in regular turn to replacing in the back.In matrix operating device of the present invention, set up rational data stream by disposing along order of operation (computing flow process), and carry out the processing of pipeline system for the circuit key element (actual part of carrying out these computings) of obtaining the required multiplication of separating of simple equation, division, addition and subtraction.Because be the processing of being undertaken by hardware, can carry out computing with maximum processing capability, thereby make processing speed bring up to 10 times as speed in the past through the hardware of LSIization.

In addition, according to matrix operating device of the present invention, rationally also reduce the number of multiplier effectively by use multiplier with the time-division, thereby promote the miniaturization and the low consumption electrification of device.

That is to say, for example replace when solving n simultaneous linear equation formula in regular turn, for the computing of separating that solves n simple equation, need use the individual simple equation of before having obtained of the 1st～the (n-1) (for example and long-pending computing) with forward direction.Therefore, if separating of (n-1) the individual simple equation before not determining to be right after just can't be obtained separating of n simple equation.

Tight consider above-mentioned situation, in obtaining the process of separating of n linear function, obtain when being right after the separating of preceding (n-1) individual simple equation when streamline ground, just can't carry out about comprise (n-1) individual simple equation separate processing.On the other hand, can carry out the processing of the item of separating that comprises the 1st～(n-2) the individual simple equation of having obtained in the past.

In view of These characteristics, matrix operating device of the present invention roughly is divided into two groups with the computing item, just comprise the simple equation before being right after the item of separating group and only do not comprise that this separates group.Then, when obtaining the separating of simple equation before being right after, carry out in advance the computing item that is used for obtaining next simple equation only be do not comprise simple equation being right after before separate the arithmetic expression of group, and temporarily keep operation result.

Then, in the stage of separating of obtaining the simple equation before being right after, again to comprising that the item that this separates carries out computing, and its result is worthwhile with the operation result that carries out in advance.Can finish thus in the computing that solves all items of separating required on n the simple equation, that comprise the individual simple equation of the 1st～the (n-1).

The multiplier time-division is not being used and providing under the situation of a plurality of multipliers, the processing of separating of next simple equation still will be obtained by the time and be right after separating of preceding simple equation.Therefore, the situation of processing time and time-division use multiplier much at one.That is to say,, can carry out miniaturization and low consumption electrification that high speed processing also reasonably realizes circuit according to the present invention.

The forward substitution computing of matrix operating device of the present invention when obtaining the separating of the simultaneous linear equation formula that comprises following triangle battle array.This device can also be applicable to back to replacement operation when obtaining the separating of the simultaneous linear equation formula that comprises upper triangular matrix.Can also be applicable in addition that when obtaining the separating of the simultaneous linear equation formula that comprises symmetric matrix symmetric matrix is decomposed by Qiao Laisiji or revises the computing that Qiao Laisiji is decomposed the simple equation of being out of shape.Can also be applicable to the inverse matrix arithmetical unit of the inverse matrix computing of using the Qiao Laisiji decomposition in addition.

Matrix operating device of the present invention can be loaded into receiving trap with associating translocation demodulation function, the receiving trap of the AAA (adaptive array) based on method of least squares is housed or the receiving trap of the adaptive equalizer that possesses transversal filter etc. is housed.

According to one embodiment of present invention, this matrix operating device is a kind of by to replacing to calculate known following triangle battle array being " L " with forward direction replacement or back, and when known upper triangular matrix is " U ", with L (perhaps U) X=Y (matrix that the X representative will be obtained, Y represents known matrix) matrix operating device of the value of separating all key elements of obtaining the described matrix X that will obtain of the simultaneous linear equation formula of performance, this matrix operating device comprises: hardware configuration and long-pending operational part, to for obtain the individual simple equation of n (n is the natural number 2 or more) separate that the required past obtained all separate that be scheduled to and long-pending computing, described all comprise in separating and be right after separating of preceding simple equation; And the linear operation portion of hardware configuration, separating of described n simple equation obtained in the linear operation of being scheduled to by the value of described and long-pending operational part output; Wherein, obtain in described linear operation portion (n-1) individual simple equation the computing of separating during, described and long-pending operational part for obtain separating of n simple equation required with long-pending computing item in, do not comprise in advance described (n-1) individual simple equation separate and long-pending computing.

According to another preferred embodiment, this matrix operating device is a kind of by to replacing to calculate known following triangle battle array being " L " with forward direction replacement or back, and when known upper triangular matrix is " U ", with L (perhaps U) X=Y (matrix that the X representative will be obtained, Y represents known matrix) matrix operating device of the value of separating all key elements of obtaining the described matrix X that will obtain of the simultaneous linear equation formula of performance, this matrix operating device comprises: first register, and temporary transient savings is in that to obtain separating of the individual simple equation of n (n is the natural number more than 2) required, separating of simple equation before being right after; Shift register, each of the simple equation of temporary transient savings before obtaining separating of described n simple equation simple equation required, before described being right after separated, and is made of the tap of dividing into first half and latter half; A plurality of switches, corresponding and be provided with each group, and organize switching and export certain value from each, described group is that first half tap and the latter half tap that will be positioned at mutual correspondence position in described shift register becomes one group, perhaps described first register and the latter half tap that is positioned at the relative position of described shift register is become one group and constitute; The coefficient maker as the coefficient that each value with described a plurality of switch outputs multiplies each other, generates the general key element of described triangle battle array L down or upper triangular matrix U with predetermined order; A plurality of multipliers, the coefficient that generates with described coefficient maker on duty that described a plurality of switches are exported respectively corresponding to each switch; Totalizer, the value addition that described a plurality of multipliers are exported respectively; Second register is temporarily put aside the addition results of described totalizer output, and when carrying out next addition process in described totalizer, this addition results of putting aside is restored to described totalizer; And linear calculating circuit, the addition results of described totalizer output is applied required linear operation calculate separating of described n simple equation; Wherein, when separating of n the simple equation that described linear calculating circuit is calculated is restored to described first register, before separating of described n simple equation is configured in described first register, make one section of described first register and described shift register displacement, and after described totalizer output addition results, undertaken by described linear calculating circuit computing during, by switching described a plurality of switch so that export the value of the described latter half tap of described shift register, be implemented as in advance separating of (n+1) individual simple equation of obtaining subsequently required with a part long-pending computing, and will obtain be restored to first register with separating of long-pending computing and continue carry out computing, determine all key elements of the described matrix X that will obtain.

Matrix operating device of the present invention be on a small scale, low power consumption, and can carry out hypervelocity and handle, therefore, can bring into play sufficient ability as the arithmetic processing apparatus in mobile station apparatus such as portable phone or the radio base station apparatus.

Description of drawings

Fig. 1 is that expression contains the figure of the contents processing of the matrix operation of triangle battle array down;

Fig. 2 is the circuit diagram of structure of an example of expression matrix operating device of the present invention;

Fig. 3 is the timing diagram of the characteristic manipulation of explanation matrix operating device shown in Figure 2;

Fig. 4 is the figure that an example of the contents processing when utilizing matrix operating device shown in Figure 2 to obtain separating of simple equation is described;

Fig. 5 is the figure of contents processing that expression contains the matrix operation of upper triangular matrix;

Fig. 6 A is the block scheme of structure that expression comprises the CDMA receiving trap of JD (joint-detection) demodulation section;

Fig. 6 B is the figure that expression sends the form of data;

Fig. 7 is the figure of propagation model of expression multi-user's transmission signal;

Fig. 8 is the figure that represents propagation model shown in Figure 7 with the form of matrix;

Fig. 9 is the figure of the generation of explanation cross-correlation matrix (F);

Figure 10 is the figure of the structure of the expression adaptive array apparatus that is suitable for matrix operating device of the present invention;

Figure 11 is the figure of the structure of the expression adaptive equalizer that is suitable for matrix operating device of the present invention; And

Figure 12 is the figure that explanation utilizes the matrix operation method of existing multiprocessor.

Embodiment

At first, the solution of utilizing Qiao Laisiji to decompose the simultaneous linear equation formula of (LU decomposes, and is also referred to as triangle decomposition) is described.

Obtain the situation of separating of the extensive simultaneous linear equation formula shown in following formula (1) in this explanation.

Fd＝r......(1)

At this, F represent n capable * known matrix of n row, r represent n capable * known matrix of 1 row, and the matrix that will obtain of d representative (n capable * 1 be listed as).

According to LU factorization, utilize triangle battle array L and its transposed matrix L down ^T, as the known symmetric matrix F of following formula (2) expression.

F＝L?L ^T......(2)

L?L ^T?d＝r.........(3)

D is solved formula (3).

This processing roughly is divided into the calculating in 2 stages.

Below, phase one processing and subordinate phase processing are described.

(phase one)

Suppose L ^TDuring d=z, formula (3) can be deformed into formula (4).

Lz＝r.........(4)

Utilize formula (4) to obtain matrix z.

Because of matrix L is following triangle battle array, the formula of obtaining matrix z can show as following formula (5).

\{\begin{matrix} z_{1} = \frac{1}{L_{11}} r_{1} \\ z_{i} = \frac{1}{L_{ii}} (r_{i} - Σ_{j - 1}^{i - 1} L_{ij} \cdot z_{j}) \end{matrix} . . . . . . . (5)

But, i=2,3...n.

Obtain matrix z by following method.

At first calculate the key element z of the 1st row ₁

Then, utilize the z that calculates ₁, calculate the 2nd key element z that goes according to formula (5) ₂Below, utilize z equally ₁～z _I-1Result of calculation, calculate z _i

Be called as forward substitution according to this computing from the 1st key element of matrix z to the order computation of n key element.

(subordinate phase)

The matrix z that utilization was calculated in the phase one is according to the formula L in the phase one displacement ^TD=z obtains and separates d.

At this, matrix L ^TThe transposed matrix of triangle battle array L, just upper triangular matrix under being.

Therefore, the formula of separating d of obtaining the simultaneous linear equation formula is following formula (6).

\{\begin{matrix} d_{N} = \frac{1}{L_{NN}} z_{N} \\ d_{i} = \frac{1}{L_{ii}} (z_{i} - Σ_{j = i + 1}^{N} L_{ij} \cdot d_{j}) \end{matrix} . . . . . . . . (6)

But, i=n-1, n-2......1.

Because calculate from 1 key element backward of a n key element to the, the computing of matrix d is called as the back to replacement operation.

Matrix operating device of the present invention can extensively be used in the computing of separating from back to replacement that as above obtain the simultaneous linear equation formula by forward substitution.

Followingly embodiments of the invention are described with reference to accompanying drawing.

(embodiment 1)

To obtain n through triangle decomposition capable * circuit structure of separating of the simultaneous linear equation formula of n column matrix describes.

Suppose n capable * the following triangle battle array of n row be L, n capable * when the known matrix of 1 row is r, show above-mentioned simultaneous linear equation formula with formula (7).

Lz＝r.........(7)

At this, z representative as the n that separates of simultaneous linear equation formula capable * 1 column matrix.

Because of matrix L is following triangle battle array, come from z according to above-mentioned formula (5) ₁To z _nObtain the simultaneous linear equation formula in regular turn.

The partial content of this computing of expression among Fig. 1.

Processing shown in Figure 1 (SP1) expression contains the content of the matrix operation of triangle battle array down.

Handle the 1st～4th simultaneous linear equation formula of (SP2) expression.

Handle (SP3) expression and obtain the concrete operation content of separating of the 1st～4th simultaneous linear equation formula.

The general formula of separating of representing to obtain each simple equation by formula (5).

Shown in the processing (SP1) of Fig. 1, following triangle battle array is that its upper right half part all is " 0 ", and partly partly disposes the matrix of matrix key element in its lower-left.

At this, the matrix key element that is positioned on the diagonal line in the following triangle battle array is called " diagonal angle key element ", " 0 " of this key element and upper right half part joins.In the processing (SP1) of Fig. 1, represent the diagonal angle key element with circle.

Other matrix key elements are called " general key element ".In the processing (SP1) of Fig. 1, represent general key element with triangle.

Define diagonal angle key element and general key element too at upper triangular matrix.

The z that separates that obtains the 4th simple equation shown in the processing (SP3) of Fig. 1 ₄Operation content as can be seen, obtain the computing of separating with following step.

The long-pending summation of the general key element that the separating of each simple equation of calculating of 1. obtaining over be multiply by the following triangle battle array corresponding with it.

2. from the key element of the correspondence of known matrix r, deduct this total value.

3. with the value of subtraction result divided by the corresponding diagonal angle key element of triangle battle array down.

Fig. 2 is the figure of concrete structure of the matrix operating device of expression realization of High Speed above-mentioned matrix operation.

And Fig. 3 is the timing diagram of the characteristic manipulation of explanation matrix operating device shown in Figure 2.

Matrix operating device shown in Figure 2 is a kind of circular form arithmetic processing circuit that is made of hardware, and this device is obtained separating of simultaneous linear equation formula by forward substitution or back in regular turn to replacing.

To usually set up rational data stream by the circuit that is configured to obtain the required multiplication of separating of simple equation, division, addition and subtraction along order of operation (computing flow process), and carry out the processing of streamline.

The structure of matrix operating device shown in Figure 2 roughly is divided into two parts.

Just, matrix operating device comprises and amasss operational part (101,102,103,105,106,107,108,109,110) and linear operation portion (111,112,113,114).

With long-pending operational part (101,102,103,105,106,107,108,109,110) to for obtain separating of n simple equation (n represent the natural number 2 or more) required, comprise be right after preceding simple equation separate obtain in the past all separate be scheduled to and the long-pending computing of execution.

Linear operation portion (111,112,113,114) carries out the calculation process by hardware.Just, separating of n simple equation obtained in the linear operation of being scheduled to the value of long-pending operational part output.

Subsequently, in this matrix operating device, when linear operational part is obtained the computing of separating of (n-1) individual simple equation, by with long-pending operational part carry out in advance obtain separating of n simple equation required with long-pending computing item in do not comprise separate and the long-pending computing of (n-1) individual simple equation.

And then obtain after the separating of (n-1) individual simple equation, just the item of separating that comprises (n-1) individual simple equation is carried out and long-pending computing.

Time-division is used the multiplier (MUL (1)～MUL (n/2)) of multiplier 107 thus.

The concrete structure of matrix operating device of the present invention below is described.

In matrix operating device shown in Figure 2, register (REG) the 101st, the register of separating of the simple equation before savings is right after.

Shift register 102 is the shift registers separated of the simple equation obtained of putting aside in regular turn.

The reason that is provided with register 101 and shift register 102 in this separation is: be lockable (placement) difference to some extent in the timing of register 101 and between with the timing of one section of the data shift of each tap of the data of register 101 and shift register 102 because consider separating of simple equation before being right after.

As shown in Figure 3, the separating of simple equation of being pinned before clock (RC) decision is right after by register is lockable (placement) timing at register 101.In addition, register pins clock and also abbreviates the pinning clock sometimes as.

In addition, control timing by shift clock (SCL) with one section of the data shift of the data of register 101 and each tap of shift register (REG (1)～REG (n-2)).

In addition, supply with register through OR-gate (OR) to register 101 and pin clock (RC) and shift clock (SCL).

Considerable at this is that shift register 102 has folding halfway shape.As a result, the output that is arranged in the delay key element (storage key element) of the first half (REG (1)～REG (n/2-1)) of shift register 102 and latter half (REG (n/2)～REG (n-2)) relative position becomes one group.Then, the signal of each group is input to each switch SW 1～SW (n/2) that is provided in switch portion 105 respectively.

The reason that adopts said structure is in order to use the multiplier (MUL (1)～MUL (n/2)) that is included in the multiplier 107 to reduce its number by the time-division.

In sum, the separating of the simple equation before being right after be not placed on register 101 during, with one section of the data shift of the data of register 101 and each tap of shift register (REG (1)～REG (n-2)).

Then, switch SW 1～SW (n/2) is switched to the b end.From the delay key element (storage key element) of the latter half of shift register 102, only extract separating of having obtained thus.Just, carry out executable computing in advance.

For this point with after be specifically described.

First storage part 103 (having M (1)～M (n-1)) storage is the value of the general key element (PX) of triangle battle array down.

The value of the above-mentioned general key element of triangle battle array down is imported into a plurality of multipliers (MUL (1)～MUL (n/2)) that are arranged on multiplier 107 through being arranged on a plurality of switches (PW1～PW (n/2)) of switch portion 106.Subsequently, with the simple equation obtained separate and the general key element of following triangle battle array multiplies each other.

Then, addition portion 108 is the output valve addition of each multiplier, and will represent that its result's data deliver to register (REG) 109 by totalizer (ADD) 110.Register 109 temporary transient these data of savings.

Then, after the release of the simple equation before being right after stays in register 101, each switch of switch portion 105 is switched to a end, and carry out same and long-pending computing.

Totalizer 110 is with above-mentioned and long-pending operation result and the results added of handling that is accumulated in register 109 in advance.

The matrix key element of second memory 111 storage known matrix r.

Subtracter 112 is carried out the computing that deducts and amass operation result from the key element of known matrix r.114 pairs of operation results of divider (DIV) remove the value of the diagonal angle key element of following triangle battle array.

113 storages of the 3rd storer are the value of the diagonal angle key element (AX) of triangle battle array down.

When the separating of the simple equation of obtaining as result of division is stored in the 4th storer (being used to put aside the storer of separating) 115, be placed on register 101.Below carry out same processing repeatedly.

Fig. 3 carries out in the explanation matrix operating device shown in Figure 2 and the timing diagram of the operation of long-pending computing (obtaining the computing of the summation of each multiplier) part.

For the convenience on illustrating, solve the situation of 8 simple equations in this supposition.T0～t3 is for obtaining first equational z of separating constantly ₁During.Following moment t2～t5, moment t4～t7, moment t6～t9, moment t8～t11, moment t10～t13, moment t12～t15, moment t14～t17 respectively do for oneself to obtain and separate z ₂, z ₃, z ₄, z ₅, z ₆, z ₇, z ₈During.

Each switch SW 1～SW (n/2) of switch portion 105 periodically switches to a end and b end in turn.

Obtain one and separate z _iThe time, switch connect begin computing after changing to b end.

In addition, switch portion 106 is carried out the switching of switch too.

Switch is switched to a when end, extract data key element (storage key element) and the register 101 from preceding partly delay of shift register 102.Relatively, when switch is switched to the b end, extract data from the later half delay key element of shift register 102.

Shift clock (SCL) and register pin between the clock (RC) phase deviation.Just, the phase place of shift clock (SCL) in advance.

This means before obtaining the separating of simple equation before being right after to make data shift, thereby upgrade the state of shift register.

Illustrate to Fig. 4 modular form and obtain the 8th the equational z of separating ₈The time operation.

As shown in the figure, in order to obtain z ₈, need comprise equational 7 additive operation of separating, the short of equational z of separating that calculates before being right after ₇, just can't carry out computing.

Therefore, shown in Fig. 4 top, with as and the item of long-pending operand roughly be divided into and do not comprise the equational A of group that separates before being right after and comprise the equational B of group that separates before being right after.

Then, finish the equational z of separating that is used to obtain before being right after in totalizer 110 ₇Additive operation after (just finish after the computing with long-pending operational part and carry out the computing of subtracter 112 or the division arithmetic of divider 114 during) upgrade the content of shift register, extract the z that has obtained in the past from the latter half of shift register ₁～z ₃Separate.Subsequently, in advance the A of execution group and long-pending computing.

There is the record of the operation content of carrying out in the bottom of Fig. 3 during each.At first, the data of the latter half of shift register are " 0 " always.Therefore, even switch is switched to b end and extract data from the latter half of shift register and carry out and amass computing, its result still is " 0 ".

Yet, along with the carrying out of computing, the simple equation that the past has been obtained separate the latter half that is displaced to shift register.Finally switch is switched to b end during (just select from the output of the latter half of shift register during), carry out in advance separating of next simple equation required with a part long-pending computing.

Realize the very effective processing of time-division use share multiplier thus.

Be the summary of the characteristic of arithmetic unit shown in Figure 2 as mentioned above.

Next matrix operating device shown in Figure 2 is elaborated.

In addition in the following description, register 101 is called first register, and register 104 is called second register.

In addition, register 109 is called the 3rd register.And, totalizer 108 is called first adder, and totalizer 110 is called second adder.

In addition, switch 105 is called first switch, and switch 107 is called second switch.

Matrix operating device shown in Figure 2 comprises: first register 101, the operation result (z that storage is obtained now _i); (n-2) Duan shift register 102 stores the operation result (z that has now obtained into ₁～z _I-1); First memory 103 is stored all the general key elements outside the diagonal angle key element of known following triangle battle array (L); And second register 104, always store 0.

In addition, matrix operating device comprises: first switch portion 105, preceding half (n/2-1) individual merging of first register 101 and shift register 102 risen be used as first half, and later half (n/2-1) of shift register is individual as latter half, and control reading of these first halfs or latter half; Second switch 106, with preceding half (n/2) the individual storer in the first memory 103 as first half, and with later half (n/2-1) the individual storer in the first memory 103 and second memory 104 as latter half, and control reading of these first halfs or latter half; And n/2 multiplier 107, carry out the multiplying of the output valve of the output valve of first switch 105 and second switch 106.

Matrix operating device also comprises: first adder 108, and will be from all operation result additions of n/2 multiplier 107 outputs; The 3rd register 109 is read latter half and when obtaining the operation result of first adder 108, the result of savings first adder 108; And second adder 110, read first half and when obtaining the operation result of first adder 108, with the value addition of the operation result of first adder 108 and savings at the 3rd register 109.

Matrix operating device also comprises: second memory 111, the storage n capable * 1 row the known matrix key element; Subtracter 112, the value of reading from second memory 111 deducts the operation result of second adder 110; The 3rd storer 113 is stored the diagonal angle key element of known following triangle battle array; Divider 114, with the output valve of subtracter 112 divided by the value of reading from the 3rd storer 113; And the 4th storer 115, the operation result of storage divider 114 outputs.

The 4th storer 115 is stored in regular turn and is separated z ₁To separating z _n

Next the circuit operation of key diagram 2.

During the beginning computing, store the general key element of known following triangle battle array L in the first memory 103.

In the second memory 111 storage n capable * all key elements of known matrix r of 1 row.

Diagonal angle key element (the L of triangle battle array L under the storage in the 3rd storer 113 ₁₁, L ₂₂..., L _Nn).

In second register 104 and the 3rd register 109, be provided with 0.

First memory 103 is made up of n-1 storer.

The general key element of triangle battle array L under the storage of systematicness ground in each storer.

In M (1) storage (0, L ₂₁, L ₃₂, L ₄₃..., L _{N, n-1}).

In M (2) storage (0,0, L ₃₁, L ₄₂, L ₅₃..., L _{N, n-2}).

Below equally in M (n-2) storage (0,0 ..., 0, L _N-1,1, L _{N, 2}), in M (n-1) storage (0,0 ..., 0, L _{N, 1}).

Each storer all has n address.The timing of storage address and shift register 102 displacements synchronously increases, the sense data in regular turn from this address.

When the beginning computing, (calculate z ₁The time), storing initial value " 0 " in first register 101 and shift register 102.

At first, first switch 105 is controlled, and makes from the latter half readout of shift register 102.Second switch 106 is controlled equally, makes from the latter half readout of first memory 103.

This moment, the operation result of n/2 multiplier 107 all was 0 because all store 0 in the shift register 102.

Therefore, the result of first adder 108 stores 0 in 0, the three register 109.

Switch first switch 105 then and control, make from the first half readout of first register 101 and shift register 102.

The data that read out are imported into multiplier 107.

Also control simultaneously, the feasible first half and second register 104 of reading first memory 103, and output to multiplier 107.

The multiplication result of first half also all is 0, and therefore, the operation result of first adder 108 also is 0.

The operation result (summation of the multiplication result of first half) of first adder 108 and the value (summation of the multiplication result of latter half) that is stored in the 3rd register 109 are input to second adder 110.

The output of second adder 110 also is 0.

Finish after the computing of second adder, read the first element r of known matrix r from second memory 111 ₁, and at subtracter 112 from r ₁Deduct the operation result of second adder 110.

In addition, the 3rd register 109 is carried out initialization.

Because the operation result of second adder 110 is 0, subtracter 112 is output as r ₁-0=r ₁

Finish after the computing of subtracter 112, read down the diagonal angle key element L of triangle battle array from the 3rd storer 113 ₁₁, and at divider 114 with the output valve of subtracter 112 divided by L ₁₁

Because divider 114 is output as r ₁/ L ₁₁, at this moment obtain separating z ₁

What obtain separates z ₁Be stored in the 4th storer 115 and first register 101.

Next explanation is obtained and is separated z ₂Operation.

Separate z ₁Calculating process in, when finishing the computing of second adder 110, the value of first register 101 is outputed to shift register 102, and is shifted one section.

The address of reading of (n-1) individual first memory 103 is increased.

Switch first switch 105 at this and control, make from the latter half readout of shift register 102.

Switch second switch 106 simultaneously and control, make from the latter half readout of first memory 103.

The latter half of shift register 102 and the latter half of first memory are imported into multiplier 107, carry out multiplying.

This moment is because the value of shift register 102 all is 0, so multiplication result all is 0.

Multiplication result is imported into first adder 108 and is added.The result of totalizer also is 0.The 3rd register 109 storage addition results.

If at this moment do not obtain separating z ₁, just do not switch first switch 105 and second switch 106, obtain and separate z ₂Computing enter waiting status.

Separate z obtaining ₁And after it is stored in first register 101, just switch first switch 105, make from the first half readout of first register 101 and shift register 102.The data that read out are imported into multiplier 107.

Simultaneously also from the first half and second register, 104 sense datas of first memory 103.The data that read out are imported into multiplier 107.

Multiplier 107 is with the output of first switch 105 and the output multiplication of second switch 106.

Store in first register 101 and separate z ₁

In addition, because the address of reading of first memory 103 is increased, from M (1), read L ₂₁

Therefore, the operation result of multiplier (MUL (1)) is z ₁L ₂₁

Because storage all is 0 in the shift register 102, the operation result outside the multiplier MUL (1) can be 0.

Therefore, the operation result of first adder 108 is z ₁L ₂₁

To put aside in the value of the 3rd register 109 and the operation result addition of first adder 108 at second adder 110.

Because savings is 0 in the 3rd register 109, second adder 110 is output as z ₁L ₂₁

The computing of finishing second adder 110 just increases the address of reading of second memory 111 afterwards, value r ₂Be read out and be input to subtracter 112.

The r that reads from second memory 111 at subtracter 112 ₂Deduct the output valve z of second adder 110 ₁L ₂₁

Therefore, the operation result of subtracter 112 is (r ₂-z ₁L ₂₁).

The computing of finishing subtracter 112 just increases the address of reading of the 3rd storer 113 afterwards, reads down the diagonal angle key element L of triangle battle array L ₂₂And be entered into divider 114.

At the operation result (r of divider 114 with subtracter 112 ₂-z ₁L ₂₁) divided by the L that reads from the 3rd storer 113 ₂₂

The operation result of divider 114 is (r ₂-z ₁L ₂₁)/L ₂₂

According to above-mentioned formula (5), z ₂=(r ₂-z ₁L ₂₁)/L ₂₂

Just, the output z of divider 114 ₂Be imported into the 4th storer 115 and first register 101.

Can obtain z subsequently equally ₃..., z _n

Now tell about the effect of the arithmetic unit of aforesaid present embodiment.

Because from first register 101 and (n-2) section shift register 102 readouts carry out multiplying, as long as being furnished with a multiplier by every section just can handle side by side, thus the shortening processing time.But, so that handle side by side, just need wait until that separating before being right after is imported into first register 101 and handles.

Therefore, according to matrix operating device of the present invention, earlier the latter half of storing the shift register of having obtained of separating 102 is carried out computing.Subsequently, as by carrying out the modes such as computing of first half obtaining moment of separating before being right after, the number of the multiplier that reduces by half, and carry out the time-division and handle.

In sum, adopt matrix operating device of the present invention, can carry out the forward substitution calculation process with the circuit structure of high speed and small scale.

(embodiment 2)

At the foregoing description the computing of triangle battle array under the utilization has been described, explanation in the present embodiment utilizes the situation of the computing of upper triangular matrix.

Suppose n capable * upper triangular matrix of n row be L, n capable * when the known matrix of 1 row is z, represent above-mentioned simultaneous linear equation formula with formula (8).

Ld＝z.........(8)

Separate d and be n capable * matrix of 1 row.

As shown in Figure 5, upper triangular matrix is that a kind of its lower-left half part all is " 0 ", and disposes the matrix of matrix key element in its upper right half part.

Because matrix L is a upper triangular matrix, can be from d _nTo d ₁Backward is obtained the simultaneous linear equation formula.

The arithmetic expression of representing this moment by above-mentioned formula (6).

Carry out this computing at matrix operating device shown in Figure 2.

As mentioned above, the matrix operating device of Fig. 2 comprises: first register 101, the operation result (d that storage is obtained now _i); (n-2) Duan shift register 102 stores the operation result (d that has now obtained into _n～d _I+1); First memory 103 is stored all the general key elements outside the diagonal angle key element of known upper triangular matrix (L); And second register 104, always store 0.

In addition, matrix operating device comprises: first switch 105, preceding half (n/2-1) individual merging of first register 101 and shift register 102 risen be used as first half, and later half (n/2-1) of shift register is individual as latter half, and control reading of these first halfs or latter half; And second switch 106, with preceding half (n/2) individual storer of first memory 103 as first half, and with later half (n/2-1) the individual storer of first memory 103 and second memory 104 as latter half, and control reading of these first halfs or latter half.

In addition, matrix operating device comprises: n/2 multiplier 107, multiply each other the output valve of first switch 105 and the output valve of second switch 106; First adder 108 will be from all operation result additions of n/2 multiplier 107 outputs; And the 3rd register 109, read latter half and when obtaining the operation result of first adder 108, the result of savings first adder 108.

Matrix operating device also comprises: second adder 110, read first half and when obtaining the operation result of first adder 108, with the value addition of the operation result of first adder 108 and savings at the 3rd register 109; Second memory 111, the storage n capable * 1 row the known matrix key element; Subtracter 112, the value of reading from second memory 111 deducts the operation result of second adder 110; The 3rd storer 113, the diagonal angle key element of storing known upper triangular matrix; Divider 114, with the output valve of subtracter 112 divided by the value of reading from the 3rd storer 113; And the 4th storer 115, the operation result of storage divider 114 outputs.

According to said structure, the 4th storer is stored in regular turn and is separated d _nTo separating d ₁

Next circuit operation is described.

During the beginning computing, store the general key element of known upper triangular matrix L in the first memory 103.

In the second memory 111 storage n capable * 1 row known matrix z (z ₁, z ₂... z _n) all key elements.

Diagonal angle key element (the L of storage upper triangular matrix L in the 3rd storer 113 ₁₁, L ₂₂..., L _Nn).

In second register 104 and the 3rd register 109, be provided with 0.

First memory 103 is made up of n-1 storer, and the general key element that upper triangular matrix L is stored on systematicness ground in each storer.

Storage (L in the M (1) of first memory 103 ₁₂, L ₂₃, L ₃₄..., L _{N-1, n}, 0).

Storage (L in M (2) ₁₃, L ₂₄, L ₃₅..., L _{N-2, n}, 0,0).

Below in M (n-2), store (L equally _{1, n-1}, L _{2, n}, 0 ..., 0), in M (n-1) storage (L _{1, n}, 0 ..., 0).

Each storer all has each address of n.

The timing of storage address and shift register 102 displacements synchronously reduces, with this from this address sense data in regular turn.

When the beginning computing, (calculate d _nThe time), storing initial value " 0 " in first register 101 and shift register 102.

At first, first switch 105 is controlled as the latter half readout from shift register 102.

Second switch 106 is controlled as the latter half readout from first memory 103.

Therefore, the result of first adder 108 stores 0 in 0, the three register 109.

Switch first switch 105 then and control, make from the first half readout of first register 101 and shift register 102, and be input to multiplier 107.

The output of second adder 110 also is 0.Finish after the computing of second adder, read the n key element z of known matrix z from second memory 111 _n, and at subtracter 112 from z _nDeduct the operation result of second adder 110.In addition, the 3rd register 109 is carried out initialization.

Because the operation result of second adder 110 is 0, subtracter 112 is output as z _n-0=z _n

Finish after the computing of subtracter 112, read the diagonal angle key element L of upper triangular matrix from the 3rd storer 113 _Nn

At divider 114 with the output valve of subtracter 112 divided by L _Nn

Because divider 114 is output as z _n/ L _Nn, at this moment obtain separating d _n

What obtain separates d _nBe stored in the 4th storer 115 and first register 101.

Next explanation is obtained and is separated d _N-1Operation.Separate d _nCalculating process in, when finishing the computing of second adder 110, the value of first register 101 is outputed to shift register 102, and is shifted one section.

The address of reading of (n-1) individual first memory 103 is reduced.

Multiplication result is input to first adder 108 and addition.

The result of totalizer also is 0.The 3rd register 109 storage addition results.

If at this moment do not obtain separating d _n, just do not switch first switch 105 and second switch 106.Obtain thus and separate d _N-1Computing enter waiting status.

Separate d obtaining _nAnd after it is stored in first register 101, just switch first switch 105, make from the first half readout of first register 101 and shift register 102.Data are imported into multiplier 107.

Also be controlled to be the first half and second register 104 of reading first memory 103 simultaneously, and be input to multiplier 107.

Store in first register 101 and separate d _n, and, because the address of reading of first memory 103 is reduced, read L from M (1) _{N-1, n}

Therefore, the operation result of the multiplier of multiplier 107 (MUL1) is d _nL _{N-1, n}

Because storage all is 0 in the shift register 102, the operation result outside the multiplier (MUL1) can be 0.

Therefore, the operation result of first adder 108 is d _nL _{N-1, n}To put aside in the value of the 3rd register 109 and the operation result addition of first adder 108 at second adder 110.

Because savings is 0 in the 3rd register 109, second adder 110 is output as d _nL _{N-1, n}

Finish the address of reading of just reducing second memory 111 after the computing of second adder 110, value z _N-1Be read out and be input to subtracter 112.The z that reads from second memory 111 at subtracter 112 _N-1Deduct the output valve d of second adder 110 _nL _{N-1, n}

Therefore, the operation result of subtracter 112 is (z _N-1-d _nL _{N-1, n}).Finish the address of reading of just reducing second memory 113 after the computing of subtracter 112, read the diagonal angle key element L of upper triangular matrix L _{N-1, n-1}And be entered into divider 114.

At the operation result (z of divider 114 with subtracter 112 _N-1-d _nL _{N-1, n}) divided by the L that reads from the 3rd storer 113 _{N-1, n-1}

The operation result of divider 114 is (z _N-1-d _nL _{N-1, n})/L _{N-1, n-1}According to formula (6), d _N-1=(z _N-1-d _nL _{N-1, n})/L _{N-1, n-1}Just, divider 114 is output as d _N-1, be imported into the 4th storer 115 and first register 101.

Can obtain d subsequently equally _N-2..., d ₁

Because from first register 101 and (n-2) section shift register 102 readouts and carry out multiplying, as long as having a multiplier by every section just can handle side by side, thus the shortening processing time.But in order to handle side by side simultaneously, separating before processing will be right after by the time is imported into first register 101.

Therefore, according to matrix operating device of the present invention, store the computing of the latter half of the shift register of having obtained of separating 102 earlier.Subsequently, as by carrying out the modes such as computing of first half obtaining moment of separating before being right after, the number of the multiplier that reduces by half, and carry out the time-division and handle.

In sum, adopt matrix operating device of the present invention, can carry out the back with the circuit structure of high speed and small scale and handle to replacement operation.

(embodiment 3)

Matrix operating device of the present invention also goes in the joint-detection demodulation as the demodulation method of radio communication received signal.

Joint-detection demodulation (being designated hereinafter simply as J D demodulation) is the demodulation method of the tdd mode communication of a kind of W-CDMA of being suitable for.

Generally speaking, different with the method for carrying out demodulation by the multiplying detection auto-correlation of extended code, convolution is detected simple crosscorrelation respectively and deducts composition outside oneself the signal at a plurality of users' of received signal signal, only extract each user's signal, just actively utilize the demodulation method of interference eliminated principle.

Because the interference component that only can't eliminate according to auto-correlation can be correctly eliminated in the JD demodulation, can realize more high-precision demodulation.

In addition, the JD demodulation can also be eliminated the interference that postpones the simple crosscorrelation that ripple causes.

Fig. 7 is the propagation model that the signal of JD demodulation is carried out in expression.

D (1)～d (K) number of delegates is the signal that the user of K sends separately, the object of demodulation that Here it is.

C (1)～c (K) represents extended code, and the propagation characteristic that h (1)～h (K) representative estimates (postpones to distribute: the impulse response of the circuit that estimates).

The vector that b (1)～b (K) representative is obtained by the convolution algorithm of extended code and propagation characteristic.

Adding noise n is exactly received signal e.

By JD demodulation section 203 it is carried out demodulation, divide transmission signal d (1)～d (K) of each user of demodulation.

Fig. 8 is the figure that represents propagation model shown in Figure 7 with the form of matrix.

According to Fig. 8, JD demodulation user formula Ad+n=e calculates matrix d.

To both sides from the associate matrix A of premultiplication with matrix A ^H, deformable is A ^HAd+A ^HN=A ^HE.

Little and can ignore the time at noise n, or can show as A at noise ^HN=σ ²During Id (I represents the unit matrix of the capable n row of n), equation just shows as Fd=r.

Just, suppose A ^HN=σ ²During Id (I represents the unit matrix of the capable n row of n), can be deformed into (A ^HA+ σ ²I) d=A ^HE.

At this A ^HCode data after e represents RAKE synthetic shows as r.

In addition, suppose A ^HA+ σ ²I=F just can show as Fd=r.

At this, matrix F is a cross-correlation matrix, and is by with matrix A and its associate matrix A ^HThe symmetric matrix that multiplies each other and generate, described matrix A are little and can ignore the time noise n ten minutes, the vectorial B1 of the circuit impulse response that extended code and convolution are estimated (=B2=Bn) configuration of systematicness ground and the matrix that generates.

In order to obtain matrix d according to aforesaid equation, the inverse matrix of generator matrix F is also carried out multiplying and is got final product.

But operand just increases when the size of matrix F is big, in fact is not easy to calculate inverse matrix.

Therefore, 203 pairs of matrix F of the JD demodulation section of present embodiment are carried out the Qiao Laisiji decomposition, obtain the key element of matrix d by solving the simultaneous linear equation formula.

Fig. 6 A is the block scheme of structure that expression comprises the CDMA receiving trap of JD demodulation section 203, and Fig. 6 B is the figure that expression sends the form of data.

The signal that receives through antenna 2 is amplified by wireless receiving portion 10, and is input to line estimation portion 201 and despreading portion 207.

Line estimation portion 201 carries out the line estimation of each user's signal according to being included in the impulse response to known signal (midamble) in the received signal.

Shown in Fig. 6 B, midamble is to be inserted in a known code time slot central portion, that be used for line estimation.

Line estimation portion 201 comprises: mid-correlation processing unit 20, midamble generating unit 24 and routing portion 22.

At the signal of despreading portion 207 despreadings through wireless receiving portion 10.The line estimation value that is obtained by line estimation portion 201 is imported into synthetic portion 202 of RAKE and JD demodulation section 203.

Symbol data after the despreading is carried out phase compensation based on the line estimation value, and it is synthetic to carry out RAKE by the synthetic portion 202 of RAKE, and the synthetic r as a result of RAKE is input to JD demodulation section 203.

JD despreading portion 203 comprises: cross-correlation matrix (F) generating unit 204, obtain cross-correlation matrix (F) from extended code generating unit 30 extended code that provides and the circuit impulse response that estimates; Qiao Laisiji decomposition portion 205 carries out the Qiao Laisiji decomposition or revises the Qiao Laisiji decomposition cross-correlation matrix, makes down the long-pending form of triangle battle array and upper triangular matrix; And simultaneous equations operational part 206, to the simultaneous equations of representing with the form of triangle battle array under comprising or upper triangular matrix, utilize forward substitution or back to calculate and separate to replacement.

Simultaneous equations operational part 206 comprises matrix operating device as shown in Figure 2.

Fig. 9 is the figure of the function of explanation cross-correlation matrix (F) generating unit 204.

Handle X1 at the convolution algorithm shown in Fig. 9 top, use totalizer 903 (903a～903c etc.) and totalizer 904 to come the extended code (C of convolution from part 900 outputs of savings extended code ₁～C _Q) and from the parameter (h of the line estimation value of part 902 outputs of storage circuit estimated value ₁～h _W), obtain vectorial b ₁-～b _Q+W-1

Subsequently, at the processing Y1 shown in Fig. 9 bottom, the vectorial b of systematicness ground configuration ₁～b _Q+W-1Generate matrix A.And handling the associate matrix ranks A that Y2 carries out matrix A and matrix A ^HMultiplying, generate matrix F (=A ^HA).

Is d in this hypothesis as the estimated signal of the transmission signal of JD demodulation result gained, just sets up following formula (9).

Fd＝r......(9)

At simultaneous equations operational part 206, solve above-mentioned formula for d.

, can carry out Qiao Laisiji and decompose (comprising that revising Qiao Laisiji decomposes) because matrix F is a symmetric matrix at this.

Use triangle battle array L down, matrix F can be decomposed into F=LL ^H

But, L ^HIt is the associate matrix of L.Carry out Qiao Laisiji by Qiao Laisiji decomposition portion 205 and decompose (or revise Qiao Laisiji and decompose).

Thus, draw LL ^HD=r is by replacing L ^HD=z becomes Lz=r, earlier z is solved the relevant simultaneous equations of triangle battle array down.Because matrix z is known, can solve the simultaneous equations L of relevant upper triangular matrix at this to d ^HD=z.

Above-mentioned by using matrix operating device of the present invention shown in Figure 2 to solve about the simultaneous linear equation formula of following triangle battle array and the simultaneous linear equation formula of relevant upper triangular matrix, can obtain very at high speed and separate.

(embodiment 4)

Matrix operating device of the present invention also can be used for the communicator of equipment based on the adaptive array of least square poor (MMSE).

Figure 10 represents the communicator of equipment based on the adaptive array of least square poor (MMSE).

With number of antennas is that 3 situation is that example describes.

From antenna 301, antenna 302 and antenna 303 input received signals.

By the signal times that receives through each antenna is carried out suitable weighting with the weight that is generated by weight generating unit 305, make and in for the detuner 304 of received signal, carry out suitable demodulation.

Suppose that from the autocorrelation matrix of antenna 301, antenna 302 and antenna 303 input received signals be R, and the cross-correlation matrix of received signal and known signal can be obtained weight w according to following formula (10) when being P.

Rw＝P......(10)

At this,, can carry out Qiao Laisiji and decompose (or revise Qiao Laisiji and decompose) because R is a symmetric matrix.Therefore, just obtain the simultaneous linear equation formula and the relevant simultaneous linear equation formula of triangle battle array down of relevant upper triangular matrix.

Thus, by utilizing matrix operating device of the present invention, can obtain suitable weight at a high speed.

(embodiment 5)

Matrix operating device of the present invention also can be used to equip the communicator of adaptive equalizer.

Adaptive equalizer is a kind of wave filter, critically controls the time response of travel path, comes the amplitude and the lag characteristic of level and smooth travel path.

The communicator of representing to equip adaptive equalizer at Figure 11.

Received signal is imported into transversal filter (FIR) 401 and weight calculation unit 402.

Weight calculation unit 402 is calculated the tap coefficient that is suitable for transversal filter 401 most.

The tap number of supposing transversal filter 401 is M.Calculate only Chou Tou Department number by following mode.Suppose only Chou Tou Department number be M capable * autocorrelation matrix of matrix w, the received signal of 1 row is the R matrix of M row (M is capable *) and received signal when being P (M capable * 1 matrix that is listed as) corresponding to the cross-correlation matrix that the expectation of known signal is replied, and can set up following formula (11).

RW＝p......(11)

When the received signal of this hypothesis time point i was r (i), the auto-correlation array R of received signal was as follows.

In addition, the expectation cross-correlation matrix P that replys d (n) and received signal is as follows.

P = [\begin{matrix} P (0) \\ P (1) \\ \cdot \\ \cdot \\ \cdot \\ P (M - 1) \end{matrix}]

By solve formula (11) for w, obtain only Chou Tou Department number and generate only wave filter.At this,, can carry out Qiao Laisiji and decompose, revise the Qiao Laisiji decomposition because R is a symmetric matrix.

By utilize matrix operating device of the present invention carry out subsequently forward substitution and the back to replacement operation, can carry out high-speed computation with small-scale circuit structure.

(embodiment 6)

Also produce effect in the Capon method computing of a kind of direction of arrival algorithm for estimating that matrix operating device of the present invention is carried out in the communicator of equipment adaptive array.

The correlation matrix of supposing received signal is R _Xx, array answer vector when being a (θ), obtain Capon method angle frequency spectrum P according to following formula (12) _Cp(θ).

P_{cp} (θ) = \frac{1}{a^{H} (θ) R_{xx}^{- 1} a (θ)} \cdot \cdot \cdot \cdot \cdot \cdot (12)

At this, because the correlation matrix R of received signal _XxBe symmetric matrix, can carry out Qiao Laisiji and decompose.Suppose that the triangle battle array is L down, can be decomposed into R _Xx=LL ^HTherefore, can be deformed into R _Xx ^-1=(LL ^H) ^-1

Utilize following formula (13) to obtain LL easily ^HInverse matrix.

Just, suppose LL ^HInverse matrix be x, when unit matrix is E, can represent by following formula (13).

LL ^Hx＝E.........(13)

By utilizing matrix operating device of the present invention to solve formula (13), can carry out high-speed computation with small-scale circuit structure for x.

As mentioned above, matrix operating device of the present invention can be obtained inverse matrix at a high speed.

As mentioned above, according to the present invention, carry out superfast matrix operation by utilizing the circular form arithmetic processing circuit that constitutes with hardware.Thus, can realize high speed processing as 10 times of in the past speed.

In addition, according to the present invention, rationally also reduce the number of multiplier effectively by use multiplier with the time-division, thereby promote the miniaturization and the low consumption electrification of device.

Just, the simple equation before be right after separate just in computing the time, just begin the computing of separating and the long-pending computing of next simple equation.

But, because and long-pending computing comprise key element before being right after of calculating at present, can't carry out all and long-pending computing.

Therefore, be divided into first half and latter half (side who comprises the key element before being right after), and a plurality of side by side multiplier together carries out multiplying, begin multiplying from latter half.

The key element of obtaining before being right after begins the multiplying of first half afterwards again.Compare with the method for together carrying out multiplying after the key element of obtaining before being right after, the number of multiplier can for example reduce by half.Processing time does not almost have difference yet.

As mentioned above, according to the present invention, with the also hardware high-speed computation of realization matrix effectively of low power consumption type on a small scale.

Matrix operating device of the present invention is suitable for LSIization, therefore, and applicable to mobile current devices such as portable phones.

This instructions is based on the Japanese patent application laid Willing 2001-314389 of application on October 11 calendar year 2001.Its content all is contained in this for reference.

Industrial applicibility of the present invention is: the present invention can be useful in be used to obtaining to comprise upper triangular matrix Or in the matrix operating device of the solution of the simultaneous linear equation formula of the form of lower triangle battle array performance.

Claims

1, a kind of matrix operating device, known following triangle battle array is made as " L ", and when known upper triangular matrix is made as " U ", by replacing with forward direction or separating of the simultaneous linear equation formula that shows with L (perhaps U) X=Y (X representative will obtain matrix, Y represents known matrix) calculated to replacing in the back, thereby obtain the value of all key elements of the described matrix X that will obtain, this matrix operating device comprises:

Hardware configuration and long-pending operational part, to for obtain the individual simple equation of n (n is the natural number more than 2) separate that the required past obtained all separate that be scheduled to and long-pending computing, described all comprise separating of previous simple equation in separating; And

The linear operation portion of hardware configuration obtains separating of described n simple equation to the linear operation of being scheduled to by the value of described and long-pending operational part output,

Wherein, obtain in described linear operation portion (n-1) individual simple equation the computing of separating during, at described and long-pending operational part, for obtain separating of n simple equation required with long-pending computing item in, do not comprise in advance described (n-1) individual simple equation separate and long-pending computing.

2, the described matrix operating device of claim 1, wherein the time-division is used the multiplier of forming described and long-pending operational part.

3, a kind of matrix operating device, known following triangle battle array is made as " L ", and when known upper triangular matrix is made as " U ", by replacing with forward direction or separating of the simultaneous linear equation formula that shows with L (perhaps U) X=Y (X representative will obtain matrix, Y represents known matrix) calculated to replacing in the back, thereby obtain the value of all key elements of the described matrix X that will obtain, this matrix operating device comprises:

First register, temporary transient savings are separated separating of required, previous simple equation what obtain the individual simple equation of n (n is the natural number more than 2);

Shift register, each that temporary transient savings is being obtained separating of described n simple equation simple equation required, before the described previous simple equation separated, and is made of the tap of dividing into first half and latter half;

A plurality of switches, corresponding and be provided with each group, and organize switching and export certain value from each, described group is that first half tap and the latter half tap that will be positioned at mutual correspondence position in described shift register becomes one group, perhaps described first register and the latter half tap that is positioned at the relative position of described shift register is become one group and constitute;

The coefficient maker as the coefficient that each value with described a plurality of switch outputs multiplies each other, generates the general key element of described triangle battle array L down or upper triangular matrix U with predetermined order;

A plurality of multipliers, the coefficient that generates with described coefficient maker on duty that described a plurality of switches are exported respectively corresponding to each switch;

Totalizer, the value addition that described a plurality of multipliers are exported respectively;

Second register is temporarily put aside the addition results of described totalizer output, and when carrying out next addition process in described totalizer, this addition results of putting aside is restored to described totalizer; And

Linear calculating circuit applies required linear operation to the addition results of described totalizer output and calculates separating of described n simple equation;

Wherein, when separating of n the simple equation that described linear calculating circuit is calculated is restored to described first register,

Separating of described n simple equation join be placed in described first register before, make one section of described first register and described shift register displacement, and after described totalizer output addition results, undertaken by described linear calculating circuit computing during, by switching described a plurality of switch so that export the value of the described latter half tap of described shift register, be implemented as in advance separating of (n+1) individual simple equation of obtaining subsequently required with a part long-pending computing

And will obtain be restored to first register with separating of long-pending computing and continue carry out computing, determine all key elements of the described matrix X that will obtain.

4, the described matrix operating device of claim 3, wherein, described linear calculating circuit comprises and carrying out the diagonal angle key element of described down triangle battle array or the upper triangular matrix division arithmetic as divisor, or with the circuit of the multiplying of this division arithmetic equivalence.

5, a kind of joint-detection demodulating equipment that the described matrix operating device of claim 1 is housed.

6, a kind of adaptive array apparatus that the described matrix operating device of claim 1 is housed.

7, a kind of adaptive equalizer that the described matrix operating device of claim 1 is housed.

8, a kind of radio communication device that the described matrix operating device of claim 1 is housed.